TPS2320
TPS2321
www.ti.com
SLVS276F – MARCH 2000 – REVISED JULY 2013
DUAL HOT SWAP POWER CONTROLLERS
WITH INDEPENDENT CIRCUIT BREAKER
Check for Samples: TPS2320, TPS2321
FEATURES
1
•
•
•
•
•
•
•
•
•
Dual-Channel High-Side MOSFET Drivers
IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
Output dV/dt Control Limits Inrush Current
Independent Circuit-Breaker With
Programmable Overcurrent Threshold and
Transient Timer
CMOS- and TTL-Compatible Enable Input
Low, 5-μA Standby Supply Current (Max)
Available in 16-Pin SOIC and TSSOP Package
–40°C to 85°C Ambient Temperature Range
Electrostatic Discharge Protection
APPLICATIONS
•
•
•
D OR PW PACKAGE
(TOP VIEW)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GATE1
GATE2
DGND
TIMER
VREG
AGND
ISENSE2
ISENSE1
DISCH1
DISCH2
ENABLE
FAULT
ISET1
ISET2
IN2
IN1
NOTE: Terminal 14 is active-high on TPS2321.
typical application
VO1
+
V1
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
Electronic Circuit Breaker
3 V–13 V
IN1
ISET1
DISCH1
ISENSE1 GATE1
VREG
AGND
DESCRIPTION
TPS2320
DGND
FAULT
TIMER
The TPS2320 and TPS2321 are dual-channel hotENABLE
swap controllers that use external N-channel
GATE2
ISENSE2
DISCH2
IN2
ISET2
MOSFETs as high-side switches in power
applications. Features of these devices, such as
V
overcurrent protection (OCP), inrush-current control,
+
V2
3 V–5.5 V
and the ability to discriminate between load transients
and faults, are critical requirements for hot-swap
applications.
A
The TPS2320/21 devices incorporate undervoltage lockout (UVLO) to ensure the device is off at startup. Each
internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance
the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs,
reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense
overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents
during power-state transitions, to disregard transients for a programmable period.
O2
Table 1. AVAILABLE OPTIONS
TA
PACKAGES
PIN
COUNT
ENABLE
ENABLE
Dual-channel with independent OCP and adjustable PG
20
TPS2300IPW
TPS2301IPW
Dual-channel with interdependent OCP and adjustable PG
20
TPS2310IPW
TPS2311IPW
16
TPS2320ID
TPS2320IPW
TPS2321ID
TPS2321IPW
14
TPS2330ID
TPS2330IPW
TPS2331ID
TPS2331IPW
HOT-SWAP CONTROLLER DESCRIPTION
–40°C to 85°C Dual-channel with independent OCP
Single-channel with OCP and adjustable PG
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
TPS2320
TPS2321
SLVS276F – MARCH 2000 – REVISED JULY 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
IN1
VREG
ISET1
ISENSE1
GATE1
PREREG
DISCH1
Clamp
dv/dt Rate
Protection
Circuit
Breaker
50 µA
Charge
Pump
Pulldown FET
Circuit Breaker
UVLO and
Power Up
AGND
75 µA
DGND
ENABLE
FAULT
Logic
Deglitcher
TIMER
Second Channel
IN2
ISET2
ISENSE2
GATE2
DISCH2
Table 2. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
6
I
Analog ground, connects to DGND as close as possible
DGND
3
I
Digital ground
DISCH1
16
O
Discharge transistor 1
DISCH2
15
O
Discharge transistor 2
ENABLE/ENABLE
14
I
Active low (TPS2320) or active high enable (TPS2321)
FAULT
13
O
Overcurrent fault, open-drain output
GATE1
1
O
Connects to gate of channel 1 high-side MOSFET
GATE2
2
O
Connects to gate of channel 2 high-side MOSFET
IN1
9
I
Input voltage for channel 1
IN2
10
I
Input voltage for channel 2
ISENSE1
8
I
Current-sense input channel 1
ISENSE2
7
I
Current-sense input channel 2
ISET1
12
I
Adjusts circuit-breaker threshold with resistor connected to IN1
ISET2
11
I
Adjusts circuit-breaker threshold with resistor connected to IN2
TIMER
4
O
Adjusts circuit-breaker deglitch time
VREG
5
O
Connects to bypass capacitor, for stable operation
2
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SLVS276F – MARCH 2000 – REVISED JULY 2013
DETAILED DESCRIPTION
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltageclamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the
controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than
5μA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. The
other channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pin
has to be toggled or the input power has to be cycled.
GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15μA to each.
The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the
turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These
capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up.
The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the external MOSFET
transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement
overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates
an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws
50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also
connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An
overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2.
To ensure proper circuit breaker operation, VI(ISENSE1) and VI(ISET1) should never exceed VI(IN1). Similarly,
VI(ISENSE2) and VI(ISET2) should never exceed VI(IN2).
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to
restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is
used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-μF ceramic capacitor should
be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the
device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry
and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than5.5 V,
VREG and IN1 may be connected together. However, under these conditions, disabling the device will not place
the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed,
thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-μF ceramic
capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1μF to 10μF.
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3
TPS2320
TPS2321
SLVS276F – MARCH 2000 – REVISED JULY 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Input voltage range
Output voltage range
(1) (2)
VALUE
UNIT
VI(IN1), VI(ISENSE1), VI(ISET1), VI(ENABLE)
–0.3 to 15
V
VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG)
–0.3 to 7
V
VO(GATE1)
–0.3 to 30
V
VO(GATE2)
–0.3 to 22
V
VO(DISCH1), VO(FAULT), VO(DISCH2), VO(TIMER)
–0.3 to 15
V
I(GATE1), I(GATE2), I(DISCH1), I(DISCH2)
0 to 100
mA
I(TIMER), I(FAULT)
0 to 10
mA
Operating virtual junction temperature range, TJ
–40 to 100
°C
Storage temperature range, Tstg
–55 to 150
°C
260
°C
Sink current range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are respect to DGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW-16
823 mW
10.98 mW/°C
329 mW
165 mW
D-16
674 mW
8.98 mW/°C
270 mW
135 mW
RECOMMENDED OPERATING CONDITIONS
MIN
VI(IN1), VI(ISENSE1), VI(ISET1)
3
VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG)
3
VI
Input voltage
TJ
Operating virtual junction temperature
VI(ISENSE1), VI(ISET1)
MAX
UNIT
13
5.5
VI(IN1)
VI(ISENSE2), VI(ISET2)
4
NOM
V
VI(IN2)
–40
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100
°C
Copyright © 2000–2013, Texas Instruments Incorporated
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TPS2321
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SLVS276F – MARCH 2000 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
over recommended operating temperature range (–40°C < TA < 85°C), 3V ≤ VI(IN1) ≤13V, 3V ≤ VI(IN2) ≤ 5.5V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
II(IN1)
Input current, IN1
VI(ENABLE) = 5 V (TPS2321),
0.5
1
mA
II(IN2)
Input current, IN2
VI(ENABLE) = 0 V (TPS2320)
75
200
µA
II(stby)
Standby current (sum of
currents into IN1, IN2,
ISENSE1, ISENSE2,
ISET1, and ISET2)
VI(ENABLE) = 0 V (TPS2321),
VI(ENABLE) = 5 V (TPS2320)
5
µA
Gate voltage
II(GATE1) = 500 nA, DISCH1 open
GATE1
VG(GATE1_3V)
VG(GATE1_4.5V)
VI(IN1) = 3 V
VG(GATE1_10.8V)
9
11.5
VI(IN1) = 4.5 V
10.5
14.5
VI(IN1) = 10.8 V
16.8
21
9
10
12
V
V
VC(GATE1)
Clamping voltage, GATE1
to DISCH1
IS(GATE1)
Source current, GATE1
3 V ≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE1) = VI(IN1) + 6 V
10
14
20
μA
Sink current, GATE1
3 V ≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE1) = VI(IN1)
50
75
100
µA
Rise time, GATE1
Cg to GND = 1 nF
tr(GATE1)
(1)
VI(IN1) = 3 V
0.5
VI(IN1) = 4.5 V
0.6
VI(IN1) = 10.8 V
1
VI(IN1) = 3 V
tf(GATE1)
Fall time, GATE1
Cg to GND = 1 nF (1)
ms
0.1
VI(IN1) = 4.5 V
0.12
VI(IN1) = 10.8 V
0.2
ms
GATE2
VG(GATE2_3V)
VG(GATE2_4.5V)
Gate voltage
II(GATE2) = 500 nA, DISCH2 open
VI(IN2) = 3 V
VI(IN2) = 4.5 V
9
11.7
10.5
14.7
9
10
12
V
V
VC(GATE2)
Clamping voltage, GATE2
to DISCH2
IS(GATE2)
Source current, GATE2
3 V ≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE2) = VI(IN2) + 6 V
10
14
20
μA
Sink current, GATE2
3 V ≤ VI(IN2)≤ 5.5 V, 3 V ≤ VO(VREG)≤ 5.5 V,
VI(GATE2) = VI(IN2)
50
75
100
µA
Rise time, GATE2
Cg to GND = 1 nF (1)
tr(GATE2)
tf(GATE2)
(1)
Fall time, GATE2
Cg to GND = 1 nF (1)
VI(IN2) = 3 V
VI(IN2) = 4.5 V
VI(IN2) = 3 V
0.5
VO(VREG) = 3 V
VI(IN2) = 4.5 V
0.6
0.1
0.12
ms
ms
Specified, but not production tested.
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TPS2320
TPS2321
SLVS276F – MARCH 2000 – REVISED JULY 2013
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ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating temperature range (–40°C < TA < 85°C), 3V ≤ VI(IN1) ≤13V, 3V ≤ VI(IN2) ≤ 5.5V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
TIMER
V(TO_TIMER)
Threshold voltage, TIMER
0.4
0.5
0.6
V
Charge current, TIMER
VI(TIMER) = 0 V
35
50
65
µA
Discharge current, TIMER
VI(TIMER) = 1 V
1
2.5
RISETx = 1 kΩ
40
50
60
RISETx = 400 Ω, TA = 25°C
14
19
24
RISETx = 1 kΩ, TA = 25°C
44
50
53
RISETx = 1.5 kΩ, TA = 25°C
68
73
78
0.1
5
mA
CIRCUIT BREAKER
VIT(CB)
Threshold voltage, circuit breaker
I(IB_ISENSEx)
Input bias current, ISENSEx
Discharge current, GATEx
Propagation (delay) time,
comparator inputs to gate output
tpd(CB)
VO(GATEx) = 4 V
400
800
VO(GATEx) = 1 V
25
150
Cg = 50 pF,
(50% to 10%),
10 mV overdrive,
CTIMER = 50 pF
mV
µA
mA
1.3
µs
ENABLE, ACTIVE LOW (TPS2320)
VIH(ENABLE)
High-level input voltage, ENABLE
VIL(ENABLE)
Low-level input voltage, ENABLE
2
RI(ENABLE)
Input pullup resistance, ENABLE
See
td(off_ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) increasing above stop threshold;
100 ns rise time, 20 mV overdrive (2)
60
μs
td(on_ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) decreasing below start threshold;
100 ns fall time, 20 mV overdrive (2)
125
μs
(1)
100
V
200
0.8
V
300
kΩ
ENABLE, ACTIVE HIGH (TPS2321)
VIH(ENABLE)
High-level input voltage, ENABLE
VIL(ENABLE)
Low-level input voltage, ENABLE
RI(ENABLE)
Input pulldown resistance, ENABLE
2
100
td(on_ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) increasing above start threshold;
100 ns rise time, 20 mV overdrive (2)
td(off_ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) decreasing below stop threshold;
100 ns fall time, 20 mV overdrive (2)
V(VREG)
PREREG output voltage
4.5 ≤ VI(IN1) ≤ 13 V
V(drop_PREREG)
PREREG dropout voltage
VI(IN1) = 3 V
V
150
0.7
V
300
kΩ
85
μs
100
µs
PREREG
(1)
(2)
6
3.5
4.1
5.5
V
0.1
V
1V
Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) = I
O_ 0V * I O_ 1V
Specified, but not production tested.
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SLVS276F – MARCH 2000 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating temperature range (–40°C < TA < 85°C), 3V ≤VI(IN1) ≤13V, 3V ≤ VI(IN2) ≤ 5.5V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(TO_UVLOstart) Output threshold voltage, start
2.75
2.85
2.95
V
V(TO_UVLOstop) Output threshold voltage, stop
2.65
2.78
50
75
VREG UVLO
Vhys(UVLO)
Hysteresis
UVLO sink current, GATEx
VI(GATEx) = 2 V
V
mV
10
mA
FAULT OUTPUT
VO(sat_FAULT)
Output saturation voltage, FAULT
IO = 2 mA
Ilkg(FAULT)
Leakage current, FAULT
VO(FAULT) = 13 V
0.4
V
1
µA
DISCH1 AND DISCH2
I(DISCH)
Discharge current, DISCHx
VIH(DISCH)
Discharge on high-level input
voltage
VI(DISCHx) = 1.5 V, VI(VIN1) = 5 V
VIL(DISCH)
Discharge on low-level input voltage
5
10
mA
2
V
1
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V
7
TPS2320
TPS2321
SLVS276F – MARCH 2000 – REVISED JULY 2013
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PARAMETER MEASUREMENT INFORMATION
Load 12 W
VI(ENABLE)
5 V/div
Load 12 W
VI(ENABLE)
5 V/div
VO(GATE1)
10 V/div
VO(DISCH1)
5 V/div
VO(GATE1)
10 V/div
VO(DISCH1)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 1. Turnon Voltage Transition of Channel 1
Figure 2. Turnoff Voltage Transition of Channel 1
Load 5 W
VI(ENABLE)
5 V/div
Load 5 W
VI(ENABLE)
5 V/div
VO(GATE2)
10 V/div
VO(GATE2)
10 V/div
VO(DISCH2)
5 V/div
VO(DISCH2)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 3. Turnon Voltage Transition of Channel 2
8
Figure 4. Turnoff Voltage Transition of Channel 2
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SLVS276F – MARCH 2000 – REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
No Capacitor on Timer
VI(ENABLE)
5 V/div
VI(ENABLE)
5 V/div
VO(GATE1)
10 V/div
No Capacitor on Timer
VO(GATE1)
10 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(OUT1)
2 A/div
IO(OUT1)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 5. Channel 1 Overcurrent Response:
Enabled Into Overcurrent Load
VI(ENABLE)
5 V/div
Figure 6. Channel 1 Overcurrent Response: an
Overcurrent
Load Plugged Into the Enabled Board
No Capacitor on Timer
No Capacitor on Timer
VI(ENABLE)
5 V/div
VO(GATE2)
10 V/div
VO(GATE2)
10 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(OUT2)
2 A/div
IO(OUT2)
2 A/div
t – Time – 0.5 ms/div
t – Time – 2 ms/div
Figure 7. Channel 2 Overcurrent Response:
Enabled Into Overcurrent Load
Figure 8. Channel 2 Overcurrent Response: an
Overcurrent Load Plugged Into the Enabled Board
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PARAMETER MEASUREMENT INFORMATION (continued)
VI(ENABLE)
5 V/div
No Capacitor on Timer
VI(ENABLE)
5 V/div
VO(GATE1)
10 V/div
VO(GATE2)
5 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
II(IN1)
2 A/div
II(IN2)
2 A/div
No Capacitor on Timer
t – Time – 1 ms/div
Figure 9. Channel 1 – Enabled Into Short Circuit
No Capacitor on Timer
t – Time – 1 ms/div
Figure 10. Channel 2 – Enabled Into Short Circuit
VI(IN1)
10 V/div
No Capacitor on Timer
VO(GATE1)
10 V/div
VI(IN1)
10 V/div
VO(GATE1)
10 V/div
VO(OUT1)
10 V/div
IO(OUT1)
1 A/div
VO(OUT1)
10 V/div
IO(OUT1)
1 A/div
t – Time – 5 ms/div
t – Time – 1 ms/div
Figure 11. Channel 1 –Hot Plug
10
Figure 12. Channel 1 –Hot Removal
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SLVS276F – MARCH 2000 – REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
No Capacitor on Timer
VI(IN2)
5 V/div
VO(GATE2)
10 V/div
VO(OUT2)
5 V/div
IO(OUT2)
1 A/div
t – Time – 5 ms/div
Figure 13. Channel 2 - Hot Plug
VI(IN2)
5 V/div
No Capacitor
on Timer
VO(GATE2)
10 V/div
VO(OUT2)
5 V/div
IO(OUT2)
1 A/div
t – Time – 1 ms/div
Figure 14. Channel 2 - Hot Removal
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TYPICAL CHARACTERISTICS
INPUT CURRENT 1 (ENABLED)
vs
INPUT VOLTAGE 1
INPUT CURRENT 2 (ENABLED)
vs
INPUT VOLTAGE 2
71.5
52
IN1 = 13 V
IN2 = 5.5 V
TA = 85°C
50
TA = 25°C
49
48
47
TA = 0°C
46
TA = 0°C
71
I I2 – Input Current 2 – mA
I I1 – Input Current 1 – mA
51
TA = –40°C
TA = –40°C
70.5
TA = 25°C
70
TA = 85°C
69.5
69
45
68.5
44
43
4
5
6
7
8
9
10
11
12
13
68
2.5
14
3
VI1 – Input Voltage 1 – V
Figure 15.
3.5
INPUT CURRENT 1 (DISABLED)
vs
INPUT VOLTAGE 1
5
5.5
6
23
TA = 85°C
IN2 = 5.5 V
IN1 = 13 V
21
14
TA = 25°C
TA = 85°C
19
13
I I2 – Input Current 2 – nA
I I1 – Input Current 1 – nA
4.5
INPUT CURRENT 2 (DISABLED)
vs
INPUT VOLTAGE 2
15
TA = –40°C
12
TA = 0°C
11
10
9
TA = –40°C
17
15
13
11
TA = 0°C
9
8
TA = 25°C
7
7
4
5
6
7
8
9
10
11
12
13
14
5
2.5
VI1 – Input Voltage 1 – V
Figure 17.
12
4
VI2 – Input Voltage 2 – V
Figure 16.
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3
3.5
4
4.5
5
5.5
6
VI2 – Input Voltage 2 – V
Figure 18.
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SLVS276F – MARCH 2000 – REVISED JULY 2013
TYPICAL CHARACTERISTICS (continued)
GATE1 OUTPUT VOLTAGE
vs
INPUT VOLTAGE 1
GATE1 VOLTAGE RISE TIME
vs
GATE1 LOAD CAPACITANCE
18
22
CL(GATE1) = 1000 pF
TA = 25°C
TA = 0°C
18
TA = –40°C
16
14
12
tr – GATE1 Voltage Rise Time – ms
VO – GATE1 Output Voltage – V
20
15
12
9
6
3
0
10
2
3
4
5
6
7
8
9
10
11
0
12
3
6
9
12
CL(GATE1) – GATE1 Load Capacitance – nF
VI1 – Input Voltage 1 – V
Figure 19.
Figure 20.
GATE1 VOLTAGE FALL TIME
vs
GATE1 LOAD CAPACITANCE
GATE1 OUTPUT CURRENT
vs
GATE1 VOLTAGE
4
15
IN1 = 12 V
TA = 25°C
14.5
IO – GATE1 Output Current – mA
t f – GATE1 Voltage Fall Time – ms
IN1 = 12 V
TA = 25°C
TA = 85°C
3
2
1
14
TA = –40°C
TA = 25°C
TA = 0°C
13
12.5
12
11.5
0
TA = 85°C
13.5
IN1 = 13 V
11
0
3
6
9
12
14 15
CL(GATE1) – GATE1 Load Capacitance – nF
Figure 21.
16
17
18
19
20
21
22
23
24
V – GATE1 Voltage – V
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
CIRCUIT-BREAKER RESPONSE TIME
vs
TIMER CAPACITANCE
LOAD VOLTAGE 1 DISCHARGE TIME
vs
LOAD CAPACITANCE
320
IN1 = 12 V
TA = 25°C
t – Load Voltage 1 Discharge Time – ms
t(res) – Circuit-Breaker Response Time – ms
12
9
6
3
0
IN1 = 12 V
IO1 = 0 A
TA = 25°C
280
240
200
160
120
80
40
0
0
0.2
0.4
0.6
0.8
CTIMER – TIMER Capacitance – nF
Figure 23.
1
0
400
100
200
300
CL – Load Capacitance – mF
Figure 24.
500
UVLO START AND STOP THRESHOLDS
vs
TEMPERATURE
V ref – UVLO Start and Stop Thresholds – V
2.9
2.88
2.86
Start
2.84
2.82
2.8
2.78
Stop
2.76
2.74
2.72
2.7
–45–35–25–15 –5 5 15 25 35 45 55 65 75 85 95
TA – Temperature – °C
Figure 25.
14
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SLVS276F – MARCH 2000 – REVISED JULY 2013
APPLICATION INFORMATION
Figure 26 shows a typical dual hot-swap application. The pullup resistor at FAULT should be relatively large
(e.g., 100 kΩ) to reduce power loss, unless it is required to drive a large load.
System
Board
RSENSE1
3 V ∼ 13 V IN1
1 µF ∼ 10 µF
VO1
+
RISET1
0.1 µF
VREG IN1 ISET1 ISENSE1 GATE1
ENABLE
FAULT
ENABLE
DGND
AGND
TIMER IN2
DISCH1
ISET2
ISENSE2 GATE2
DISCH2
VO1 or VO2
RISET2
3 V ∼ 5.5 V IN2
1 µF ∼ 10 µF
FAULT
TPS2321
VO2
+
RSENSE2
Figure 26. Typical Dual Hot-Swap Application
INPUT CAPACITOR
A 0.1-μF ceramic capacitor in parallel with a 1-μF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The
TPS2320/01 does not need to be mounted near the connector or to these input capacitors. For applications with
more severe power environments, a 2.2-μF, or higher, ceramic capacitor is recommended near the input
terminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device.
OUTPUT CAPACITOR
A 0.1-μF ceramic capacitor is recommended per load on the TPS2320/21; these capacitors should be placed
close to the external FETs and to TPS2320/21. A larger bulk capacitor is also recommended on the load. The
value of the bulk capacitor should be selected based on the power requirements and the transients generated by
the application.
EXTERNAL FET
To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. A
few widely used MOSFETs are shown in Table 3. But many other MOSFETs on the market can also be used
with TPS23xx in hot-swap systems.
Table 3. Some Available N-Channel MOSFETs
CURRENT RANGE
(A)
0 to 2
PART NUMBER
DESCRIPTION
MANUFACTURER
IRF7601
N-channel, rDS(on) = 0.035 Ω, 4.6 A, Micro-8
International Rectifier
MTSF3N03HDR2
N-channel, rDS(on) = 0.040 Ω, 4.6 A, Micro-8
ON Semiconductor
MMSF5N02HDR2
Dual N-channel, rDS(on) = 0.04 Ω, 5 A, SO-8
ON Semiconductor
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Table 3. Some Available N-Channel MOSFETs (continued)
CURRENT RANGE
(A)
2 to 5
5 to 10
PART NUMBER
DESCRIPTION
MANUFACTURER
IRF7401
N-channel, rDS(on) = 0.022 Ω, 7 A, SO-8
International Rectifier
MMSF5N02HDR2
N-channel, rDS(on) = 0.025 Ω, 5 A, SO-8
ON Semiconductor
IRF7313
Dual N-channel, rDS(on) = 0.029 Ω, 5.2 A, SO-8
International Rectifier
SI4410
N-channel, rDS(on) = 0.020 Ω, 8 A, SO-8
Vishay Dale
IRLR3103
N-channel, rDS(on) = 0.019 Ω, 29 A, d-Pak
International Rectifier
IRLR2703
N-channel, rDS(on) = 0.045 Ω, 14 A, d-Pak
International Rectifier
TIMER
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitor
should be connected between TIMER and ground. The presence of an overcurrent condition on either channel of
the TPS2320/TPS2321 causes a 50-μA current source to begin charging this capacitor. If the over-current
condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321 latches off
the offending channels and pulls the FAULT pin low. The timer capacitor can be made as large as desired to
provide additional time delay before registering a fault condition. PWRGDx will not correctly report power
conditions when the device is disabled. The time delay is approximately:
dt(sec) = CTIMER(F) × 10,000(Ω).
OUTPUT-VOLTAGE SLEW-RATE CONTROL
When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with a
current of approximately 15 μA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance Cgd of the external MOSFET capacitor to a value approximating:
dV s
15 mA
+
C gd
dt
(1)
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG CAPACITOR
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF or
0.22-µF ceramic capacitor is recommended.
GATE-DRIVE CIRCUITRY
The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal:
• A charging current of approximately 15 μA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1
or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET
source terminals to ensure proper operation of this circuitry.
• A discharge current of approximately 75 μA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gates of the external MOSFET transistors remain at a low voltage.
• During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS
transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry also helps
hold the external MOSFET transistors off when power is suddenly applied to the system.
• During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition
will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from
the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO
driver is enabled instead. If one channel experiences an overcurrent condition and the other does not, then
only the channel that is conducting excessive current will be turned off rapidly. The other channel will continue
to operate normally.
16
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SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
Using channel 1 as an example, the current sensing resistor RISENSE1 and the current-limit-setting resistor RISET1
determine the current limit of the channel, and can be calculated by the following equation:
R
50 10 –6
I LMT1 + ISET1
R ISENSE1
(2)
Typically RISENSE1 is very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between the
junction of RISENSE1 and ISENSE1 and the junction of RISENSE1 and RISET1 are greater than 10% of the RISENSE1
value, then these resistance values should be added to the RISENSE1 value used in the calculation above.
The above information and calculation also apply to channel 2. Table 4 shows some of the current sense
resistors available in the market.
Table 4. Some Current Sense Resistors
CURRENT RANGE (A)
PART NUMBER
DESCRIPTION
0 to 1
WSL-1206, 0.05 1%
0.05 Ω, 0.25 W, 1% resistor
1 to 2
WSL-1206, 0.025 1%
0.025 Ω, 0.25 W, 1% resistor
2 to 4
WSL-1206, 0.015 1%
0.015 Ω, 0.25 W, 1% resistor
4 to 6
WSL-2010, 0.010 1%
0.010 Ω, 0.5 W, 1% resistor
6 to 8
WSL-2010, 0.007 1%
0.007 Ω, 0.5 W, 1% resistor
8 to 10
WSR-2, 0.005 1%
0.005 Ω, 0.5 W, 1% resistor
MANUFACTURER
Vishay Dale
UNDERVOLTAGE LOCKOUT (UVLO)
The TPS2320/TPS2321 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from IN1
through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV. While
the undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldown
transistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies have
fallen to 0 V.
SINGLE-CHANNEL OPERATION
Some applications may require only a single external MOS transistor. Such applications should use GATE1 and
the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the circuitry
associated with the GATE2 pin.
POWER-UP CONTROL
The TPS2320/TPS2321 includes a 500 μs (nominal) startup delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry will provide adequate protection against undervoltage operation.
3-CHANNEL HOT-SWAP APPLICATION
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt
control of 3.3 V, 5 V, and 12 V is required. By using Channel 2 to drive both the 3.3-V and 5-V power rails and
Channel 1 to drive the 12-V power rail, as is shown below, TPS2320/01 can deliver three different voltages to
three loads while monitoring the status of two of the loads.
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System
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Board
RSENSE1
12 V IN1
1 µF ∼ 10 µF
+
VO1
RISET1
0.1 µF
VREG
ENABLE
IN1 ISET1 ISENSE1
1 µF ∼ 10 µF
FAULT
TPS2321
IN2 ISET2 ISENSE2
RISET2
3.3 V IN2
DISCH1
FAULT
ENABLE
DGND
AGND
TIMER
GATE1
GATE2
DISCH2
VO1 or VO2
Rg1
VO2
+
RSENSE2
Rg2
5 V IN3
VO3
1 µF ∼ 10 µF
+
Figure 27. Three-Channel Application
Figure 28 shows ramp-up waveforms of the three output voltages.
VO – Output Voltage – 2 V/div
VO1
VO3
VO2
t – Time – 2.5 ms/div
Figure 28.
18
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SLVS276F – MARCH 2000 – REVISED JULY 2013
REVISION HISTORY
Note: Revision history for previous versions is not available. Page numbers of previous versions may differ.
Changes from Revision E (November 2006) to Revision F
Page
•
Added text to ISENSE1, ISENSE2, ISET1, ISET2 pin description paragraph for clarification. ............................................ 3
•
Added additional VI specs to ROC table for clarification ...................................................................................................... 4
•
Added minus sign to 40°C MIN TJ temperature ................................................................................................................... 4
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19
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS2320ID
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2320I
Samples
TPS2320IDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2320I
Samples
TPS2320IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2320I
Samples
TPS2320IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2320I
Samples
TPS2321ID
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2321I
Samples
TPS2321IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2321I
Samples
TPS2321IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2321I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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