TPS23753APW

TPS23753A TPS23753A SLVS933D – JULY 2009 – REVISED DECEMBER 2020 SLVS933D – JULY 2009 – REVISED DECEMBER 2020 www.ti.com TPS23753A IEEE 802.3 PoE Interface and Converter Controller with Enhanced ESD Immunity The TPS23753A supports a number of input-voltage ORing options including highest voltage, external adapter preference, and PoE preference. 1 Features Enhanced ESD ride-through capability Optimized for isolated converters Complete PoE interface Adapter ORing support 12-V adapter support Programmable frequency with synchronization Robust 100-V, 0.7-Ω hotswap MOSFET Small 14-Pin TSSOP package 15-kV and 8-kV system level ESD capable –40°C to 125°C junction temperature range Design procedure application note – SLVA305 Adapter oring application note – SLVA306 The PoE interface features an external detection signature pin that can also be used to disable the internal hotswap MOSFET. This allows the PoE function to be turned off. Classification can be programmed to any of the defined types with a single resistor. The DC-DC controller features a bootstrap start-up mechanism with an internal, switched current source. This provides the advantages of cycling overload fault protection without the constant power loss of a pullup resistor. The programmable oscillator may be synchronized to a higher-frequency external timing reference. The TPS23753A features improvements for uninterrupted device operation through an ESD event. 2 Applications • • • • IEEE 802.3at compliant powered devices VoIP telephones Access points Security cameras Device Information (1) PART NUMBER TPS23753A The TPS23753A is a combined Power over Ethernet (PoE) powered device (PD) interface and currentmode DC-DC controller optimized specifically for isolated converter designs. The PoE implementation supports the IEEE 802.3at standard as a 13-W, type 1 PD. The requirements for an IEEE 802.3at type 1 device are a superset of IEEE 802.3-2008 (originally IEEE 802.3af). (1) PACKAGE BODY SIZE (NOM) TSSOP (14) 5.00 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. BR1 T1 RFRS R APD1 Adapter RAPD2 DA V OUT R VC VDD M1 * VB GATE CS CTL VB R CTL CVB APD FRS * C OUT D VC CVC V SS TPS23753 RCLS BR2 RBLNK CLS DS VC RTN BLNK DEN VDD1 C IN D1 58V RDEN C1 0.1mF From Spare Pairs or Transformers From Ethernet Transformers 3 Description RCS • • • • • • • • • • • • R OB C CTL C IZ C IO TLV431 R FBU R FBL * Adapter interface and R BLNK are Optional Copyright © 2016, Texas Instruments Incorporated Basic TPS23753A Implementation An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS23753A 1 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Product Information........................................................ 3 6 Pin Configuration and Functions...................................3 7 Specifications.................................................................. 4 7.1 Absolute Maximum Ratings........................................ 4 7.2 ESD Ratings............................................................... 4 7.3 Recommended Operating Conditions.........................4 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics: Controller Section Only......5 7.6 Electrical Characteristics: PoE and Control................ 6 7.7 Typical Characteristics................................................ 8 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 11 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................14 9 Application and Implementation.................................. 25 9.1 Application Information............................................. 25 9.2 Typical Application.................................................... 25 10 Power Supply Recommendations..............................27 11 Layout........................................................................... 27 11.1 Layout Guidelines................................................... 27 11.2 Layout Example...................................................... 27 12 Device and Documentation Support..........................28 12.1 Documentation Support.......................................... 28 12.2 Support Resources................................................. 28 12.3 Electrostatic Discharge Caution..............................28 12.4 Glossary..................................................................28 13 Mechanical, Packaging, and Orderable Information.................................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2016) to Revision D (December 2020) Page • Updated the numbering format for tables, figures and cross-references throughout the document...................1 • Changed Start-up time unit from "V" to "ms" in Electrical Characteristics: Controller Section Only table.......... 5 Changes from Revision B (January 2010) to Revision C (April 2016) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................................................................................................................ 1 • Deleted Dissipation Ratings ...............................................................................................................................6 Changes from Revision A (September 2009) to Revision B (January 2010) Page • Changed From: IEEE 802.3-2005 To: IEEE 802.3at throughout the data sheet................................................ 1 • Changed the text in paragraph one of the DESCRIPTION.................................................................................1 • Changed the Thermal resistance note in the DISSIPATION RATINGS table to include additional information... 6 • Changed text in the second paragraph of Classic PoE Overdrive From: The PD may return the default 12.95 W (often referred to as 13 W) current-encoded class, or one of four other choices. To: The PD may return the default 13-W current-encoded class, or one of four other choices................................................................... 14 • Changed Table 8-1 - Notes for the Class 4 row................................................................................................16 Changes from Revision * (July 2009) to Revision A (September 2009) Page • Changed the ESDS statement............................................................................................................................1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 5 Product Information DEVICE DUTY CYCLE POE UVLO ON / HYST. DC-DC UVLO ON / HYST. TPS23753A 0 – 78% 35/4.5 9/3.5 6 Pin Configuration and Functions CTL 1 14 FRS VB 2 13 BLNK CS 3 12 APD VC 4 11 CLS GATE 5 10 DEN RTN 6 9 VDD VSS 7 8 VDD1 Figure 6-1. PW Package 14-Pin TSSOP Top View Table 6-1. Pin Functions PIN NO. 1 NAME CTL I/O DESCRIPTION I The control loop input to the PWM (pulse width modulator). Use VB as a pullup for CTL. 2 VB O 5-V bias rail for DC-DC control circuits. Apply a 0.1-μF ceramic capacitor to RTN. VB may be used to bias an external optocoupler for feedback. 3 CS I DC-DC converter switching MOSFET current-sense input. Connect CS to the high side of RCS. 4 VC I/O DC-DC converter bias voltage. The internal start-up current source and converter bias winding output power this pin. Connect a 0.22-μF minimum ceramic capacitor to RTN, and a larger capacitor to facilitate start-up. 5 GATE O Gate drive output for the DC-DC converter switching MOSFET. 6 RTN — RTN is the negative rail input to the DC-DC converter and output of the PoE hotswap. 7 VSS — Negative power rail derived from the PoE source. 8 VDD1 — Source of DC-DC converter start-up current. Connect to VDD for most applications. 9 VDD — Positive input power rail for PoE interface circuit. Derived from the PoE source. 10 DEN I/O Connect a 24.9-kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this pin to VSS during powered operation causes the internal hotswap MOSFET to turn off. 11 CLS O Connect a resistor from CLS to VSS to program the classification current. 12 APD I Pull APD above 1.5 V to disable the internal PD hotswap switch, forcing power to come from an external adapter. Connect to the adapter through a resistor divider. 13 BLNK I/O Connect to RTN to use the internally set blanking period or connect through a resistor to RTN to program the blanking period. 14 FRS I/O Connect a resistor from FRS to RTN to program the converter switching frequency. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 3 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings Voltage are with respect to VSS (unless otherwise noted)(1) per Figure 9-1 per Table 8-1 VI 100 VDD1 to RTN –0.3 100 CLS(3) –0.3 6.5 6.5 VB VC to RTN –0.3 19 GATE(3) to RTN –0.3 VC + 0.3 GATE Storage temperature VB (3)] –0.3 VB CTL, FRS(3), –0.3 Sourcing current Operating junction temperature BLNK(3), to RTN UNIT CS to RTN Average sourcing or sinking current TJ (2) (3) MAX –0.3 [APD, Input voltage Tstg (1) MIN VDD, VDD1, DEN, RTN(2) V Internally limited mA 25 mARMS –40 to Internally Limited –65 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. IRTN = 0 for VRTN > 80 V. Do not apply voltage to these pins. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) V(ESD) (1) (2) (3) Electrostatic discharge UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 IEC 61000-4-2 contact discharge(3) ±8000 IEC 61000-4-2 air-gap discharge(3) ±15000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the TPS23753AEVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure threshold. 7.3 Recommended Operating Conditions Voltage with respect to VSS (unless otherwise noted) MIN VI Input voltage, VDD, VDD1, RTN 0 NOM Input voltage, VC to RTN 0 18 Input voltage, APD, CTL to RTN 0 VB Input voltage, CS to RTN 0 VB sourcing current VB capacitance RBLNK 4 Operating junction temperature 0 2.5 0.1 Submit Document Feedback 350 mA 5 mA μF 350 25 –40 V 2 0.08 0 Synchronization pulse width input (when used) UNIT 57 RTN current (TJ ≤ 125°C) TJ MAX kΩ ns 125 °C Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 7.4 Thermal Information TPS23753A THERMAL METRIC(1) PW (TSSOP) UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 106.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.9 °C/W RθJB Junction-to-board thermal resistance 49.1 °C/W ψJT Junction-to-top characterization parameter 1.9 °C/W ψJB Junction-to-board characterization parameter 48.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics: Controller Section Only Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C [VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VC UVLO_1 UVLO_H Undervoltage lockout Operating current tST Start-up time, CVC = 22 μF Start-up current source - IVC VC rising 8.65 9 9.3 Hysteresis(1) 3.3 3.5 3.7 VC = 12 V, CTL = VB 0.4 0.58 0.85 V mA VDD1 = 10.2 V, VVC(0) = 0 V 50 85 175 VDD1 = 35 V, VVC(0) = 0 V 30 48 85 0.44 1.06 1.8 2.5 4.3 6 4.75 5.1 5.25 V 223 248 273 kHz 76% 78.5% 81% 2 2.2 2.4 V 1.7 V VDD1 = 10.2 V, VVC = 8.6 V VDD1 = 48 V, VVC = 0 V ms mA VB Voltage 6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA FRS Switching frequency CTL= VB, Measure GATE RFRS = 60.4 kΩ DMAX Duty cycle CTL= VB, Measure GATE VSYNC Synchronization Input threshold 0% duty cycle threshold VCTL ↓ until GATE stops 1.3 1.5 Soft-start period Interval from switching start to VCSMAX 400 800 70 100 145 35 52 75 RBLNK = 49.9 kΩ 41 52 63 CTL VZDC Input resistance μs kΩ BLNK In addition to t1 Blanking delay BLNK = RTN ns CS VCSMAX Maximum threshold voltage VCTL = VB, VCS ↑ until GATE duty cycle drops 0.5 0.55 0.6 V t1 Turnoff delay VCS = 0.65 V 25 41 60 ns VSLOPE Internal slope compensation voltage Peak voltage at maximum duty cycle, referred to CS 90 118 142 mV ISL_EX Peak slope compensation current VCTL = VB, ICS at maximum duty cycle (ac component) 30 42 54 μA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 5 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C [VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2 3 4.2 μA Bias current (sourcing) Gate high, DC component of CS current Source current VCTL = VB, VC = 12 V, GATE high, Pulsed measurement 0.3 0.46 0.6 A Sink current VCTL = VB, VC = 12 V, GATE low, Pulsed measurement 0.5 0.79 1.1 A VAPD↑ 1.42 1.5 1.58 Hysteresis(1) 0.28 0.3 0.32 135 145 155 GATE APD VAPDEN VAPDH Threshold voltage V THERMAL SHUTDOWN Turnoff temperature Hysteresis(2) (1) (2) °C 20 °C The hysteresis tolerance tracks the rising threshold for a given device. These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. 7.6 Electrical Characteristics: PoE and Control Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C [VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. [VDD = VDD1] or [VDD1 = RTN], VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX 62 64.3 66.5 UNIT DEN (DETECTION) (VDD = VDD1 = RTN = VSUPPLY POSITIVE) Measure ISUPPLY Detection current VDD = 1.6 V VDD = 10 V Detection bias current VPD_DIS Hotswap disable threshold Ilkg DEN leakage current 399 μA 406 413 5.2 12 4 5 V 0.1 5 μA 1.8 2.14 2.4 VDD = 10 V, DEN open, Measure ISUPPLY 3 VDEN = VDD = 57 V, Float VDD1 and RTN, Measure IDEN μA CLS (CLASSIFICATION) (VDD = VDD1 = RTN = VSUPPLY POSITIVE) 13 V ≤ VDD ≤ 21 V, Measure ISUPPLY ICLS Classification current VCL_ON VCL_HYS VCU_OFF Classification regulator lower threshold RCLS = 1270 Ω 1.8 2.14 2.4 RCLS = 243 Ω 9.9 10.6 11.3 RCLS = 137 Ω 17.6 18.6 19.4 RCLS = 90.9 Ω 26.5 27.9 29.3 RCLS = 63.4 Ω 38 39.9 42 Regulator turns on, VDD rising 10 11.7 13 Hysteresis(1) 1.9 2.05 2.2 Classification regulator upper threshold Regulator turns off, VDD rising 21 22 23 VCU_HYS Hysteresis(1) 0.5 0.77 1 Ilkg Leakage current VDD = 57 V, VCLS = 0 V, DEN = VSS, Measure ICLS 1 mA V V μA RTN (PASS DEVICE) (VDD1 = RTN) ON-resistance Ilkg 6 0.7 1.2 Ω Current limit VRTN = 1.5 V, VDD = 48 V, Pulsed Measurement 405 450 505 mA Inrush limit VRTN = 2 V, VDD: 0 V → 48 V, Pulsed Measurement 100 140 180 mA Foldback voltage threshold VDD rising 11 12.3 13.6 V Leakage current VDD = VRTN = 100 V, DEN = VSS 40 μA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C [VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. [VDD = VDD1] or [VDD1 = RTN], VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX 33.9 UNIT UVLO UVLO_R UVLO_H Undervoltage lockout threshold VDD rising Hysteresis (1) 35 36.1 4.4 4.55 4.7 135 155 V THERMAL SHUTDOWN Turnoff temperature Hysteresis(2) (1) (2) 145 20 °C °C The hysteresis tolerance tracks the rising threshold for a given device. These parameters are provided for reference only. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 7 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 7.7 Typical Characteristics 458 8 7 456 PoE - Current Limit - mA IVDD - Bias Current - mA 6 TJ = 125°C 5 4 3 TJ = 25°C 2 454 452 450 448 1 TJ = -40°C 0 0 2 6 4 VVDD-VSS - PoE Voltage - V 446 -40 10 8 VVC = 8.6 V CVC = 22 mF 140 TJ = -40°C 5 IVC - Source Current - mA VVDD1 = 10.2 V 120 100 80 VVDD1 = 19.2 V 60 TJ = 125°C 3 2 0 -20 0 20 40 60 80 TJ - Junction Temperature - °C 100 5 120 10 15 20 25 Gate Open VVC = 12 V 50 55 60 Gate Open TJ = 25°C 500 kHz 700 VC - Controller Bias Current - mA 800 250 kHz 600 100 kHz 500 400 50 kHz 300 200 VCTL = 0 V 1000 500 kHz 800 250 kHz 600 100 kHz 400 50 kHz 200 VCTL = 0 V 100 0 -20 0 20 40 60 80 TJ - Junction Temperature - °C 100 120 7 9 11 13 15 17 VC - Controller Bias Voltage - V Figure 7-5. Controller Bias Current vs Temperature 8 45 1200 1000 0 -40 30 35 40 VVDD1-RTN - V Figure 7-4. Converter Start-Up Source Current vs VVDD1 Figure 7-3. Converter Start Time vs Temperature 900 TJ = 25°C 4 1 VVDD1 = 35 V 40 20 -40 120 100 6 160 Converter Start Time - ms 20 40 60 80 TJ - Junction Temperature - °C Figure 7-2. PoE Current Limit vs Temperature Figure 7-1. Detection Bias Current vs Voltage IVC - Sinking - mA 0 -20 Figure 7-6. Controller Bias Current vs Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 7.7 Typical Characteristics (continued) 300 650 800 600 200 550 RFRS = 30.1 kW (500 kHz) 150 500 RFRS = 148.5 kW (100 kHz) 450 100 RFRS = 301 kW (50 kHz) Typical 500 400 300 200 100 350 -20 0 60 40 80 20 TJ - Junction Temperature - °C 100 0 0 120 40 50 -1 Figure 7-8. Switching Frequency vs Programmed Resistance 124 VSLOPE - Slope Compensation - mVPP RFRS = 301 kW (50 kHz) 78 RFRS = 148.5 kW (100 kHz) 77.5 RFRS = 60.4 kW (250 kHz) 77 RFRS = 30.1 kW (500 kHz) 76.5 -20 0 60 80 20 40 TJ - Junction Temperature - °C 100 122 120 118 116 114 -40 120 Blanking Period (RBLNK 115 kW) - ns 0 -40 Maximum Duty Cycle - % 600 400 50 ISLOPE - Slope Compensation - mAPP Ideal 700 Switching Frequency - kHz 250 Switching Frequency - kHz Switching Frequency - kHz RFRS = 60.4 kW (250 kHz) 0 20 40 60 80 TJ - Junction Temperature - °C 100 120 Figure 7-12. Blanking Period vs Temperature Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 9 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 450 18 400 14 350 10 300 6 250 2 200 -2 150 -6 100 -10 50 -14 0 0 50 100 150 200 250 RBLNK - kW 300 350 Difference from Computed - ns Blanking Period - ns 7.7 Typical Characteristics (continued) -18 400 Figure 7-13. Blanking Period vs RBLNK 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 8 Detailed Description 8.1 Overview The TPS23753A device has a PoE that contains all of the features needed to implement an IEEE802.3at Type 1 powered device (PD) such as detection, classification, and 140-mA inrush current mode DC-DC controller optimized specifically for isolated converters. The TPS23753A device integrates a low 0.7-Ω internal switch to allow for up to 405 mA of continuous current through the PD during normal operation. The TPS23753A device contains several protection features such as thermal shutdown, current limit foldback, and a robust 100-V internal switch. 8.2 Functional Block Diagram VC VDD1 Oscillator FRS CTL enb 800ms Soft Start 50kW CONV. OFF enb + 1 0.75V enb 40mA (pk) RTN CLRB Blank Switch Matrix 2.875kW CS GATE D Q CK + 50kW Control Converter Thermal Monitor + 0.55V VB Regulator Reference - RTN 1.5V & 1.2V APDb BLNK APD VDD 11.5V & 9. 5V Class Regulator AUXb CLS 2.53V 22V & 21.25V 12.5V & 1V V SS DEN 400ms Common Circuits and PoE Thermal Monitor S Q R 35V & 30.5V CONV. OFF H L 1 ILIMb + 0 EN VSS RTN 80mW AUXb 4.5V APDb Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Pin Description See Figure 9-1 for component reference designators (RCS for example ), and Electrical Characteristics: Controller Section Only for values denoted by reference (VCSMAX for example). Electrical Characteristic values take precedence over any numerical values used in the following sections. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 11 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 8.3.1.1 APD APD forces power to come from an external adapter connected from VDD1 to RTN by opening the hotswap switch. TI recommends using a resistor divider. The divider provides ESD protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the adapter can support the PD before the PoE current is cut off. Select the APD divider resistors per Equation 1 and Equation 2, where VADPTR-ON is the desired adapter voltage that enables the APD function as adapter voltage rises. RAPD1 = RAPD 2 x (VADPTR _ ON - VAPDEN ) VAPDEN VADPTR _ OFF = RAPD1 + RAPD 2 RAPD 2 (1) x (VAPDEN - VAPDH ) (2) The CLS output is disabled when a voltage above VAPDEN is applied to the APD pin. Place the APD pulldown resistor adjacent to the APD pin. APD must be tied to RTN when not used. 8.3.1.2 BLNK Blanking provides an interval between the gate drive going high and the current comparator on CS actively monitoring the input. This delay allows the normal turnon current transient (spike) to subside before the comparator is active, preventing undesired short duty cycles and premature current limiting. Connect BLNK to RTN to obtain the internally set blanking period. Connect a resistor from BLNK to RTN for a programmable blanking period. The relationship between the desired blanking period and the programming resistor is defined by Equation 3. RBLNK (k Ω ) = t BLNK (ns ) (3) Place the resistor adjacent to the BLNK pin when it is used. 8.3.1.3 CLS Connect a resistor from CLS to VSS to program the classification current per IEEE 802.3-at. The PD power ranges and corresponding resistor values are listed in Table 8-1. The power assigned must correspond to the maximum average power drawn by the PD during operation. The TPS23753A supports class 0 – 3 power levels. 8.3.1.4 CS The current-sense input for the DC-DC converter should be connected to the high side of the current-sense resistor of the switching MOSFET. The current-limit threshold, VCSMAX, defines the voltage on CS above which the GATE ON-time are terminated regardless of the voltage on CTL. The TPS23753A provides internal slope compensation to stabilize the current mode control loop. If the provided slope is not sufficient, the effective slope may be increased by addition of RS per Figure 8-8. Routing between the current-sense resistor and the CS pin must be short to minimize cross-talk from noisy traces such as the gate drive signal. 8.3.1.5 CTL CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC causes GATE to stop switching. Increasing VCTL above VZDC raises the switching MOSFET programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The AC gain from CTL to the PWM comparator is 0.5. Use VB as a pullup source for CTL. 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 8.3.1.6 DEN Connect a 24.9-kΩ resistor from DEN to VDD to provide the PoE detection signature. DEN goes to a high impedance state when not in the detection voltage range. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator to turn off. 8.3.1.7 FRS Connect a resistor from FRS to RTN to program the converter switching frequency. Select the resistor using Equation 4. RFRS ( k Ω ) = 15000 fSW ( kHz ) (4) The converter may be synchronized to a frequency above its maximum free-running frequency by applying short AC-coupled pulses into the FRS pin. More information is provided in Application and Implementation. The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. 8.3.1.8 GATE Gate drive output for the DC-DC converter switching MOSFET. 8.3.1.9 RTN RTN is internally connected to the drain of the PoE hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (ground plane) for the DC-DC controller and converter primary to maintain signal integrity. 8.3.1.10 VB VB is an internal 5-V control rail that must be bypassed by a 0.1-μF capacitor to RTN. VB should be used to bias the feedback optocoupler. 8.3.1.11 VC VC is the bias supply for the DC-DC controller. The MOSFET gate driver runs directly from VC. VB is regulated down from VC, and is the bias voltage for the rest of the converter control. A start-up current source from VDD1 to VC is controlled by a comparator with hysteresis to implement a bootstrap start-up of the converter. VC must be connected to a bias source, such as a converter auxiliary output, during normal operation. A minimum 0.22-μF capacitor, located adjacent to the VC pin, must be connected from VC to RTN to bypass the gate driver. A larger total capacitance is required for start-up. 8.3.1.12 VDD Positive input power rail for PoE control that is derived from the PoE. VDD should be bypassed to VSS with a 0.1-μF (X7R,10%) capacitor as required by the standard. A transient suppressor (Zener) diode, must be connected from VDD to VSS to protect against overvoltage transients. 8.3.1.13 VDD1 Source of DC-DC converter start-up current. Connect to VDD for most applications. VDD1 may be isolated by a diode from VDD to support PoE-priority operation. 8.3.1.14 VSS VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch. A local VSS reference plane should be used to connect the input components and the VSS pin. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 13 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 8.4 Device Functional Modes The following text is intended as an aid in understanding the operation of the TPS23753A, but it is not a substitute for the actual IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a type 1 device, and devices with high power or enhanced classification is referred to as type 2 devices. The TPS23753A is intended to power type 1 devices (up to 13 W), and is fully compliant to IEEE 802.3at for hardware classes 0 - 3. Standards change and must always be referenced when making design decisions. 2.7 10.1 14.5 3/06/08 20.5 30 Maximum Input Voltage Must Turn On byVoltage Rising Lower Limit Proper Operation Must Turn Off by Voltage Falling Classification Upper Limit Shutdown Classify Detect 0 Classification Lower Limit Detection Upper Limit Detection Lower Limit The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable, and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as (hardware) classification. Only Type 2 PSEs are required to do hardware classification. The PD may return the default 13-W current-encoded class, or one of four other choices. The PSE may then power the PD if it has adequate capacity. Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 8-1 shows the operational states as a function of PD input voltage. Normal Operation 36 57 42 PI Voltage (V) Figure 8-1. IEEE 802.3-2005 (Type 1) Operational States The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops in the cable and operating margin. The IEEE 802.3at standard uses a cable resistance of 20 Ω for type 1 devices to derive the voltage limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power of 15.4 W at the PSE, only 13 W is available at the PI due to the worst-case power loss in the cable. The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between the two spare pairs (4–5 and 7–8). The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23753A specifications. The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second interval. A Type 1 PSE compliant to IEEE 802.3at is required to limit current to between 400 mA and 450 mA during powered operation, and it must disconnect the PD if it draws this current for more than 75 ms. Class 0 and 3 PDs may draw up to 400-mA peak currents for up to 50 ms. The PSE may set lower output current limits based on the declared power requirements of the PD. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 8.4.1 Threshold Voltages Operational State The TPS23753A has a number of internal comparators with hysteresis for stable switching between the various states as shown in Figure 8-1. Figure 8-2 relates the parameters in Electrical Characteristics: Controller Section Only and Electrical Characterisics: PoE and Control to the PoE states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are all high impedance. PD Powered Idle Classification VVDD-VSS Detection VCL_HYS 1.4V VCL_ON VUVLO_H VCU_HYS VCU_OFF VUVLO_R Note: Variable names refer to Electrical Characteristic Table parameters Figure 8-2. Threshold Voltages 8.4.2 PoE Start-Up Sequence The waveforms of Figure 8-3 demonstrate detection, classification, and start-up from a Type 1 PSE. The key waveforms shown are VVDD-VSS, VRTN-VSS, and IPI. IEEE 802.3at requires a minimum of two detection levels; however, four levels are shown in this example. Four levels guard against misdetection of a device when plugged in during the detection sequence. Figure 8-3. PoE Start-Up Sequence 8.4.3 Detection The TPS23753A is in detection mode whenever VVDD-V SS is below the lower classification threshold. When the input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 15 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and 26.25 kΩ at the PI. The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the parallel combination of RDEN and the TPS23753A bias loading. The incremental resistance of the input diode bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partially cancelled by the effective resistance of the TPS23753A during detection. 8.4.4 Hardware Classification Hardware classification allows a PSE to determine the power requirements of a PD before starting, and helps with power management once power is applied. The maximum power entries in Table 8-1 determine the class the PD must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than its stated Class power. The standard permits the PD to draw limited current peaks; however, the average power requirement always applies. Voltage from 14.5 V to 20.5 V is applied to the PD for up to 75 ms during hardware classification. A fixed output voltage is sourced by the CLS pin, causing a fixed current to be drawn from VDD through RCLS. The total current drawn from the PSE during classification is the sum of bias and RCLS currents. PD current is measured and decoded by the PSE to determine which of the five available classes is advertised (see Table 8-1). The TPS23753A disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off during PD thermal limit or when APD or DEN are active. The CLS output is inherently current-limited, but should not be shorted to VSS for long periods of time. Table 8-1. Class Resistor Selection CLASS CLASS CURRENT REQUIREMENT POWER AT PD PI RESISTOR (Ω) MINIMUM (W) MAXIMUM (W) 0 0.44 12.95 0 4 1270 1 0.44 3.84 9 12 243 2 3.84 6.49 17 20 137 3 6.49 12.95 26 30 90.9 4 12.95 25.5 36 44 63.4 NOTES MINIMUM (mA) MAXIMUM (mA) Only permitted for type 2 devices 8.4.5 Maintain Power Signature (MPS) The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (at a duty cycle of at least 75 ms on every 225 ms) and an AC impedance lower than 26.25 kΩ in parallel with 0.05 μF. The AC impedance is usually accomplished by the minimum CIN requirement of 5 μF. When APD or DEN are used to force the hotswap switch off, the DC MPS is not met. A PSE that monitors the DC MPS will remove power from the PD when this occurs. A PSE that monitors only the AC MPS may remove power from the PD. 8.4.6 TPS23753A Operation 8.4.6.1 Start-Up and Converter Operation The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges CIN, CVC, and CVB while the PD is unpowered. Thus VRTN-VDD will be a small voltage just after full voltage is applied to the PD, as seen in Figure 8-3. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VDD rises above the UVLO turnon threshold (VUVLO-R, approximately 35 V) with RTN high, the TPS23753A enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-4 for an example. Converter switching is disabled while CIN charges and VRTN falls from VDD to nearly VSS; however, the converter start-up circuit is allowed to charge CVC. Once the inrush current falls about 10% below the inrush 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is permitted. Converter switching is allowed if the PD is not in inrush and the VC UVLO circuit permits it. Continuing the startup sequence shown in Figure 8-4, VVC rises as the start-up current source charges CVC and M1 switching is inhibited by the status of the VC UVLO. The VB regulator powers the internal converter circuits as VVC rises. Start-up current is turned off, converter switching is enabled, and a soft-start cycle starts when VVC exceeds UVLO1 (approximately 9 V). VVC falls as it powers both the internal circuits and the switching MOSFET gate. If the converter control-bias output rises to support VVC before it falls to UVLO1 – UVLO1H (approximately 5.5 V), a successful start-up occurs. Figure 8-4 shows a small droop in VVC while the output voltage rises smoothly and a successful start-up occurs. 10 100mA/Div INRUSH 8 Exaggerated primarysecondary softstart handoff IPI 6 10V/DIV 7 VC-RTN 5 4 VOUT Turn ON 2V/DIV 3 -0.5 50V/DIV 2 1 0 -0.6 VDD-RTN -0.7 t - Time 10 - ms/DIV Figure 8-4. Power Up and Start If VVDD-VSS drops below the lower PoE UVLO (UVLOR – UVLOH, approximately 30.5 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if VVC falls below the converter UVLO (UVLO1 – UVLOH, approximately 5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by VCTL (VCTL < VZDC, approximately 1.5 V), or the converter is in thermal shutdown. 8.4.6.2 PD Self-Protection The PD section has the following self-protection functions. • • • Hotswap switch current limit Hotswap switch foldback Hotswap thermal protection The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The PSE output cannot be relied on to protect the PD MOSFET against transient conditions, requiring the PD to provide fault protection. High stress conditions include converter output shorts, shorts from VDD1 to RTN, or transients on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as a result. If VRTN rises above approximately 12 V for longer than approximately 400 μs, the current limit reverts to the inrush limit, and turns the converter off. The 400-μs deglitch feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 8-5 shows an example of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a relatively low current, recovers to 420-mA, full-current limit, and charges the input capacitor while the converter continues to run. The MOSFET did not go into foldback because VRTN-VSS was below 12 V after the 400-μs deglitch. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 17 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 Figure 8-5. Response to PSE Step Voltage The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown (OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD restarts in inrush current limit when exiting from a PD overtemperature event. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature allows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous converter topologies that can deliver power in both directions. The hotswap switch is forced off under the following conditions: • • • • VAPD above VAPDEN (approximately 1.5 V) VDE N ≤ VPD_DIS when VVDD-VSS is in the operational range PD over temperature VVDD-VSS < PoE UVLO (approximately 30.5 V) 8.4.6.3 Converter Controller Features The TPS23753A DC-DC controller implements a typical current-mode control as shown in Figure 8-6. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start, and gate driver. In addition, an internal current-compensation ramp generator, frequency synchronization logic, thermal shutdown, and start-up current source with control are provided. The TPS23753A is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM and converter. There is an offset of VZDC (approximately 1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL below VZDC stops converter switching, while voltages above (VZDC + 2 × VCSMAX) does not increase the requested peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range. The internal start-up current source and control logic implement a bootstrap-type start-up. The start-up current source charges CVC from VDD1 when the converter is disabled (either by the PD control or the VC control), while operational power must come from a converter (bias winding) output. Loading on VC and VB must be minimal while CVC charges, otherwise the converter may never start. The optocoupler does not load VB when the converter is off. The converter shuts off when VC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A restart initiates as described in Start-Up and Converter Operation if the converter turns off and there 18 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 is sufficient VDD1 voltage. This type of operation is sometimes referred to as hiccup mode, which provides robust output short protection by providing time-average heating reduction of the output rectifier. Take care in the design of the transformer and VC bias circuit to obtain hiccup overload protection. Leading-edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected tracking with output voltage. RVC (Figure 9-1) is often required slow the peak charging. Good transformer bias-to-outputwinding coupling results in reduced overshoot and better voltage tracking. The start-up current source transitions to a resistance as (VDD1 – VC) falls below 7 V, but starts the converter from 12-V adapters within tST (VDD1 ≥ 10.2, tST approximately 85 ms). The converter starts from lower voltages, limited by the case when charge current equals the device bias current at voltage below the upper VC UVLO. The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual power loss of external resistors. The start-up current source does not charge above the maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to charge higher. The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 8-8 to increase slope compensation. This makes it easier to design the current limit to a fixed value. The TPS23753A blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This avoids current-sense waveform distortion, which tends to get worse at light output loads. While the internally set blanking period is relatively precise, almost all converters require their own blanking period. The TPS23753A provides the BLNK pin to allow this programming. There may be some situations or designers that prefer an R-C approach. The TPS23753A provides a pulldown on CS during the GATE OFF-time to improve sensing when an R-C filter must be used. The CS input signal must be protected from nearby noisy signals like GATE drive and the MOSFET drain. Converters require a soft start on the voltage error amplifier to prevent output overshoot on start-up. Figure 8-6 shows a common implementation of a secondary-side soft start that works with the typical TL431 error amplifier shown in Figure 9-1. This secondary-side error amplifier does not become active until there is sufficient voltage on the secondary. The TPS23753A provides a primary-side soft start, which persists long enough (approximately 800 μs) for secondary side voltage-loop soft start to take over; however, the actual start-up is typically shorter than this. The primary-side current-loop soft-start controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. The lower of the CTL and soft-start ramps controls the PWM comparator. Figure 8-4 shows an exaggerated handoff between the primary and secondary-side soft start that is most easily seen in the IPI waveform. The output voltage rises in a smooth monotonic fashion with no overshoot. The soft-start handoff in this example could have been optimized by decreasing the secondary-side soft-start period. From Regulated Output Voltage ROB RSS RFBU CIZ DSS CSS RFBL TLV 431 Copyright © 2016, Texas Instruments Incorporated Figure 8-6. Example of Soft-Start Circuit Added to Error Amplifier Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 19 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 The DC-DC controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver, bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, resets the soft-start generator, and forces the VC control into an undervoltage state. 8.4.7 Special Switching MOSFET Considerations Take special care in selecting the converter switching MOSFET. The TPS23753A converter section has minimum VC operating voltage of approximately 5.5 V, which is reflected in the applied gate voltage. This occurs during an output overload, or towards the end of a (failed) bootstrap start-up. The MOSFET must be able to carry the anticipated peak fault current at this gate voltage. 8.4.8 Thermal Considerations Sources of nearby local PCB heating must be considered during the thermal design. Typical calculations assume that the TPS23753A is the only heat source contributing to the PCB temperature rise. It is possible for a normally operating TPS23753A device to experience an OTSD event if it is excessively heated by a nearby device. 8.4.9 FRS and Synchronization The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the TPS23753A converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls the current-compensation ramp circuit, making the ramp height independent of frequency. RFRS must be selected per Equation 5. RFRS ( k Ω ) = 15000 fSW ( kHz ) (5) The TPS23753A may be synchronized to an external clock to eliminate beat frequencies from a sampled system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by applying a short pulse ( > 25 ns) of magnitude VSYNC to FRS as shown in Figure 8-7. RFRS must be chosen so that the maximum free-running frequency is just below the desired synchronization frequency. The synchronization pulse terminates the potential ON-time period, and the OFF-time period does not begin until the pulse terminates. A short pulse is preferred to avoid reducing the potential ON-time. TSYNC RFRS FRS 47pF TSYNC 1000pF VSYNC RTN 47pF Synchronization Pulse RFRS FRS RT Synchronization Pulse RTN Figure 8-7 shows examples of nonisolated and transformer-coupled synchronization circuits RT reduces noise susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because it is high impedance. 1:1 VSYNC Copyright © 2016, Texas Instruments Incorporated Figure 8-7. Synchronization 8.4.10 Blanking – RBLNK The TPS23753A BLNK feature permits programming of the blanking period with specified tolerance. Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every device between the gate-driver and output capacitors. There is a critical range of blanking period that is bounded on the short side by erratic operation, and on the long side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by the ability of the output rectifier to withstand the currents experienced during a converter output short. 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 The TPS23753A provides a choice between internal fixed and programmable blanking periods. The blanking period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator delays. The default period (see Electrical Characteristics: Controller Section Only and Electrical Characterisics: PoE and Control) is selected by connecting BLNK to RTN, and the programmable period is set with a resistor from BLNK to RTN using Equation 6. RBLNK (k Ω ) = t BLNK (ns ) (6) For example, a 100-ns period is programmed by a 100-kΩ resistor. For a brand-new design, TI recommends designing an initial blanking period of 125 ns. This period must be turned when the converter is operational. 8.4.11 Current Slope Compensation Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer) current for stability at duty cycles near and over 50%. The TPS23753A has a maximum duty cycle limit of 78%, permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a narrower, 36-V to 57-V range. The TPS23753A provides a fixed internal compensation ramp that suffices for most applications. RS (see Figure 8-8) may be used if the internally provided slope compensation is not enough. It works with ramp current (IPK = ISL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on. The IPK specification does not include the approximately 3-μA fixed current that flows out of the CS pin. Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp voltage / switching period); however, Electrical Characteristics: Controller Section Only specifies the slope peak (VSLOPE) based on the maximum duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full period, compute RS per Equation 7 where VSLOPE, DMAX, and ISL-EX are from Electrical Characteristics: Controller Section Only with voltages in mV, current in μA, and the duty cycle is unitless (for example, DMAX = 0.78).  VSLOPE (mV )  VSLOPE _ D (mV ) −  DMAX   ⋅ 1000 RS (Ω) = ISL _ EX ( µA) (7) RTN GATE 5/09/08 CS RS CS RCS Copyright © 2016, Texas Instruments Incorporated Figure 8-8. Additional Slope Compensation CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to appear at the CS pin. The TPS23753A has an internal pulldown on CS ( approximately 400 Ω maximum) while the MOSFET is OFF to reduce cycle-to-cycle carry-over voltage on CS. 8.4.12 Adapter ORing Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular installation. While most applications only require that the PD operate when both sources are present, the Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 21 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 TPS23753A supports forced operation from either of the power sources. Figure 8-9 illustrates three options for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies power to the TPS23753A PoE input, option 2 applies power between the TPS23753A PoE section and the power circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and disadvantages. A detailed discussion of the TPS23753A and ORing solutions is covered in application note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306). VSS VDD1 VDD DEN CLS Low Voltage Output Power Circuit TPS23753 RCLS 58V From Spare Pairs or Transformers 0.1uF RDEN From Ethernet Transformers Optional for PoE Priority 5/8/08 RTN Adapter Option 1 Adapter Option 2 Adapter Option 3 Copyright © 2016, Texas Instruments Incorporated Figure 8-9. ORing Configurations Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity. Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the combinations. However, the TPS23753A offers several built-in features that simplify some combinations. Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to assure which source was active. A second example is combining a 12-V adapter with PoE using option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example is use of a 12-V adapter with ORing option 1. The PD hotswap would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power from the PD. If adapter power is then lost, the PD stops operating until the PSE detects and powers the PD. The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC power fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD momentarily loses power until the PSE completes its start-up cycle. The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET, and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven from the secondary side of the converter. The least popular technique is PoE priority. It is implemented by placing a diode between the PD supply voltage, VDD, and the DC-DC controller bias voltage, VDD1. The diode prevents reverse biasing of the PoE input diode bridges when option 2 adapter ORing is used. The PSE may then detect, classify, and provide power to the PD 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 while a live adapter is connected. As long as the PoE voltage is greater than the adapter voltage, the PSE powers the load. The APD function is not used in this technique. The IEEE standards require that the PI conductors be electrically isolated from ground and all other system potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter. Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in option 3. 8.4.13 Protection A TVS across the rectified PoE voltage per Figure 9-1 must be used. For general indoor applications, TI recommends an SMAJ58A or a part with equal to or better performance. If an adapter is connected from VDD1 to RTN, as in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the internal PD capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the Absolute Maximum Ratings. Configurations that use DVDD as in Figure 8-10 may require additional protection against ESD transients that would turn DVDD off and force all the voltage to appear across the internal hotswap MOSFET. CVDD and DRTN per Figure 8-10 provide this additional protection. From Ethernet Transformers CVDD 0.01mF CIN VDD1 VDD RDEN VSS RTN RCLS DEN CLS 58V DRTN From Spare Pairs or Transformers C1 0.1mF D1 58V DVDD Copyright © 2016, Texas Instruments Incorporated Figure 8-10. Additional Protection Against ESD Outdoor applications require more extensive protection to lightning standards. 8.4.14 Frequency Dithering for Conducted Emissions Control The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions. Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 have requirements for noise injected onto the Ethernet cable based on compatibility with data transmission. Occasionally, a technique referred to as frequency dithering is used to provide additional EMI measurement reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 23 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 bandwidth, thus lowering peak measurements. The circuit of Figure 8-11 modulates the switching frequency by feeding a small AC signal into the FRS pin. These values may be adapted to suit individual needs. 10kΩ 49.9kΩ VB + - 6.04kΩ TL331IDBV 4.99kΩ 0.01µF 10kΩ 301kΩ 1uF To FRS RTN Figure 8-11. Frequency Dithering 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The TPS23753A supports power supply topologies that require a single PWM gate drive with current-mode control. Figure 9-1 provides an example of a simple diode rectified flyback converter. BR1 T1 VDD M1 VB R CTL R OB C CTL RCS * VB GATE CS CTL RBLNK Adapter RFRS R APD1 RAPD2 DA V OUT R VC CVB APD FRS * C OUT D VC CVC RCLS V SS DS VC TPS23753 CLS BR2 RTN BLNK DEN VDD1 C IN D1 58V RDEN C1 0.1mF From Spare Pairs or Transformers From Ethernet Transformers 9.2 Typical Application C IZ C IO TLV431 R FBU R FBL * Adapter interface and R BLNK are Optional Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Basic TPS23753A Implementation 9.2.1 Design Requirements Selecting a converter topology along with a design procedure is beyond the scope of this applications section. For more specific converter design examples refer to the following application notes: • Advanced Adapter ORing Solutions using the TPS23753, SLVA306 • Implementing a Buck Converter with the TPS23753A, SLVA440 • Using the TPS23753A with an External Error Amplifier, SLVA433 9.2.2 Detailed Design Procedure A detailed design procedure for PDs using the TPS23753A is covered in Designing with the TPS23753 Powered Device and Power Supply Controller, SLVA305. Several designs with data are provided in the evaluation module documentation SLVU314 and SLVU315. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 25 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 9.2.3 Application Curves 10 100mA/Div INRUSH 8 Exaggerated primarysecondary softstart handoff IPI 6 10V/DIV 7 VC-RTN 5 4 VOUT Turn ON 2V/DIV 3 -0.5 50V/DIV 2 1 -0.6 VDD-RTN 0 -0.7 t - Time 10 - ms/DIV Figure 9-3. Power Up and Start Figure 9-2. PoE Start-Up Sequence 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 10 Power Supply Recommendations The TPS23753A converter must be designed such that the input voltage of the converter is capable of operating within the IEEE802.3at-recommended input voltage as shown in Figure 8-1 and the minimum operating voltage of the adapter if applicable. 11 Layout 11.1 Layout Guidelines Printed-circuit board layout recommendations are provided in the evaluation module (EVM) documentation available for these devices. 11.2 Layout Example Figure 11-1. Top-Side Placement Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A 27 TPS23753A www.ti.com SLVS933D – JULY 2009 – REVISED DECEMBER 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • IEEE Standard for Information Technology … Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, IEEE Computer Society, IEEE 802.3™at (Clause 33) • Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement, International Electrotechnical Commission, CISPR 22 Edition 5.2, 2006-03 • Designing with the TPS23753 Powered Device and Power Supply Controller, Eric Wright, TI, SLVA305 • Advanced Adapter ORing Solutions using the TPS23753, Eric Wright, TI, SLVA306 • Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V. Comiskey, TI, SLUA469 • TPS23753AEVM-004: Evaluation Module for TPS23753A, SLVU314 • TPS23753AEVM-0041 Evaluation Module for TPS23753A, SLVU315 • Implementing a Buck Converter with the TPS23753A, SLVA440 • Using the TPS23753A with an External Error Amplifier, SLVA433 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.4 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS23753A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS23753APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T23753A TPS23753APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T23753A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of