TPS23753
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SLVS853C – JUNE 2008 – REVISED JANUARY 2010
IEEE 802.3 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER
Check for Samples: TPS23753
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Optimized for Isolated Converters
Complete PoE Interface
Adapter ORing Support
12 V Adapter Support
Programmable Frequency with Synch.
Robust 100 V, 0.7 Ω Hotswap MOSFET
Small TSSOP 14 Package
15 kV / 8 kV System Level ESD Capable
–40°C to 125°C Junction Temperature Range
Design Procedure Application Note - SLVA305
Adapter ORing Application Note - SLVA306
The TPS23753 is a combined Power over Ethernet
(PoE) powered device (PD) interface and
current-mode dc/dc controller optimized specifically
for
isolated
converter
designs.
The
PoE
implementation supports the IEEE 802.3at standard
as a 13 W, type 1 PD. The requirements for an IEEE
802.3at type 1 device are a superset of IEEE
802.3-2008 (originally 802.3af) requirements.
The TPS23753 supports a number of input-voltage
ORing options including highest voltage, external
adapter preference, and PoE preference.
The PoE interface features an external detection
signature pin that can also be used to disable the
internal hotswap MOSFET. This allows the PoE
function to be turned off. Classification can be
programmed to any of the defined types with a single
resistor.
APPLICATIONS
•
•
•
•
IEEE 802.3at Compliant Powered Devices
VoIP Telephones
Access Points
Security Cameras
The dc/dc controller features a bootstrap startup
mechanism with an internal, switched current source.
This provides the advantages of cycling overload fault
protection without the constant power loss of a pull up
resistor.
BR1
T1
VDD1
M1
VB
GATE
CS
CTL
*
VB
R CTL
RCS
Adapter
RFRS
R APD1
RAPD2
DA
V OUT
R VC
CVB
APD
FRS
*
C OUT
D VC
CVC
V SS
TPS23753
RCLS
BR2
DS
VC
RBLNK
CLS
RTN
BLNK
DEN
VDD
C IN
D1
58V RDEN
C1
0.1µF
From Spare
Pairs or
Transformers
From Ethernet
Transformers
The programmable oscillator may be synchronized to
a higher-frequency external timing reference.
R OB
C CTL
C IZ
C IO TLV431
R FBU
R FBL
* Adapter interface and R BLNK are Optional
Figure 1. Basic TPS23753 Implementation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
TPS23753
SLVS853C – JUNE 2008 – REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION (1)
(1)
DEVICE
DUTY CYCLE
PoE UVLO ON / HYST.
PACKAGE
MARKING
TPS23753
0 – 80%
35/4.5
PW (TSSOP-14)
TP23753
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Voltages are with respect to VSS (unless otherwise noted)
VI
Input voltage range
VALUE
UNIT
VDD, VDD1, DEN, RTN (2)
–0.3 to 100
V
VDD1 to RTN
–0.3 to 100
V
CLS (3)
–0.3 to 6.5
V
(3)
(3)
[APD, BLNK , CTL, FRS , VB
(3)
–0.3 to 6.5
V
CS to RTN
] to RTN
–0.3 to VB
V
VC to RTN
–0.3 to 19
V
GATE to RTN
–0.3 to VC + 0.3
V
Sourcing current
VB
Internally limited
mA
Average sourcing or sinking current
GATE
25
mARMS
HBM
2
kV
CDM
500
V
8/15
kV
–40 to Internally
Limited
°C
ESD rating
ESD – system level (contact/air) (4)
TJ
(1)
(2)
(3)
(4)
Operating junction temperature range
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
IRTN = 0 for VRTN > 80V.
Do not apply voltage to these pins.
Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the
TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure
threshold.
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
Ψ JT
(°C/W) (1)
θJA
(°C/W) (2)
θJA
(°C/W) (1)
PW (TSSOP-14)
0.97
173.6
99.3
JEDEC method with high-k board (4 layers, 2 signal and 2 planes). TJ = TTOP + (Ψ
JEDEC method with low-k board (2 signal layers).
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JT
x PJ). Use Ψ
JT
to validate TJ from measurements.
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SLVS853C – JUNE 2008 – REVISED JANUARY 2010
RECOMMENDED OPERATING CONDITIONS
Voltage with respect to VSS (unless otherwise noted)
MIN
VI
NOM
MAX
0
57
V
Input voltage range, VDD, VDD1 to RTN
0
57
V
Input voltage range, VC to RTN
0
18
V
Input voltage range, APD, CTL to RTN
0
VB
V
Input voltage range, CS to RTN
0
2
RTN current (TJ ≤ 125°C)
VB sourcing current
VB capacitance
RBLNK
Synchronization pulse width input (when used)
TJ
UNIT
Input voltage range, VDD, VDD1, RTN
Operating junction temperature range
V
350
mA
mA
0
2.5
5
0.08
0.1
2.2
μF
0
350
kΩ
25
150
ns
–40
125
°C
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF,
RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C
Controller Section Only
[VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
8.65
9
9.3
3.3
3.5
3.7
UNIT
VC
UVLO1
UVLOH
Undervoltage lockout
Operating current
Startup time, CVC = 22 μF
tST
Startup current source - IVC
VC rising
Hysteresis (1)
VC = 12 V, CTL = VB
V
0.40
0.58
0.85
VDD1 = 10.2 V, VC(0) = 0 V
50
85
175
VDD1 = 35 V, VC(0) = 0 V
30
48
85
0.44
1.06
1.80
2.5
4.3
6.0
4.75
5.10
5.25
V
223
248
273
kHz
VDD1 = 10.2 V, VVC = 8.6 V
VDD1 = 48 V, VVC = 0 V
mA
ms
mA
VB
Voltage
6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA
FRS
Switching frequency
CTL= VB, Measure GATE
RFRS = 60.4 kΩ
DMAX
Duty cycle
CTL= VB, Measure GATE
76
78.5
81
%
VSYNC
Synchronization
Input threshold
2.0
2.2
2.4
V
0% duty cycle threshold
VCTL ↓ until GATE stops
1.3
1.5
1.7
Softstart period
Interval from switching start to VCSMAX
400
800
70
100
145
kΩ
BLNK = RTN
35
52
75
ns
RBLNK = 49.9 kΩ
41
52
63
CTL
VZDC
Input resistance
V
μs
BLNK
In addition to t1
Blanking delay
(1)
The hysteresis tolerance tracks the rising threshold for a given device.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 μF,
RDEN = 24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C
Controller Section Only
[VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS
VCSMAX
Maximum threshold voltage
VCTL = VB, VCS ↑ until GATE duty cycle drops
0.50
0.55
0.60
V
t1
Turn off delay
VCS = 0.65 V
25
41
60
ns
VSLOPE
Internal slope compensation voltage
Peak voltage at maximum duty cycle, referred to CS
90
118
142
mV
ISL_EX
Peak slope compensation current
VCTL = VB, ICS at maximum duty cycle (ac component)
30
42
54
μA
Bias current (sourcing)
Gate high, dc component of CS current
2
3
4.2
μA
Source current
VCTL = VB, VC = 12 V, GATE high, Pulsed measurement
0.30
0.46
0.60
A
Sink current
VCTL = VB, VC = 12 V, GATE low, Pulsed measurement
0.50
0.79
1.1
A
VAPD↑
1.42
1.5
1.58
Hysteresis (2)
0.28
0.3
0.32
135
145
155
GATE
APD
VAPDEN
VAPDH
Threshold voltage
V
THERMAL SHUTDOWN
Turn off temperature
Hysteresis (3)
(2)
(3)
°C
20
°C
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
ELECTRICAL CHARACTERISTICS
PoE and Control
[VDD = VDD1] or [VDD1] = RTN, VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 1.6 V
62
64.3
66.5
μA
VDD = 10 V
399
406
413
5.2
12
4
5
V
0.1
5
μA
DEN (DETECTION)
(VDD = VDD1 = RTN = VSUPPLY positive)
Measure ISUPPLY
Detection current
Detection bias current
VPD_DIS
Hotswap disable threshold
Ilkg
DEN leakage current
VDD = 10 V, DEN open, Measure ISUPPLY
3
VDEN = VDD = 57 V, Float VDD1 and RTN, Measure IDEN
CLS (CLASSIFICATION)
μA
(VDD = VDD1 = RTN = VSUPPLY positive)
13 V ≤ VDD ≤ 21 V, Measure ISUPPLY
ICLS
Classification current
RCLS = 1270 Ω
1.8
2.14
2.4
RCLS = 243 Ω
9.9
10.6
11.3
RCLS = 137 Ω
17.6
18.6
19.4
RCLS = 90.9 Ω
26.5
27.9
29.3
42
RCLS = 63.4 Ω
38
39.9
Classification regulator lower
threshold
Regulator turns on, VDD rising
10
11.7
13
Hysteresis (1)
1.9
2.05
2.2
Classification regulator upper
threshold
Regulator turns off, VDD rising
21
22
23
VCU_HYS
Hysteresis (1)
0.5
0.77
1
Ilkg
Leakage current
VDD = 57 V, VCLS = 0 V, DEN = VSS, Measure ICLS
VCL_ON
VCL_HYS
VCU_OFF
(1)
4
1
mA
V
V
μA
The hysteresis tolerance tracks the rising threshold for a given device.
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SLVS853C – JUNE 2008 – REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
PoE and Control
[VDD = VDD1] or [VDD1] = RTN, VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C.
PARAMETER
TEST CONDITIONS
RTN (PASS DEVICE)
MIN
TYP
0.7
1.2
Ω
450
505
mA
mA
On resistance
Ilkg
MAX
UNIT
(VDD1 = RTN)
Current limit
VRTN = 1.5 V, VDD = 48 V, Pulsed Measurement
405
Inrush limit
VRTN = 2 V, VDD: 0 V → 48 V, Pulsed Measurement
100
140
180
Foldback voltage threshold
VDD rising
11
12.3
13.6
V
Leakage current
VDD = VRTN = 100 V, DEN = VSS
40
μA
UVLO
UVLO_R
UVLO_H
Undervoltage lockout threshold
VDD rising
Hysteresis
(2)
33.9
35
36.1
4.40
4.55
4.70
135
145
155
V
THERMAL SHUTDOWN
Turn off temperature
Hysteresis (3)
(2)
(3)
20
°C
°C
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
DEVICE INFORMATION
TOP VIEW
CTL
VB
CS
VC
GATE
RTN
V SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FRS
BLNK
APD
CLS
DEN
V DD
V DD1
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NO.
NAME
1
CTL
I
The control loop input to the PWM (pulse width modulator). Use VB as a pull up for CTL.
2
VB
O
5 V bias rail for dc/dc control circuits. Apply a 0.1 μF to RTN. VB may be used to bias an external optocoupler for
feedback.
3
CS
I
Dc/dc converter switching MOSFET current sense input. Connect CS to the high side of the RTN-referenced
current sense resistor.
4
VC
I/O
Dc/dc converter bias voltage. The internal startup current source and converter bias winding output power this pin.
Connect a 0.22 μF minimum ceramic capacitor to RTN, and a larger capacitor to facilitate startup.
5
GATE
O
Gate drive output for the dc/dc converter switching MOSFET.
6
RTN
RTN is the negative rail input to the dc/dc converter and output of the PoE hotswap.
7
VSS
Negative power rail derived from the PoE source.
8
VDD1
Source of dc/dc converter startup current. Connect to VDD for most applications.
9
VDD
Positive input power rail for PoE interface circuit. Derived from the PoE source.
10
DEN
I/O
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this pin to VSS during
powered operation causes the internal hotswap MOSFET to turn off.
11
CLS
O
Connect a resistor from CLS to VSS to program the classification current per Table 2.
12
APD
I
Pull APD above 1.5 V to disable the internal PD hotswap switch, forcing power to come from an external adapter.
Connect to the adapter through a resistor divider.
13
BLNK
I/O
Connect to RTN to utilize the internally set blanking period or connect through a resistor to RTN to program the
blanking period.
14
FRS
I/O
Connect a resistor from FRS to RTN to program the converter switching frequency.
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VC
VDD1
Oscillator
FRS
CTL
enb
800ms
Soft Start
50kW
CONV.
OFF
enb
+
1
0.75V enb
40mA
(pk)
2.875kW
GATE
D
Q
CK
+
50kW
Control
CLRB
RTN
Blank
Switch
Matrix
CS
Converter
Thermal
Monitor
+
Regulator
VB
Reference
-
0.55V
RTN
1.5V
& 1.2V
APDb
BLNK
VDD
11.5V &
9.5V
Class
Regulator
AUXb
APD
CLS
2.53V
22V &
21.25V
12.5V
& 1V
V SS
DEN
400ms
Common
Circuits and
PoE Thermal
Monitor
S Q
R
35V &
30.5V
CONV.
OFF
H
L
1
ILIMb
+
0
EN
VSS
RTN
80mW
AUXb
4.5V
APDb
Figure 2. TPS23753 Functional Block Diagram
Pin Description
Refer to Figure 1 for component reference designators ®CS for example ), and the Electrical Characteristics table
for values denoted by reference (VCSMAX for example). Electrical Characteristic values take precedence over any
numerical values used in the following sections.
APD
APD forces power to come from an external adapter connected from VDD1 to RTN by opening the hotswap
switch. A resistor divider is recommended on APD when it is connected to an external adapter. The divider
provides ESD protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage
qualification assures the adapter can support the PD before the PoE current is cut off.
Select the APD divider resistors per the following equations where VADPTR-ON is the desired adapter voltage that
enables the APD function as adapter voltage rises.
(
)
RAPD1 = RAPD 2 ⋅ VADPTR _ ON − VAPDEN VAPDEN
6
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VADPTR _ OFF =
SLVS853C – JUNE 2008 – REVISED JANUARY 2010
RAPD1 + RAPD 2
RAPD 2
⋅ (VAPDEN − VAPDH )
(2)
The CLS output is disabled when a voltage above VAPDEN is applied to the APD pin.
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to RTN when not used.
BLNK
Blanking provides an interval between the gate drive going high and the current comparator on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparator is active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to RTN to obtain the internally set blanking period. Connect a resistor from BLNK to RTN for a
programmable blanking period. The relationship between the desired blanking period and the programming
resistor is defined by the following equation.
RBLNK (k Ω ) = t BLNK (ns )
(3)
Place the resistor adjacent to the BLNK pin when it is used.
CLS
Connect a resistor from CLS to VSS to program the classification current per IEEE 802.3at. The PD power ranges
and corresponding resistor values are listed in Table 2. The power assigned should correspond to the maximum
average power drawn by the PD during operation. The TPS23753 supports class 0 – 3 power levels.
CS
The current sense input for the dc/dc converter should be connected to the high side of the switching MOSFET’s
current sense resistor. The current-limit threshold, VCSMAX, defines the voltage on CS above which the GATE ON
time will be terminated regardless of the voltage on CTL.
The TPS23753 provides internal slope compensation to stabilize the current mode control loop. If the provided
slope is not sufficient, the effective slope may be increased by addition of RS per Figure 22.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
CTL
CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC causes GATE
to stop switching. Increasing VCTL above VZDC raises the switching MOSFET programmed peak current. The
maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The ac gain from CTL to the PWM
comparator is 0.5.
Use VB as a pull up source for CTL.
DEN
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. DEN goes to a high
impedance state when not in the detection voltage range. Pulling DEN to VSS during powered operation causes
the internal hotswap MOSFET and class regulator to turn off.
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FRS
Connect a resistor from FRS to RTN to program the converter switching frequency. Select the resistor per the
following relationship.
RFRS ( k Ω ) =
15000
fSW ( kHz )
(4)
The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin. More information is provided in the Applications section.
The FRS pin is high impedance. Keep the connections short and apart from potential noise sources.
GATE
Gate drive output for the dc/dc converter switching MOSFET.
RTN
RTN is internally connected to the drain of the PoE hotswap MOSFET, and the dc/dc controller return. RTN
should be treated as a local reference plane (ground plane) for the dc/dc controller and converter primary to
maintain signal integrity.
VB
VB is an internal 5V control rail that should be bypassed by a 0.1 μF capacitor to RTN. VB should be used to bias
the feedback optocoupler.
VC
VC is the bias supply for the dc/dc controller. The MOSFET gate driver runs directly from VC. VB is regulated
down from VC, and is the bias voltage for the rest of the converter control. A startup current source from VDD1 to
VC is controlled by a comparator with hysteresis to implement a bootstrap startup of the converter. VC must be
connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.22 μF capacitor, located adjacent to the VC pin, should be connected from VC to RTN to bypass the
gate driver. A larger total capacitance is required for startup.
VDD
Positive input power rail for PoE control that is derived from the PoE. VDD should be bypassed to VSS with a 0.1
μF (X7R,10%) capacitor as required by the standard. A transient suppressor (Zener) diode, should be connected
from VDD to VSS to protect against overvoltage transients.
VDD1
Source of dc/dc converter startup current. Connect to VDD for most applications. VDD1 may be isolated by a diode
from VDD to support PoE priority operation.
VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited
hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch. A
local VSS reference plane should be used to connect the input components and the VSS pin.
8
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SLVS853C – JUNE 2008 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS
DETECTION BIAS CURRENT
vs
VOLTAGE
PoE CURRENT LIMIT
vs
TEMPERATURE
458
8
7
456
PoE - Current Limit - mA
IVDD - Bias Current - mA
6
TJ = 125°C
5
4
3
TJ = 25°C
2
454
452
450
448
1
TJ = -40°C
0
0
2
6
VVDD-VSS - PoE Voltage - V
4
446
-40
10
8
20
40
60
80
TJ - Junction Temperature - °C
Figure 4.
CONVERTER START TIME
vs
TEMPERATURE
CONVERTER STARTUP SOURCE CURRENT
vs
VVDD1
120
6
VVC = 8.6 V
CVC = 22 mF
140
TJ = -40°C
5
IVC - Source Current - mA
VVDD1 = 10.2 V
120
100
80
VVDD1 = 19.2 V
60
VVDD1 = 35 V
40
20
-40
100
Figure 3.
160
Converter Start Time - ms
0
-20
TJ = 25°C
4
TJ = 125°C
3
2
1
0
-20
0
20
40
60
80
TJ - Junction Temperature - °C
100
120
5
10
Figure 5.
15
20
25
30
35
40
VVDD1-RTN - V
45
50
55
60
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
CONTROLLER BIAS CURRENT
vs
TEMPERATURE
CONTROLLER BIAS CURRENT
vs
VOLTAGE
1200
1000
Gate Open
VVC = 12 V
900
Gate Open
TJ = 25°C
500 kHz
IVC - Sinking - mA
700
VC - Controller Bias Current - mA
800
250 kHz
600
100 kHz
500
400
50 kHz
300
200
VCTL = 0 V
1000
500 kHz
800
250 kHz
600
100 kHz
400
50 kHz
200
VCTL = 0 V
100
0
-40
0
-20
0
20
40
60
80
TJ - Junction Temperature - °C
100
7
120
9
11
15
13
17
VC - Controller Bias Voltage - V
Figure 7.
Figure 8.
SWITCHING FREQUENCY
vs
TEMPERATURE
SWITCHING FREQUENCY
vs
PROGRAMMED RESISTANCE
300
650
800
600
200
550
RFRS = 30.1 kW (500 kHz)
150
500
RFRS = 148.5 kW (100 kHz)
450
100
RFRS = 301 kW (50 kHz)
Ideal
700
Switching Frequency - kHz
250
Switching Frequency - Hz
Switching Frequency - Hz
RFRS = 60.4 kW (250 kHz)
600
Typical
500
400
300
200
400
50
100
0
-40
350
-20
0
60
40
80
20
TJ - Junction Temperature - °C
100
120
0
0
20
30
40
6
50
-1
Programmed Resistance (10 / RFRS ) - W
Figure 9.
10
10
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
MAXIMUM DUTY CYCLE
vs
TEMPERATURE
CURRENT SLOPE COMPENSATION VOLTAGE
vs
TEMPERATURE
124
RFRS = 301 kW (50 kHz)
78
RFRS = 148.5 kW (100 kHz)
77.5
RFRS = 60.4 kW (250 kHz)
77
RFRS = 30.1 kW (500 kHz)
76.5
76
-40
-20
0
60
80
20
40
TJ - Junction Temperature - °C
100
120
118
116
114
-40
120
-20
0
20
40
60
Figure 11.
Figure 12.
CURRENT SLOPE COMPENSATION CURRENT
vs
TEMPERATURE
BLANKING PERIOD
vs
TEMPERATURE
Blanking Period (RBLNK 115 kW) - ns
Maximum Duty Cycle - %
78.5
VSLOPE - Slope Compensation - mVPP
79
235
-20
Figure 13.
0
20
40
60
80
TJ - Junction Temperature - °C
100
120
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
450
18
400
14
350
10
300
6
250
2
200
-2
150
-6
100
-10
50
-14
0
0
50
100
150
200
250
RBLNK - kW
300
350
Difference from Computed - ns
Blanking Period - ns
BLANKING PERIOD
vs
RBLNK
-18
400
Figure 15.
12
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APPLICATIONS
Classic PoE Overview
The following text is intended as an aid in understanding the operation of the TPS23753 but not as a substitute
for the actual IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33
(PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE
802.3-2008 will be referred to as a Type 1 device, and devices with high power or enhanced classification will be
referred to as Type 2 devices. Standards change and should always be referenced when making design
decisions.
Detect
0
2.7
10.1 14.5
20.5
30
Maximum Input
Voltage
Must Turn On byVoltage Rising
Shutdown
Classify
3/06/08
Lower Limit Proper Operation
Must Turn Off by Voltage Falling
Classification
Upper Limit
Classification
Lower Limit
Detection
Upper Limit
Detection
Lower Limit
The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable, and then
removing power if a PD is disconnected. The process proceeds through an idle state and three operational states
of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically
looks to see if something has been plugged in; this is referred to as detection. The low power levels used during
detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may
inquire how much power the PD requires; this is referred to as classification. Type 2 PSEs are required to do
hardware classification. The PD may return the default 13W current-encoded class, or one of four other choices.
The PSE may then power the PD if it has adequate capacity. Once started, the PD must present the maintain
power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and
turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 16 shows the
operational states as a function of PD input voltage.
Normal Operation
36
57
42
PI Voltage (V)
Figure 16. IEEE 802.3at (Type 1) Operational States
The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops in the cable and operating
margin. The IEEE 802.3at standard uses a cable resistance of 20 Ω (for type 1 devices) to derive the voltage
limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power
of 15.4 W at the PSE, only 13 W is available at the PI due to the worst-case power loss in the cable. The PSE
can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between
the two spare pairs (4–5 and 7–8). The PSE may only apply voltage to one set of pairs at a time. The PD uses
input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated
with the input bridges create a difference between the standard limits at the PI and the TPS23753 specifications.
The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second
interval. A type 1 PSE compliant to IEEE 802.3at is required to limit current to between 400 mA and an
upper-bound template (IEEE 802.3-2008 was 450 mA) during powered operation. The PSE must disconnect the
PD if it draws this current for more than 75 ms. Class 0 and 3 PDs may draw up to 400 mA peak currents for up
to 50 ms. The PSE may set lower output current limits based on the PD’s declared power requirements.
Threshold Voltages
The TPS23753 has a number of internal comparators with hysteresis for stable switching between the various
states as shown in Figure 16. Figure 17 relates the parameters in the Electrical Characteristics section to the
PoE states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN
pins are all high impedance.
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PD Powered
Idle
Classification
VVDD-VSS
Detection
VCL_HYS
1.4V
VCL_ON
VUVLO_H
VCU_HYS
VUVLO_R
VCU_OFF
Note: Variable names refer to Electrical Characteristic
Table parameters
Figure 17. Threshold Voltages
PoE Startup Sequence
The waveforms of Figure 18 demonstrate detection, classification, and startup from a type 1 PSE. The key
waveforms shown are VVDD-VSS, VRTN-VSS, and IPI. IEEE 802.3at requires a minimum of two detection levels;
however; four levels are shown in this example. Four levels guard against misdetection of a device when plugged
in during the detection sequence.
Figure 18. PoE Startup Sequence
Detection
The TPS23753 is in detection mode whenever VVDD-V SS is below the lower classification threshold. When the
input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in
detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS.
An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor since it only sees
a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and
26.25 kΩ at the PI.
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The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and the TPS23753 bias loading. The input diode bridge’s incremental resistance
may be hundreds of Ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge
resistance is partially cancelled by the TPS23753's effective resistance during detection.
Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before starting and helps with
power management once power is applied. The maximum power entries in Table 2 determine the class the PD
must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than its
stated Class power. The standard permits the PD to draw limited current peaks, however the average power
requirement always applies.
Voltage between 14.5 V and 20.5 V is applied to the PD for up to 75 ms during hardware Classification. A fixed
output voltage is sourced by the CLS pin, causing a fixed current to be drawn from VDD through RCLS. The total
current drawn from the PSE during classification is the sum of bias and RCLS currents. PD current is measured
and decoded by the PSE to determine which of the five available classes is advertised (see Table 2). The
TPS23753 disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off
during PD thermal limit or when APD or DEN are active. The CLS output is inherently current limited, but should
not be shorted to VSS for long periods of time.
Table 2. Class Resistor Selection
POWER AT PD PI
Class Current Requirement
CLASS
MINIMUM
(W)
MAXIMUM (W)
MINIMUM (mA)
MAXIMUM
(mA)
RESISTOR (Ω)
0
0.44
12.95
1
0.44
3.84
0
4
1270
9
12
2
3.84
243
6.49
17
20
137
3
4
6.49
12.95
26
30
90.9
12.95
25.5
36
44
63.4
NOTES
Only permitted for type 2 devices
Maintain Power Signature (MPS)
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (at a duty cycle of at least 75 ms on
every 225 ms) and an ac impedance lower than 26.25 kΩ in parallel with 0.05 μF. The ac impedance is usually
accomplished by the minimum CIN requirement of 5 μF. When APD or DEN are used to force the hotswap switch
off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power from the PD when this
occurs. A PSE that monitors only the ac MPS may remove power from the PD.
TPS23753 Operation
Startup and Converter Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits will discharge CIN, CVC, and CVB while the PD is unpowered. Thus VRTN-VDD
will be a small voltage just after full voltage is applied to the PD, as seen in Figure 18.
The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VDD rises
above the UVLO turn-on threshold (VUVLO-R, ~35 V) with RTN high, the TPS23753 enables the hotswap
MOSFET with a ~140 mA (inrush) current limit. Refer to the waveforms of Figure 19 for an example. Converter
switching is disabled while CIN charges and VRTN falls from VDD to nearly VSS, however the converter startup
circuit is allowed to charge CVC. Once the inrush current falls about 10% below the inrush current limit, the PD
control switches to the operational level (~450 mA) and converter switching is permitted.
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Converter switching is allowed if the PD is not in inrush and the VC under-voltage lock out (UVLO) permits it.
Continuing the startup sequence shown in Figure 19, VVC rises as the startup current source charges CVC and
M1 switching is inhibited by the status of the VC UVLO. The VB regulator powers the internal converter circuits as
VVC rises. Startup current is turned off, converter switching is enabled, and a softstart cycle starts when VVC
exceeds UVLO1 (~9 V). VVC falls as it powers both the internal circuits and the switching MOSFET gate. If the
converter control-bias output rises to support VVC before it falls to UVLO1 – UVLO1H (~5.5 V), a successful
startup occurs. Figure 19 shows a small droop in VVC while the output voltage rises smoothly and a successful
startup occurs.
10
100mA/Div
INRUSH
8
Exaggerated primarysecondary softstart handoff
IPI
6
10V/DIV
7
VC-RTN
5
4
VOUT
Turn ON
2V/DIV
3
-0.5
50V/DIV
2
1
-0.6
VDD-RTN
0
-0.7
000.0E 10.0E-3 20.0E-3 30.0E-3 40.0E-3 50.0E-3 60.0E-3 70.0E-3 80.0E-3 90.0E-3 100.0Et - Time 10 - ms/DIV
+0
3
Figure 19. Power Up and Start
If VVDD-VSS drops below the lower PoE UVLO (UVLOR – UVLOH, ~30.5 V), the hotswap MOSFET is turned off,
but the converter will still run. The converter will stop if VVC falls below the converter UVLO (UVLO1 – UVLOH,
~5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by VCTL (VCTL < VZDC, ~1.5 V), or
the converter is in thermal shutdown.
PD Interface Features
The PD section has the following functions, with the first four covered above.
• Detection
• Classification
• VDD to VSS UVLO
• Orderly sequencing of CIN charge and converter operation
• Hotswap switch current limit
• Hotswap switch foldback
• Hotswap thermal protection
The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The
PSE output cannot be relied on to protect the PD MOSFET against transient conditions, so the PD implements
its own protection. High stress conditions include converter output shorts, shorts from VDD to RTN, or transients
on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as a result. If
VRTN rises above ~12 V for longer than ~400 μs, the current limit reverts to the inrush limit, and turns the
converter off. The 400 μs deglitch feature prevents momentary transients from causing a PD reset, provided that
recovery lies within the bounds of the hotswap and PSE protection. Figure 20 shows an example of recovery
from a 15 V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a relatively
low current, recovers to 420 mA full current limit, and charges the input capacitor while the converter continues to
run. The MOSFET did not go into foldback because VRTN-VSS was below 12 V after the 400 μs deglitch.
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Figure 20. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or
operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD
state machine will always restart in inrush current limit when exiting from a PD overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature
allows a PD with secondary-side adapter ORing to achieve adapter priority. Care must be taken with
synchronous converter topologies that can deliver power in both directions.
The hotswap switch will be forced off under the following conditions:
• VAPD above VAPDEN (~1.5 V)
• VDE N ≤ VPD_DIS when VVDD-VSS is in the operational range
• PD over temperature
• VVDD-VSS < PoE UVLO (~30.5 V).
Converter Controller Features
The TPS23753 dc/dc controller implements a typical current-mode control as shown in Figure 2. Features
include oscillator, overcurrent and PWM comparators, current-sense blanker, softstart, and gate driver. In
addition, an internal current-compensation ramp generator, frequency synchronization logic, thermal shutdown,
and startup current source with control are provided.
The TPS23753 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the
optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM and
converter. There is an offset of VZDC (~1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL
below VZDC will stop converter switching, while voltages above (VZDC + 2 × VCSMAX) will not increase the
requested peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control
range.
The internal startup current source and control logic implement a bootstrap-type startup. The startup current
source charges CVC from VDD1 when the converter is disabled (either by the PD control or the VC control), while
operational power must come from a converter (bias winding) output. Loading on VC and VB must be minimal
while CVC charges, otherwise the converter may never start. The optocoupler will not load VB when the converter
is off. The converter will shut off when VC falls below its lower UVLO. This can happen when power is removed
from the PD, or during a fault on a converter output rail. When one output is shorted, all the outputs fall in voltage
including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A
restart will initiate as described in "Startup and Converter Operation" if the converter turns off and there is
sufficient VDD1 voltage. This type of operation is sometimes referred to as “hiccup mode,” which provides robust
output short protection by providing time-average heating reduction of the output rectifier.
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Care in design of the transformer and VC bias circuit is required to obtain hiccup overload protection.
Leading-edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected
tracking with output voltage. RVC (Figure 1) is often required slow the peak charging. Good transformer
bias-to-output-winding coupling results in reduced overshoot and better voltage tracking.
The startup current source transitions to a resistance as (VDD1 - VC) falls below 7 V, but will start the converter
from 12 V adapters within tST (VDD1 ≥ 10.2, V~85 ms). The bootstrap source provides reliable startup from widely
varying input voltages, and eliminates the continual power loss of external resistors. The startup current source
will not charge above the maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to
charge higher.
The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 22 to increase
slope compensation. This makes it easier to design the current limit to a fixed value.
The TPS23753 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. While the internally set
blanking period is relatively precise, almost all converters will require their own blanking period. The TPS23753
provides the BLNK pin to allow this programming. There may be some situations or designers that prefer an R-C
approach. The TPS23753 provides a pull-down on CS during the GATE off time to improve sensing when an
R-C filter must be used. The CS input signal should be protected from nearby noisy signals like GATE drive and
the MOSFET drain.
Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure 21
shows a common implementation of a secondary-side softstart that works with the typical TL431 error amplifier
shown in Figure 1. This secondary-side error amplifier will not become active until there is sufficient voltage on
the secondary. The TPS23753 provides a primary-side softstart which persists long enough (~800 μs) for
secondary side voltage-loop softstart to take over. The primary-side current-loop softstart controls the switching
MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. Figure 19 shows
an exaggerated handoff between the primary and secondary-side softstart that is most easily seen in the IPI
waveform. The output voltage rises in a smooth monotonic fashion with no overshoot. This handoff can be
optimized by decreasing the secondary-side softstart period.
From Regulated
Output Voltage
ROB
RSS
R FBU
C IZ
DSS
CSS
RFBL
TLV431
Figure 21. Example of Softstart Circuit Added to Error Amplifier
The dc/dc controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver,
bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, resets the
softstart generator, and forces the VC control into an under-voltage state.
Special Switching MOSFET Considerations
Special care must be used in selecting the converter switching MOSFET. The TPS23753 converter section has
minimum VC operating voltage of ~5.5 V, which is reflected in the applied gate voltage. This will occur during an
output overload, or towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the
anticipated peak fault current at this gate voltage.
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Thermal Considerations
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS23753 is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS23753 device to experience an OTSD event if it is excessively heated by a nearby
device.
Blanking – RBLNK
The TPS23753 BLNK feature permits programming of the blanking period with specified tolerance. Selection of
the blanking period is often empirical because it is affected by parasitics and thermal effects of every device
between the gate-driver and output capacitors.
There is a critical range of blanking period that is bounded on the short side by erratic operation, and on the long
side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum
blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent
current “spike” that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by
the output rectifier's ability to withstand the currents experienced during a converter output short. A short on the
flyback transformer secondary will cause very large peak MOSFET currents that are worsened by longer
blanking periods. A long blanking time also increases the minimum load required before cycle skipping occurs in
a non-synchronous converter.
The TPS23753 provides a choice between internal fixed and programmable blanking periods. The blanking
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with a resistor from BLNK to RTN per the following equation.
RBLNK (k Ω ) = t BLNK (ns )
(5)
For example, a 100 ns period is programmed by a 100 kΩ resistor. For a brand-new design, it is recommended
that an initial blanking period of 125 ns be designed in. This period should be tuned once the converter is
operational.
Current Slope Compensation
Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer)
current for stability at duty cycles near and over 50%. The TPS23753 has a maximum duty cycle limit of 80%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 80%, converters may be designed that run at duty cycles well below 80% for a
narrower, 36 V to 57 V range. The TPS23753 provides a fixed internal compensation ramp that suffices for most
applications. RS (see Figure 22) may be used if the internally provided slope compensation is not enough. It
works with ramp current (IPK = ISL-EX, ~40 μA) that flows out of the CS pin when the MOSFET is on. The IPK
specification does not include the ~3 μA fixed current that flows out of the CS pin.
Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp
voltage / switching period), however the electrical characteristics table specifies the slope peak (VSLOPE) based
on an 80% duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full period,
compute RS per the following equation where VSLOPE, DMAX, and ISL-EX are from the electrical characteristics table
with voltages in mV, current in μA, and the duty cycle is unitless (e.g. DMAX = 0.8).
VSLOPE (mV )
VSLOPE _ D (mV ) −
DMAX
⋅ 1000
RS (Ω) =
ISL _ EX ( µA)
(6)
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RTN
GATE
5/09/08
CS
RS
RCS
CS
Figure 22. Additional Slope Compensation
CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to
appear at the CS pin. The TPS23753 has an internal pull-down on CS ( ~500 Ω ) while the MOSFET is OFF to
reduce cycle-to-cycle carry-over voltage on CS.
FRS and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23753 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 80% and
controls the current-compensation ramp circuit. RFRS should be selected per the following equation.
RFRS ( k Ω ) =
15000
fSW ( kHz )
(7)
The TPS23753 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse ( > 25 ns) of magnitude VSYNC to FRS as shown in Figure 23. RFRS should be chosen so
that the maximum free-running frequency is just below the desired synchronization frequency. The
synchronization pulse terminates the potential on-time period, and the off-time period doesn’t begin until the
pulse terminates. A short pulse is preferred to avoid reducing the potential on-time.
Figure 23 shows examples of non-isolated and transformer-coupled synchronization circuits The pulse at the
FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and rise/fall times
less than 10 ns. The FRS node should be protected from noise because it is high-impedance.
FRS
RTN
V SYNC
T SYNC
RFRS
47pF
4/30/08
Synchronization
Pulse
FRS
47pF
VSYNC
TS YNC
1000pF
RTN
RFRS
Synchronization
Pulse
1:1
Example:
Pulse PA0184
4/30/08
Figure 23. Synchronization
Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular
installation. While most applications only require that the PD operate when both sources are present, the
TPS23753 supports forced operation from either of the power sources. Figure 24 illustrates three options for
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SLVS853C – JUNE 2008 – REVISED JANUARY 2010
diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies
power to the TPS23753 PoE input, option 2 applies power between the TPS23753 PoE section and the power
circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and
disadvantages. A detailed discussion of the TPS23753 and ORing solutions is covered in application note
Advanced Adapter ORing Solutions using the TPS23753, literature number SLVA306.
VSS
VDD1
VDD
DEN
CLS
Low Voltage
Output
Power
Circuit
TPS23753
RCLS
58V
From Spare
Pairs or
Transformers
0.1uF
RDEN
From Ethernet
Transformers
Optional for PoE Priority
5/8/08
RTN
Adapter
Option 2
Adapter
Option 1
Adapter
Option 3
Figure 24. ORing Configurations
Preference of one power source presents a number of challenges. Combinations of adapter output voltage
(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
Several factors which add to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits
(necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for
many of the combinations. However the TPS23753 offers several built-in features that simplify some
combinations.
Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with
PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to
assure which source was active. A second example is combining a 12 V adapter with PoE using option 2. The
converter will draw approximately four times the current at 12 V from the adapter than it does from PoE at 48 V.
Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The
converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher
voltage and lower input current. A third example is use of a 12 V adapter with ORing option 1. The PD hotswap
would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal
power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power
from the PD. If ac power is then lost, the PD will stop operating until the PSE detects and powers the PD.
The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled
when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution
works well with a wide range of adapter voltages, is simple, and requires few external parts. When the ac power
fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD will
momentarily loose power until the PSE completes its startup cycle.
The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority
implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET
and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven
from the secondary side of the converter.
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The least popular technique is PoE priority. It is implemented by placing a diode between the PD supply voltage,
VDD, and the dc/dc controller bias voltage, VDD1. The diode prevents reverse biasing of the PoE input diode
bridges when option 2 adapter ORing is used. The PSE may then detect, classify, and provide power to the PD
while a live adapter is connected. As long as the PoE voltage is greater than the adapter voltage, the PSE will
power the load. The APD function is not used in this technique.
The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The
adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections
for options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the
adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.
Protection
A TVS across the rectified PoE voltage per Figure 1 must be used. An SMAJ58A, or a part with equal to or better
performance, is recommended for general indoor applications. If an adapter is connected from VDD1 to RTN, as
in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the internal PD
capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the absolute
maximum ratings. Configurations that use DVDD as in Figure 25 may require additional protection against ESD
transients that would turn DVDD off and force all the voltage to appear across the internal hotswap MOSFET.
CVDD and DRTN per Figure 25 provide this additional protection.
CIN
VDD1
VDD
RDEN
DEN
CLS
RTN
VSS
58V
RCLS
C1 0.1mF
D1 58V
DVDD
DRTN
From Spare
Pairs or
Transformers
From Ethernet
Transformers
CVDD
0.01mF
Figure 25.
Outdoor applications require more extensive protection to lightning standards.
Frequency Dithering for Conducted Emissions Control
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted
emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit
board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A
more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE
Powered Device With Isolated Flyback, TI literature number SLUA469. Additionally, IEEE802.3at section 33.4
has requirements for noise injected onto the Ethernet cable based on compatibility with data transmission.
22
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SLVS853C – JUNE 2008 – REVISED JANUARY 2010
Occasionally, a technique referred to as frequency dithering is utilized to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements. The circuit of Figure 26 modulates the switching frequency by
feeding a small ac signal into the FRS pin. These values may be adapted to suit individual needs.
10kΩ
49.9kΩ
VB
+
-
6.04kΩ
TL331IDBV
4.99kΩ
0.01µF
10kΩ
301kΩ
1uF
To
FRS
RTN
Figure 26. Frequency Dithering
Design Procedure
A detailed design procedure for PDs using the TPS23753 is covered in Designing with the TPS23753 Powered
Device and Power Supply Controller , literature number SLVA305.
References
IEEE Standard for Information Technology … Part 3: Carrier sense multiple access with collision detection
(CSMA/CD) access method and physical layer specifications, IEEE Computer Society, IEEE 802.3™at (Clause
33)
Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement,
International Electrotechnical Commission, CISPR 22 Edition 5.2, 2006-03
Designing with the TPS23753 Powered Device and Power Supply Controller, Eric Wright, TI, SLVA305
Advanced Adapter ORing Solutions using the TPS23753, Eric Wright, TI, SLVA306
Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V.
Comiskey, TI, SLUA469
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REVISION HISTORY
Changes from Original (June 2008) to Revision A
Page
•
Changed data sheet From: Product Preview To: Production ............................................................................................... 1
•
Changed the TPS23753 Functional Block Diagram. ............................................................................................................ 6
•
Added the Typical Characteristics section. ........................................................................................................................... 9
Changes from Revision A (June 2008) to Revision B
•
Page
Changed the ESDS statement. ............................................................................................................................................. 2
Changes from Revision B (September 2009) to Revision C
Page
•
Changed From: IEEE 802.3-2005 To: IEEE 802.3 throughout the data sheet. ................................................................... 1
•
Changed the 1st paragraph in the Description From: The PoE implementation supports the IEEE 802.3-2005
(previously 802.3af) standard, 12.95 W (13 W) PD. To: The PoE implementation supports the IEEE 802.3-2005. An
IEEE802.3at type 1 device is equivalent to IEEE802.3-2008 (originally 802.3af) standard as a 13 W type 1 PD. ............. 1
•
Changed Note 1 in the Dissipations Ratings table to include additional information. .......................................................... 2
•
Changed section Classic PoE Overview second paragraph: From: The PD may return the default 12.95W (often
referred to as 13W) current-encoded class, or one of four other choices. To: The PD may return the default 13W
current-encoded class, or one of four other choices .......................................................................................................... 13
•
Changed Table 2 - Notes for the Class 4 row .................................................................................................................... 15
•
Added text and Figure 25 to the Protection section ........................................................................................................... 22
24
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS23753PW
NRND
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TP23753
TPS23753PWG4
NRND
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TP23753
TPS23753PWR
NRND
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TP23753
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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