TPS2379EVM-106

User's Guide SLVU687A – March 2012 – Revised May 2014 TPS2379 EVM User’s Guide This User’s Guide describes the evaluation module (EVM) for the TPS2379 (TPS2379EVM-106). TPS2379 is an IEEE802.3at type 2 compliant powered device (PD) controller with a GATE output for controlling external booster MOSFETs. 7 Contents Introduction ................................................................................................................... 2 1.1 Features .............................................................................................................. 2 1.2 Applications .......................................................................................................... 2 Electrical Specifications at 25°C ........................................................................................... 2 Description .................................................................................................................... 3 Schematic ..................................................................................................................... 4 General Configuration and Description ................................................................................... 5 5.1 Physical Access ..................................................................................................... 5 5.2 Test Setup ........................................................................................................... 6 EVM Assembly Drawings and Layout Guidelines ....................................................................... 6 6.1 PC Drawings ........................................................................................................ 6 6.2 Layout Guidelines ................................................................................................. 10 6.3 EMI Containment .................................................................................................. 10 Bill of Materials ............................................................................................................. 11 1 TPS2379EVM Schematic ................................................................................................... 4 2 Typical TPS2379EVM Test Setup ......................................................................................... 6 3 Top Side Placement ......................................................................................................... 7 4 Top Side Routing ............................................................................................................ 7 5 Layer Two Routing........................................................................................................... 8 6 Layer Three Routing......................................................................................................... 8 7 Bottom Side Routing 8 Bottom Side Placement ..................................................................................................... 9 1 2 3 4 5 6 List of Figures ........................................................................................................ 9 List of Tables ............................................................. 1 TPS2379EVM Electrical and Performance Specifications 2 Connector Functionality ..................................................................................................... 5 3 Test Points .................................................................................................................... 5 4 Jumpers ....................................................................................................................... 5 5 TPS2379EVM Bill of Materials ........................................................................................... SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback TPS2379 EVM User’s Guide Copyright © 2012–2014, Texas Instruments Incorporated 2 11 1 Introduction 1 www.ti.com Introduction The TPS2379EVM allows reference circuit evaluation of the TI TPS2379 PD controller. The TPS2379 features GATE output for controlling external MOSFETs for extended power applications. It also features a 100 V pass transistor, 140 mA inrush current limiting, type-2 indication, auto-retry fault protection, and an open-drain power-good output. 1.1 Features • • • • • • • • 1.2 Applications • • • • • 2 Gigabit Ethernet pass through interface Switched output return for “ease of use” loading GATE output to drive the external MOSFET Extra detection and class signature selection for non-standard applications IEEE 802.3at type-2 hardware classification with status flag (T2P) and LED DC/DC converter enable (CDB) Robust 100 V, 0.5 Ω internal hotswap MOSFET and 100 V, 64 mΩ external MOSFET Operating power in excess of 60W with four-pair PSE IEEE 802.3at-compliant devices Video and VoIP telephones Multiband access points Security cameras Pico-base stations Electrical Specifications at 25°C Table 1. TPS2379EVM Electrical and Performance Specifications PARAMETER CONDITION MIN TYP MAX UNITS POWER INTERFACE Input Voltage Applied to the power pins of connectors J1 or J3 Operating Voltage After start up. Input UVLO Rising input voltage at device terminals. Falling input voltage. – 57 V – 57 V – – 40 30.5 – – – 10.1 V – 23.0 V Detection voltage At device terminals 1.4 Classification voltage At device terminals 11.9 Detection signature Classification current J6 shunt removed 24.9 J6 shunt installed 12.5 38 – 42 J7 shunt installed 64 – 72 100 – 180 850 – 1200 Operating current-limit Efficiency Internal MOSFET only (R13 removed) Internal plus external (R13 installed) Four input pairs. Measured from J1 to J4 60W output power TPS2379 EVM User’s Guide 2260 V kΩ J7 shunt removed Inrush current-limit 2 0 30 mA mA mA 97.5% SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Description www.ti.com 3 Description TPS2379EVM-106 enables full evaluation of the TPS2379 device. Refer to the schematic shown in Figure 1. Ethernet power is applied from J1 to T1/T2 and is dropped to the diode bridges (D3/D4/D8/D9 or D5/D6/D10/D11) from the T1/T2 center taps. The series R-C circuit from each center tap help balance the Ethernet cable impedance and are critical for ESD and EMI/EMC performance. These circuits are terminated at TP10 (EGND) through the high voltage capacitor, C9. At the output of the diode bridges is the EMI/EMC filter and transient protection for the TPS2379. R7 provides the detection signature and R8 provides the class 4 signature resistance to the PSE. A shunt on J6 can be installed to present a 12.5kΩ detection signature resistance. A shunt on J7 can be installed to present a 45.2Ω (55mA) class signature resistance. To the right of the TPS2379 (U1) is the switched side of the PD controller. The TPS2379 RTN pin provides inrush limited turn on and charge of the bulk capacitor, C3. During inrush, the TPS2379 GATE pin is pulled low (with respect to VSS) disabling the external boost MOSFET, Q2. When inrush is complete, the GATE pin goes high and enables a parallel conduction path through Q2 and the TPS2379 internal MOSFET. Q1 provides current limit for the external MOSFET when the voltage between TP12 and TP11 reaches the base-emitter on threshold of Q1. Additionally during inrush, the TPS2379 CDB pin is pulled low (with respect to the RTN pin). Since the CDB pin is connected to the GATE of Q3, Q3 is off during inrush and J4 pin 1 is not connected to the RTN pin. This allows the output load to remain connected during EVM testing. LED’s D1 and D2 provide operational visual indications of T2P and ON respectively. SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback TPS2379 EVM User’s Guide Copyright © 2012–2014, Texas Instruments Incorporated 3 Schematic 4 www.ti.com Schematic 14 T1 ETH1-230LD 1 R1 12 J1 POE INPUT 75 J2 ETHERNET DATA 3 1 2 3 4 5 6 7 8 13 1 2 3 4 5 6 7 8 2 LINE PHY 10 5 R2 9 14 75 4 11 6 T2 ETH1-230LD LED BIAS J3 1 R3 12 75 C1 1 1000pF 2 + - 3 13 2 LINE PHY 10 J6 5 R4 R5 12.1k 12.1k 1 R6 75 2 D1 4 11 XDEN 9 VDD TP1 R19 6 D2 (ON) (T2P) LN1271RAL LN1371G T2P TP2 24.9k FB1 500 PAIR12 TP3 D3 D4 D5 D6 PAIR78 TP7 B2100 B2100 B2100 B2100 C4 0.01uF C5 C6 D7 C2 SMAJ58A 0.1uF 0.01uF 0.01uF 0.01uF R9 R10 R12 75 75 24.9k J7 C7 1 2 C8 C9 R11 75 75 1000pF D8 D9 D10 D11 B2100 B2100 B2100 B2100 XCLS 2 47uF 2 DEN T2P 7 3 T2P 3 CLS CDB 6 2 CDB 1 SRTN 4 VSS 63.4 4 RTN 5 R14 100k R13 9 200k 150 TP8 CDB TP9 RTN 2 158 R17 0.27 NOT USED VDD GATE 8 J5 Q1 FMMT493TC NOTES J4 C3 1 VDD R16 1000pF 1 R8 + R15 FB2 500 EGND TP10 U1 TPS2379DDA R7 PWPD PAIR45 TP5 SWITCHED OUTPUT +54V@1A GATE TP6 PAIR36 TP4 TP11 VSS 1 2 Q2 BUK7275-100A R18 1 Use for switched RTN D12 Q3 BZT52C18V IRFR3410PbF TP12 ESNS Figure 1. TPS2379EVM Schematic 4 TPS2379 EVM User’s Guide SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated General Configuration and Description www.ti.com 5 General Configuration and Description 5.1 Physical Access Table 2 lists the TPS2379EVM connector functionality, Table 3 describes the test point availability and Table 4 describes the jumper functionality. Table 2. Connector Functionality Connector Label J1 PWR+DATA J2 DATA J4 J4 Description Power over ethernet (POE) input. Connect to power sourcing equipment (PSE) power and data source. Ethernet data pass through. Connect to downstream ethernet device. Output connector to load. Connect pin #4 (VDD) to positive input and pin #1 (RTN) to low side of load. Pin #2 (CDB) can be used to inhibit the converter while the TPS2379 output is ramping up. Pin #3 (T2P) can be used to notify the load of when high power source is present. D1 (RED) T2P T2P (type 2 PSE) LED. When ON this indicates that a type 2 PSE is detected. D2 (GREEN) ON TPS2379 Output Powered. Table 3. Test Points Test Point Color Label Description TP6 WHT GATE Gate output to external MOSFET TP3 RED PAIR12 Data pair from pins 1 and 2 of J1 TP4 ORG PAIR36 Data pair from pins 3 and 6 of J1 TP5 RED PAIR45 Spare pair from pins 4 and 5 of J1 TP7 ORG PAIR78 Spare pair from pins 7 and 8 of J1 TP1 RED VDD High side output from bridge TP2 WHT T2P Type 2 PSE output from TPS2379 TP9 BLK RTN Switched low side from TPS2379 TP8 WHT CDB Converter disable output from TPS2379 TP11 BLK VSS Low side output from bridge TP10 SM EGND Earth or chassis ground point TP12 BLK ESNS External MOSFET current sense point Table 4. Jumpers Jumper Label J3 J4 Description LED bias jumper. Install to furnish LED bias for T2P and ON LED’s J5 J5 Switched output return bypass jumper. J6 XDEN This jumper can be used to switch in alternate non-standard detection resistors. When the shunt is removed, the standard 24.9kΩ is used and when the shunt is installed, the detection resistance is ~12.5kΩ J7 XCLS This jumper can be used to switch in alternate non-standard classification resistors. When the shunt is removed, the standard class 4 63.4Ω (40mA) resistor is used and when the shunt is installed, the classification resistance is ~45.2Ω (55mA). SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback TPS2379 EVM User’s Guide Copyright © 2012–2014, Texas Instruments Incorporated 5 General Configuration and Description 5.2 www.ti.com Test Setup Figure 2 shows a typical test setup for TPS2379EVM. Connect J1 to the power sourcing equipment (PSE) Power for the Ethernet device is available at J4 and the pass through Ethernet data is available at J2. PSE (Ethernet Cable) J1 VDD T2P CDB SRTN DUT TPS2379EVM J2 J4 Ethernet Device Figure 2. Typical TPS2379EVM Test Setup 6 EVM Assembly Drawings and Layout Guidelines 6.1 PC Drawings The following figures show component placement and layout of the EVM. 6 TPS2379 EVM User’s Guide SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated www.ti.com EVM Assembly Drawings and Layout Guidelines Figure 3. Top Side Placement Figure 4. Top Side Routing SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback TPS2379 EVM User’s Guide Copyright © 2012–2014, Texas Instruments Incorporated 7 EVM Assembly Drawings and Layout Guidelines www.ti.com Figure 5. Layer Two Routing Figure 6. Layer Three Routing 8 TPS2379 EVM User’s Guide SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated www.ti.com EVM Assembly Drawings and Layout Guidelines Figure 7. Bottom Side Routing Figure 8. Bottom Side Placement SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback TPS2379 EVM User’s Guide Copyright © 2012–2014, Texas Instruments Incorporated 9 EVM Assembly Drawings and Layout Guidelines 6.2 www.ti.com Layout Guidelines The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set of recommendations include: • Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode bridges, TVS and 0.1-µF capacitor, and TPS2379. • All leads should be as short as possible with wide power traces and paired signal and return. • There should not be any crossovers of signals from one part of the flow to another. • Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output. • The TPS2379 should be located over split, local ground planes referenced to VSS for the PoE input and to RTN for the switched output. • Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay copper fills should be used in the power path. 6.3 EMI Containment • • • • • • • • • • • • 10 Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives) Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes (minimize exposed radiating surface). Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with ground floods) Use 4 layer PCB if economically feasible (for better grounding) Minimize the amount of copper area associated with input traces (to minimize radiated pickup) Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground) Use of ferrite beads on input (allow for possible use of beads or 0 ohm resistors) Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as boundary line) Possible use of common-mode inductors Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations) End-product enclosure considerations (shielding) TPS2379 EVM User’s Guide SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Bill of Materials www.ti.com 7 Bill of Materials Table 5. TPS2379EVM Bill of Materials Count Ref Des Value Description Size Part Number Supplier 2 FB1-2 500 Bead, Ferrite, 2000mA, 60m-ohm 1206 MI1206L501R-10 Steward 4 C4-7 0.01uF Capacitor, Ceramic, 100V, X7R, 10% 603 STD STD 1 C8 1000pF Capacitor, Ceramic, 100V, X7R, 10% 603 STD STD 1 C2 0.1uF Capacitor, Ceramic, 100V, X7R, 10% 805 STD STD 2 C1 C9 1000pF Capacitor, Ceramic, 2kV, X7R, 15% 1210 Std STD 1 C3 47uF Capacitor, Aluminum, 63V, ±20% 0.328 x 0.390 inch EEE-FK1J470P Panasonic 2 J1-2 5520252-4 Connector, Jack, Modular, 8 POS 0.705 x 0.820 inch 5520252-4 AMP 1 D12 BZT52C18V Diode, Zener, Planar Power, 500mW, 18V SOD-123 BZT52C18-7-F Diodes, Inc 1 D1 LN1271RAL Diode, LED, Ultra Bright Red, 10-mA, 5-mcd 0.114 X 0.049 inch LN1271RAL Panasonic 1 D2 LN1371G Diode, LED, Green, 10-mA, 2.6-mcd 0.114 X 0.049 inch LN1371G Panasonic 8 D3-6 D8-11 B2100 Diode, Schottky, 2-A, 100-V SMB B2100-13-F Diodes, Inc 1 D7 SMAJ58A Diode, TVS, 58-V, 1W SMA SMAJ58A-13-F Diodes, Inc 4 J3 J5-7 PEC02SAAN Header, Male 2-pin, 100mil spacing 0.100 inch x 2 PEC02SAAN Sullins 1 R14 100k Resistor, Chip, 1/16W, 1% 603 STD STD 1 R16 200k Resistor, Chip, 1/16W, 1% 603 STD STD 2 R7 R19 24.9k Resistor, Chip, 1/16W, 1% 603 STD STD 1 R13 150 Resistor, Chip, 1/16W, 1% 603 STD STD 8 R1-3 R6 R9-12 75 Resistor, Chip, 1/16W, 1% 603 STD STD 1 R8 63.4 Resistor, Chip, 1/10W, 1% 805 STD STD 1 R15 158 Resistor, Chip, 1/10W, 1% 805 STD STD 2 R4-5 12.1k Resistor, Chip, 0.6W, 1% 2010 STD STD 1 R17 0.27 Resistor, Chip, 1W, 1% 2512 STD STD 0 R18 0.27 Resistor, Chip, 1W, 1% 2512 STD STD 1 J4 ED120/4DS Terminal Block, 4-pin, 15-A, 5.1mm 0.80 x 0.35 inch ED120/4DS OST 3 TP1 TP3 TP5 5010 Test Point, Red, Thru Hole 0.125 x 0.125 inch 5010 Keystone 3 TP9 TP11-12 5011 Test Point, Black, Thru Hole 0.125 x 0.125 inch 5011 Keystone 3 TP2 TP6 TP8 5012 Test Point, White, Thru Hole 0.125 x 0.125 inch 5012 Keystone 2 TP4 TP7 5013 Test Point, Orange, Thru Hole 0.125 x 0.125 inch 5013 Keystone 1 U1 TPS2379DDA IC, IEEE 802.3at PoE High Power PD Controller TPS2379DDA TPS2379DDA TI 1 TP10 5016 Test Point, SM, 0.150 x 0.090 0.185 x 0.135 inch 5016 Keystone 1 Q1 FMMT493TC Trans, NPN Midium Power, 100V 1A SOT-23 FMMT493TC Diodes 1 Q2 BUK7275 MOSFET, N-ch, 100-V, 22-A, 75 milliohm DPAK BUK7275 NXP SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback TPS2379 EVM User’s Guide Copyright © 2012–2014, Texas Instruments Incorporated 11 Bill of Materials www.ti.com Table 5. TPS2379EVM Bill of Materials (continued) Count Ref Des Value Description Size Part Number Supplier 1 Q3 IRFR3410 MOSFET, N-ch, 100-V, 31-A, 39 milliohm DPAK IRFR3410TRLPBF IRF 2 T1-2 ETH1-230LD Transformer, High-Power PoE Magnetics S0 14 Wide ETH1-230LD Coilcraft Shunt, Black 100-mil 929950-00 3M PWR106 Any 1 1 12 — PCB, 3.5 In x 1.7 In x 0.062 In TPS2379 EVM User’s Guide SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Revision History www.ti.com Revision History Changes from Original (March 2012) to A Revision ....................................................................................................... Page • • • • Changed the Description From: 37.4Ω (68mA) class signature resistance. To: 45.2Ω (55mA) class signature resistance 3 Changed R15 From 90.9 to 158 in Figure 1 ........................................................................................... 4 Changed the description of Jumper J7 in Table 4 From: ~37.4Ω (68mA) To: ~45.2Ω (55mA) ................................. 5 Changed the value of R15 in the Bill of Materials table From: 90.9 To 158 ..................................................... 11 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SLVU687A – March 2012 – Revised May 2014 Submit Documentation Feedback Revision History Copyright © 2012–2014, Texas Instruments Incorporated 13 ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR EVALUATION MODULES Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following: 1. User agrees and acknowledges that EVMs are intended to be handled and used for feasibility evaluation only in laboratory and/or development environments. Notwithstanding the foregoing, in certain instances, TI makes certain EVMs available to users that do not handle and use EVMs solely for feasibility evaluation only in laboratory and/or development environments, but may use EVMs in a hobbyist environment. All EVMs made available to hobbyist users are FCC certified, as applicable. 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Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated spacer Important Notice for Users of EVMs Considered “Radio Frequency Products” in Japan EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan. If user uses EVMs in Japan, user is required by Radio Law of Japan to follow the instructions below with respect to EVMs: 1. 2. 3. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use EVMs only after user obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or Use of EVMs only after user obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless user gives the same notice above to the transferee. Please note that if user does not follow the instructions above, user will be subject to penalties of Radio Law of Japan. http://www.tij.co.jp 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品の ご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・インスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル http://www.tij.co.jp Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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