TPS23841
www.ti.com
SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
HIGH-POWER, WIDE VOLTAGE RANGE, QUAD-PORT ETHERNET POWER SOURCING
EQUIPMENT MANAGER
FEATURES
APPLICATIONS
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Quad-Port Power Management With Integrated
Switches and Sense Resistors
High Power PoE up to 25 W at PD Input
Operating from a 53-V Minimum Input Power
Rail
Wide Range Single Supply: 21.5 V up to 57 V
ICUT = 615 mA, ILIM = 650 mA Nominal
IEEE 802.3af Compatible
Individual Port 15-bit A/D Converters
Auto, Semi-Auto and Power Management
Modes
Controlled Current Ramp Power-Up/Down for
EMI Reduction
Over-Temperature Protection
DC Disconnect Detection, Supports AC
Disconnect
High-Speed 400-kHz I2C Interface
Supports Legacy PD Detection
PowerPAD™ Package
Comprehensive Power Management Software
Available for MPS430 Microcontroller
Medical/Industrial Applications at 24 V
High Power Ethernet Enterprise Switches
SOHO Hubs, Ethernet Hubs
Ethernet High Power Mid-Spans
High Power PSE Injectors
DESCRIPTION
The TPS23841 is a high-power, wide voltage range,
quad-port sourcing equipment manager. The
TPS23841 can provide up to 570 mA per port over a
wide temperature range (-40°C to +125°C). Each
port may operate from 21.5 V up to 57 V. The
integrated
output
eliminates
two
external
components per port (MOSFET and sense resistor)
and survives 100-V transients. Four individual 15-bit
A/D converters are used to measure signature
resistance, voltage, current and die temperature,
resulting in a simple and robust PSE solution. The
TPS23841 comes with a comprehensive software
solution to meet the most demanding applications
which can serve as a core for all PoE system
designs.
TYPICAL APPLICATION
PSE
D1
PD
FB1
Z
+55V
F1
TX
Up to 100m
of CAT 5A
RJ45
RJ45
3
3
6
6
TX
VDD
TPS2376-H
Px
C1
TPS23841
High-current
PoE Xfmr
High-current
PoE Xfmr
1
1
DET
CLASS
RTN
RX
Nx
VPOE
RTN
RETx
SCL
SDA_I
SDA_O
Z
FB2
Optional
MSP430
Micro
2
2
4
4
5
5
7
7
8
8
RX
DC/DC
Converter
VSS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TPS23841
www.ti.com
SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
DESCRIPTION (CONTINUED)
The TPS23841 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply.
These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought out
separately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for powering
external loads up to 2 mA. For more demanding loads it is highly recommended to use external buffers to
prevent system degradation. When the TPS23841 is initially powered up an internal Power-on-Reset (POR)
circuit resets all registers and sets all ports to the off state to ensure that the device is powered up in a known
safe operating state.
The TPS23841 has three modes of operation; auto mode (AM), semi-auto mode (SAM) and power management
mode (PMM).
• In auto mode the TPS23841 performs discovery, classification and delivery of power autonomously to a
compliant PD without the need of a micro-controller.
• In semi-auto mode the TPS23841 operates in auto mode but users can access the contents of all read status
registers and A/D registers through the I2C serial interface. All write control registers are active except for D0
through D3 of port control register 1 (Address 0010) for limited port control. The semi-auto mode allows the
TPS23841 to detect valid PD's without micro-controller intervention but adds a flexibility to perform power
management activities.
• Power management mode (with a micro-controller) allows users additional capabilities of discovering
non-compliant (legacy) PDs, performing AC Disconnect and advanced power management system control
that are based on real time port voltages and currents. All functions in this mode are programmed and
controlled through read/write registers over the I2C interface. This allows users complete freedom in
detecting and powering devices. A comprehensive software package is available that mates the power of the
TPS23841 with the MSP430 micro-controller.
TPS23841 integrated output stage provides port power and low-side control. The internal low-side circuitry is
designed with internal current sensing so there are no external resistors required. The output design ensures the
power switches operate in the fully enhanced mode for low power dissipation.
The I2C interface allows easy application of opto-coupler circuitry to maintain Ethernet port isolation when a
ground based micro-controller is required. The TPS23841 five address pins (A1–A5) allow the device to be
addressed at one of 31 possible I2C addresses. Per-port write registers separately control each port state
(discovery, classification, legacy, power up, etc) while the read registers contain status information of the entire
process along with parametric values of discovery, classification, and real-time port operating current, voltage
and die temperature.
The proprietary 15-bit integrating A/D converter is designed to meet the harsh environment where the PSEPM
resides. The converter is set for maximum rejection of power line noise allowing it to make accurate
measurements of line currents during discovery, classification and power delivery for reliable power
management decisions.
The TPS23841 is available in either 64-pin PowerPAD™ down (PAP) or 64-pin PowerPAD up (PJD) packages.
ORDERING INFORMATION
(1)
(2)
2
PACKAGED DEVICES (1)
TEMPERATURE RANGE
TA = TJ
TQFP – 64 (PAP) (2)
TQFP – 64 (PJD) (2)
–40°C to 125°C
TPS23841PAP
TPS23841PJD
The PAP and PJD packages are available taped and reeled. Add R suffix to device type
(e.g.TPS23841PAPR) to order quantities of 1,000 devices per reel.
PAP = PowerPad down, PJD = PowerPad up.
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TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
PARAMETER
VALUE
UNIT
V10 current sourced
100
µA
V3.3 current sourced
5
mA
Applied voltage on CINT#, CT, RBIAS
–0.5 to 10
Applied voltage on SCL, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, MS, PORB, WD_DIS,
ALT_A/B, AC_LO, AC_HI
–0.5 to 6
V
Applied voltage on V48, P#, N#
–0.5 to 80
TJ
Junction operating temperature
–40 to 125
Tstg
Storage temperature --55 to 150
–55 to 150
Tsol
Lead temperature (soldering, 10 sec.)
(1)
(2)
°C
260
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the
Data book for thermal limitations and considerations of packages.
DISSIPATION RATINGS (1)
(1)
PACKAGE
THERMAL RESISTANCE
JUNCTION TO CASE θJC
THERMAL RESISTANCE
JUNCTION TO AMBIENT θJA
PAP
0.38°C/W
21.47°C/W
PJD
0.38°C/W
21.47°C/W
Thermal Resistance measured using 2-oz copper trace and copper pad solder following layout recommendation in TI Publication
PowerPAD Thermally Enhanced Package Technical Brief SLMA002.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VIN
PARAMETER
Input voltage, V48 pin
21.5
48
57
UNIT
V
TJ
Junction temperature
-40
125
°C
ELECTRO STATIC DISCHARGE (ESD) PROTECTION
MAX
Human body model
UNIT
1.5
CDM
1
Machine model
kV
0.2
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TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4
9
12
10
14
UNIT
Power Supply
V48 quiescent current
Off mode (all ports)
V48 quiescent current
Powered mode (all ports)
V10, internal analog supply
ILOAD = 0
9.75
10.5
11.5
V3.3, internal digital supply
ILOAD = 0 to 3 mA
3
3.3
3.7
V3.3 short circuit current
V=0
3
V6.3, internal supply
ILOAD = 0
5
6.3
7
V2.5, internal reference supply
ILOAD = 0
2.46
2.5
2.54
VUVLO_R, V48 UVLO
Input voltage rising
16.0
21.5
VUVLO_F, V48 UVLO
Input voltage falling
14
21
VHYSUV, UVLO hysteresis
0.2
Internal POR time out(I2C)
After all supplies are good I2C activity is valid
Internal POR time out (Port)
After all supplies are good Port active to I2C
commands
12
1.0
mA
V
mA
V
2.0
8
Clock
Pulses
66000
Port Discovery
Port off #P to #N input resistance
400
Discovery open circuit voltage
600
22
Discovery 1 voltage loop control
70 µA < IPORT < 3 mA
Discovery 2 voltage loop control
70 µA < IPORT < 3 mA
Discovery current limit
P = N = 48 V
Auto-mode discovery resistance
acceptance Band
2.8
4.4
8.8
3
kΩ
30
4
V
10
5
19
26.5
Auto-mode discovery resistance low
end rejection
0
15
Auto-mode discovery resistance high
end rejection
33
Discovery1,2 A/D conversion scale
factor
100 µA < IPORT < 3 mA
Discovery1,2 A/D conversion time
IPORT= 120 µA
5.30
6.10
mA
kΩ
6.75 count/µA
ms
Port Classification
Classification voltage loop control
100 µA < IPORT < 50 mA
15
17.5
20
Classification current limit
P = N = 48 V
50
60
100
Class 0 to 1 detection threshold
5.5
6.5
7.5
Class 1 to 2 detection threshold
13
14.5
16
Class 2 to 3 detection threshold
21
23
25
Class 3 to 4 detection threshold
31
33
35
Class 4 to 0 detection threshold
Classification A/D conversion scale
factor
Classification A/D conversion time
4
IPORT = 50 mA
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45
48
375
424
18
V
mA
51
475 Count/m
A
22
ms
TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Port Legacy Detection
Legacy current limit
P = N = 48 V
Legacy voltage A/D conversion scale
factor
100 mV < VPORT < 17.5 V
Legacy A/D conversion time
0 V < VPORT < 15 V
2.6
3.5
4.3
1365
1400
1445
mA
18
22
ms
Ω
Count/V
Port Powered Mode
Port on resistance
20 mA < IPORT < 300 mA
ICUT
Over current threshold
RBIAS = 124 kΩ, CT = 220 pF,
ILIM
Output current limit
ILIM ICUT
Threshold delta
Disconnect timer current threshold
TMPDO Disconnect detection time
1.3
1.8
570
615
665
600
650
700
2
RBIAS = 124 kΩ, CT = 220 pF
ILOAD < current threshold, RBIAS = 124 kΩ, CT =
220 pF
70
7.5
300
10
400
Port output UV
42.0
42.7
44.0
Port output OV
54
55
56
TOVLD
Over current time out
RBIAS = 124 kΩ, CT = 220 pF
50
TLIM
Short circuit time out
RBIAS = 124 k., CT = 220 pF
50
Turn--off delay from UV/OV faults
RBIAS = 124 k., CT = 220 pF, After port enabled
and ramped up
Port current A/D conversion scale
factor
20 mA < IPORT < 56 V
Port current A/D conversion time
IPORT < 300 mA
Port voltage A/D conversion scale
factor
mA
ms
V
75
75
ms
3
31
36.41
40 Count/m
A
18
22
ms
335
353
370
Count/V
18
22
ms
45 V < VPORT < 56 V
Port voltage A/D conversion time
Port temperature A/D conversion
(17500 - counts)/16
°C
Port Disable Mode
Port N voltage
P = 48 V
47
V
AC LO and AC HI Specification
AC_LO, AC_HI – low output voltage
0
0.5
AC_LO – high output voltage
3.0
5.0
AC_HI – high output voltage
5.0
7.0
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V
5
TPS23841
www.ti.com
SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)
PARAMETER
Digital
I2C
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Specifications
SCL, SDA_I, A1–A5 ,WD_DIS,
ALTA/B, MS, PORB logic input
threshold
1.5
SCL, SDA_I input hysteresis
250
MS, PORB input hysteresis
150
WD_DIS, ALTA/B, MS, PORB input
pulldown resistance
Input voltage 0.5 to 3 V
V
mV
50
kΩ
10
µA
SDA_O logic high leakage
Drain = 5 V
100
nA
SDA_O logic low
ISINK = 10 mA
200
mV
INTB logic high leakage
Drain = 6 V
INTB logic low
ISINK = 10 mA
A1–A5 pull-down current
10
µA
200
mV
Digital I2C Timing
SCL clock frequency
Pulse duration
0
SCL high
0.6
SCL low
1.3
Rise time, SCL to SDA
kHz
0.300
Fall time, SCL to SDA
6
400
0.300
Setup time, SDA to SCL
0.250
Hold time, SCL to SDA
0.300
Bus free time between start and stop
1.3
Setup time, SCL to start condition
0.6
Hold time, start condition to SCL
0.6
Setup time, SCL to stop condition
0.6
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0.900
µs
TPS23841
www.ti.com
SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
TPS23841 SINGLE PORT BLOCK DIAGRAM
Diff Amp
(Fix Gain)
UV/OV
Comparators
600 kW
Two
8 Bits
Status
Register
Loop Cntri Amp
Detect/Class Modes
Two
8 Bits
Status
Register
Auto
Seq
Logic
Analog
Control
Circurty
LCA
Power Mode
Thermal
Detector
A2D
Registers
Resistor
Voltage
Current
&
Die Temp
Max I
Thld
OVI
OVI
Thld
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TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
PAP
I/O
DESCRIPTION
PJD
POWER AND GROUND
V48
60
5
I
48-V input to the device. This supply can have a range of 22 V to 57 V. This pin should be decoupled
with a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible.
V10
58
7
O
10-V analog supply. The 10-V reference is generated internally and connects to the main internal
analog power bus. A 0.1-µF de-coupling capacitor should terminate as close to this node and the
AG1 pin as possible. Do not use for an external supply.
V6.3
59
6
O
6.3-V analog supply. A 0.1-µF de-coupling capacitor should terminate as close to this pin and the
AG1 pin as possible. Do not use for an external supply.
V3.3
24
41
O
3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power
bus. A 0.1-µìF de-coupling capacitor should terminate as close to this node and the DG pin as
possible. This output can be used as a low current supply to external logic.
V2.5
54
11
O
2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power
bus. This pin should not be tied to any external supplies. A 0.1-µF de-coupling capacitor should
terminate as close to this node and the RG pin as possible. Do not use for an external supply.
AG1
57
8
Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be
GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three
de-coupling capacitors tied to V48, V10 and V6.3.
AG2
61
4
Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the
GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be
tied together directly for the best noise immunity.
DG
23
42
GND
Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the
common copper 48-V return plane.
RG
56
9
GND
Reference ground. This is a precision sense of the external ground plane. The integration capacitor
(CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be
used to form a printed wiring board ground guard ring around the active node of the integration
capacitor (CINT). It should tie to common copper 48-V return plane.
PORT ANALOG SIGNAL
8
P1
7
58
I
P2
10
55
I
P3
39
26
I
P4
42
23
I
N1
6
59
I
N2
11
54
I
N3
38
27
I
N4
43
22
I
RET1
5
60
I
RET2
12
53
I
RET3
37
28
I
RET4
44
21
I
CINT1
4
61
I
CINT2
13
52
I
CINT3
36
29
I
CINT4
45
20
I
Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with
respect to each Port N pin Optionally, if the application warrants, this high side path can be protected
with the use of a self resetting poly fuse.
Port negative. 48-V load return pin. The low side of the load is switched and protected by internal
circuitry that will limit the current.
48 V return pin
Integration capacitor. This capacitor is used for the ramp A/D converter signal integration. Connect A
0.027- µF capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene,
polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with
increased conversion error.
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
PAP
I/O
DESCRIPTION
PJD
ANALOG SIGNALS
This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When
the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description)
CT
53
12
I
The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the
device. This internal clock is used for the internal state machine, integrating A/D counters, POR time
out, faults and delay timers of each port. Using a 220-pF capacitor for CT and a 124-kΩ resistor for
RBIAS sets the internal clock to 245 kHz and ensure IEEE 802.3af compliance along with maximizing
the rejection of 60-Hz line frequency noise from A/D measurements.
RBIAS
55
10
I
Bias set resistor. This resistor sets all precision bias currents within the chip. This pin will regulate to
1.25V (V2.5/2) when a resistor is connected between RBIAS and RG. This voltage and RBIAS
generate a current which is replicated and used throughout the chip. This resistor also works in
conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistor
should be connected RG. RBIAS is a high impedance input and care needs to be taken to avoid
signal injection from the SYN pin or I2C signals.
SYN
52
13
I/O
This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0v
to 3.3V pulse of the internal clock which can be used to drive other TPS23841 SYN pins for
elimination of a timing capacitor. When the CT pin is grounded this pin becomes an input pin that can
be driven from a master TPS23841 or any other clock generator signal.
AC_LO
51
14
O
Totem-pole output pin for AC Disconnect excitation.
AC_HI
50
15
O
Totem-pole output pin for AC Disconnect excitation.
DIGITAL SIGNALS
SCL
25
40
I
Serial clock input pin for the I2C interface.
SDA_I
26
39
I
Serial data input pin for the I2C interface. When tied to the SDA_O pin, this connection becomes the
standard bi-directional serial data line (SDA)
SDA_O
27
38
O
Serial data open drain output for the I2C interface. When tied to the SDA_I pin, this connection
becomes the standard bi-directional serial data line (SDA). This is a open drain output that can
directly drive opto-coupler.
WD_DIS
22
43
I
The WD_DIS pin disables the watchdog timer function when connected to 3.3 V. The pin has internal
50-k. resistor to digital ground. The watchdog timer monitors the I2C clock pin (SCL) and the internal
oscillator activity in power management mode and only the internal oscillator activity in auto mode.
INTB
20
45
O
This is an open-drain output that goes low if a fault condition occurs on any of the 4 ports.
ALTA/B
21
44
I
When this input is set to logic low there is no back-off time after a discovery failure. When this pin set
to a logic high there is a back-off time (approximately 2 seconds) before initiating another discovery
cycle. This pin has an internal 50-kΩ resistor pull-down to digital ground.
A1
28
37
I
A2
29
36
I
A3
30
35
I
A4
31
34
I
A5
32
33
I
MS
PORB
63
62
2
3
Address 1 through 5 These are the I2C address select inputs. Select the appropriate binary address
on these pins by connecting to the chip ground for a logic low or tying to the V3.3 pin for a logic high.
Each address line has an internal current source pull-down to digital ground.
I
The MS pin selects either the auto mode (MS low) or the power management mode, PMM, (MS
high). This pin can be held low for controller-less standalone applications. When MS is low and the
POR timing cycle is complete the chip will sequentially Discover, Classify and Power on each port.
When MS is set high the ports are controlled by register setting via the I2C bus. The MS pin has an
internal 50-kΩ resistor pull-down to analog ground.
I
This pin can be used to override the internal POR. When held low, the I2C interface, all the state
machines, and registers are held in reset. When all internal and external supplies are within
specification, and this pin is set to a logic high level, the POR delay will begin. The I2C interface and
registers will become active within 70µs of this event and communications to read or preset registers
can begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin has
an internal 50-kΩ resistor pull-down to analog ground.
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TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
CONNECTION DIAGRAM
TPS23841
64 Pin Power Pad
TQFP_PAP
10
(1)
NIC = No internal connection. Pins are floating.
(2)
NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from
unused pins.
(3)
NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
POWERPAD
OUTLINE
LASER MARKER
PIN 1 IDENTIFIER
TOP VIEW
TPS23841
64 PIN POWER PAD
UP
TQFP - PJD
(1)
NIC = No internal connection. Pins are floating.
(2)
NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from
unused pins.
(3)
NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
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TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
AUTO MODE FUNCTIONAL DESCRIPTION
Auto Mode
Auto mode (AM, MS = 0) operation is the basic approach for applying power to IEEE compliant PD’s. When AM
has been selected the TPS23841 automatically performs the following functions:
• Discovery of IEEE 802.3af compliant powered devices (PD's)
• Classification
• Power delivery
• Port over/under voltage detection, (if enabled, see Over/Under Voltage Fault section)
• Port over current detection (570 mA < IPORT < 665 mA
• Port maximum current limit (600 mA < IPORT < 700 mA)
• DC Disconnect (5 mA < IPORT < 10 mA)
• Thermal shutdown protection (TSD), (TJ > 150°C)
• Internal oscillator watchdog
In AM the contents of all read registers are available via the I2C interface. In addition all control registers except
for the function bits can be written. This supports a semi-auto mode where the TPS23841 auto detects compliant
PD's while a host can access the A/D registers and class information and then implement power management
(including turning a port off, responding to faults, etc).
The write registers that are still active in AM are:
• All ports disable – Common Control register 0001b
• Over/Under Voltage Faults – Common Control register 0001b
• Software reset – Common Control register 0001b
• Disconnect disable – Port Control 1 register 0010b
• Discovery fault disable – Port Control 1 register 0010b
• Port enable – Port Control 2 register 0011b
For alternative B, semi-auto mode implementations which will manipulate the all ports disable or Port Enable
bits, please contact the factory for additional application information.
12
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TPS23841
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SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
AUTO MODE FUNCTIONAL DESCRIPTION (continued)
Auto Mode Functional Description
Update
Class Register
PortPwr
Update Reg
OVI = Over Current Fault
U/O V = Under or Over Voltage Fault
TSD = Thermal Shutdown Fault
TMPDO = PD Maintain Power Dropout Time Limit
TED = Error Delay Timing
A2D V/I
Measurements
300 ms
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