Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
TPS2384 Quad Integrated Power Sourcing Equipment Power Manager
1 Features
3 Description
•
The TPS2384 is a quad-port power sourcing
equipment power manager (PSEPM) and is compliant
to the Power-over-Ethernet (PoE) IEEE 802.3af
standard. The TPS2384 operates from a single 48-V
supply and over a wide temperature range (–40°C to
125°C). The integrated output eliminates two external
components per port (FET and sense resistor) and
will survive 100-V transients. Four individual 15-bit
A/D converters are used to measure port resistance,
voltage, current and die temperature making PSE
solutions simple and robust. The TPS2384 comes
with a comprehensive software solution to meet the
most demanding applications which can serve as a
core for all PoE system designs.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Quad-Port Power Management With Integrated
Switches and Sense Resistors
Compliant to IEEE 802.3af Standard
Operates from a Single 48-V Input Supply
Individual Port 15-bit A/D
Auto, Semi-Auto and Power Management
Operating Modes
Controlled Current Ramps for Reduced EMI and
Charging of PD's Bulk Capacitance
I2C Clock and Oscillator Watchdog Timers
Over-Temperature Protection
DC and DC Modulated Disconnect
Supports Legacy Detection for Non-Compliant
PD's
Supports AC Disconnect
High-Speed 400-kHz I2C Interface
Comprehensive Power Management Software
Available
Operating Temperature Range –40°C to 125°C
TheTPS2384 is available in either 64-pin
PowerPAD™ down (PAP) or 64-pin PowerPAD™ up
(PJD) packages.
Device Information(1)
PART NUMBER
TPS2384
PACKAGE
HTQFP (64)
BODY SIZE (NOM)
10.0mm x 10.0mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
Ethernet Enterprise Switches
Ethernet Hubs
SOHO Hubs
Ethernet Mid-Spans
PSE Injectors
4 Typical Application
RJ45
Up to 100 m
RJ45
of CAT 5
PSE
Spare Pair
+48 V
TPS2384
Optional
MSP430
MicroController
TPS2375
Singnal Pair
SCL
SDA - I
SDA - O
ILIM
CLASS
DC/DC
Converter
Singnal Pair
+48 V
Return
Spare Pair
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
1
2
3
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Timing Requirements ............................................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagrams ..................................... 13
9.3
9.4
9.5
9.6
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps ........................................................
14
15
31
34
10 Application and Implementation........................ 43
10.1 Application Information.......................................... 43
10.2 Typical Application ............................................... 44
11 Power Supply Recommendations ..................... 46
12 Layout................................................................... 47
12.1 Layout Guidelines ................................................. 47
12.2 Layout Example .................................................... 47
12.3 Thermal Consideration.......................................... 48
13 Device and Documentation Support ................. 49
13.1
13.2
13.3
13.4
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
14 Mechanical, Packaging, and Orderable
Information ........................................................... 49
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2007) to Revision E
Page
•
Added ESD Rating table, Thermal Information table Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Changed text in the description of pins A1-A5 From: "connecting to chip ground" To: "connecting to digital ground" ......... 6
•
Changed the first 5 rows in the Digital I2C DC Spec3ifications of the Electrical Characteristics ........................................... 9
•
Added values for Discovery1,2 A/D conversion time in Timing Requirements TYP = 18, MAX = 22 ms.............................. 9
•
Changed text in the Auto Mode From: "please contact the factory for additional application information." To: "refer to
(SLUZ014)". .......................................................................................................................................................................... 15
•
Changed text in Start/Stop from "and not used by the TPS2384." To: (See Note
•
Changed text in the first sentence of Chip Address ............................................................................................................ 32
•
Added Note
•
Changed text in Note 2 of Table 5 From: "Consult factory for Alternative B,." To: "refer to (SLUZ014) "for Alternative
B,." ........................................................................................................................................................................................ 37
•
Changed text in Note 2 of Table 7 From: "Consult factory for Alternative B,." To: "refer to (SLUZ014) "for Alternative
B,." ........................................................................................................................................................................................ 38
•
Changed the connections to pins 50 and 51 in Figure 40 ................................................................................................... 44
(1)
2
(1)
(1)
in Table 1) ........................................ 32
to Table 1 .................................................................................................................................................... 33
TPS2384 will acknowledge four slave address values for each setting of A5-A1 (A7,A6 = 00, 01, 10, 11). Slave devices sharing the bus
with TPS2384(s) should use unique A5-A1 values not matching those of the TPS2384(s).
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
6 Pin Configuration and Functions
PAP Package
64-Pin HTQFP
Top View
(1)
NIC = No internal connection. Pins are floating.
(2)
NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from
unused pins.
(3)
NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
3
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
PJD Package
64-Pin HTQFP
Top View
PowerPAD
OUTLINE
LASER MARKER
PIN 1 IDENTIFIER
4
(1)
NIC = No internal connection. Pins are floating.
(2)
NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from
unused pins.
(3)
NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
Pin Functions
PIN
NAME
NO.
PAP
I/O
DESCRIPTION
PDJ
Power and Ground
V48
60
5
I
48-V input to the device. This supply can have a range of 44 to 57 V. This pin should be decoupled
with a 0.1-μF capacitor from V48 to AG1 placed as close to the device as possible.
V10
58
7
O
10-V analog supply. The 10-V reference is generated internally and connects to the main internal
analog power bus. A 0.1-μF de-coupling capacitor should terminate as close to this node and the AG1
pin as possible. Do not use for an external supply.
V6.3
59
6
O
6.3-V analog supply. A 0.1-μF de-coupling capacitor should terminate as close to this pin and the
AG1 pin as possible. Do not use for an external supply.
V3.3
24
41
O
3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power
bus. A 0.1-μF de-coupling capacitor should terminate as close to this node and the DG pin as
possible. This output can be used as a low current supply to external logic.
V2.5
54
11
O
2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power
bus. This pin should not be tied to any external supplies. A 0.1-μF de-coupling capacitor should
terminate as close to this node and the RG pin as possible. Do not use for an external supply.
AG1
57
8
Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be
GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three
de-coupling capacitors tied to V48, V10 and V6.3.
AG2
61
4
Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the
GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be
tied together directly for the best noise immunity.
DG
23
42
GND
9
Reference ground. This is a precision sense of the external ground plane. The integration capacitor
(CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be
GND
used to form a printed wiring board ground guard ring around the active node of the integration
capacitor (CINT). It should tie to common copper 48-V return plane.
RG
56
Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the
common copper 48-V return plane.
Port Analog Signal
P1
7
58
I
P2
10
55
I
P3
39
26
I
P4
42
23
I
N1
6
59
I
N2
11
54
I
N3
38
27
I
N4
43
22
I
RET1
5
60
I
RET2
12
53
I
RET3
37
28
I
RET4
44
21
I
CINT1
4
61
I
CINT2
13
52
I
CINT3
36
29
I
CINT4
45
20
I
Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with
respect to each Port N pin. Optionally, if the application warrants, this high-side path can be protected
with the use of a self-resetting poly fuse.
Port negative. 48-V load return pin. The low side of the load is switched and protected by internal
circuitry that limits the current.
48 V return pin.
Integration capacitor This capacitor is used for the ramp A/D converter signal integration. Connect A
0.027- μF capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene,
polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with
increased conversion error.
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
5
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
Pin Functions (continued)
PIN
NO.
NAME
PAP
I/O
DESCRIPTION
PDJ
Analog Signals
This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When
the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description).
CT
53
12
I
The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the device.
This internal clock is used for the internal state machine, integrating A/D counters, POR time out,
faults and delay timers of each port. Using a 220-pF capacitor for CT and a 124-kΩ resistor for RBIAS
sets the internal clock to 245 kHz and ensure IEEE 802.3af compliance along with maximizing the
rejection of 60-Hz line frequency noise from A/D measurements.
Bias set resistor. This resistor sets all precision bias currents within the chip. This pin will regulate to
1.25V (V2.5/2) when a resistor is connected between RBIAS and RG. This voltage and RBIAS
generate a current which is replicated and used throughout the chip. This resistor also works in
conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistor
should be connected RG. RBIAS is a high impedance input and care needs to be taken to avoid
signal injection from the SYN pin or I2C signals.
RBIAS
55
10
I
SYN
52
13
I/O
This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0 V
to 3.3V pulse of the internal clock which can be used to drive other TPS2384 SYN pins for elimination
of a timing capacitor. When the CT pin is grounded this pin becomes an input pin that can be driven
from a master TPS2384 or any other clock generator signal.
AC_LO
51
14
O
Totem-pole output pin for AC Disconnect excitation.
AC_HI
50
15
O
Totem-pole output pin for AC Disconnect excitation.
Digital Signals
SCL
25
40
I
Serial clock input pin for the I2C interface.
SDA_I
26
39
I
Serial data input pin for the I2C interface. When tied to the SDA_O pin, this connection becomes the
standard bi-directional serial data line (SDA)
SDA_O
27
38
O
Serial data open drain output for the I2C interface. When tied to the SDA_I pin, this connection
becomes the standard bi-directional serial data line (SDA). This is a open drain output that can
directly drive opto-coupler.
WD_DIS
22
43
I
The WD_DIS pin disables the watchdog timer function when connected to 3.3 V. The pin has internal
50-kΩ resistor to digital ground. The watchdog timer monitors the I2C clock pin (SCL) and the internal
oscillator activity in power management mode and only the internal oscillator activity in auto mode.
INTB
20
45
O
This is an open-drain output that goes low if a fault condition occurs on any of the 4 ports.
ALTA/B
21
44
I
When this input is set to logic low there is no back-off time after a discovery failure. When this pin set
to a logic high there is a back-off time (approximately 2 seconds) before initiating another discovery
cycle. This pin has an internal 50-kΩ resistor pull-down to digital ground.
A1
28
37
I
A2
29
36
I
A3
30
35
I
A4
31
34
I
A5
32
33
I
MS
PORB
6
63
62
2
3
Address 1 through 5 These are the I2C address select inputs. Select the appropriate binary address
on these pins by connecting to digital ground for a logic low or tying to the V3.3 pin for a logic high.
Each address line has an internal current source pull-down to digital ground.
I
The MS pin selects either the auto mode (MS low) or the power management mode, PMM, (MS high).
This pin can be held low for controller-less standalone applications. When MS is low and the POR
timing cycle is complete the chip will sequentially Discover, Classify and Power on each port. When
MS is set high the ports are controlled by register setting via the I2C bus. The MS pin has an internal
50-kΩ resistor pull-down to analog ground.
I
This pin can be used to override the internal POR. When held low, the I2C interface, all the state
machines, and registers are held in reset. When all internal and external supplies are within
specification, and this pin is set to a logic high level, the POR delay will begin. The I2C interface and
registers will become active within 70 μs of this event and communications to read or preset registers
can begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin has
an internal 50-kΩ resistor pull-down to analog ground.
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
V10 current sourced
V3.3 current sourced
MIN
MAX
UNIT
100
100
μA
mA
5
5
–0.5 to 10
10
Applied voltage on SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, MS, PORB, WD_DIS,
ALT_A/B, AC_LO, AC_HI
–0.5
6
Applied voltage on CINT#, CT, RBIAS
V
Applied voltage on V48, P#, N#
–0.5
80
TJ
Junction operating temperature
–40
125
Tstg
Storage temperature -55 to 150
–55
150
(1)
(2)
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±100
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VDD
Input voltage, V48
TJ
Junction temperature
MIN
TYP
MAX
44
48
57
V
125
°C
-40
UNIT
7.4 Thermal Information
THERMAL METRIC (1)
PAP [HTQFP]
PJD [HTQFP]
64 PINS
64 PINS
RθJA
Junction-to-ambient thermal resistance
23.9
30.1 (2)
RθJC(top)
Junction-to-case (top) thermal resistance
8.4
0.3
RθJB
Junction-to-board thermal resistance
6.9
7.4
ψJT
Junction-to-top characterization parameter
0.2
0.2
ψJB
Junction-to-board characterization parameter
6.8
7.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.2
N/A
(1)
(2)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RθJA will vary with the heat sink used. Data modeled using 15 mm x 15 mm x 5 mm copper block heat sink.
7.5 Electrical Characteristics
V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 μF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
V48 quiescent current
Off mode (all ports)
V48 quiescent current
Powered mode (all ports)
4
9
12
10
14
V10, internal analog supply
ILOAD = 0
V3.3, internal digital supply
ILOAD = 0 to 3 mA
9.75
10.5
11.5
3
3.3
3.7
V3.3 short circuit current
V=0
3
12
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
mA
V
mA
7
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
Electrical Characteristics (continued)
V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 μF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V6.3, internal supply
ILOAD = 0
5
6.3
7
V2.5, internal reference supply
ILOAD = 0
2.46
2.5
2.54
26
32
Input UVLO
Internal POR time out(I2C)
After all supplies are good I2C activity is valid
Internal POR time out (Port)
After all supplies are good Port active to I2C commands
8
UNIT
V
Clock
Pulses
66000
Port Discovery
Port off #P to #N input resistance
400
600
2.8
4.4
Discovery open circuit voltage
kΩ
22
Discovery 1 voltage loop control
70 μA < IPORT < 3 mA
Discovery 2 voltage loop control
70 μA < IPORT < 3 mA
Discovery current limit
P = N = 48 V
Auto-mode discovery resistance
acceptance Band
3
30
V
8.8
10
4
5
19
26.5
Auto-mode discovery resistance low end
rejection
0
15
Auto-mode discovery resistance high end
rejection
33
Discovery1,2 A/D conversion scale factor
100 μA < IPORT < 3 mA
5.30
6.10
mA
kΩ
6.75 count/μA
Port Classification
Classification voltage loop controll
100 μA < IPORT < 50 mA
15
17.5
20
Classification current limit
P = N = 48 V
50
60
100
V
Class 0 to 1 detection threshold
5.5
6.5
7.5
Class 1 to 2 detection threshold
13
14.5
16
Class 2 to 3 detection threshold
21
23
25
Class 3 to 4 detection threshold
31
33
35
Class 4 to 0 detection threshold
45
48
51
375
424
475
Count/
mA
2.6
3.5
4.3
mA
1365
1400
1445
1.3
1.8
375
400
425
450
7.5
10
Classification A/D conversion scale factor
mA
Port Legacy Detection
Legacy current limit
P = N = 48 V
Legacy voltage A/D conversion scale
factor
100 mV < VPORT < 17.5 V
Count/V
Port Powered Mode
Port on resistance
Over current threshold (ICUT)
Output current limit (ILIM)
Disconnect timer current threshold
20 mA < IPORT < 300 mA
RBIAS = 124 kΩ, CT = 220 pF, –25 ≤ TJ ≤ 105
350
RBIAS = 124 kΩ, CT = 220 pF
Ω
mA
Port output UV
42.0
42.7
44.0
Port output OV
54
55
56
31
36.41
40
Count/
mA
335
353
370
Count/V
Port current A/D conversion scale factor
20 mA < IPORT < 56 V
Port voltage A/D conversion scale factor
45 V < VPORT < 56 V
Port temperature A/D conversion
(17500 - counts)/16
V
°C
Port Disable Mode
Port N voltage
8
P = 48 V
47
Submit Documentation Feedback
V
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
Electrical Characteristics (continued)
V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 μF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC LO and AC HI Specification
AC_LO, AC_HI – low output voltage
0
0.5
AC_LO – high output voltage
3.0
5.0
AC_HI – high output voltage
5.0
7.0
V
Digital I2C DC Specifications
SCL logic low input threshold (VIL)
SDA_I logic low input threshold (VIL)
0.5
V
1.25
V
SCL, SDA_I logic high input threshlod (VIH)
1.75
V
A1–A5 ,WD_DIS, ALTA/B, MS, PORB logic input threshold
1.5
V
MS, PORB input hysteresis
150
V
50
kΩ
WD_DIS,ALTA/B, MS, PORB input
pulldown resistance
Input voltage 0.5 to 3 V
10
μA
SDA_O logic high leakage
Drain = 5 V
100
nA
SDA_O logic low
ISINK = 10 mA
200
mV
INTB logic high leakage
Drain = 6 V
INTB logic low
ISINK = 10 mA
A1–A5 pull-down current
10
μA
200
mV
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
IPORT= 120 μA
18
22
ms
IPORT = 50 mA
18
22
ms
0 V < VPORT < 15 V
18
22
ms
300
400
ms
Port Discovery
Discovery1,2 A/D conversion time
Port Classification
Classification A/D conversion time
Port Legacy Detection
Legacy A/D conversion time
Port Powered Mode
tMPDO, disconnect detection time
RBIAS = 124 kΩ, CT = 220 pF, ILOAD <
current threshold
Over current time out (TOVLD)
RBIAS = 124 kΩ, CT = 220 pF
50
75
Short circuit time out (TLIM)
RBIAS = 124 kΩ, CT = 220 pF
50
75
Turn--off delay from UV/OV faults
RBIAS = 124 kΩ, CT = 220 pF, After port
enabled and ramped up
Port curent A/D conversion time
IPORT < 300 mA
18
22
ms
Port voltage A/D conversion time
45 V < VPORT < 56 V
18
22
ms
400
kHz
ms
3
Digital I2C Timing
SCL clock frequency, fSCL
0
Pulse duration, tHIGH
SCL high
0.6
Pulse duration, tLOW
SCL low
1.3
Rise time, SCL and SDA, tr
0.300
Fall time, SCL and SDA, tf
0.300
Setup time, SDA to SCL, tSU;DAT
0.250
Hold time, SCL to SDA, tHD;DAT
0.300
Bus free time between start and stop, tBUF
1.3
Setup time, SCL to start condition, tSU;STA
0.6
Hold time, start condition to SCL, tHD;STA
0.6
Setup time, SCL to stop condition, tSU;STO
0.6
0.900
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
μs
9
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
7.7 Typical Characteristics
10
Figure 1. Invalid (33 kΩ and 15 kΩ) and
Valid Discovery (25 kΩ)
Figure 2. Four Port Discovery, Class, Power On
Figure 3. Port Over-current Response
Figure 4. Port Under-current Response in DC Disconnect
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
8 Parameter Measurement Information
tr
SDAI/
SDAO
tf
tLOW
tr
tHD,STA
tHIGH
tSU,DAT
tBUF
tf
SCL
Start Condition
tHD,DAT
tSU,STA
Repeated Start
Condition
tSU,STO
Stop Condition
Start Condition
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
11
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
9 Detailed Description
9.1 Overview
The TPS2384 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply.
These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought out
separately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for powering
external loads up to 2 mA. For more demanding loads it is highly recommended to use external buffers to
prevent system degradation. When the TPS2384 is initially powered up an internal Power-on-Reset (POR) circuit
resets all registers and sets all ports to the off state to ensure that the device is powered up in a known safe
operating state.
The TPS2384 has three modes of operation; automode (AM), semi-automode (SAM) and power management
mode (PMM).
• In auto mode the TPS2384 performs discovery, classification and delivery of power autonomously to a
compliant PD without the need of a micro-controller.
• In semi-automode the TPS2384 operates in automode but users can access the contents of all read status
registers and A/D registers through the I2C serial interface. All write control registers are active except for D0
through D3 of Port Control register 1 (Address 0010) for limited port control. The semi-auto mode allows the
TPS2384 to detect valid PD's without micro-controller intervention but adds a flexibility to perform power
management activities.
• Power management mode (with a micro-controller) allows users additional capabilities of discovering noncompliant (legacy) PDs, performing AC Disconnect and advanced power management system control that are
based on real time port voltages and currents. All functions in this mode are programmed and controlled
through read/write registers over the I2C interface. This allows users complete freedom in detecting and
powering devices. A comprehensive software package is available that mates the power of the TPS2384 with
the MSP430 micro-controller.
TPS2384 integrated output stage provides port power and low-side control. The internal low-side circuitry is
designed with internal current sensing so there are no external resistors required. The output design ensures the
power switches operate in the fully enhanced mode for low power dissipation.
The I2C interface allows easy application of opto-coupler circuitry to maintain Ethernet port isolation when a
ground based micro-controller is required. The TPS2384 five address pins (A1–A5) allow the device to be
addressed at one of 31 possible I2C addresses. Per-port write registers separately control each port state
(discovery, classification, legacy, power up, etc) while the read registers contain status information of the entire
process along with parametric values of discovery, classification, and real-time port operating current, voltage
and die temperature.
The proprietary 15-bit integrating A/D converter is designed to meet the harsh environment where the PSEPM
resides. The converter is set for maximum rejection of power line noise allowing it to make accurate
measurements of line currents during discovery, classification and power delivery for reliable power management
decisions.
12
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
9.2 Functional Block Diagrams
Diff Amp
(Fix Gain)
UV/OV
Comparators
600 kW
Two
8 Bits
Status
Register
Loop Cntri Amp
Detect/Class Modes
Two
8 Bits
Status
Register
Auto
Seq
Logic
Analog
Control
Circurty
LCA
Power Mode
Thermal
Detector
A2D
Registers
Resistor
Voltage
Current
&
Die Temp
Max I
Thld
OVI
OVI
Thld
Figure 5. Single Port Block Diagram
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
13
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
Functional Block Diagrams (continued)
NOTE: A fuse may be required to provide additional protection if isolation is lost or the low-side current sense fails.
Figure 6. System Block Diagram
9.3 Feature Description
9.3.1 PMM Faults
PMM faults are the same as those shown in the AM Faults and INTB Output section. In PM mode, the port
under- and overvoltage and under-current faults can be disabled by writing to the control bits in the appropriate
register. Monitoring for these fault conditions is enabled by default after device POR or other reset operation. The
enable state of these features can be toggled by writing to the corresponding control bit as defined below and in
Table 4 and Table 5.
The PMM faults are:
• Port under- and over-voltage faults (disable via Common Control register 0001b, bit D2)
• Overcurrent fault (cannot be disabled)
• Under-current (DC Disconnect) fault (disable via Port Control register 0010b, bit D4)
• Thermal shutdown (TSD) fault (cannot be disabled)
• Watchdog fault (disable via WD_DIS pin)
Any one of these faults causes the port to shutdown. Once a fault has occurred the port can not be repowered
until a Disable function is sent. The Disable function clears the fault latch and the fault register.
INTB pin operation is essentially the same in PMM as in AM, with the following exceptions:
14
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
TPS2384
www.ti.com
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
Feature Description (continued)
•
•
For load under-current to generate a fault shutdown and status indication, the condition of load current less
than the threshold must be detected by the continuous sample (C_SAMPLE) function (0111b).
In PMM only, a Watchdog timer fault also asserts INTB.
9.3.2 Watchdog Timer
TPS2384 has two watchdog timers. One monitors the I2C clock and the other monitors the internal clock. When
automode is selected and the watchdog timer has not been disabled only the internal clock ismonitored. When in
power management mode and the watchdog timer has not been disabled then both the I2C and internal clocks
are monitored. If there is no I2C clock activity for approximately two seconds then all ports are disabled. There
are three means to enable ports after a I2C clock fault and they are:
1. Hard power reset
2. PORB pulse
3. Writing a software reset to the Common Control register
In both auto mode and power management mode if the internal oscillator is lost for more than 20 ms all ports are
disabled.
Loss of these signals is considered catastrophic since the system loses its ability to talk to each port. Therefore
the watchdog timers disabling all ports protects the system.
This function can be easily over ridden by setting the WD_DIS pin high.
9.4 Device Functional Modes
9.4.1 Auto Mode
Auto mode (AM, MS = 0) operation is the basic approach for applying power to IEEE compliant PD’s. When AM
has been selected the TPS2384 automatically performs the following functions:
• Discovery of IEEE 802.3af compliant powered devices (PD's)
• Classification
• Power delivery
• Port over/under voltage detection
• Port over current detection (350 mA < IPORT < 400 mA
• Port maximum current limit (400 mA < IPORT < 450 mA)
• DC Disconnect (5 mA < IPORT < 10 mA)
• Thermal shutdown protection (TSD), (TJ > 150°C)
• Internal oscillator watchdog
In AM the contents of all read registers are available via the I2C interface. In addition all control registers except
for the function bits can be written. This supports a semi-automode where the TPS2384 auto detects compliant
PD's while a host can access the A/D registers and class information and then implement power management
(including turning a port off, responding to faults, etc).
The write registers that are still active in AM are:
• All ports disable – Common Control register 0001b
• Over/Under Voltage Faults – Common Control register 0001b
• Software reset – Common Control register 0001b
• Disconnect disable – Port Control 1 register 0010b
• Discovery fault disable – Port Control 1 register 0010b
• Port enable – Port Control 2 register 0011b
For Alternative B, semi-auto mode implementations which will manipulate the all Ports Disable or Port Enable
bits, refer to (SLUZ014).
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TPS2384
15
TPS2384
SLUS634E – NOVEMBER 2004 – REVISED MARCH 2015
www.ti.com
Device Functional Modes (continued)
9.4.2 Auto Mode Functional Description
Update
Class Register
PortPwr
Update Reg
OVI = Over Current Fault
U/O V = Under or Over Voltage Fault
TSD = Thermal Shutdown Fault
TMPDO = PD Maintain Power Dropout Time Limit
TED = Error Delay Timing
300 ms
工商网监
湘ICP备2023018690号
