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TPS23861
SLUSBX9I – MARCH 2014 – REVISED JULY 2019
TPS23861 IEEE 802.3at Quad Port Power-over-Ethernet PSE Controller
1 Features
3 Description
•
The TPS23861 is an easy-to-use, flexible,
IEEE802.3at PSE solution. As shipped, it
automatically manages four 802.3at ports without the
need for any external control.
1
•
•
•
•
•
•
•
•
IEEE 802.3at Quad Port PSE controller
– Auto Detect, classification
– Auto Turn-On and disconnect
– Efficient 255-mΩ sense resistor
Pin-Out enables Two-Layer PCB
Kelvin Current Sensing
4-Point detection
Automatic mode – as shipped
– No External terminal setting required
– No Initial I2C communication required
Semi-Automatic mode – set by I2C command
– Continuous Identification and Classification
– Meets IEEE 400-ms TPON specification
– Fast-Port shutdown input
– Operates best when used in conjunction with
system reference code
http://www.ti.com/product/TPS23861/toolssoftw
are
Optional I2C control and monitoring
–40°C to 125°C Temperature range
TSSOP 28 Package 9.8 mm x 6.6 mm
The TPS23861 automatically detects Powered
Devices (PDs) that have a valid signature, determines
power requirements according to classification and
applies power. Two-event classification is supported
for type-2 PDs. The TPS23861 supports DC
disconnection and the external FET architecture
allows designers to balance size, efficiency and
solution cost requirements.
The unique pin-out enables 2-layer PCB designs via
logical grouping and clear upper and lower
differentiation of I2C and power pins. This delivers
best-in-class thermal performance, Kelvin accuracy
and low-build cost.
In addition to automatic operation, the TPS23861
supports Semi-Auto Mode via I2C control for precision
monitoring and intelligent power management.
Compliance with the 400-ms TPON specification is
ensured whether in semi-automatic or automatic
mode.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
TPS23861
Ethernet switches and routers
Surveillance NVR and DVRs
Residential gateways
PoE Pass-Through systems
Wireless backhaul
BODY SIZE
9.80 mm x 6.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TOP CONDUCTORS
Simplified Schematic
3.3 V
PACKAGE
TSSOP (28)
FETs Uniformly Spread Over Surface
48 V
100 nF
100 V
VDD VPWR
PORTn
47
RESET
DRAINn
SHTDWN
GATEn
22
SENn
TPS23861
255 m
BOTTOM GND PLANE
Continuous, Robust Backside GND Plane
A3
KSENSx
SCL
INT
SDAI
AIN
SDAO
AGND DGND
AOUT
Note: only port n shown
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS23861
SLUSBX9I – MARCH 2014 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 11
Switching Characteristics ........................................ 12
Typical Characteristics ............................................ 16
Detailed Description ............................................ 21
7.1
7.2
7.3
7.4
7.5
8
1
1
1
2
5
6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Map – I2C-Addressable ............................
21
25
25
40
45
Application and Implementation ........................ 85
8.1
8.2
8.3
8.4
9
Introduction to PoE .................................................
Application Information............................................
Typical Application ..................................................
System Examples ...................................................
85
85
87
93
Power Supply Recommendations...................... 97
9.1 VDD......................................................................... 97
9.2 VPWR ..................................................................... 97
9.3 VPWR-RESET Sequencing .................................... 97
10 Layout................................................................... 98
10.1 Layout Guidelines ................................................. 98
10.2 Layout Example .................................................... 99
11 Device and Documentation Support ............... 100
11.1 Documentation Support .....................................
11.2 Receiving Notification of Documentation
Updates..................................................................
11.3 Community Resources........................................
11.4 Trademarks .........................................................
11.5 Electrostatic Discharge Caution ..........................
11.6 Glossary ..............................................................
100
100
100
100
100
100
12 Mechanical, Packaging, and Orderable
Information ......................................................... 100
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (November 2017) to Revision I
•
Page
Added figure titles to the Application Curves........................................................................................................................ 92
Changes from Revision G (October 2016) to Revision H
Page
•
Deleted "or unknown" from Auto subsection ........................................................................................................................ 42
•
Deleted "and Auto Modes" from TSTART Indicators of Detect and Class Failures subsection........................................... 44
•
Changed fault conditions for Auto mode in Detect and Class Failure Indicators table ........................................................ 44
•
Added information to Step 2 in Start/ILIM Event Register subsection ................................................................................. 53
Changes from Revision F (July 2016) to Revision G
•
Page
Deleted the MAX value of 150 mA from IGO- in the Electrical Characteristics ........................................................................ 8
Changes from Revision E (March 2016) to Revision F
Page
•
Legacy Device Detection, Changed the paragraph, "in general,..." ..................................................................................... 30
•
Changed section From: Independent Operation when the Bit is Set To: Independent Operation when the AUTO Bit
is Set..................................................................................................................................................................................... 34
•
I2C Slave Address and AUTO Bit Programming, Added NOTE: "When using I2C scan...".................................................. 37
•
Start/ILIM Event Register, Changed the third list item From: "Detect fault or classification unknown,.." To:
"Overcurrent or class mismatch on second finger in Semi-Auto or Manual Mode." ........................................................... 53
•
Timing Configuration Register, Added new NOTE under TLIM[1:0]: " If ILIM and ICUT are set to same value..." ............ 61
•
Timing Configuration Register, Added new NOTE under TICUT[1:0]: " If ILIM and ICUT are set to same value..." .......... 62
•
Two-Event Classification Register, Changed the second list item to include: "CLEn is set or a" ....................................... 67
2
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•
SLUSBX9I – MARCH 2014 – REVISED JULY 2019
Replaced Figure 58 .............................................................................................................................................................. 95
Changes from Revision D (September 2015) to Revision E
Page
•
Added note in Features, "Semi-Automatic Mode " ................................................................................................................. 1
•
Updated Pin Functions table .................................................................................................................................................. 5
•
Added new Figure 37 .......................................................................................................................................................... 22
•
Added new Functional Block Diagram.................................................................................................................................. 25
•
Changed note in A/D Converter and I2C Interface .............................................................................................................. 32
•
Changed the Note in I2C Slave Address and AUTO Bit Programming ................................................................................ 35
•
Added note to I2C Slave Address and AUTO Bit Programming .......................................................................................... 35
•
Changed I2C slave address register note............................................................................................................................. 35
•
Added new Figure 43 ........................................................................................................................................................... 39
•
Added a note to Manual about type 2 power 2 event classification. .................................................................................... 40
•
Added content to Semi-Auto................................................................................................................................................. 41
•
Added "PoEPn" column to Bits Description.......................................................................................................................... 70
•
Added a note to PoE Plus Register ..................................................................................................................................... 77
Changes from Revision C (June 2015) to Revision D
Page
•
Added reference note to Figure 5 and Figure 6 ................................................................................................................... 15
•
Changed RESET note to add addition reference link. ........................................................................................................ 23
•
Added SDAO pin note. ........................................................................................................................................................ 24
•
Changed I2C Slave Address and AUTO Bit Programming note. ......................................................................................... 35
•
Added Figure 42, I2C/SMBus Interface Slave Address Programming Protocol. ................................................................. 38
•
Added note 3 to Table 10 ..................................................................................................................................................... 45
•
Changed Connections on Unused Ports section.................................................................................................................. 86
•
Added reference link to the VPWR-RESET Sequencing note. ............................................................................................ 97
Changes from Revision B (April 2015) to Revision C
Page
•
Added Figure 5 and Figure 6................................................................................................................................................ 15
•
Changed Figure 36, Disconnected AIN pin from GND......................................................................................................... 22
•
Added SHTDWN note. ......................................................................................................................................................... 23
•
Added RESET note. ............................................................................................................................................................ 23
•
Added Device Power On Initialization section...................................................................................................................... 44
•
Added note 2 to Table 10 ..................................................................................................................................................... 45
•
Added Port n Status Register note....................................................................................................................................... 55
•
Added Operating Mode Register Command note. .............................................................................................................. 58
•
Added Operating Mode Register Bit Description note. ........................................................................................................ 58
•
Added Detect/Class Enable Register Command note. ....................................................................................................... 59
•
Added Detect/Class Restart Register Command note. ........................................................................................................ 64
•
Added Power Enable Register Command note.................................................................................................................... 65
•
Added Power Enable Register Bit Descriptions note. .......................................................................................................... 65
•
Added Reset Register Command note................................................................................................................................. 66
•
Added Reset Register Bit Descriptions note. ...................................................................................................................... 66
•
Changed Figure 46, Disconnected AIN pin from GND......................................................................................................... 85
•
Changed Figure 48, Disconnected AIN pin from GND......................................................................................................... 87
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•
Changed Figure 49, Disconnected AIN pin from GND......................................................................................................... 88
•
Changed Figure 50, Disconnected AIN pin from GND......................................................................................................... 89
•
Changed QPn description in Per Port Components ............................................................................................................. 90
•
Changed maximum VDD supply current from 10 mA to 6 mA in first paragraph and changed wording in second
paragraph of VDD................................................................................................................................................................. 97
•
Added VPWR-RESET Sequencing ...................................................................................................................................... 97
Changes from Revision A (June, 2014) to Revision B
Page
•
Changed VDD current consumption from 10 mA (MAX) to 6.0 mA (MAX)............................................................................ 7
•
Deleted Processor watchdog trip delay specification. .......................................................................................................... 11
•
Added When using the I2C interface note. .......................................................................................................................... 32
•
Added When using the I2C interface note. .......................................................................................................................... 35
•
Changed FULL SCALE VALUE from 146.2°C to 150°C (typical). ....................................................................................... 71
•
Changed LSB VALUE from 0.652°C to 7°C......................................................................................................................... 71
•
Added Temperature sensor performance note..................................................................................................................... 71
Changes from Original (March 2014) to Revision A
•
4
Page
Added full TPS23861 IEEE 802.3at Quad Port Power-over-Ethernet PSE Controller datasheet. ........................................ 1
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SLUSBX9I – MARCH 2014 – REVISED JULY 2019
5 Pin Configuration and Functions
PW Package
28-Pin TSSOP
Top View
VDD
1
28
VPWR
RESET
2
27
N/C
SCL
3
26
AOUT
SDAI
4
25
AIN
SDAO
5
24
SHTDWN
INT
6
23
A3
DGND
7
22
AGND
SEN3
8
21
GATE2
DRAIN3
9
20
DRAIN2
GATE3
10
19
SEN2
KSENSB
11
18
KSENSA
SEN4
12
17
GATE1
DRAIN4
13
16
DRAIN1
GATE4
14
15
SEN1
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A3
23
I
I2C A3 address line. Internally pulled up to VDD.
AGND
22
P
Analog ground.
AIN
25
I
I2C address programming input line; this pin is internally pulled up to VDD.
AOUT
26
O
I2C address programming line; this output is open drain.
DGND
7
P
Digital ground.
DRAIN3
9
I
DRAIN4
13
I
DRAIN1
16
I
DRAIN2
20
I
GATE3
10
O
GATE4
14
O
GATE1
17
O
GATE2
21
O
INT
6
O
Interrupt; this pin asserts low when a bit in the interrupt register is asserted. This pin is
updated between I2C transactions. This output is open drain.
KSENSA
18
I
Kelvin point connection for SEN1 and SEN2.
KSENSB
11
I
Kelvin point connection for SEN3 and SEN4.
N/C
27
x
Used to effect regulatory voltage-spacing compliance. Leave this pin open.
RESET
2
I
Reset; when asserted low, the device resets. This pin is internally pulled up to VDD.
SCL
3
I
Serial clock input for I2C bus.
SDAI
4
I
Serial data input for I2C bus; this pin can be connected to SDAO for non-isolated systems.
SDAO
5
O
Serial data output for I2C bus; this pin can be connected to SDAI for non-isolated systems.
This output is open drain.
SEN3
8
I
SEN4
12
I
SEN1
15
I
SEN2
19
I
SHTDWN
24
I
Low-priority ports shutdown.
VDD
1
P
Digital 3.3-V supply. Bypass VDD to DGND using a 0.1-μF capacitor.
VPWR
28
P
Analog 48-V supply. Bypass VPWR to AGND using a 0.1-μF capacitor.
Port 1-4 output voltage monitor; connect to output port through a 47-Ω resistor.
Port 1-4 gate-drive output.
Port 1-4 current-sense input; connect to current-sense resistor through a 22-Ω resistor.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature, voltages are referenced to DGND and AGND tied together (unless otherwise noted)
(1)
MIN
MAX
UNIT
Input voltage
VPWR
–0.3
70
V
Input voltage
VDD
–0.3
4
V
Voltage
AGND
–0.3
0.3
V
Voltage
SDAI, SDAO (2), SCL, AIN, AOUT, SHTDWN, RESET, INT, A3 (2)
–0.3
4
V
Output voltage
GATE1-4
–0.3
13
V
Input voltage
SEN1-4 (5), KSENSA, KSENSB
–0.3
3
V
Voltage
DRAIN1-4 (2) (6)
–0.3
70
V
Voltage
N/C pin
0
70
V
Sinking current
INT, SDAO
20
mA
260
°C
150
°C
(3) (4)
Lead temperature 1.6 mm (1/16-inch) from case for 10 seconds
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
(5)
(6)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Do not apply external voltage sources directly.
Application of voltage is not implied – these are internally driven pins.
If there is a short between drain and gate, the GATE pin may internally permanently disconnect to prevent cascade damage. The three
other ports will continue to operate.
SEN1-4 will be tolerant to 15-V transients to avoid fault propagation when a MOSFET fails in short-circuit.
Short transients (µs range) up to 80 V are allowed.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature, voltages are referenced to DGND (unless otherwise noted)
MIN
NOM
MAX
VVDD
3.0
3.3
3.6
VVPWR
44
48
57
V
1
V/µs
Voltage slew rate on DRAIN1-4
UNIT
V
TJ
Operating junction temperature
-40
125
°C
TA
Operating free-air temperature
-40
85
°C
6.4 Thermal Information
TPS23861
THERMAL METRIC (1)
PW (TSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
70.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.2
°C/W
RθJB
Junction-to-board thermal resistance
28.2
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
27.8
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLUSBX9I – MARCH 2014 – REVISED JULY 2019
6.5 Electrical Characteristics
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VPWR
IVPWR
VPWR current consumption
VVPWR = 57 V
VUVLOPW_F
VPWR UVLO falling threshold
Internal oscillator stops operating
VPUV_F
VPWR Undervoltage falling
threshold
VPUV for port de-assertion
VUVLOPW_R
VPWR UVLO rising threshold
3.5
14.5
25
26.5
15.5
7
mA
17.5
V
28
V
18.5
V
INPUT SUPPLY VDD
IVDD
VDD current consumption
VUVDD_F
VDD UVLO falling threshold
VUVDD_R
VDD UVLO rising threshold
VUVDD_HYS
Hysteresis VDD UVLO
For port turn off
5
6
2
2.2
2.4
V
2.4
2.6
2.8
V
(1)
0.4
mA
V
DETECTION
IDET
Detection current
First detection point,
VVPWR – VDRAINn = 0 V
145
160
190
µA
2nd detection point,
VVPWR – VDRAINn = 0 V
235
270
300
µA
High Current detection point,
VVPWR – VDRAINn = 0 V
490
540
585
µA
98
110
118
µA
17.5
19
22
V
ΔIDET
2nd – 1st detection currents
At VVPWR – VDRAINn = 0 V
Vdetect
Open circuit detection voltage
VVPWR – VDRAINn
RREJ_LOW
Rejected resistance low range
0.85
15
kΩ
RREJ_HI
Rejected resistance high range
33
50
kΩ
RACCEPT
Accepted resistance range
19
26.5
kΩ
RSHORT
Shorted port threshold
350
Ω
ROPEN
Open port threshold
25
55
kΩ
CLASSIFICATION
VCLASS
Classification voltage
VVPWR – VDRAINn, VSENn ≥ 0 mV ,
Iport ≥ 180 µA,
ICLASS_Lim
Classification current limit
VVPWR – VDRAINn = 0 V
ICLASS_TH
Classification threshold current
18.5
20.5
70
V
90
mA
Class 0-1
5
8
mA
Class 1-2
13
16
mA
Class 2-3
21
25
mA
Class 3-4
31
35
mA
Class 4- overcurrent
45
51
mA
7
10
V
90
mA
VMARK
Mark voltage
4 mA ≥ Iport ≥ 180 µA, VVPWR –
VDRAINn
IMARK_Lim
Mark sinking current Limit
VVPWR – VDRAINn = 0 V
(1)
15.5
10
70
These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
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Electrical Characteristics (continued)
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12.5
V
GATE
VGOH
Gate drive voltage
VGATEn , IGATE = –1 μA
10
IGO-
Gate sinking current with power-on
reset, shutdown detected or port
turn off command
VGATEn = 5 V
80
100
IGO short–
Gate sinking current with port short- VGATEn = 5 V, VSENn ≥ VSHORT (or
circuit
VSHORT2X if 2x mode)
80
100
150
mA
IGO+
Gate sourcing current
VGATEn = 0 V, IGATE = 0
39
50
63
µA
IGATE = 1
18
25
34
µA
mA
DRAIN INPUT
VPGT
Power good threshold
Measured at VDRAINn
1.0
2.13
3
V
VSHT
Shorted FET threshold
Measured at VDRAINn
4
6
8
V
RDRAIN
Resistance from DRAINn to VPWR
Any operating mode except during
detection or while the port is ON,
including in device reset state
80
100
190
kΩ
IDRAIN
DRAINn pin bias current
1
µA
75
100
µA
0.8
1
ms
VDRAINn = 48 V, port OFF (not in
detection)
VVPWR - VDRAINn = 30 V, port ON
A/D CONVERTER
TCONV
Conversion time , A/D #1 to 4
ADCBW (1)
ADC integration bandwidth (–3
dB) (1)
TINT_CUR
Integration (averaging) time, current Each port, port ON current
TINT_DET
Integration (averaging) time,
detection (1)
0.65
320
80
100
MAINS bit = 0
Hz
125
ms
20
ms
At VVPWR – VDRAINn = 57 V, 0°C to
125°C
15175
15565
15955
Counts
At VVPWR – VDRAINn = 44 V, 0°C to
125°C
11713
12015
12316
Counts
At VVPWR – VDRAINn = 57 V, –40°C
to 125°C
15020
15565
16110
Counts
At VVPWR – VDRAINn = 44 V, –40°C
to 125°C
11594
12015
12436
Counts
Powered port current conversion
scale factor and accuracy
At port current = 770 mA
12300
12616
12932
Counts
At port current = 7.5 mA
90
123
156
Counts
Input voltage conversion scale
factor and accuracy
At VVPWR = 57 V
15175
15565
15955
Counts
At VVPWR = 44 V
11713
12015
12316
Counts
Powered port voltage conversion
scale factor and accuracy
VOS
Powered port voltage conversion
offset
δV/VPORT
Voltage reading accuracy
δI/Iport
Current reading accuracy
8
All ranges, each port current
At VVPWR – VDRAINn = 0.3 V
0
600
At 44 V to 57 V –40°C to 125°C
–3.5%
3.5%
At 44 V to 57 V 0°C to 125°C
–2.5%
2.5%
At 50 mA to 770 mA
–2.5%
2.5%
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SLUSBX9I – MARCH 2014 – REVISED JULY 2019
Electrical Characteristics (continued)
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDRAINn = 0 V, ICUT port n[2:0] =
000, default
90.60
95.37
100.14
mV
VDRAINn = 0 V, ICUT port n[2:0] =
001
26.65
28.05
29.45
mV
VDRAINn = 0 V, ICUT port n[2:0] =
010
49.42
52.02
54.62
mV
VDRAINn = 0 V, ICUT port n[2:0] =
110
156.27
164.5
172.72
mV
VDRAINn = 0 V, ICUT port n[2:0] =
111
222.87
234.6
246.33
mV
PORT CURRENT SENSE
VCUT
δICUT/ICUT
ICUT limit
ICUT tolerance
–5%
At port turn on,
VVPWR – VDRAINn = 1 V
VINRUSH
VLIM
VLIM2X
IInrush limit
ILIM limit with PoEPn = 0
ILIM limit with PoEPn = 1
VSHORT
ISHORT threshold with PoEPn = 0
VSHORT2X
ISHORT threshold with PoEPn = 1
IBIAS
Sense pin bias current
VI(min)
Disconnect threshold
5%
10
23
VVPWR - VDRAINn = 10 V
20
33
VVPWR - VDRAINn = 30 V
102
VVPWR – VDRAINn = 55 V
102
114.7
mV
VDRAINn = 1 V
102
114.7
mV
VDRAINn = 13 V
102
114.7
mV
VDRAINn = 30 V
15
31
mV
23
31
mV
46
mV
114.7
mV
VDRAINn = 48 V
15
23
31
mV
VDRAINn = 1 V
260
270.3
285
mV
VDRAINn = 10 V
127
140
153
mV
VDRAINn = 30 V
15
23
31
mV
VDRAINn = 48 V
15
23
31
mV
140
183
mV
mV
Threshold for GATE to be less than
1 V,
2 μs after application of pulse
357
408
Port ON or during class
-2.25
0
µA
DCTHn = 00, default
1.275
2.55
mV
DCTHn = 01
2.55
5.1
mV
DCTHn = 10
5.1
10.2
mV
DCTHn = 11
8.5
17
mV
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Electrical Characteristics (continued)
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INTERFACE AT VVDD = 3.3 V
VIH
Digital input high
VIL
Digital input low
VIT_HYS
Input voltage hysteresis (SCL,
SDAI, AIN, A3, RESET, SHTDWN)
VOL
Digital output Low, SDAO
IOL = 9 mA
Digital output Low, INT
IOL = 3 mA
Pullup resistor to VDD
RESET, AIN, A3, SHTDWN
Rpullup
2.1
V
0.9
0.17
V
0.4
30
V
50
V
0.4
V
80
kΩ
0.7
V
AOUT OUTPUT
VOL_AOUT
AOUT output low voltage
During slave address programming,
IAOUT = 1 mA
2
EEPROM (I C Slave Address)
nEE_cyc
EEPROM endurance
40 V < VVPWR < 57 V
tWC
Write cycle time (byte or page)
40 V < VVPWR < 57 V
25
cycles
10
100
ms
154
161
°C
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
Hysteresis
10
Temperature rising
(1)
143
8
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6.6 Timing Requirements
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
MIN
TYP
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
10
tLOW
LOW period of SCL clock
1.3
µs
tHIGH
HIGH period of SCL clock
0.6
µs
SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 10 pF, 10-kΩ pullup
to 3.3 V
21
250
ns
SDAO output fall time, SDAO, 2.3 → 0.8 V, Cb = 400 pF, 1.3-kΩ
pullup to 3.3 V
60
250
ns
10
pF
6
pF
tfo
CI2C
SCL capacitance
CI2C_SDA
SDAI, SDAO capacitance
tSU,DATW
Data set-up time (write operation)
100
ns
tSU,DATR
Data set-up time (read operation), SDAO, 2.3 ↔ 0.8 V, Cb = 400 pF,
1.3-kΩ pull up to 3.3 V
600
ns
tHD,DATW
Data hold time (write operation)
0
ns
tHD,DATR
Data hold time (read operation)
150
600
ns
tfSDA
Input fall times of SDAI, 2.3 → 0.8 V
20
250
ns
trSDA
Input rise times of SDAI, 0.8 → 2.3 V
20
300
ns
tr
Input rise time of SCL, 0.8 → 2.3 V
20
300
ns
tf
Input fall time of SCL, 2.3 → 0.8 V
20
200
tBUF
Bus free time between a stop and start condition
1.3
µs
tHD,STA
Hold time after (repeated) start condition
0.6
µs
tSU,STA
Repeated start condition set-up time
0.6
µs
tSU,STO
Stop condition set-up time
0.6
µs
tFLT_INT (1)
Fault to INT assertion, Time to internally register an interrupt in
response to a fault
tARA_INT
ARA to INT negation
tDG
Suppressed spike pulse width, SDAI and SCL
tRDG
RESET input minimum pulse width (deglitch time)
tWDT_I2C
I2C Watchdog trip delay
tSTP_AOUT
Delay STOP bit to AOUT high during I2C address programming
(1)
ns
150
µs
500
ns
5
µs
50
1.1
ns
2.2
3.3
s
1.25
µs
These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
trSDA
SDAI/
SDAO
tfSDA
tLOW
tr
tSU,DAT
tfo
tf
tBUF
SCL
tHD,STA
t HIGH
Start Condition
tHD,DAT
tSU,STA
Repeated
Start Condition
t SU,STO
Stop Condition
Start Condition
Figure 1. I2C Timings
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6.7 Switching Characteristics
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Duty cycle of IPORT with current
fault
δIfault
TICUT = 00, default as supplied
tOVLD
ICUT time limit
tLIM
ILIM time limit
MIN
TYP
MAX
UNIT
5.5%
6.7%
50
70
ms
TICUT = 01
25
35
ms
TICUT = 10
100
140
ms
TICUT = 11
200
280
ms
POEPn = 0, default as supplied
50
70
ms
POEPn = 1, TLIM = 00
50
70
ms
POEPn = 1, TLIM = 01
28.4
30
34
ms
POEPn = 1, TLIM = 10
14.7
15.5
17
ms
POEPn = 1, TLIM = 11
9.025
11.5
ms
50
70
ms
TSTART = 00, default as supplied
tSTART
Maximum current limit duration in
TSTART = 01
port start-up
TSTART = 10
25
35
ms
100
140
ms
tDET
Four-point detection duration
Time to complete a detection
275
500
ms
Pause between detection
attempts
VVPWR – VDRAINn > 2.5 V
300
500
ms
VVPWR – VDRAINn < 2.5 V
tDET_BOFF
tCLE
tpdc
Classification duration
Classification duration
0
150
ms
1st and 2nd class event, Auto Mode,
Semi-Auto Mode, from detection
complete
6.5
13
ms
1-event physical layer class timing, Auto
Mode and Semi-Auto Mode, from
detection complete
6.5
13
ms
Manual mode, from beginning of
classification
6.5
14
ms
6
12
ms
4
ms
tME
Mark duration
1st and 2nd mark event, from class 4
complete
tp(on)
Port power-on delay
Manual mode, from port turn-on
command to port turn on completed
12
400
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Switching Characteristics (continued)
–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all
outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB
(SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating
registers loaded with default values (unless otherwise noted)
PARAMETER
ted
tMPDO
TEST CONDITIONS
Fault delay timing. Delay before
next attempt to power a port
following power removal due to
fault condition
PD maintain power signature
dropout time limit
MIN
TYP
MAX
ICUT , ILIM or start fault, Auto Mode,
Semi-Auto Mode,
CLDN = 0X, default as supplied
0.8
1
1.2
s
ICUT , ILIM or start fault, Auto Mode,
Semi-Auto Mode,
CLDN = 10
1.6
2
2.4
s
ICUT , ILIM or start fault, Auto Mode,
Semi-Auto Mode,
CLDN = 11
3.2
4
4.8
s
TDIS = 00, default as supplied
300
400
ms
TDIS = 01
75
100
ms
TDIS = 10
150
200
ms
TDIS = 11
600
800
ms
1
5
µs
900
µs
5
µs
POEPn = 0,
VDRAINn = 1 V , from VSENn pulsed to
0.425 V
0.9
µs
POEPn = 1,
VDRAINn = 1 V , from VSENn pulsed to 0.62
V
0.9
µs
23
ms
5
µs
tD_off_SHDW Gate turn-off time from SHTDWN From SHTDWN to VGATEn < 1 V, VSENn =
input
0V
N
tP_off_CMD
Gate turn-off time from port off
command
From port off command to VGATEn < 1 V,
VSENn = 0 V
tP_off_RST
Gate turn-off time with RESET
pin
From RESET low to, VGATEn < 1 V, VSENn
=0V
tD_off_SEN
Gate turn-off time from SENn
input
tPOR
Device power-on-reset delay
tRESET
Reset time duration from RESET
pin
1
1
UNIT
VLIM
VCUT
SEN
0V
GATE
0V
tOVLD
Figure 2. Overcurrent Fault Timing
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Port Turn-On
Class
VCLASS
Four-Point Detection
VPORT
tpdc
0V
tDET
Figure 3. Detection, 1-Event Classification, and Turn On
Port Turn-On
VCLASS
Class
Four-Point Detection
VMARK
Mark
VPORT
0V
tDET
tCLE
tME
Tpon
Figure 4. Detection, 2-Event Classification, and Turn On
14
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V VDD
3.0V < VVDD < 3.6V
VUVDDR
V UVDDF
t POR
Time
For more information refer to the application note, TPS23861 Power-On Considerations, SLVA723.
Figure 5. VDD Power-On-Reset
V VPWR
44V < VVPWR < 57V
V UVLOPW _ F
VUVLOPW_ R
t POR
Time
For more information refer to the application note, TPS23861 Power-On Considerations, SLVA723.
Figure 6. VPWR Power-On-Reset
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6.8 Typical Characteristics
17.0
VUVLOPWR_F-VPWR UVLO-V
VUVDD-VDD UVLO-V
2.4
2.3
2.2
2.1
2.0
±40
±20
0
20
40
60
80
100
TJ-Junction Temperature-ƒC
120
16.5
16.0
15.5
15.0
14.5
14.0
±40.0 ±20.0
20.0
40.0
60.0
80.0
100.0 120.0
TJ-Junction Temperature-ƒC
Figure 7. VDD UVLO vs Junction Temperature
C002
Figure 8. VPWR UVLO vs Junction Temperature
7.0
2.0
1.9
IVDD-VDD Current-mA
VIMN-DC DISCONNECT-mV
0.0
C001
1.8
1.7
6.5
6.0
TJ=-40°C
5.5
1.6
TJ=25°C
1.5
±40.0 ±20.0
0.0
20.0
40.0
60.0
80.0
TJ=125°C
5.0
2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70
100.0 120.0
TJ-Junction Temperature-ƒC
VDD-V
C003
C004
Figure 10. VDD Current vs VDD
Figure 9. DC Disconnect vs Junction Temperature
7.00
110
TJ=25°C
109
TJ=125°C
6.00
VLIM-Current Limit-mV
IVPWR VPWR Current-mA
6.50
TJ=-40°C
5.50
5.00
105
30.00
40.00
50.00
VPWR-V
60.00
±40
±20
0
20
40
60
80
TJ-Junction Temperature-°C
C005
Figure 11. VPWR Current vs VPWR
16
107
106
4.50
4.00
20.00
108
100
120
C006
Figure 12. Current Limit (1x threshold) vs Junction
Temperature
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Typical Characteristics (continued)
300
1x
110
100
90
80
70
60
50
40
200
150
100
30
50
20
10
0
0
0
10
20
30
40
0
50
Port Voltage-V
10
20
30
40
50
FET VDS-V
C007
C008
Figure 14. Current Limit Threshold vs FET Voltage
Figure 13. Inrush Current Limit Threshold vs Port Voltage
22
VCLASS-Classification Voltage-V
280
VLIMT2X-Current Limit-mV
2x
250
ILIM-Limit-mV
VINRUSH-Inrush Limit Threshold-mV
120
278
276
274
272
20
18
16
TJ=-40°C
14
TJ=25°C
TJ=125°C
12
270
±40
±20
0
20
40
60
80
TJ-Junction Temperature-°C
100
120
0
10
20
30
40
50
60
Classification Current-mA
C009
70
C010
Figure 15. Current Limit (2x threshold) vs Junction
Temperature
Figure 16. Classification Voltage vs Port Classification
Current
Figure 17. Valid PD Detection (25 kΩ and 0.1 µF) and CLASS
0 Classification
Figure 18. Valid PD Detection (25 kΩ and 0.1 µF) and CLASS
3 Classification
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Typical Characteristics (continued)
Figure 19. Detection with Invalid PD (15 kΩ and 0.1 µF)
Figure 20. Detection with Invalid PD (open circuit)
Figure 21. Detection with Invalid PD (25 kΩ and 10 µF)
Figure 22. 2-Event Class and Startup with Valid PD
Figure 23. Powering Up Into a 100-µF Load
18
Figure 24. Semi-Auto Sequenced Turn On
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Typical Characteristics (continued)
Figure 25. All Ports Fast Shutdown
Figure 26. Overcurrent (ICUT) Timeout
Figure 27. Rapid Response to a 1-Ω Short: 802.3af Mode
Figure 28. Rapid Response to a 1-Ω Short: PoE+ Mode
Figure 29. Response to a 50-Ω Load: 802.3af Mode
Figure 30. Response to a 25-Ω Load: PoE+ Mode
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Typical Characteristics (continued)
Figure 31. Current Limit Timeout: 802.3af Mode, 85-Ω Load
Figure 32. Current Limit 15-ms Timeout: PoE+ Mode, 45-Ω
Load
Figure 33. Inrush Fault Timeout: 100-Ω Load
Figure 34. Current Limit Timeout Restart Delay
Figure 35. Response to 8-mA to 6-mA Load, DC Disconnect Enabled
20
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7 Detailed Description
7.1 Overview
The TPS23861 is a four-port PSE for power over ethernet applications. Each of the four ports provides fully
automatic detection, classification, protection, and shut down in compliance with the IEEE 802.3at standard.
The schematic of Figure 36 depicts automatic mode operation of the TPS23861, providing turnkey functionality
ready to power PoE loads. No connection to the I2C bus or any type of host control is required. In Figure 36 the
TPS23861 automatically:
1. Performs four-point load detection.
2. Performs classification including type-2 (two-finger) of up to Class 4 loads.
3. Enables power with protective foldback current limiting, and ICUT value based on load class.
4. Shuts down in the event of fault loads and shorts.
5. Performs Maintain Power Signature function to ensure removal of power if load is disconnected.
6. Undervoltage lock out occurs if VPWR falls below VPUV_F (typical 26.5 V).
Following a power-off command, disconnect or shutdown due to a start, ICUT or ILIM fault, the port powers
down. Following port power off due to a power off command or disconnect, the TPS23861 will continue automatic
operation starting with a detection cycle. If the shutdown is due to a start, ICUT or ILIM fault, the TPS23861
enters into a cool-down period. After the end of the cool-down period the TPS23861 continues automatic
operation starting with a detection cycle.
The TPS23861 will not automatically apply power to a port under the following circumstances:
• The detect status is not Resistance Valid.
• If the classification status is overcurrent, class mismatch, or unknown.
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Overview (continued)
VPWR
VDD
0.1PF
50V
VPWR
1 VDD
P3
RJ45
&
XFMR
+
0.1PF
100V
-
0.1PF
100V
TPS23861PW
2 RESET
VPWR
VPWR 28
P2
N/C 27
SMBJ58A-13-F
+
0.1PF
100V
-
SMBJ58A-13-F
3 SCL
C1S 1.5
4 SDAI
FDMC3612
5 SDAO
10MQ100NTRPBF
(Optional)
6 INT
:
AOUT 26
C1S 1.5
RJ45
&
XFMR
AIN 25
FDMC3612
SHTDWN 24
10MQ100NTRPBF
(Optional)
A3 23
7 DGND
AGND 22
8 SEN3
GATE2 21
:
22.1:
:
10 GATE3
11 KSENSB
FDMC3612
RJ45
&
XFMR
DRAIN2 20
:
22.1:
(Optional)
10MQ100NTRPBF
P4
:
9 DRAIN3
:
(Optional)
10MQ100NTRPBF
SEN2 19
KSENSA 18
FDMC3612
22.1:
C1S 1.5
12 SEN4
:
0.1PF
100V
+
:
13 DRAIN4
14 GATE4
0.1PF
100V
+
DRAIN1 16
SMBJ58A-13-F
22.1:
SMBJ58A-13-F
P1
C1S 1.5
GATE1 17
SEN1 15
RJ45
&
XFMR
VPWR
VPWR
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Automatic 4-Port Operation Schematic
VDD
VPWR
VPWR
Port 2±4 Analog Control Functions
RESET
SHTDWN
Processor
Port 1 Analog Control Functions
IDET =
160/270/
540 A
Foldback Schedulers
Ilim
Fast Ishort Protection
Gm
dv/dt Ramping Control
Driver
Rapid Overload Recovery
Class Current Limit
Class Port Voltage Control
PD
Load
DRAINx
GATEx
SENx
0.255
KSENSEA,B
Copyright © 2016, Texas Instruments Incorporated
Figure 37. Simplified Block Diagram
22
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Overview (continued)
7.1.1 Detailed Pin Description
The following descriptions refer to the pinout and the functional block diagram.
DRAIN1-DRAIN4: Port 1-4 output voltage monitor and detect sense. Used to measure the port output voltage,
for port voltage monitoring, port-power-good detection and foldback action. Detection probe currents also flow
into this pin. The TPS23861 uses an innovative 4-point technique in order to provide a reliable PD detection.
Detection is performed by sinking two different current levels via the DRAINn pin, while the PD voltage is
measured from VPWR to DRAINn. The 4-point measurement provides the capability to distinguish between an
IEEE-standard-compliant PD and a capacitive or legacy load. If the Port n is not used, DRAINn can be left
floating or tied to AGND.
GATE1-GATE4: Port 1-4 gate drive output used for external N-channel MOSFET gate control. At port turn on, it
is driven positive by a low-current source to turn the MOSFET on. GATEn is pulled low whenever any of the
input supplies are low or if an over-current timeout has occurred. GATEn will also be pulled low if its port is
turned off during fast shutdown. Leave floating if unused. For a robust design, a current-foldback function limits
the power dissipation of the MOSFET during low resistance load or a short-circuit event. The foldback
mechanism measures the port voltage across AGND and DRAINn to reduce the current-limit threshold as shown
in Figure 14, Figure 57, and Figure 58. The fast overload protection is for major faults like a direct short. This
forces down the current within the current limit in less than a microsecond. When ICUT threshold is exceeded
while a port is on, a timer starts. During that time, linear current limiting makes sure the current will not exceed
ILIM combined with current-foldback action. When the timer reaches its tOVLD (or tSTART if at port turn on) limit, the
port shuts off. When the port current goes below ICUT , the counter counts down at a rate 1/16th of the increment
rate, and it must reach a count of zero before the port can be turned on again.
KSENSA, KSENSB: Kelvin point connection used to perform a differential voltage measurement across the
associated current sense resistors. KSENSA is shared between SEN1 and SEN2, while KSENSB is shared
between SEN3 and SEN4. In order to optimize the accuracy of the measurement, the PCB layout (see
Figure 61) must be done carefully to minimize impact of PCB trace resistance.
SHTDWN: Shutdown, active low. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter.
The Port Power Priority register is used to determine which port(s) is (are) shut down in response to an external
assertion of the SHTDWN pin. The turn-off procedure is similar to a port reset or a reset command (Reset
register).
NOTE
After a SHTDWN cycle occurs, the I2C host should reinitialize the TPS23861 register set
according to the desired user configuration. More detail regarding use of the SHTDWN pin
to power off low priority ports can be obtained by consulting a Texas Instruments technical
representative.
RESET: Reset input, active low. When asserted, the TPS23861 resets, turning off all ports and forcing the
registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter.
External RC network can be used to delay the turn-on. There is also an internal power-on-reset which is
independent of the RESET input.
NOTE
After RESET pin de-assertion, there is a delay of approximately 20 ms before TPS23861
can process I2C commands. For more information, refer to the application note TPS23861
Power-On Considerations, SLVA723.
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Overview (continued)
SEN1- SEN4: Port 1-2 current sense input relative to KSENSA, and port 3-4 current sense relative to KSENSB.
A differential measurement is performed using KSENSA and KSENSB Kelvin point connection. It monitors the
external MOSFET current by use of either a 255-mΩ (two 510 mΩ in parallel) or a 250-mΩ (four 1 Ω in parallel)
current-sense resistors connected to AGND. Used by current foldback engine and also during classification. Can
be used to perform load current monitoring via A/D conversion.
NOTE
A classification is done while using the external MOSFET so performing a classification on
more than one port at the same time is possible without exceeding dissipation in the
TPS23861.
For the current limit with foldback function, there is an internal 2-µs analog filter on the SEN1-4 pins to provide
glitch filtering. For measurements through an A/D converter, an anti-aliasing filter is present on the SEN1-4 pins.
This includes the port-powered current monitoring and disconnect. If the port is not used, tie SENn to AGND.
VDD: 3.3-V logic power supply input.
VPWR: High-voltage power supply input. Nominally 48 V.
7.1.2 I2C Detailed Pin Description
AIN: Used to program the I2C slave device address. This pin is internally pulled up to VDD. See I2C Slave
Address and AUTO Bit Programming for more details.
AOUT: Used to program the I2C slave device address for multiple devices. See I2C Slave Address and AUTO Bit
Programming for more details. AOUT is open drain.
A3: I2C A3 address input, used during normal operation and during slave address programming. This pin is
internally pulled up to VDD.
INT: Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This pin is updated
between I2C transactions. This output is open-drain. Interrupt functional diagram is shown in Figure 43.
SCL: Serial clock input for I2C bus. Requires an external pull-up resistor to VDD.
SDAI: Serial data input for I2C bus. Requires an external pull-up resistor to VDD. This pin can be connected to
SDAO for non-isolated systems. See Figure 50.
SDAO: Open-drain I2C bus output data line. Requires an external resistive pull up. The TPS23861 uses separate
SDAO and SDAI lines to allow optoisolated I2C interface. SDAO can be connected to SDAI for non-isolated
systems.
NOTE
Both VPWR and VDD must be present for proper system level I2C operation.
24
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7.2 Functional Block Diagram
VDD
VPWR
VDD UVLO
Inte rnal Ra ils
Goo d
SHTDWN Direct Shu tdo wn for Ports
PG
PG
RESET
RST Bl ock
VPWR
Por t 2-4 Ana log Co ntro l Functions
SHTDWN
Por t 1 Ana log Co ntro l Functions
RST to Blks
AOUT
AIN
Fast Ishort Protectio n
Ena ble
dv/dt Rampin g Control
Gm
Driver
Rapid Overloa d Recovery
1 Byte EE NVM
7-Bit A ddress/Incl uding
State o f A3 Pin
18 V
Pro cessor
PD LOAD
DRA INx
Ilim
Discrete IO Cond itio ners
A3
SHTDWN/POR
Foldba ck S ch edulers
AIN/AOUT Mux
IDE T =
160/
270/
540uA
GATEx
2X Power
SENx
Class Current Limit
Class Port Voltage Control
SDAI
I2C Interface
Registe r File
INT
14-Bit A DC
(Voltage)
SHTDWN
IPORT
320-Hz LPF
KSE NS EA,B
ICL ASS
BIT
Var iable Average r
Range Se lect
SCL Watchdo g
14-Bit A DC
(Curren t)
Bus IF
SCL
Range Se lect
0.255
SDAO
Vdisco
Vpo rt
Vds
VEE
Temp
BIT
PORT DIFF AMP
4:1 MUX
V48
DRA IN1±4
DRA IN1±4
V48
PTAT Diod es
Ana log BIT MUX
Var iable Average r
Ana log Te st
AIN
7.3 Feature Description
7.3.1 Detection Resistance Measurement
The detect resistance can be measured and reported in the Port n Detect Resistance Register. Fourteen bits of
resistance information are reported in two bytes. Useful range of measurement is 500 Ω to 55 kΩ. Resolution (1
LSB) is approximately 11 Ω. Measurement repeatability is on the order of ±200 Ω. Additionally, in the MSB of the
resistance register (Port n Resistance: MSByte) the RSn field reports whether a low-resistance circuit, open
circuit or MOSFET short fault is detected.
Before detection begins, the TPS23861 backs-off for up to 400 ms to allow the port voltage to drop below 2.8 V.
This will allow any PD on the port to reset prior to an attempt to detect, classify and apply power to the PD.
Table 1. RSn Field Encoding
RSn1
RSn0
DETECT STATUS
RSTEP BIT WEIGHT
0
0
Other
11.0966 Ω/bit
0
1
Low (< 2 kΩ)
Additional detect 4.625 Ω/bit
1
0
Open circuit
N/A
1
1
MOSFET short fault
N/A
7.3.2 Physical Layer Classification
Whether one or two classification events will be executed depends on the operating mode and the value of the
TECLENn field in the Two-Event Classification Register. See Device Functional Modes for details.
See Figure 38 and Figure 39 for illustrations of the voltage on the Power Interface (PI) during single-event
(802.3af) and 2-event (802.3at) classification.
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Powered On
802.3 optional
classification
xxxxxxx
xxx
xxxxxxxxx
xxxxxxx
xxx
xxxxxxxxx
xxxxxxx
xxx
xxxxxxxxx
xxx
xx
xxxxxxxxxxxx
xxx xx
xxxxxxxxxxxx
Voltage
20.5
Free Format
Transition
15.5
Four Point Detection
10
2.8
Figure 38. 802.3af with Classification
Powered On
nd
2
Class
1st Class
Voltage
20.5
15.5
10
2.8
1st Mark
2nd Mark
Figure 39. P802.3at with Classification
26
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7.3.3 Class and Detect Fields
The results of the detection cycle and classification cycle are each stored in a 4-bit field for each port in the
Detect Pn and Class Pn fields of the Port n Status Register. The results of a detection and classification event
are encoded as follows.
Table 2. Detect Pn Field Encoding
DETECT Pn
DETECT STATUS
0000
Unknown (POR value)
0001
Short circuit (
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