TPS2399DGKR


 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003    
  
    
 
 FEATURES D Wide Input Supply Range: −36 V to −80 V D Transient Rating to −100 V D Improved Transient Response D Enable Input (EN) D Programmable Current Limit D Programmable Current Slew Rate D Fault Timer to Eliminate Nuisance Trips D Open-Drain Power Good Output (PG) D 8-Pin MSOP Package DESCRIPTION The TPS2398 and TPS2399 integrated circuits are hot swap power managers optimized for use in nominal −48-V systems. For redundant-supply systems, they incorporate an improved circuit breaker response that provides rapid protection from short circuits, while still enabling plug-ins to tolerate large transients that can be generated by the sudden switchover to a higher voltage supply. They are designed for supply voltage ranges up to −80 V, and are rated to withstand spikes to −100 V. In conjunction with an external N-channel FET and sense resistor, they can be used to enable live insertion of plug-in cards and modules in powered systems. Both devices provide load current slew rate and peak magnitude limiting, easily programmed by sense resistor value and a singleexternal capacitor. ⋅APPLICATIONS D −48-V Distributed Power Systems D Redundant Negative Voltage Supplies D Central Office Switching APPLICATION DIAGRAM −48V_RTN VIN+ R3 30 kΩ 0.5 W EN VDD VOUT+ 10 µA + R2 100 kΩ VIN− D2 −48V_INB D1 C1 0.047 µF 1 PG RTN 8 2 EN GATE 7 + COUT C3 100 µF 100 V TPS2398/TPS2399 VOUT+ VOUT− VOUT− DC/DC CONVERTER Q1 IRF530 3 FLTTIME ISENS 6 4 IRAMP −VIN 5 C2 3900 pF R1 0.02 Ω 1% UDG−03069 −48V_INA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
  
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 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 DESCRIPTION (continued) They also provide single-line fault reporting, electrical isolation of faulty cards, and protection against nuisance overcurrent trips. The TPS2398 latches off in response to current faults, while the TPS2399 periodically retries the load in the event of a fault. ABSOLUTE MAXIMUM RATINGS (See Note 1) Input voltage range, all pins except RTN, EN, PG(2) Input voltage range, RTN(2) Input voltage range, EN(2)(3) Output voltage range, PG(2)(4) TPS2398/1 UNIT −0.3 V to 15 V −0.3 V to 100 V −0.3 V to 100 V −0.3 V to 100 V 10 mA Continuous output current, PG Continuous total power dissipation see Dissipation Rating Table Operating junction temperature range, TJ −55_C to 125_C _C Storage temperature range, Tstg −65_C to 150_C _C 260_C _C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds NOTES 1: Stresses beyond those listed under ”absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is not implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability. 2: All voltages are with respect to −VIN (unless otherwise noted). 3: With 100-kΩ minimum input series resistance, −0.3 V to 15 V with low impedance. 4: With 10-kΩ minimum series resistance, −0.3 V to 80 V with low impedance. ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN UNIT Human Body Model (HBM) 1.5 kV Charged Device Model (CDM) 1.5 kV RECOMMENDED OPERATING CONDITIONS† MIN Nominal input supply, −VIN to RTN Operating junction temperature range † All voltages are with respect to −VIN (unless otherwise noted) MAX UNIT −80 NOM −36 V −40 85 _C DISSIPATION RATING TABLE PACKAGE TA < 25_C POWER RATING DERATING FACTOR ABOVE TA = 25_C TA = 85_C POWER RATING MSOP-8 420 mW 4.3 mW/_C 160 mW AVAILABLE OPTIONS OPERATING TA −40_C to 85_C 2 FAULT OPERATION PACKAGED DEVICES MSOP (DGK) Latch off TPS2398DGK Periodically retry TPS2399DGK www.ti.com 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS VI(−VIN) = −48 V with respect to RTN, VI(EN) = 2.8 V, VI(ISENS) = 0, all outputs unloaded, TA = −40_C to 85_C (unless otherwise noted)(1)(2) input supply PARAMETER TEST CONDITIONS ICC1 ICC2 Supply current, RTN Supply current, RTN VI(RTN) = 48 V VI(RTN) = 80 V VUVLO_L VHYS UVLO threshold, input voltage rising To GATE pull-up, referenced to RTN UVLO hysteresis MIN TYP MAX UNIT 700 1000 µA 1000 1500 µA −36 −30 −25 V 1.8 2.3 3.0 V enable input (EN) PARAMETER TEST CONDITIONS VTH VHYS_EN Threshold voltage, input voltage rising IIH High-level input current To GATE pull-up EN hysteresis VI(EN) = 5 V MIN TYP MAX UNIT 1.3 1.4 1.5 V 22 60 90 mV −2 1 2 µA linear current amplifier (LCA) PARAMETER VOH ISINK High-level output, GATE II VREF_K VIO Input offset voltage TEST CONDITIONS MIN TYP 11 14 Output sink current VI(ISENS) = 0 V VI(ISENS) = 80 mV, VO(GATE) = 5V, Fault mode 50 100 Input current, ISENS 0 V < VI(ISENS) < 0.2 V −1 Reference clamp voltage VO(IRAMP) = open VO(IRAMP) = 2 V 33 40 −7 MAX 17 UNIT V mA 1 µA 46 mV 6 mV ramp generator PARAMETER TEST CONDITIONS ISRC1 ISRC2 IRAMP source current, slow turn-on rate VOL AV Low-level output voltage IRAMP source current, normal rate VO(IRAMP) = 0.25 V VO(IRAMP) = 1 V, 3 V VI(EN) = 0 V VO(IRAMP) = 1 V, 3 V Voltage gain, relative to ISENS MIN TYP MAX UNIT −850 −600 −400 nA −11 −10 −9 µA 5 mV 9.5 10.0 10.5 mV/V MAX UNIT overload comparator PARAMETER VTH_OL tDLY TEST CONDITIONS Current overload threshold, ISENS Glitch filter delay time VI(ISENS) = 200 mV MIN TYP 80 100 120 mV 2 4 7 µs fault timer PARAMETER TEST CONDITIONS VOL ICHG Low-level output voltage VFLT IDSG Fault threshold voltage Discharge current, retry mode TPS2399 D Output duty cycle TPS2399 Charging current, current limit mode VI(EN) = 0 V VI(ISENS) = 80 mV, VO(FLTTIME) = 2 V VI(ISENS) = 80 mV, VO(FLTTIME) = 2 V IRST Discharge current, timer reset mode VO(FLTTIME) = 2 V,VI(ISENS) = 0 V NOTES 1: All voltages are with respect to the −VIN terminal unless otherwise stated. 2: Currents are positive into and negative out of the specified terminal. www.ti.com MIN TYP MAX UNIT 5 mV −55 −50 −45 µA 3.75 4.00 4.25 V 0.38 0.75 µA 1 1.5 % 1 mA 3 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS (continued) VI(−VIN) = −48 V with respect to RTN, VI(EN) = 2.8 V, VI(ISENS) = 0, all outputs unloaded, TA = −40_C to 85_C (unless otherwise noted)(1)(2) PG output PARAMETER IOH RDS(ON) TEST CONDITIONS High-level output (leakage) current MIN VI(EN) = 0 V, VO(PG) = 65 V VI(ISENS) = 80 mV, VO(FLTTIME) = 5V, IO(PG) = 1 mA Driver ON resistance NOTES 1: All voltages are with respect to the −VIN terminal unless otherwise stated. 2: Currents are positive into and negative out of the specified terminal. TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION NO. EN 2 I Enable input to turn on/off power to the load. PG FLTTIME 1 O Open-drain, active-low indication of a load power good condition. 3 I/O Connection for user-programming of the fault timeout period. GATE IRAMP 7 O Gate drive for external N-channel FET. 4 I/O Programming input for setting the inrush current slew rate. ISENS 6 I Current sense input. RTN 8 I Positive supply input for the TPS2398 and TPS2399. −VIN 5 I Negative supply input and reference pin for the TPS2398 and TPS2399. DGK PACKAGE (TOP VIEW) 4 PG 1 8 RTN EN 2 7 GATE FLTTIME 3 6 ISENS IRAMP 4 5 −VIN www.ti.com TYP 35 MAX UNIT 10 µA 80 Ω 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 DETAILED PIN DESCRIPTIONS EN: Enable input to turn on/off power to the load. The EN pin is referenced to the −VIN potential of the circuit. When this input is pulled high (above the nominal 1.4-V threshold) the device enables the GATE output, and begins the ramp of current to the load. When this input is low, the linear current amplifier (LCA) is disabled, and a large pull-down device is applied to the FET gate, disabling power to the load. FLTTIME: Connection for user-programming of the fault timeout period. An external capacitor connected from FLTTIME to −VIN establishes the timeout period to declare a fault condition. This timeout protects against indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary current spikes or surges. The TPS2398 and TPS2399 define a fault condition as voltage at the ISENS pin at or greater than the 40-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by charging the external capacitor to the 4-V fault threshold, then subsequently discharging it to reset the timer (TPS2398), or discharging it at approximately 1% the charge rate to establish the duty cycle for retrying the load (TPS2399). Whenever the internal fault latch is set (timer expired), the pass FET is rapidly turned off, and the PG output is deasserted. GATE: Gate drive for external N-channel FET. When enabled, and the input supply is above the UVLO threshold, the gate drive is enabled and the device begins charging an external capacitor connected to the IRAMP pin. This pin voltage is used to develop the reference voltage at the non-inverting input of the internal LCA. The inverting input is connected to the current sense node, ISENS. The LCA acts to slew the pass FET gate to force the ISENS voltage to track the reference. The reference is internally clamped at 40 mV, so the maximum current that can be sourced to the load is determined by the sense resistor value as IMAX ≤ 40 mV/RSENSE. Once the load voltage has ramped up to the input dc potential, and current demand drops off, the LCA drives the GATE output to about 14 V to fully enhance the pass FET, completing the low-impedance supply return path for the load. IRAMP: Programming input for setting the inrush current slew rate. An external capacitor connected between this pin and −VIN establishes the load current slew rate whenever power to the load is enabled. The device charges the external capacitor to establish the reference input to the LCA. The closed-loop control of the LCA and pass FET acts to maintain the current sense voltage at ISENS at the reference potential. Since the sense voltage is developed as the drop across a resistor, the charging current ramp rate is set by the voltage ramp rate at the IRAMP pin. When the output is disabled via the EN input or due to a load fault, the capacitor is discharged and held low to initialize for the next turn-on. ISENS: Current sense input. An external low value resistor connected between this pin and −VIN is used to feed back current magnitude information to the TPS2398/99. There are two internal device thresholds associated with the voltage at the ISENS pin. During charging of the load’s input capacitance, or during other periods of excessive demand, the HSPM acts to limit this voltage to 40 mV. Whenever the LCA is in current regulation mode, the capacitor at FLTTIME is charged to activate the timer. If, when the LCA is driving to its supply rail, a fast-acting fault such as a short-circuit, causes the ISENS voltage to exceed 100 mV (the overload threshold), the GATE pin is pulled low rapidly, bypassing the fault timer. PG: Open-drain, active-low indication of load power good. A power good status is declared when the output is enabled, the GATE pin voltage has ramped to at least 7 V, and the voltage on the IRAMP pin exceeds approximately 5 V. This last condition assures that full programmed sourcing current is available prior to declaring power good, even with very slow current ramp rates. This additional protection prevents potential discharging of the module input bulk capacitance during load turn-on. RTN: Positive supply input for the TPS2398/99. For negative voltage systems, the supply pin connects directly to the return node of the input power bus. Internal regulators step down the input voltage to generate the various supply levels used by the TPS2398 and TPS2399. −VIN: Negative supply input and reference pin for the TPS2398/99. This pin connects directly to the input supply negative rail. The input and output pins and all internal circuitry are referenced to this pin, so it is essentially the GND or VSS pin of the device. www.ti.com 5 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS LIVE INSERTION EVENT VIN = −48 V LIVE INSERTION EVENT VIN = −80 V EN (20 V/div.) EN (20 V/div.) VDRAIN (50 V/div.) VDRAIN (20 V/div.) Power Applied Power Applied CLOAD = 100 µF CIRAMP = 3900 pF CFLT = 0.1 µF CLOAD = 50 µF ILOAD (500 mA/div.) ILOAD (500 mA/div.) t − TIme − 1 ms/div t − TIme − 1 ms/div Figure 1 Figure 2 LOAD CURRENT RAMP PROFILES START-UP FROM ENABLE ASSERTION IRAMP (2 V/div.) EN (5 V/div.) CIRAMP = .022 µF VDRAIN 50 V/div. CIRAMP = 3900 pF CIRAMP = .047 µF IRAMP (5 V/div.) CLOAD = 100 µF EN driven from logiclevel signal, ref to −VIN ILOAD (1 A/div.) ILOAD t − TIme − 10 ms/div t − TIme − 1 ms/div Figure 4 Figure 3 6 CFLT = 0.33 µF CLOAD = 600 µF (500 mA/div.) www.ti.com 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS TURN-ON INTO SHORTED LOAD (TPS2399) TURN-ON INTO SHORTED LOAD (TPS2398) PG (50 V/div.) PG (50 V/div.) VIRAMP (5 V/div.) VIRAMP (5 V/div.) FLTTIME (2 V/div.) FLTTIME (2 V/div.) ILOAD (1 A/div.) CIRAMP = 3900 pF CFLT = 0.047 µF RPG = 100 kΩ CIRAMP = 3900 pF CFLT = 0.047 µF RPG = 100 kΩ t − TIme − 1 ms/div t − TIme − 1 ms/div Figure 5 FAULT RETRY OPERATION (TPS2399) ILOAD (1 A/div.) Figure 6 RECOVERY FROM A FAULT − LARGE SCALE VIEW (TPS2399) PG (50 V/div.) PG (50 V/div.) FLTTIME (2 V/div.) FLTTIME (2 V/div.) VDRAIN (20 V/div.) VDRAIN (20 V/div.) CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF RLOAD = 12.5 Ω ILOAD (1 A/div.) ILOAD (1 A/div.) t − TIme − 50 ms/div t − TIme − 50 ms/div Figure 7 Figure 8 www.ti.com 7 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS PG OUTPUT TIMING, VOLTAGE QUALIFIED RECOVERY FROM A FAULT − EXPANDED VIEW (TPS2399) PG (50 V/div) CIRAMP = 3900 pF CFLT = 0.1 µF CLOAD = 150 µF FLTTIME (2 V/div.) VIRAMP (2 V/div) VDRAIN (20 V/div) VDRAIN (20 V/div) CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF ILOAD (1 A/div) PG (50 V/div) t − TIme − 1 ms/div t − TIme − 1 ms/div Figure 10 Figure 9 SUPPLY CURRENT vs AMBIENT TEMPERATURE PG OUTPUT TIMING, CURRENT QUALIFIED 1200 VTH_PG 1000 ICC − Supply Current − µA CIRAMP = 0.01 µF CFLT = 0.1 µF CLOAD = 50 µF VIRAMP (2 V/div) VDRAIN (20 V/div) VRTN = 80 V 800 600 VRTN = 48 V 400 VRTN = 36 V 200 PG (50 V/div) 0 −40 t − TIme − 1 ms/div −15 10 35 60 TA − Ambient Temperature − °C Figure 11 8 Figure 12 www.ti.com 85 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS IRAMP OUTPUT CURRENT vs AMBIENT TEMPERATURE, SLOW TURN-ON GATE HIGH-LEVEL OUTPUT vs AMBIENT TEMPERATURE −0.50 17.0 ISRC1 − IRAMP Output Current − µA VI(ISENS) = 0 V VOH − Output Voltage − V 16.5 VRTN = 80 V 16.0 VRTN = 48 V 15.5 15.0 −0.54 VRTN = 80 V −0.58 VRTN = 48 V VRTN = 36 V −0.62 14.5 VO(IRAMP) = 0.25 V VRTN = 36 V −066 14.0 −40 −15 10 35 60 −40 85 −15 35 85 Figure 14 Figure 13 IRAMP OUTPUT CURRENT vs AMBIENT TEMPERATURE, NORMAL RATE TIMER CHARGING CURRENT vs AMBIENT TEMPERATURE −9.5 −45 VI(ISENS) = 80 mV VO(FLTTIME) =2V Average for VO(IRAMP) = 1 V, 3 V VRTN = 36 V to 80 V −9.7 ICHG − Charging Current − µA −47 −9.9 −10.1 −10.3 −49 VRTN = 80 V −51 −53 VRTN = 36 V VRTN = 48 V −10.5 −40 60 TA − Ambient Temperature − °C TA − Ambient Temperature − °C ISRC2 − IRAMP Output Current − µA 10 −55 −15 10 35 60 85 TA − Ambient Temperature − °C −40 −15 10 35 60 85 TA − Ambient Temperature − °C Figure 15 Figure 16 www.ti.com 9 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS FLTTIME DISCHARGE CURRENT vs AMBIENT TEMPERATURE (TPS2399) FAULT LATCH THRESHOLD vs AMBIENT TEMPERATURE 4.25 0.50 VFLT − Threshold Voltage − V IDSG − Discharge Current − µA 0.47 VRTN = 48 V VI(ISENS) = 80 mV VO(FLTTIME) = 2 V VRTN = 36 V to 80 V 0.44 0.41 0.38 0.35 0.32 4.13 4.00 3.88 0.29 0.26 −40 −15 10 35 60 85 −15 10 35 60 TA − Ambient Temperature − °C TA − Ambient Temperature − °C Figure 17 10 3.75 −40 Figure 18 www.ti.com 85 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION When a plug-in module or printed circuit card is inserted into a live chassis slot, discharged supply bulk capacitance on the board can draw huge transient currents from the system supplies. Without some form of inrush limiting, these currents can reach peak magnitudes ranging up to several hundred amps, particularly in high-voltage systems. Such large transients can damage connector pins, PCB etch, and plug-in and supply components. In addition, current spikes can cause voltage droops on the power distribution bus, causing other boards in the system to reset. The TPS2398 and TPS2399 are hot swap power managers designed to limit these peaks to preset levels, as well as control the slew rate (di/dt) at which charging current ramps to the user-programmed limit. These devices use an external N-Channel pass FET and sense element to provide closed-loop control of current sourced to the load. Input supply undervoltage lockout (UVLO) protection allows hot swap circuits to turn on automatically with the application of power, or to be controlled with a system command via the EN input. External capacitors control both the current ramp rate, and the time−out period for load voltage ramping. In addition, an internal overload comparator provides circuit breaker protection against shorts occurring during steady-state (post-turn-on) operation of the card. The TPS2398 and TPS2399 operate directly from the input supply (nominal −48 VDC rail). The −VIN pin connects to the negative voltage rail, and the RTN pin connects to the supply return. Internal regulators convert input power to the supply levels required by the device circuitry. An input UVLO circuit holds the GATE output low until the supply voltage reaches a nominal 30-V level. A second comparator monitors the EN input; this pin must be pulled above the 1.4-V enable threshold to turn on power to the load. Once enabled, and when the input supply is above the UVLO threshold, the GATE pull-down is removed, the linear control amplifier (LCA) is enabled, and a large discharge device in the RAMP CONTROL block is turned off. Subsequently, a small current source is now able to charge an external capacitor connected to the IRAMP pin. This results in a linear voltage ramp at IRAMP. The voltage ramp on the capacitor actually has two discrete slopes. As shown in Figure 17, charging current is supplied from either of two sources. Initially at turn-on, the 600-nA source is selected, to provide a slow turn-on rate. This slow turn-on helps ensure that the LCA is pulled out of saturation, and is slewing to the voltage at its non-inverting input before normal rate load charging is allowed. This mechanism helps reduce current steps at turn-on. Once the voltage at the IRAMP pin reaches approximately 0.5 V, an internal comparator deasserts the SLOW signal, and the 10-µA source is selected for the remainder of the ramp period. The voltage at IRAMP is divided down by a factor of 100, and applied to the non-inverting input of the LCA. Load current magnitude information at the ISENS pin is applied to the inverting input. This voltage is developed by connecting the current sense resistor between ISENS and −VIN. The LCA slews the gate of the external pass FET to force the ISENS voltage to track the divided down IRAMP voltage. Consequently, the load current slew rate tracks the linear voltage ramp at the IRAMP pin, producing a linear di/dt of the load current. The IRAMP capacitor is charged to about 6.5 V; however, the LCA input is clamped at 40 mV. Therefore, the current sourced to the load during turn-on is limited to a value given by IMAX ≤ 40 mV/RSENSE, where RSENSE is the value of the sense resistor. The resultant load current, regulated by the controller, charges the module’s input bulk capacitance in a safe fashion. Under normal conditions, this capacitance eventually charges up to the dc input potential. At this point, the load demand drops off, and the voltage at ISENS decreases. The LCA now drives the GATE output to its supply rail. The device detects this condition as the GATE voltage rises through 7 V or 8 V, latches this status and asserts the PG output. If the full sourced current limit is not yet available to the load, as evidenced by the IRAMP voltage being less than 5 V, then the PG assertion is delayed until that condition is also met. The peak, steady-state GATE pin output, typically 14 V, ensures sufficient overdrive to fully enhance the external FET, while not exceeding the typical 20-V VGS rating of common N-channel power FETs. www.ti.com 11 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION GATEHI Ramp Control 600 nA 10 µA 1 RAMPHI S PG Q FLT SLOW R Q ENA VDD IRAMP 4 99 R R + LCA 40 mV OVERLOAD COMPARATOR ENA EN 2 + EN_AMP 1.4 V 7 GATE OC 6 ISENS + OL 100 mV 50 µA RTN 8 OC 4V ON + + 30 V FLT VDD Q S LATCH/ LOGIC RTRY RST 3 FLTTIME 0.4 µA + 0.5 V 14 V −VIN 5 DCHG TPS2399 ONLY TIMER BLOCK ENA UDG−03068 Figure 19. Block Diagram Fault timing is accomplished by connecting a capacitor between the FLTTIME and −VIN pins, allowing user-programming of the timeout period. Whenever the hot swap controller is in current control mode as described above, the LCA asserts an overcurrent indication (OC in the Figure 17 diagram). Overcurrent fault timing is inhibited during the slow turn-on portion of the IRAMP waveform. However, once the device transitions to the normal rate current ramp (VO(IRAMP) ≥ 0.5 V), the external capacitor is charged by a 50-µA source, generating a voltage ramp at the FLTTIME pin. If the load voltage ramps successfully, the fault capacitor is discharged (DCHG signal), and load initialization can begin. However, if the timing capacitor voltage attains the 4-V fault threshold, the LCA is disabled, the pass FET is rapidly turned off, and the fault is latched. Fault capacitor charging ceases, and the capacitor is then discharged. In addition, latching of a fault condition causes rapid discharge of the IRAMP capacitor. In this manner, the soft-start function is then reset and ready for the next output enable, if and when conditions permit. 12 www.ti.com 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION Subsequent to a plug-in’s start-up, and during the module’s steady-state operation, load faults that force current limit operation also initiate fault timing cycles as described above. In this case, a fault timeout also clears the previously latched power good status. The TPS2398 latches off in response to faults; once a fault timeout occurs, the DCHG signal turns on a large NMOS device to rapidly discharge the external capacitor, resetting the timer for any subsequent device reset. The TPS2398 can only be reset by cycling power to the device, or by cycling the EN input. In response to a latched fault condition, the TPS2399 enters a fault retry mode, wherein it periodically retries the load to test for continued existence of the fault. In this mode, the FLTTIME capacitor is discharged slowly by a about a 0.4-µA constant-current sink. When the voltage at the FLTTIME pin decays below 0.5 V, the LCA and RAMP CONTROL circuits are re-enabled, and a normal turn-on current ramp ensues. Again, during the load charging, the OC signal causes charging of the FLTTIME capacitor until the next delay period elapses. The sequential charging and discharging of the FLTTIME capacitor results in a typical 1% retry duty cycle. If the fault subsides, the timing capacitor is rapidly discharged, duty-cycle operation stops, and the PG output is asserted. Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly greater than the nominal 1% value. However, sourced current during this period peaks at only about one-eighth the maximum limit. The duty cycle of the normal ramp and constant-current periods is approximately 1%. The FAULT LOGIC within the TIMER BLOCK automatically manages capacitor charge and discharge actions, and the enabling of the GATE output (DCHG and ON signals). supply transient response The TPS2398 and TPS2399 also feature a fast-acting overload comparator which acts to clamp large transients from catastrophic faults occurring once the pass FET is fully enhanced, such as short circuits. This function provides a back-up protection to the LCA by providing a hard gate discharge action when the LCA is saturated. If sense voltage excursions above 100 mV are detected, this comparator rapidly pulls down the GATE output, bypassing the fault timer, and terminating the short−circuit condition. Once the spike has been brought down below the overload threshold, the GATE output is released, allowing the circuit to turn on again in either current-ramp or current-limit mode. A 4−µs deglitch filter is applied to the OL signal to help reduce the occurrence of nuisance trips. In redundant-supply systems, the sudden switchover to a supply of higher voltage potential is one more source of large current spikes. Due to the low impedance of filter capacitance under such high-frequency transients, these spikes are generally indistinguishable from true short-circuit faults to a hot swap controller. However, the TPS2398and TPS2399 transient response addresses this issue by providing rapid circuit-breaker protection for load faults along with minimal interruption of power flow during supply switching events. The scope plots in Figure 20 illustrate how. Figure 20 is a scope capture of the TPS2398/99 response in a diode-OR configuration to such an input transient event. (All waveforms are referenced to the −VIN pin.) In this example, the module is initially operating from a nominal −44-V supply (relative to the backplane supply return node). At the second major time division, another power supply, with an output of −48 V, is suddenly hot swapped into a secondary, or INB, input. This sudden voltage step is reflected in the −48V_RTN trace. On this board, the 4−V potential difference caused a greater than 6-A spike, as shown by the IINB trace. The GATE pin is rapidly pulled low, which quickly terminates the overload spike. However, it is quickly released, and seen to drive back to the pass FET ON-threshold, in this case, about 4.5 V. The resultant current-limit operation of the circuit is evidenced by the 2-A load on the B supply. Once supply current is flowing again, the filter capacitance is charged up to the new input supply level, seen here on the VDRAIN trace. Once the capacitance is fully charged, the load demand rolls off to the operating 1-A level. As an added benefit, this event is transparent to the PG signal, which remains asserted throughout the disturbance. www.ti.com 13 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION INPUT TRANSIENT RESPONSE −48V_RTN (5 V/div) (Offset 44 V) CLOAD = 100 µF RLOAD = 50 Ω RSNS = 20 mΩ CIRAMP = 3900 pF IINB= (2 A/div) GATE (5 V/div) VDRAIN (5 V/div) PG (50 V/div) t − TIme − 100 µs/div Figure 20 In order for downstream loads (bricks, etc.) to operate through the distribution bus transient, it is important to properly size the filtering capacitance to supply the needed energy during the OFF-time of the pass FET. In this example, once the RTN node stabilizes at about 3.5 V higher than the original potential, about 4.5 V develops across the FET, indicating approximately a 1-V droop across the brick input. Therefore, due to the fast response of the TPS2398/99 devices, the 100-µF capacitor achieves excellent hold-up of the brick input voltage. Actual requirements depend heavily on the individual application. Whether the device turns back on in either current-ramp or current-limit mode depends in part on the size of the ramp capacitor (CIRAMP) and the input capacitance of the pass FET. But in any case, the circuit turns back on in a controlled-current manner after rapidly clamping the potentially damaging spike. 14 www.ti.com 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION setting the sense resistor value Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage VI(ISENS) to its internal reference. Once the voltage at the IRAMP pin exceeds approximately 4 V, this limit is the clamp voltage, VREF_K. Therefore, a maximum sense resistor value can be determined from equation (1). R SENSE v 33 mV IMAX (1) where: • • RSENSE is the resistor value, and IMAX is the desired current limit. When setting the sense resistor value, it is important to consider two factors, the minimum current that may be imposed by the TPS2398 or TPS2399, and the maximum load under normal operation of the module. For the first factor, the specification minimum clamp value is used, as seen in equation (1). This method accounts for the tolerance in the sourced current limit below the typical level expected (40 mV/RSENSE). (The clamp measurement includes LCA input offset voltage; therefore, this offset does not have to be factored into the current limit again.) Second, if the load current varies over a range of values under normal operating conditions, then the maximum load level must be allowed for by the value of RSENSE. One example of this is when the load is a switching converter, or brick, which draws higher input current, for a given power output, when the distribution bus is at the low end of its operating range, with decreasing draw at higher supply voltages. To avoid current-limit operation under normal loading, some margin should be designed in between this maximum anticipated load and the minimum current limit level, or IMAX > ILOAD(max), for equation (1). For example, using a 20-mΩ sense resistor for a nominal 1-A load application provides a minimum of 650 mA of overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 2 A (40 mV/20 mΩ). setting the inrush slew rate The TPS2398 and TPS2399 devices enable user-programming of the maximum current slew rate during load start-up events. A capacitor tied to the IRAMP pin (C2 in the typical application diagram) controls the di/dt rate. Once the sense resistor value has been established, a value for ramp capacitor CIRAMP, in microfarads, can be determined from equation (2). C IRAMP + 11 100 R SENSE ǒdtdiǓ (2) MAX where: • • RSENSE is in ohms, and (di/dt)MAX is the desired maximum slew rate, in amperes/second. For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for CIRAMP is about 3700 pF. Selecting the next larger standard value of 3900 pF (as shown in the diagram) provides some margin for capacitor and sense resistor tolerances. www.ti.com 15 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION As described earlier in this section, the TPS2398 and TPS2399 initiate ramp capacitor charging, and consequently, load current di/dt at a reduced rate. This reduced rate applies until the voltage on the IRAMP pin is about 0.5 V. The maximum di/dt rate, as set by equation (2), is effective once the device has switched to the 10-µA charging source. setting the fault timing capacitor The fault timeout period is established by the value of the capacitor connected to the FLTTIME pin, CFLT. The timeout period permits riding out spurious current glitches and surges that may occur during operation of the system, and prevents indefinite sourcing into faulted loads swapped into a live system. However, to ensure smooth voltage ramping under all conditions of load capacitance and input supply potential, the minimum timeout should be set to accommodate these system variables. To do this, a rough estimate of the maximum voltage ramp time for a completely discharged plug-in card provides a good basis for setting the minimum timer delay. Due to the three-phase nature of the load current at turn-on, the load voltage ramp potentially has three distinct phases ( compare Figures 1 and 2). This profile depends on the relative values of load capacitance, input dc potential, maximum current limit and other factors. The first two phases are characterized by the two different slopes of the current ramp; the third phase, if required for bulk capacitance charging, is the constant-current charging at IMAX. Considering the two current ramp phases to be one period at an average di/dt simplifies calculation of the required timing capacitor. For the TPS2398 and TPS2399, the typical duration of the soft-start ramp period, tSS, is given by equation (3). t SS + 1183 C IRAMP (3) where: • • tSS is the soft-start period in ms, and CIRAMP is given in µF During this current ramp period, the load voltage magnitude which is attained is estimated by equation (4). V LSS + i AVG 2 C LOAD C IRAMP 100 R SENSE ǒtSSǓ 2 (4) where: • • • • VLSS is the load voltage reached during soft-start, iAVG is 3.38 µA for the TPS2398 and TPS2399, CLOAD is the amount of the load capacitance, and tSS is the soft-start period, in seconds The quantity iAVG in equation (4) is a weighted average of the two charge currents applied to CIRAMP during turn-on, considering the typical output values. 16 www.ti.com 

 SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION If the result of equation (4) is larger than the maximum input supply value, then the load can be expected to charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than the maximum supply input, VIN(max), the HSPM transitions to the constant-current charging of the load. The remaining amount of time required at IMAX is determined from equation (5). t CC + C LOAD ǒ ǒVIN (max) * VLSSǓ V REF_K (min) R SENSE Ǔ (5) where: • • tCC is the constant-current voltage ramp time, in seconds, and VREF_K(min) is the minimum clamp voltage, 33 mV. With this information, the minimum recommended value timing capacitor CFLT can be determined. The delay time needed will be either a time tSS2 or the sum of tSS2 and tCC, according to the estimated time to charge the load. The quantity tSS2 is the duration of the normal rate current ramp period, and is given by equation (6). t SS2 + 0.35 C RAMP (6) where: • CRAMP is given in microfarads Since fault timing is generated by the constant−current charging of CFLT, the capacitor value is determined from either equation (7) or (8), as appropriate. C C FLT(min) + FLT(min) + 55 55 t SS2 3.75 (7) ǒtSS2 ) tCCǓ 3.75 (8) where: • • • CFLT(min) is the recommended capacitor value, in microfarads, tSS2 is the result of equation (6), in seconds, and tCC is the result of equation (5), in seconds. Continuing the typical application example, using a 100-µF input capacitor (CLOAD), equations (3) and (4) estimate the load voltage ramping to approximately −46 V during the soft-start period. If the module should operate down to −72 V input supply, approximately another 1.58-ms of constant-current charging may be required. Therefore, equations (6) and (8) are used to determine CFLT(min), and the result of 0.043-µF suggests the 0.047-µF standard value. www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2398DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2398DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2398DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2398DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2399DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2399DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2399DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2399DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2398DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS2399DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2398DGKR MSOP DGK 8 2500 346.0 346.0 29.0 TPS2399DGKR MSOP DGK 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS2398DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 2398 Samples TPS2399DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 2399 Samples TPS2399DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 2399 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of