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TPS2421-1, TPS2421-2
SLUS907K – JANUARY 2009 – REVISED JUNE 2019
TPS2421-x 5-A, 20-V Integrated FET Hot Swap
1 Features
3 Description
•
•
•
•
The TPS2421 device provides highly integrated hot
swap power management and superior protection in
applications where the load is powered by busses up
to 20 V. The TPS2421 device is well suited to
standard bus voltages as low as 3.3 V because of the
maximum-UV turnon threshold of 2.9 V. These
devices are very effective in systems where a voltage
bus must be protected to prevent shorts from
interrupting or damaging the unit. The TPS2421
device is an easy to use devices in an 8-pin
PowerPad™ SO-8 package.
1
•
•
•
•
•
•
Integrated Pass MOSFET
Up to 20-V Bus Operation
Programmable Fault Current
Current Limit Proportionally Larger than Fault
Current
Programmable Fault Timer
Internal MOSFET Power Limiting
Latch-Off on Fault (TPS2421-1) and Retry
(TPS2421-2) Versions
SO-8 PowerPad™ Package
–40°C to +125°C Junction Temperature Range
UL2367 Recognized - File Number E169910
The TPS2421 device has multiple programmable
protection features. Load protection is accomplished
by a non-current limiting fault threshold, a hard
current limit, and a fault timer. The current dual
thresholds allow the system to draw short high
current pulses, while the fault timer is running, without
causing a voltage droop at the load. An example of
this is a disk drive startup. This technique is ideal for
loads that experience brief high demand, but benefit
from protection levels in-line with their average
current draw.
2 Applications
•
•
•
•
•
•
•
RAID Arrays
Telecommunications
Plug-In Circuit Boards
Disk Drives
SSDs
PCIE
Fan Control
Hotswap MOSFET protection is provided by power
limit circuitry which protects the internal MOSFET
against SOA related failures.
The TPS2421 device is available in latch-off on fault
(TPS2421-1) and retry on fault (TPS2421-2).
Device Information(1)
PART NUMBER
TPS2421-1
PACKAGE
HSOP (8)
TPS2421-2
BODY SIZE (NOM)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VIN
2
EN
VOUT
VOUT 7
FLT
ISET
CT
PG
4
5
6
8
CLOAD
CCT
GND
1
Optional: To
System Monitor
3
R RSET
VIN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2421-1, TPS2421-2
SLUS907K – JANUARY 2009 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
5
5
6
7.1
7.2
7.3
7.4
7.5
7.6
6
6
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
8.5 Programming........................................................... 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 20
10.1 PowerPad™ .......................................................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (October 2016) to Revision K
•
Page
Updated the VIN, VOUT Unit in the Electrical Characteristics table ...................................................................................... 7
Changes from Revision I (January 2015) to Revision J
Page
•
Updated Maximum Allowable Load to Ensure Successful Startup section.......................................................................... 14
•
Updated Equation 6.............................................................................................................................................................. 14
Changes from Revision H (January 2014) to Revision I
Page
•
Changed the package and ordering information to the Device Comparison Table ............................................................... 5
•
Added the I/O column to the Pin Functions table .................................................................................................................. 5
•
Added the ESD Ratings table and changed the CDM value From: 400V To: ±500V ........................................................... 6
•
Replaced the Dissipation Ratings table with the Thermal Information table .......................................................................... 6
•
Added the Detailed Description section................................................................................................................................ 11
•
Changed the PIN DESCRIPTION section to the Feature Description section..................................................................... 12
•
Added the Application and Implementation section ............................................................................................................ 17
•
Added the Power Supply Recommendations section .......................................................................................................... 20
•
Added Figure 23 ................................................................................................................................................................... 21
Changes from Revision G (May 2013) to Revision H
Page
•
Deleted minimum voltage from voltage range in the document title, features list and description ........................................ 1
•
Added 5-A to document title ................................................................................................................................................... 1
•
Changed listed to recognized in UL FEATURES bullet, also added specific UL number...................................................... 1
•
Added SSDs, PCIE, and Fan Control to the APPLICATIONS list.......................................................................................... 1
2
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Copyright © 2009–2019, Texas Instruments Incorporated
Product Folder Links: TPS2421-1 TPS2421-2
TPS2421-1, TPS2421-2
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SLUS907K – JANUARY 2009 – REVISED JUNE 2019
•
Added maximum-UV turn-on threshold of 2.9 V sentence to the first paragraph of the DESCRIPTION............................... 1
•
Deleted capacitor, CVIN, and diode from the Typical Application image. Also changed RSET to RRSET and COUT to
CLOAD. Removed voltage range and changed OUT to VOUT. Also removed note on the former COUT stating that this
is only required in systems with lead and/or load inductance ................................................................................................ 1
•
Changed COUT to CLOAD and RSET to RRSET throughout document ......................................................................................... 1
•
Changed current limit value of the ISET description from 125% to 150% in thePin Functions table. Also removed
TPS2421 only text form this description................................................................................................................................. 5
•
Changed COUT to CVOUT for the power limit parameter in the Electrical Characteristics table................................................ 7
•
Changed RSET = 100 kW to RRSET = 100 kΩ in the FAULT CURRENT vs JUNCTION TEMPERATURE graph................... 9
•
Added note for TPS2421-1 to the VIN description in the PIN DESCRIPTION section ........................................................ 13
•
Changed VIN to VVIN in the functional block diagram, Equation 6 ........................................................................................ 14
•
Changed In to VVIN in Equation 17 ....................................................................................................................................... 18
Changes from Revision G (May 2013) to Revision H
Page
•
Deleted minimum voltage from voltage range in the document title, features list and description ........................................ 1
•
Added 5-A to document title ................................................................................................................................................... 1
•
Changed listed to recognized in UL FEATURES bullet, also added specific UL number...................................................... 1
•
Added SSDs, PCIE, and Fan Control to the APPLICATIONS list.......................................................................................... 1
•
Added maximum-UV turn-on threshold of 2.9 V sentence to the first paragraph of the DESCRIPTION............................... 1
•
Deleted capacitor, CVIN, and diode from the Typical Application image. Also changed RSET to RRSET and COUT to
CLOAD. Removed voltage range and changed OUT to VOUT. Also removed note on the former COUT stating that this
is only required in systems with lead and/or load inductance ................................................................................................ 1
•
Changed COUT to CLOAD and RSET to RRSET throughout document ......................................................................................... 1
•
Changed current limit value of the ISET description from 125% to 150% in thePin Functions table. Also removed
TPS2421 only text form this description................................................................................................................................. 5
•
Changed COUT to CVOUT for the power limit parameter in the Electrical Characteristics table................................................ 7
•
Changed RSET = 100 kW to RRSET = 100 kΩ in the FAULT CURRENT vs JUNCTION TEMPERATURE graph................... 9
•
Added note for TPS2421-1 to the VIN description in the PIN DESCRIPTION section ........................................................ 13
•
Changed VIN to VVIN in the functional block diagram, Equation 6 ........................................................................................ 14
•
Changed In to VVIN in Equation 17 ....................................................................................................................................... 18
Changes from Revision F (April 2013) to Revision G
•
Page
Deleted ISET, CT Voltage from the Absolute Maximum Ratings (1) table.................................................................................. 6
Changes from Revision E (September 2011) to Revision F
Page
•
Changed CCT values From: MIN = 100 pF/µF To 0.1 nF and MAX From: 10 pF/µF To: -- in the Recommended
Operating Conditions table ..................................................................................................................................................... 6
•
Added RRSET to the Recommended Operating Conditions table ............................................................................................ 6
•
Changed the conditions statement of the Electrical Characteristics table ............................................................................. 7
•
Changed the TEST CONDITIONS for RON ............................................................................................................................. 7
•
Changed ILIM / IFLT To: ILIM / ISET.............................................................................................................................................. 7
•
Changed the PIN DESCRIPTION section ............................................................................................................................ 12
•
Changed the Application Information section. ...................................................................................................................... 17
Copyright © 2009–2019, Texas Instruments Incorporated
Product Folder Links: TPS2421-1 TPS2421-2
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SLUS907K – JANUARY 2009 – REVISED JUNE 2019
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Changes from Revision D (August 2010) to Revision E
Page
•
Changed RFLT to RSET ........................................................................................................................................................ 9
•
Changed equation 3 from RIFLT to RISET and IFAULT to ISET ........................................................................................ 12
Changes from Revision C (July 2010) to Revision D
•
Page
Added Feature: UL Listed - File Number E169910 ................................................................................................................ 1
Changes from Revision B (June 2010) to Revision C
•
Page
Changed TSD (ms) column in Table 3. (the table was deleted in revision F) ....................................................................... 14
Changes from Revision A (March 2009) to Revision B
•
4
Page
Added For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or visit the device product folder on www.ti.com............................................................................................ 5
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Copyright © 2009–2019, Texas Instruments Incorporated
Product Folder Links: TPS2421-1 TPS2421-2
TPS2421-1, TPS2421-2
www.ti.com
SLUS907K – JANUARY 2009 – REVISED JUNE 2019
5 Device Comparison Table
DEVICE
FEATURE
TPS2421-1
Latch-off
TPS2421-2
Auto-retry
6 Pin Configuration and Functions
TPS2421-x
DDA Package
Top View
1 FLT
PG
8
2 EN
VOUT
7
CT
6
ISET
5
3
VIN
4
GND
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
1
FLT
O
Fault low indicated the fault time has expired and the FET is switched off
2
EN
I
Device is enabled when this pin is pulled low
3
VIN
I
Power In and control supply voltage
4
GND
—
GND
5
ISET
I/O
A resistor to ground sets the fault current, the current limit is 150% of the fault current
6
CT
I/O
A capacitor to ground sets the fault time
7
VOUT
O
Output to the load
8
PG
O
Power Good low represents the output voltage is within 300 mV of the input voltage
Copyright © 2009–2019, Texas Instruments Incorporated
Product Folder Links: TPS2421-1 TPS2421-2
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SLUS907K – JANUARY 2009 – REVISED JUNE 2019
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted) (2)
MIN
MAX
VVIN, VVOUT
Input voltage
–0.3
25
V
EN
Input voltage
–0.3
6
V
FLT, PG
Voltage
–0.3
20
V
CT, (3) ISET (3) Voltage
–0.3
3
V
IMAX
Maximum continuous output current
FLT, PG
Output sink current
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
9
A
10
mA
Internally Limited
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Do not apply voltage to these pins.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
VVIN, VVOUT
Input voltage
3
20
V
EN
Voltage
0
5
V
FLT, PG
Voltage
0
20
V
IOUT
Continuous output current
0
6
A
FLT, PG
Output sink current
0
1
mA
49.9
200
kΩ
–40
125
°C
CCT
0.1
RRSET
TJ
Junction temperature
UNIT
nF
7.4 Thermal Information
TPS2421-x
THERMAL METRIC (1)
DDA (HSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
41.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.7
°C/W
RθJB
Junction-to-board thermal resistance
22.3
°C/W
ψJT
Junction-to-top characterization parameter
5.3
°C/W
ψJB
Junction-to-board characterization parameter
22.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLUS907K – JANUARY 2009 – REVISED JUNE 2019
7.5 Electrical Characteristics
Unless otherwise noted: 3 V ≤ VVIN ≤ 18 V, EN = 0 V, PG = FLT = open, ROUT = open, RRSET = 49.9 kΩ, –40°C ≤ TJ ≤ +125°C,
No external capacitor connected to VOUT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VIN
UVLO
VIN rising
2.6
Hysteresis
2.85
2.9
150
V
mV
EN = 2.4 V
25
100
μA
EN = 0 V
3.9
5
mA
RON
RVIN-VOUT, IVOUT < ILIM, 1 A ≤ IVOUT ≤ 4.5 A
33
50
mΩ
Power limit
TPS242x
VVIN: 12 V, CVOUT = 1000 μF, EN: 3 V → 0 V
5
7.5
W
Reverse diode
voltage
VVOUT > VVIN , EN = 5 V, IVIN = –1 A
0.77
1
V
Bias current
VIN, VOUT
3
ISET
IVOUT ↑, ICT: sinking → sourcing, pulsed test
0°C ≤ TJ ≤ +85°C
ISET
Fault current
threshold
–40°C ≤ TJ ≤ +125°C
ILIM /
ISET
ILIM
Ratio ILIM / ISET
Current limit
RRSET = 200 kΩ
0.8
1.2
RRSET = 100 kΩ
1.8
2.2
RRSET = 49.9 kΩ
3.6
4.4
RRSET = 200 kΩ
0.75
1.25
RRSET = 100 kΩ
1.75
2.25
RRSET = 49.9 kΩ
3.6
A
4.4
RRSET = 200 kΩ
1.1
1.8
2.6
RRSET = 100 kΩ
1.1
1.5
2.1
RRSET = 49.9 kΩ
1.1
1.4
1.6
RRSET = 200 kΩ
1.1
1.8
2.4
A
RRSET = 100 kΩ
2.3
3
3.7
A
RRSET = 49.9 kΩ
4.6
5.5
6.3
A
IVOUT rising, VVIN–VOUT = 0.3 V, pulsed test
A
CT
Charge-discharge ICT sourcing, VCT = 1 V, In current limit
current
ICT sinking (–2), VCT = 1 V, drive CT to 1 V, measure current
Threshold voltage
ON/OFF fault
duty cycle
29
35
41
1
1.4
1.8
VCT rising
1.3
1.4
1.5
VCT falling, drive CT to 1 V, measure current
0.1
0.16
0.3
VVOUT = 0 V
μA
V
2.8% 3.7% 4.6%
EN
V EN falling
0.8
1
1.5
V
Hysteresis
20
150
250
mV
VEN = 2.4 V
–2
0
0.5
VEN = 0.2 V
–3
1
0.5
Turnon
VVIN = 3.3 V, ILOAD = 1 A, V EN : 2.4 V → 0.2 V,
propagation delay VVOUT: rising 90% × VVIN
350
500
Turnoff
VVIN = 3.3 V, ILOAD = 1 A, V EN : 0.2 V → 2.4 V,
propagation delay VVOUT: ↓ 10% × VVIN
30
50
Threshold voltage
Input bias current
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μA
μs
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Electrical Characteristics (continued)
Unless otherwise noted: 3 V ≤ VVIN ≤ 18 V, EN = 0 V, PG = FLT = open, ROUT = open, RRSET = 49.9 kΩ, –40°C ≤ TJ ≤ +125°C,
No external capacitor connected to VOUT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
FLT
VOL
Low level output
voltage
VCT = 1.8 V, I FLT = 1 mA
Leakage current
V FLT = 18 V
0.2
0.4
V
1
μA
PG
PG threshold
VOL
V(VIN–VOUT) falling
0.4
0.5
0.75
Hysteresis
0.1
0.25
0.4
0.2
0.4
Low level output
voltage
I PG = 1 mA
Leakage current
V PG = 18 V
1
V
μA
THERMAL SHUTDOWN
TSD
Thermal
shutdown
Junction temperature rising
160
Hysteresis
8
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°C
10
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SLUS907K – JANUARY 2009 – REVISED JUNE 2019
7.6 Typical Characteristics
2.20
1.50
2.15
VTHRESH – Fault Timer Threshold Voltage -– V
RSET = 100 kW
2.10
2.50
2.00
1.95
1.90
1.85
1.80
–50
TJ
0
50
100
– Junction
Temperature – °C
150
1.45
1.40
1.35
1.30
–50
TJ
Figure 1. Fault Current vs Junction Temperature
50
– Junction
Temperature – °C
100
150
Figure 2. Fault Timer Threshold Voltage vs Junction
Temperature
24
8.0
7.5
0
ILOAD = 1 A
Sleep Mode
7.0
ISupply – Supply Current – mA
PLIMIT – Power Limit Level – W
22
6.5
6.0
5.5
5.0
4.5
20
18
16
14
4.0
12
3.5
3.0
–50
TJ
0
50
100
– Junction
Temperature – °C
150
Figure 3. Power Limit vs Junction Temperature
10
–50
TJ
0
50
– Junction
Temperature – °C
100
150
Figure 4. Supply Current vs Junction Temperature
PG
PG
VCT
EN
3 V startup into 3.2 A load
RRSET = 49.9 kΩ
ILOAD
3.3 V overload step from 3.8 A to 5.5
A, RRSET = 49.9 kΩ
ILOAD
VOUT
VOUT
Figure 5. 3-V Startup into 1-Ω Load
Figure 6. 3-V Firm Overload, Load Stepped
from 3.8 A to 5.5 A
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Typical Characteristics (continued)
PG
FLT
VCT
VCT
ILOAD
ILOAD
3.3 V overload shorted while under 3.5
A load, RRSET = 49.9 kΩ
3.3 V overload step from 3.8 A to 7.1
A, RRSET = 49.9 kΩ
VOUT
VOUT
Figure 7. 3-V Hard Overload, Load Stepped
from 3.8 A to 7.1 A
Figure 8. 3-V Output Shorted While Under 3.5-A Load
3.3 V attempting startup into 1 W,
2200 µF load, retry mode - CT = 0.1 µF
PG
EN
RRSET = 49.9 kΩ
VCT
VCT
ILOAD
ILOAD
3.3 V, 1600 µF added while under 3.5
A load, RRSET = 49.9 kΩ
VOUT
VOUT
Figure 9. 3 V, 1600 μF Added to 3.5-A Load
Figure 10. 3-V Retry Startup into 1-Ω, 2200-μF Load
Figure 11. Startup into a Short Circuit Output
10
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SLUS907K – JANUARY 2009 – REVISED JUNE 2019
8 Detailed Description
8.1 Overview
The TPS2421 device provides highly integrated hot swap power management and superior protection in
applications where the load is powered by busses up to 20 V.
The device has multiple programmable protection features. Load protection is accomplished by a non-current
limiting fault threshold, a hard current limit, and a fault timer. Hotswap MOSFET protection is provided by power
limit circuitry which protects the internal MOSFET against SOA related failures.
8.2 Functional Block Diagram
I(D)
Detector
IVOUT
VIN 3
7 VOUT
V(DS) Detector
+
6
t
10 µA
8
Q
Pump
Internal Rail
GND 4
LCA
+
Constant
Power
Engine
ILIM
VVIN ±500 mV
PLIM
1 FLT
1.6 u ILIM
+
Fast Trip
Comparator
1.5 u ISET
+
1V
ISET 5
+
ISET
200 k
1V
RRSET
EN
PG
+
2.85 V / 2.7 V
2
+
VVIN
+
1.15 V / 1.00 V
10 0Ÿ
THERMAL
SHUTDOWN
16.8 0Ÿ
S
Q
R
Q
VIN
LATCH -1
RETRY -2
FACTORY
SET
50 NŸ
35 µA
CT
1.4 V
+
0.16 V
6
+
40 µA
1.4 µA
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8.3 Feature Description
8.3.1 CT
Connect a capacitor from CT to GND to set the fault time. The fault timer starts when IVOUT exceeds ISET or when
SOA protection mode is active, charging the capacitor with 35 μA from GND towards an upper threshold of 1.4 V.
If the capacitor reaches the upper threshold, the internal pass MOSFET is turned off. For the TPS2421-1 device,
the MOSFET remains off until EN is cycled. For the TPS2421-2 device, the capacitor discharges at 1.4 μA to
0.16 V and then re-enable the pass MOSFET. If the upper threshold is not crossed, the capacitor discharges at
40 μA to 0.16 V and then to 0 V at 1.4 μA. When the device is disabled, CT is pulled to GND through a 50-kΩ
resistor.
The timer period must be chosen long enough to allow the external load capacitance to charge. The nominal (not
including component tolerances) fault timer period is selected using Equation 1 where TFAULT is the minimum
timer period in seconds and CCT is in Farads.
CCT =
TFAULT
40 x 103
(1)
For the TPS2421-2 device, the second and subsequent retry timer periods are slightly shorter than the first retry
period. CT nominal (not including component tolerances) discharge time, tSD from 1.4 V to 0.16 V is shown in
Equation 2, where CCT is in Farads and tSD is in seconds.
TSD = 885.7 ´ 103 ´ CCT
(2)
The nominal ratio of on to off times represents about a 3.7% duty cycle when a hard fault is present on the
output.
8.3.2 FLT
Open-drain output that pulls low on any condition that causes the output to open. These conditions are either an
overload with a fault time-out, or a thermal shutdown. FLT becomes operational before UV, when VVIN is greater
than 1 V. FLT pulses low momentarily prior to the onset of VVOUT ramp up during IN or EN based startup.
8.3.3 GND
This is the most negative voltage in the circuit and is used as reference for all voltage measurements unless
otherwise specified.
8.3.4 ISET
A resistor from this pin to GND sets both the fault current (ISET) and current limit (ILIM) levels. The current limit is
internally set at 150% of the fault current. The fault timer described in the CT section starts when IVOUT exceeds
ISET.
The internal MOSFET actively limits current if IVIN reaches the current limit set point. The fault timer operation is
the same in this mode as described previously.
The fault current value is programmed as shown in Equation 3:
200kW
RRSET =
ISET
(3)
EN: When this pin is pulled low, the device is enabled. The input threshold is hysteretic, allowing the user to
program a startup delay with an external RC circuit. EN is pulled to VIN with a 10-MΩ resistor and to GND with a
16.8-MΩ resistor. Because high impedance pullup and pulldown resistors are used to reduce current draw, any
external FET controlling this pin must be low leakage.
8.3.5 VIN
Input voltage to the TPS2421 device. The recommended operating voltage range is 3 V to 20 V. Connect VIN to
the power source.
12
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Feature Description (continued)
NOTE
(For TPS2421-1 only) Brownout-type conditions (VIN < 2.85 V) prior to startup can trigger
the fault logic and prevent startup. For more information go to E2E.TI.com.
8.3.6 VOUT
Output connection for the TPS2421 device. VVOUT in the ON condition considering the ON resistance of the
internal MOSFET, RON is shown in Equation 4:
VVOUT = VVIN - RON ´ IVOUT
(4)
Connect VOUT to the load.
8.3.7 PG
Active low, Open Drain output, Power Good indicates that there is no fault condition and the output voltage is
within 0.5 V of the input voltage. PG becomes operational before UV, whenever VVIN is greater than 1 V.
8.4 Device Functional Modes
8.4.1 Startup
Large inrush current occurs when power is applied to discharged capacitors and load. During the inrush period,
the TPS2421 device operates in power limit (or SOA protect mode) managing the current as VVOUT rises. In SOA
protect mode, the internal MOSFET power dissipation ([VVIN – VVOUT] × IVOUT) is regulated at 5 W typical while
the fault timer starts and CCT ramps up. As the charge builds on CLOAD, the current increases towards ILIM. When
the capacitor is fully charged, IVOUT drops to the dc load value, the fault timer stops, and CCT ramps down. In
order for the TPS2421 device to start properly, the fault timer duration must exceed CLOAD startup time, tON.
Startup time without additional dc loading is calculated using Equation 5 where PLIM = 5 W (typical).
t ON =
CLOAD ´ PLIM
2
2 ´ ILIM
+
2
CLOAD ´ VVIN
2 ´ PLIM
(5)
When the load has a resistive component in addition to CLOAD, the fault time must be extended because the
resistive load current is unavailable to charge CLOAD. Use Table 1 and Table 2 to predict startup time in the
presence of resistive dc loading.
Refer to the TPS2421 Design Calculator Tool (SLUC427) for assistance with design calculations.
Table 1. Startup Time (ms) with DC Loading: VIN = 5 V, PLIM = 3 W, ILIM = 5 A
RLOAD_(Ω)
CLOAD_ = 100 µF
CLOAD_ = 220 µF
CLOAD_ = 470 µF
CLOAD_ = 1000 µF
1000
0.43
0.95
2.03
4.33
10
0.5
1.11
2.36
5.03
5
0.61
1.34
2.87
6.1
3
0.91
2
4.28
9.11
2.5
1.31
2.88
6.14
13.07
Table 2. Startup Time (ms) with DC Loading: VIN = 12 V, PLIM = 3 W, ILIM = 5 A
RLOAD_(Ω)
CLOAD_ = 100 µF
CLOAD_ = 220 µF
CLOAD_ = 470 µF
CLOAD_ = 1000 µF
10000
2.46
5.41
11.56
24.59
100
2.67
5.87
12.55
26.69
50
2.93
6.45
13.79
29.34
15
6.7
14.74
31.5
67.01
13
11.68
25.69
54.87
116.75
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8.4.2 Maximum Allowable Load to Ensure Successful Startup
The power limiting function of the TPS2421 provides effective protection and limits the maximum allowable
resistive load (RMIN) during startup to ensure SOA of the device. Load resistance lower than RMIN can cause the
output to shut off due to CT timeout or thermal shutdown. The equation for maximum load RMIN as a function of
VIN, PLIM and ILIM is given by Equation 6:
§
·
VIN2
VIN
RLOAD ! RMIN max ¨
,
¸
© 4 u PLIM(min) ILIM(min) u K ¹
§ VIN2
·
VIN
max ¨
,
¸
© 12 ILIM(min) u K ¹
where
•
•
•
•
K = 0.15 for RRSET = 200 kΩ
K = 0.3 for RRSET = 100 kΩ
K = 0.5 for RRSET = 49.9 kΩ
ILIM(min) is the current limit minimum specification given in the EC Table
(6)
The device fails to start if RLOAD < RMIN. It either enters thermal shutdown or CT timer may timeout. The load
resistance during startup (RLOAD) must be higher than RMIN for a successful startup. Ensure that RLOAD is > RMIN
per Equation 6.
8.4.2.1 Enable Pin Considerations
For the case when EN is simply connected to GND, the TPS2421 device starts ramping the voltage on VOUT as
VIN rises above UVLO (approximately 2.85 V typical). If IN does not ramp monotonically, the TPS2421 may
momentarily turnoff then on during startup if IN falls below approximately 2.7 V. To avoid this problem, EN
assertion can be delayed until IN is sufficiently above UVLO. A simple approach is shown in Figure 12. The 100kΩ pullup resistor de-asserts EN when VIN is above approximately 1.75 V maximum which is well below the
minimum UVLO of approximately 2.6 V. The Zener diode ensures that EN remains below 5 V. User control to
enable the TPS2421 device is applied at the ON node to turn on the FET once IN has risen sufficiently above
UVLO.
12-V Bus
3
VIN
100 k
TPS2421
2
FET
ON
EN
GND
ISET
CT
4
5
6
VOUT
7
FLT
1
PG
8
Optional:
To System
Monitor
CLOAD
4.6 V
80.6 k
0.56 µF
Figure 12. EN Delay Circuit
8.4.2.2 Fault Timer
The fault timer is active when the TPS2421 device is in SOA protect mode or the current is above ISET. Figure 13
illustrates operation during non-faulted startup (CLOAD = 470 µF and IVOUT = 1 A in a 12 V system). CCT charges
at approximately 35 µA until TPS2421 device exits SOA protect mode, discharges quickly (approximately 40 µA)
to approximately 0.16 V, and then decays slowly (approximately 1.4 µA) towards zero.
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2V/div
FLT
0.5V/div
CT
1A/div
ILOAD
5V/div
VOUT
5ms/div
Figure 13. Fault Timer Operation During Startup
CCT can be chosen for fault-free startup including expected CLOAD and CCT capacitance tolerance as shown in
Equation 7.
(1 + CLOAD_TOL + CCT_TOL ) ´ t ON
CCT =
40000
(7)
8.4.2.3 Normal Operation
When load current exceeds ISET during normal operation the fault timer starts. If load current drops below ISET
before the fault timer expires, normal operation continues. If load current stays above the ISET threshold the fault
timer expires and a fault is declared. When a fault is declared a TPS2421-1 device turns off an can be restarted
by cycling power or toggling the EN signal. A TPS2421-2 device attempts to turn on at a 3.7% duty cycle until the
fault is cleared. When ILIM is reached during a fault the device goes into current limit and the fault timer keeps
running.
8.4.2.4 Startup into a Short
The controller attempts to power on into a short for the duration of the timer. Figure 11 shows a small current
resulting from power limiting the internal MOSFET. This occurs only once for theTPS2421-1 device. For the
TPS2421-2 device, the cycle repeats at a 3.7% duty cycle as shown in Figure 10.
8.4.3 Shutdown Modes
8.4.3.1 Hard Overload - Fast Trip
When a hard overload causes the load current to exceed approximately 1.6 × ILIM the TPS2421 immediately
shuts off current to the load without waiting for the fault timer to expire. After such a shutoff the TPS2421 device
enters startup mode and attempts to apply power to the load. If the hard overload was caused by a transient,
then normal startup can be expected. If the hard overload is caused by a persistent, continuous failure then the
TPS2421 device enters into current limit during the restart attempt and either latches off (TPS2421-1) or attempts
retry (TPS2421-2).
8.4.3.2 Overcurrent Shutdown
Overcurrent shutdown occurs when the output current exceeds ISET for the duration of the fault timer. Figure 18
shows a step rise in output current which exceeds the ISET threshold but not the ILIM threshold. The increased
current is on for the duration of the timer. When the timer expires, the output is turned off.
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8.5 Programming
8.5.1 Fault (ISET) and Current-Limit (ILIM) Thresholds
The ISET and ILIM thresholds is user programmable with a single external resistor connected to ISET and the ILIM
threshold is internally set according to the ILIM/ISET ratio specified in the electrical characteristics table. The
TPS2421 device uses an internal regulation loop to provide a regulated voltage on the ISET pin. The fault and
current-limit thresholds are proportional to the current sourced out of ISET. The recommended 1% resistor range
is 49.9 kΩ ≤ RRSET ≤ 200 kΩ to ensure the rated accuracy. Many applications require that minimum fault and
current limits are known or that maximum current limit is bounded. Considering the tolerance of the fault and
current limit thresholds, as well as RRSET when selecting values is important. See the Electrical Characteristics
table for specific fault and current limit settings.
Using the data for ISET and ILIM from the Electrical Characteristics, equations are generated and used for other
set points. Equation 8 and Equation 9 are used to calculate minimum and maximum ISET where RRSET,max and
RRSET,min include RRSET tolerances. Equation 10 and Equation 11 calculate RRSET,max and RRSET,min where RTOL is
the 1% resistor tolerance.
185.58
ISET,min =
- 0.13
RRSET,max
(8)
ISET,max =
213.68
+ 0.13
RRSET,min
RRSET,min
213.68
= (1 + RTOL )´
ISET,max - 0.13
(10)
RRSET,max
185.58
= (1 - RTOL )´
ISET,min + 0.13
(11)
(9)
Equation 12 and Equation 13 are used to calculate minimum and maximum ILIM where RRSET,max and RRSET,min
include RRSET tolerances.
232.19
ILIM,min =
- 0.06
RRSET,max
(12)
ILIM,max =
16
259.26
+ 1.11
RRSET,min
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2421 is an integrated FET hot swap device. It is typically used for Hot-Swap and Power rail protection
applications. It operates from 3 V to 20 V with programmable fault current limit, and fault Timer.
The following design procedure can be used to select component values for the device. This section presents a
simplified discussion of the design process.
9.2 Typical Application
12-V Bus
3
VIN
TPS2421
2
EN
GND
ISET
CT
4
5
6
80.6 k
VOUT
7
FLT
1
PG
8
Optional:
To System
Monitor
CLOAD
0.56 µF
Figure 14. Design Example Schematic
9.2.1 Design Requirements
A
•
•
•
•
•
typical design is shown in Figure 14 with the following requirements:
Nominal input voltage, VVIN: 12 V
Maximum expected load current, IVOUT: 2.1 A
Load capacitance, CLOAD: 220 µF
Expected resistive load, RLOAD during startup: 15 Ω
Example calculations are shown in the TPS2421 Design Calculator Tool (SLUC427).
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Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Calculate maximum RRSET to ensure that minimum ISET is above maximum operating load current using
Equation 11 as shown below in Equation 14.
RRSET,max = 0.99 ´
185.58
= 82.39kW
2.1 + 0.13
(14)
● Choose a standard 1% value below RRSET,max for RRSET = 80.6 kΩ
● ISET,min = 2.15 A using Equation 8 meets the maximum operating current requirement of 2.1 A without
starting the fault timer during maximum steady state operation for RRSET = 80.6 kΩ, 1%.
● ISET,max = 4.359 A using Equation 9 for RRSET = 80.6 Ω, 1%.
2. Calculate minimum and maximum ILIM.
● ILIM,min = 2.792 A and ILIM,max = 4.359 A using Equation 12 and Equation 13 for RRSET = 80.6 kΩ, 1%.
3. Minimum RLOAD at startup using Equation 6 is 12 Ω. Because RLOAD = 15 Ω is present during circuit
startup, use tON = 15 ms from Table 2 for CLOAD = 220 µF and RLOAD = 15 Ω.
● Calculate CCT = 0.48 µF including CLOAD and CCT tolerances (CLOAD_TOL = 20% and CCT_TOL = 10%)
using Equation 15.
CCT =
(1 + CLOAD _ TOL + CT _ TOL ) ´ t ON
40000
=
(1 + 0.2 + 0.1) ´ 0.012
= 0.48 mF
40000
(15)
9.2.2.1 Transient Protection
The need for transient protection in conjunction with hot-swap controllers must always be considered. When the
TPS2421 device interrupts current flow, input inductance generates a positive voltage spike on the input and
output inductance generates a negative voltage spike on the output. Such transients can easily exceed twice the
supply voltage if steps are not taken to address the issue. Typical methods for addressing transients include;
• Minimizing lead length/inductance into and out of the device
• Voltage Suppressors (TVS) on the input to absorb inductive spikes
• Schottky diode across the output to absorb negative spikes
• A combination of ceramic and electrolytic capacitors on the input and output to absorb energy
• Use PCB GND planes
Equation 16 estimates the magnitude of these voltage spikes:
VSPIKE(absolute ) = VNOM + ILOAD ´ L
C
where
•
•
•
•
VNOM is the nominal supply voltage
ILOAD is the load current
C is the capacitance present at the input or output of the TPS2421 device
L equals the effective inductance seen looking into the source or the load
(16)
Calculating the inductance due to a straight length of wire is shown in Equation 17.
æ 4´L
ö
- 0.75 ÷ (nH)
Lstraightwire » 0.2 ´ L ´ VVIN ç
è D
ø
where
•
•
18
L is the length of the wire
D is diameter of the wire
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Typical Application (continued)
Some applications may require the addition of a TVS to prevent transients from exceeding the absolute ratings if
sufficient capacitance cannot be included.
9.2.3 Application Curves
PG
PG
EN
VCT
12 V Startup into 15 W, 700 mF Load
RRSET = 49.9 kW
ILOAD
Temperature capacitive overload,
power limit tripped
12-V load at 1.5 A, then 140 mF added to
load
ILOAD
RRSET = 49.9 kW
VOUT
VOUT
Figure 15. 12-V Startup into 15-Ω, 700-μF Load
Figure 16. 12 V, 140 μF Added to 8-Ω Load
PG
VIN
12-V failed startup in 4 W, 0 mF load
VCT
EN
ILOAD
FLT
Soft overload, power limit not tripped,
12-V load stepped from 3 A to 4.2 A,
CLOAD = 700 µF, R RSET = 49.9 kΩ
VOUT
VOUT
Figure 17. 12-V Faulted Startup into 4-Ω Load
Figure 18. 12-V Soft Overload, 3 A to 4.2 A,
Power Limit Not Tripped
PG
PG
VCT
VCT
ILOAD
ILOAD
Overload, power limit tripped,
12-V load stepped from 3 A to 5.4 A,
CLOAD = 700 µF, R RSET = 49.9 kΩ
12-V load at 3.6 A, then short applied
to output, RRSET = 49.9 kΩ
VOUT
VOUT
Figure 19. 12-V Firm Overload, 3 A to 5.4 A,
Power Limit Tripped
Figure 20. 12-V Hard Overload, 3.6-A Load then Short
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Typical Application (continued)
12-V PLIM during startup into 60 Ω, 800
µF
RRSET = 49.9 kΩ
RFLT =ILOAD
100 k
12-V PLIM during startup into
overload, CT = 0.1 µF
RRSET = 49.9 kΩ
P dissipation internal FET
VOUT
CT
VOUT
P dissipation internal FET
ILOAD
Figure 21. Power Dissipation During 12-V
Startup into 60 Ω, 800 μF
Figure 22. Power Dissipation During 12-V
Startup into 15 Ω, 140 μF
10 Power Supply Recommendations
10.1 PowerPad™
When properly mounted the PowerPad package provides significantly greater cooling ability than an ordinary
package. To operate at rated power the PowerPAD must be soldered directly to the PC board GND plane
directly under the device. The PowerPAD is at GND potential and can be connected using multiple vias to inner
layer GND. Other planes, such a the bottom side of the circuit board can be used to increase heat sinking in
higher current applications. Refer to Technical Briefs: PowerPad™ Thermally Enhanced Package (SLMA002)
and PowerPad™ Made Easy (SLMA004) or more information on using this PowerPad™ package. These
documents are available at www.ti.com (Search by Keyword).
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11 Layout
11.1 Layout Guidelines
•
•
•
Locate all TPS2421 support components, RRSET, CCT, or any input or output voltage clamps, close to their
connection pin.
Connect the other end of the component to the inner layer GND without trace length.
The trace routing the RRSET resistor to the TPS2421 device must be as short as possible to reduce parasitic
effects on fault and current-limit accuracy.
11.2 Layout Example
Top layer
Bottom layer signal ground plane
Via to signal ground plane
FLT
1
8
PG
EN
2
7
VOUT
VIN
3
6
CT
GND
4
5
ISET
VIN
High Frequency
Bypass Capacitor
VIN
*
(1)
Ground Bottom
layer
See
Note 1
VOUT
Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 23. Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Using the TPS2420, TPS2421-1, TPS2421-2
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS2421-1
Click here
Click here
Click here
Click here
Click here
TPS2421-2
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PowerPad, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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15-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS2421-1DDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2421-1
TPS2421-1DDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2421-1
TPS2421-2DDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2421-2
TPS2421-2DDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2421-2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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