TPS2481PW

TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Positive Voltage Intelligent Protection Device Hotswap Controller and I2C Current Monitor Check for Samples: TPS2480, TPS2481 FEATURES DESCRIPTION • • • • • • The TPS2480/81 are designed to minimize inrush into applications and protect both the load and the FET from over-current or short circuit events. They control an external N-channel MOSFET switch and provide accurate voltage, current, and power monitoring using a configurable 12 bit A/D converter via an I2C interface. The independently adjustable power limit and current limit ensure that the external MOSFET operates within the FET's Safe Operating Area (SOA). 1 • • Programmable FET Power Limit External N-Channel FET Gate Drive Programmable Fault Timer Open Drain Power Good Output I2C monitoring of Current, Voltage and Power High Accuracy Current Monitoring (1% over temperature) Dynamic Calibration 9-V to 26-V Input Range The flexible design includes a Power Good output which can be used for sequencing as well as load fault indication. An external timer capacitor can set the fault time to help immunize the system from nuisance shutdowns during brief transient events. APPLICATIONS • • • • Servers Hard Drives Storage Networks Base Stations The monitoring circuitry incorporates a high accuracy A/D converter which can be configured from a 9 to 13 bit converter. The internal gain of the A/D can be configured to scale the current, voltage and power readings to the needs of the application. An additional multiplying register calculates power in Watts. The I2C interface uses multi-level addressing to allow up to 16 programmable addresses. Simplified Application Diagram 2 mW 9 V to 26 V 0.01 mF 3.3 V to 5 V 0.01 mF 10 kW 10 kW 10kW 4 17 VS VINP 2 SCL 1 SDA 6 EN 7 VREF 15 14 18 13 12 VCC SENSE VINM GATE VOUT PG 11 TPS2480/1 PROG GND GND A0 A1 TIMER 190 kW 8 10 16 20 19 9 0.01mF 33 kW 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com DESCRIPTION (CONT.) The TPS2480 and TPS2481 monitors shunts on buses that can vary from 9 V to 26 V and with a few external components it is possible to monitor buses as high as 80 V. The monitoring circuitry uses a single 3-V to 5.5-V supply, drawing a maximum of 1 mA of supply current. DEVICE INFORMATION (1) DEVICE JUNCTION TEMPERATURE PACKAGE TPS2480 -40°C to 125°C TPS2481 -40°C to 125°C (3) (4) FUNCTION MARKING PW20 Latch Off TPS2480 PW20 Auto Retry TPS2481 For package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at www.ti.com. DISSIPATION RATINGS (1) (1) (2) (1) (2) (3) PACKAGE qJA HIGH K, °C/W qJA (Air Flow) HIGH-k TPS2480 88.3 74.5 TPS2481 88.3 74.5 (4) , °C/W Tested per JEDEC JESD51, natural convection. The definitions of high-k and low-k are per JESD 51-7and JESD 51-3. Low-k (2 signal - no plane, 3 in. by 3 in. board, 0.062 in. thick, 1 oz. copper) test board with the pad soldered, and an additional 0.12 in.2 of top-side copper added to the pad. High-k is a (2 signal – 2 plane) test board with the pad soldered. The best case thermal resistance is obtained using the recommendations per SLMA002A (2 signal - 2 plane with the pad connected to the plane). RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Input voltage range 9 80 PROG Input voltage range 0.4 4 VREF Sourcing current 0 1 VS Input voltage range 3 5.5 VINP, VINM Input voltage range 0 24 Tstg Operating free air temperature -40 85 TJ Operating junction temperature -40 125 (1) 2 (1) V mA V °C Hotswap circuits may experience voltage surges during events such as hotplug and output shorts. The maximum Recommended Operating Voltage is derated below the Absolute Maximum to allow for tolerance of protection devices (clamps). If the application does not have input surges, the TPS2480 may be used up to its Absolute Maximum Rating with no degradation of performance or reliability. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) UNIT Input voltage range, VCC, Sense, Enable, OUT -0.3 to 100 Supply voltage, VS GND - 0.3 to 6 Input voltage, common mode, VINP, VINM GND- 0.3 to + 26 Input voltage, differential, VINP, VINM -26 to + 26 Input voltage range, PROG Output voltage range, GATE, PG -0.3 to 100 Output voltage range, TIMER, VREF -0.3 to 6 Sink current, PG 10 Source current, VREF 0 to 2 Sink current, PROG GND- 0.3 to + 6.0 SCL GND- 0.3 to VS + 0.3 Current into SDA, SCL, VS, VINP, VINM, A0, A1, GNDB 5 Open drain digital output current 10 ESD rating, HBM 2k ESD rating, CDM 500 Operating junction temperature range, TJ - 40 to + 125 Storage temperature range, Tstg (2) (3) mA 2 SDA (1) V -0.3 to 6 - 40 to 150 V mA V °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND unless otherwise stated. Do not apply voltage to these pins. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 3 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current (VCC) IVCC IVS VPOR Enabled VEN = Hi VSENSE = VOUT = VVCC 450 1000 Disabled VEN = Lo VSENSE = VVCC = VOUT = 0 90 250 Quiescent current operating 0.7 1.0 mA Quiescent current Power down mode 6 15 mA Power On reset threshold 2 mA V Current Sense Input (SENSE) ISENSE Input bias current VSENSE = VVCC VOUT = VVCC 7.5 20 mA 4 4.1 V 5 mA 375 600 Ω 25 33 Reference Voltage Output (VREF) VREF Reference voltage 0 < IVREF < 1 mA 3.9 Power Limiting Input (PROG) IPROG Input bias current; device enabled; sourcing or sinking 0 < VPROG < 4 V VEN = 48 V RPROG Pulldown resistance; device disabled IPROG = 200 mA; VEN = 0 V Power Limiting and Current Limiting (SENSE) VCL Current sense threshold V(VCC-SENSE) with power limiting trip VPROG = 2.4 V; VOUT = 0 V or VPROG = 0.9 V; VOUT = 30 V; VVCC = 48 V VSENSE Current sense threshold V(VCC-sense) without power limiting trip VPROG = 4 V; VSENSE = VOUT tF_TRIP VPROG = 4 V; VOUT = VSENSE; V(VCC-SENSE): 0 Large overload response time rising to 200 mV; C(GATE-OUT) = 2 nF; V(GATE-OUT) = to GATE low 1V 17 mV 45 50 55 1.2 ms Timer Operation (TIMER) ISOURCE ISINK Charge current (sourcing) Discharge current (sinking) VTIMER = 0 V 15.0 25.0 34.0 VTIMER = 0 V; TJ = 25°C 20.0 25.0 30.0 VTIMER = 5 V 1.50 2.5 3.70 VTIMER = 5 V; TJ = 25°C 2.10 2.5 3.10 3.9 4.0 4.1 TIMER upper threshold voltage DRETRY mA V TIMER lower reset threshold voltage TPS2481 only 0.96 1.0 1.04 Fault retry duty cycle TPS2481 only 0.5% 0.75% 1.0% Gate Drive Output (GATE) IGATE GATE sourcing current GATE sinking current VSENSE = VVCC; V(GATE-OUT) = 7 V; VEN = Hi 15 22 35 VEN = Lo; VGATE = VVCC 1.8 2.4 2.8 VEN = Hi; VGATE = VVCC; V(VCC-SENSE)³ 200 mV 75 125 250 VGATE-OUT GATE output voltage tD_ON Propagation delay: EN going true to GATE output high VEN = 0 → 2.5 V, 50% of VEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MOhm 25 40 tD_OFF Propagation delay: EN going false (0 V) to GATE output low VEN = 2.5 V → 0 V, 50% of VEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ, tFALL < 0.1 ms 0.5 1 Propagation delay: TIMER expires to GATE output low VTIMER: 0 → 5 V, tRISE < 0.1 ms. 50% of VTIMER to 50% of VGATE, VOUT = VCC , R(GATE-OUT) = 1 MΩ, 0.8 1 4 12 Submit Documentation Feedback 16 mA mA V ms Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Good Output (PG) IPG = 2 mA 0.1 0.25 IPG = 4 mA 0.25 0.5 1.25 1.7 VPG_L Low voltage (sinking) VPGTL PG threshold voltage; VOUT rising; PG goes open drain VSENSE = VVCC; measure V(VCC-OUT) VPGTH PG threshold voltage; VOUT falling; PG goes low VSENSE = VVCC; measure V(VCC-OUT) VHYST_PG PG threshold hysteresis voltage; V(SENSE-OUT) VSENSE = VVCC tDPG PG deglitch delay; detection to output; rising and falling edges VSENSE = VVCC Leakage current; PG false; open drain 0.8 V 2.2 2.7 3.2 1.4 5 9 15 ms 10 mA Output Voltage Feedback Input (OUT) IOUT Bias current VOUT = VVCC, VEN = Hi; sinking VOUT = GND; VEN = Lo; sourcing 8 20 18 40 mA Enable Input (EN) VEN_H Threshold VEN going high 1.32 1.35 1.38 VEN_L Threshold VEN going low 1.20 1.25 1.30 VEN hysteresis Leakage current 100 VEN = 30 V V mV 1 mA Input Supply UVLO (VCC) VVCC turn on Rising VVCC turn off Falling 8.4 7.2 Hysteresis 8.8 8.3 75 V mV Digital Inputs (SDA in input mode, SCL, A0, A1 ) CIN Input capacitance ILEAKAGE Input leakage current VIN Logic Hi input level HI VINLO Logic low input level VHYS Hysteresis 3 0 < VIN < VS -0.3 pF 0.1 1 0.7(VS) 6 0.3(VS) mA V 0.5 Open Drain Digital Output (SDA) VLO SDA Low Output Sinking 5 mA ILEAKAGE High level leakage current VOUT = VS 0.15 0.4 V 0.1 1.0 mA Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 5 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Full-scale current sense (input) voltage range Bus voltage (input voltage) range Common-mode rejection CMRR Input offset VOS PGA = x 1 0 PGA = x 2 0 ±80 PGA = x 4 0 ±160 PGA = x 8 0 ±320 BRNG = 1 0 32 BRNG = 0 0 16 VIN+ = 0 V to 26 V 100 GainCSA IVNP IVINM ILEAKAGE 120 ±10 ±100 PGA = x 2 ±20 ±125 PGA = x 4 ±30 ±150 PGA = x 8 ±40 ±200 VS = 3 V to 5.5 V CSA gain error mV V dB PGA = x 1 Temp stability PSRR ±40 mV 0.1 mV/°C 10 mV/V ±0.04% Temp stability 10 ppm 20 mA Input bias current Active mode IVNP, IVINM Power down mode, leakage input current 0.1 Shunt voltage 10 mV 4 mV 20 || 320 mA || kΩ ±0.5 mA A/D Converter Step Size 1 LSB Current Accuracy Current measurement Error Temp drift Over full range Bus voltage measurement Error Temp drift ( -25°C to 85°C ) Over full range Voltage Accuracy TCONV Conversion time TLOWCONV Conversion time Bus voltage ±0.2% ±1.0% ±0.2% ±0.5% ±1.0% 12 Bit 532 586 11 Bit 276 304 10 Bit 148 163 84 92 9 Bit 6 ±0.5% Minimum A/D conversion time Submit Documentation Feedback ms 4 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 DEVICE INFORMATION Functional Block Diagram VINM VS 18 4 X ADC SDA 2 SCL 20 A0 Voltage Register GND 16 19 A1 4V Reference VCC 15 Constant Power Engine Enable PROG I2C Interface Current Register VINP 17 PGA 1 Power Register 8 A V(DS) Detector Charge Pump 50mV max A 2B VREF 22m A + Gate Control Amplifier B S 7 13 GATE 14V 12 OUT S I(D) Detector 11 PG Inrush complete SENSE 14 + + 8.4V/ 8.3V EN 6 9-ms Deglitch 2.7V/ 1.25V 2mA 25m A UVLO Enable + 1.35V/ 1.25V Fault Logic Enable + 4V/1V GND 10 POR 2.5m A For autoretry option with duty cycle of 75% 9 TIMER Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 7 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Register Block Diagram Power (1) Bus Voltage (1) ´ Shunt Voltage Channel Current (1) ADC Bus Voltage Channel Full-Scale Calibration (2) ´ Shunt Voltage (1) PGA (In Configuration Register) NOTES: (1) Read-only (2) Read/write 8 Data Registers Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 20-Pin TSSOP SDA 1 20 A0 SDL 2 19 A1 NC 3 18 VINM VS 4 17 VINP NC 5 16 GND EN 6 15 VCC VREF 7 14 SENSE PROG 8 13 GATE TIMER 9 12 OUT GND 10 11 PG TPS2480/81 Table 1. TERMINAL FUNCTIONS FUNCTION TPS2480/81 SDA 1 I2C Data Line DESCRIPTION SCL 2 I2C Clock NC 3 Tie to GND or float VS 4 Power input to the I2C block, 3.3 V to 5 V NC 5 No connection, tie to GND or float EN 6 Device enable VREF 7 Reference voltage output, used to set power threshold on PROG pin PROG 8 Power-limit setting input TIMER 9 Fault timing capacitor GND 10 GND PG 11 Power good reporting output, open-drain OUT 12 Output voltage feedback GATE 13 Gate output SENSE 14 Current-limit sense input VCC 15 Main power supply input to device and FET GND 16 GND VINP 17 Positive differential shunt voltage. Connect to positive side of shunt resistor VINM 18 Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is measured from this pin to GND A1 19 Address pin. Table 2 shows pin settings and corresponding addresses. A0 20 Address pin. Table 2 shows pin settings and corresponding addresses. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 9 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Pin Description A0, A1: Address pins for setting the TPS2480 I2C address. These bits can be tied to one of four pins ( GND, SDA, SCL, VS ) which gives a total of 16 different address as shown in Table 2. EN: The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by R1/R2 in the Functional Block Diagram, or it can be tied to VCC to always enable the TPS2480/81. The hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition and shutting the downstream circuits off. A TPS2480 that has latched off can be reset by cycling EN below its negative threshold and back high. GATE: Provides the high side (above VCC) gate drive for the external FET. It is controlled by the internal gate drive amplifier, which provides a pull-up of 22 mA from an internal charge pump and a strong pull-down to ground of 75 mA (min). The pull-down current is a non-linear function of the amplifier overdrive; it provides small drive for small overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut the external FET off when EN or UVLO causes this to happen. An internal clamp protects the gate of the external FET (to OUT) and generally eliminates the need for an external clamp in almost all cases for devices with 20-V VGS(max) ratings; an external Zener may be required to protect the gate of devices with VGS(max) < 16 V. A small series resistance of 10 Ω should be inserted in the gate lead if the CISS of the external FET > 200 pF, otherwise use 33 Ω for small MOSFETs. A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile without affecting the amplifier stability. Add a series resistor of about 1 kΩ to the gate capacitor to maintain the gate clamping and current limit response time. GND: This pin is connected to system ground. OUT: This input pin is used by the constant power engine and the PG comparator to measure VDS of the external FET as V(SENSE-OUT). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can drive OUT below ground, connect a clamp (or freewheel) diode from OUT (cathode) to GND (anode). PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG goes open-drain (high voltage with a pull-up) after VDS of the external FET has fallen to about 1.25 V and a 9-ms deglitch time period has elapsed. PG is false (low or low resistance to ground) whenever EN is false, VDS of the external FET is above 2.7 V, or UVLO is active. PG can also be viewed as having an input and output voltage monitor function. The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a momentary overload or input voltage step. VPG voltage can be greater than VVCC because its ESD protection is only with respect to ground. PROG: The voltage applied to this pin (0.4 V to 4.0 V) programs the power limit used by the constant power engine. Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to the following equation: VPROG = PLIM (10 ´ ILIM ) (1) where PLIM is the desired power limit of the external FET and ILIM is the current limit setpoint (see SENSE). PLIM is determined by the desired thermal stress on the external FET: PLIM < TJ(max) - TS(max) RqJC(max) (2) where TJ(max) is the maximum desired transient junction temperature of the external FET and TS(max) is the maximum case temperature prior to a start or restart. VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine. ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of the external FET full on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship. A capacitor may be tied from PROG to 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp. PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2480 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor. SCL: This pin is the clock input for the I2C interface. SDA: This pin is the data input for the I2C interface. SENSE: Monitors the voltage at the drain of the external FET, and the downstream side of RS providing the constant power limit engine with feedback of both the external FET current (ID) and voltage (VDS). Voltage is determined by the difference between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit at low VDS. The maximum current limit is set by the following equation: ILIM = 50mV RS (3) Design the connections to SENSE to minimize RS voltage sensing errors. Don't drive SENSE to a large voltage difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by connecting SENSE to VCC. TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the fault-time for both versions and the restart interval for the TPS2481. The timer charges at 25 mA whenever the TPS2480/81 is in power limit or current limit and discharges at 2.5 mA otherwise. The charge-to-discharge current ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the TPS2480 pulls GATE to ground, latches off, and discharges CT. The TPS2491 pulls GATE to ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V followed by 15 more charge and discharge cycles. The TPS2480 can be reset by either cycling the EN pin or the UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin should be tied to ground if this feature is not used. The general equation for fault retry time as a function of CT is: TF = CT ´ 1347 ´ 106 (4) VCC: This pin is associated with three functions: 1. biasing power to the integrated circuit, 2. input to power on reset (POR) and under voltage lockout (UVLO) functions, and 3. voltage sense at one terminal of RS for the external FET current measurement. The voltage must exceed the POR (about 6 V for roughly 400 ms) and the internal UVLO (about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize RS voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RS rather than at the device pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR are active. VINM: This pin is Kelvin connected to the negative (load) side of the current sensing resistor. It will appear to external circuitry as a 20-mA sink in parallel with a 320-kΩ resistor to GND. VINP: This pin is Kelvin connected to the positive (source) side of the current sensing resistor. It will typically sink ~ 20 mA. VS: Power source for the logic and I2C interface. Typically between 3 V and 5 V. VREF: Provides a 4.0-V reference voltage for use in conjunction with the resistor divider of a typical application circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA is drawn. Although not typically required, up to 1000 pF can be placed on this pin. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 11 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS A/D FREQUENCY RESPONSE 2.0 ADC SHUNT OFFSET vs TEMPERATURE 100 VS+ = 5V 80 1.5 320mV Range 1.0 160mV Range 40 0.5 Offset (mV) Input Currents (mA) 60 VS+ = 3V 0 VS+ = 3V 20 0 -20 80mV Range -60 -1.0 -80 VS+ = 5V -1.5 -100 10 5 0 15 20 25 30 0 -40 -25 VIN- Voltage (V) 80 45 60 40 40 35 160mV Range 0 -20 -40 75 100 125 ADC BUS VOLTAGE OFFSET vs TEMPERATURE 50 Offset (mV) Gain Error (m%) ADC SHUNT GAIN ERROR vs TEMPERATURE 320mV Range 50 Figure 2. 100 20 25 Temperature (°C) Figure 1. 30 25 20 16V Range 32V Range 15 80mV Range 40mV Range -60 10 -80 5 0 -100 -40 -25 0 25 50 75 100 125 -40 -25 0 25 Temperature (°C) 50 75 100 125 Temperature (°C) Figure 3. Figure 4. ADC BUS GAIN ERROR vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT VOLTAGE 100 20 80 15 60 10 40 16V 20 INL (mV) Gain Error (m%) 40mV Range -40 -0.5 0 -20 0 -5 32V -40 5 -10 -60 -15 -80 -100 -40 -25 0 25 50 75 100 125 -20 -0.4 -0.3 Figure 5. 12 -0.2 -0.1 0 0.1 0.2 0.3 0.4 Input Voltage (V) Temperature (°C) Figure 6. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) INPUT CURRENTS WITH LARGE DIFFERENTIAL VOLTAGES (VIN+ at 12V, Sweep of VIN–) ACTIVE IQ vs TEMPERATURE 0 1.2 -10 1.0 -20 VS = 5V 0.8 -40 IQ (mA) Gain (dB) -30 -50 0.6 VS = 3V -60 0.4 -70 -80 0.2 -90 0 -100 10 100 1k 10k 100k 1M -40 -25 0 25 Input Frequency (Hz) 50 100 Figure 7. Figure 8. SHUTDOWN IQ vs TEMPERATURE ACTIVE IQ vs I2C CLOCK FREQUENCY 125 1.0 16 0.9 14 VS = 5V 0.8 12 0.7 IQ (mA) 10 IQ (mA) 75 Temperature (°C) VS = 5V 8 6 VS = 3V 4 0.6 VS = 3V 0.5 0.4 0.3 0.2 2 0.1 0 0 -40 -25 0 25 50 75 100 125 100k 10k 1k Temperature (°C) 1M 10M SCL Frequency (Hz) Figure 9. Figure 10. SHUTDOWN IQ vs I2C CLOCK FREQUENCY 300 250 VS = 5V IQ (mA) 200 150 100 50 VS = 3V 0 1k 10k 100k 1M 10M SCL Frequency (Hz) Figure 11. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 13 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com APPLICATION INFORMATION Basic Operation The TPS2480/81 provides all the features needed for a positive hotswap controller. These features include: 1. Under-voltage lockout; 2. Adjustable (system-level) enable; 3. Turn-on inrush limit; 4. High-side gate drive for an external N-channel MOSFET; 5. MOSFET protection (power limit and current limit); 6. Adjustable overload timeout (also called an electronic circuit breaker); 7. Charge-complete indicator for downstream converter sequencing; and 8. Optional automatic restart mode. The TPS2480/81 features superior power-limiting, MOSFET protection that allows independent control of current limit (to set maximum full-load current), power limit and overload time (to keep FET in its SOA), and overload time (to control case temperature rise). The typical application circuit, and oscilloscope plots of Figure 12 and Figure 16 demonstrate many of the functions described above. Board Plug-In (Figure 12) Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS2480/81 is held inactive, and GATE, PROG, TIMER, and PG are held low for less than 1 ms while internal voltages stabilize, then GATE, PROG, TIMER, and PG are released and the part begins sourcing current to the GATE pin and the external FET begins to turn on while the voltage across it, V(SENSE-OUT), and current through it, V(VCC-SENSE), are monitored. Current initially rises to the value which satisfies the power limit engine (PLIM÷VVCC) since the output capacitor was discharged. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 TIMER and PG Operation (Figure 12) The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when limiting stops. If the voltage on CT reaches 4 V before the output is charged, the external FET is turned off and either a latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a deglitched end-of-charge indication which is based on the voltage across the external FET. PG is useful for preventing a downstream DC-to-DC converter from starting while CO is still charging. PG goes active (open drain) about 9 ms after CO is charged. This delay allows the external FET to fully turn on and any transients in the power circuits to end before the converter starts up. The resistor pull-up shown on pin PG in the typical application diagram only demonstrates operation; the actual connection to the converter depends on the application. Timing can appear to terminate early in some designs if operation transitions out of the power limit mode into a gate charge limited mode at low VDS values. Figure 12. Basic Board Insertion Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 15 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Action of the Constant Power Engine (Figure 13) The calculated power dissipated in the external FET, VDS x ID, is computed under the same startup conditions as Figure 12. The current of the external FET, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is 54 W / 48 V = 1.1 A. The 54-W value is programmed into the engine by setting the PROG voltage using Equation 1. VDS of the external FET, which is calculated as V(SENSE-OUT) , falls as CO charges, thus allowing the the external FET drain current to increase. This is the result of the internal constant power engine adjusting the current limit reference to the GATE amplifier as CO charges and VDS falls. The calculated device power in Figure 13, labeled MOSFET POWER, is seen to be flat-topped and constant within the limitations of circuit tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine output to 50 mV when VDS is low. This protection technique can be viewed as a specialized form of foldback limiting; the benefit over linear foldback is that it yields the maximum output current from a device over the full range of VDS and still protects the device. Figure 13. Computation of the External FET Stress During Startup 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Response to a Hard Output Short (Figure 14 and Figure 15) Figure 14 shows the short circuit response over the full time-out period. This begins when the output voltage falls and ends when the external FET is turned off. The external FET current is actively controlled by the power limiting engine and gate amplifier circuit while the TIMER pin charges CT to the 4-V threshold. Once this threshold is reached, the TPS2480/81 disable and latch off the external FET. The TPS2480 remains latched off until either the input voltage drops below the UVLO threshold or EN cycles through the false (low) state. The TPS2481 will attempt a restart after going through a timing cycle. Figure 14. Current Limit Overview Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 17 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com The TPS2480/81 responds rapidly to the short circuit as seen in Figure 15. The falling OUT voltage is the result of the external FET and CO currents through the short circuit impedance. The internal GATE clamp causes the GATE voltage to follow the output voltage down and subsequently limits the negative VDS to 1.2 V. The rapidly rising fault current overdrives the GATE amplifier causing it to overshoot and rapidly turn the external FET off by sinking current to ground. The external FET slowly turns back on as the GATE amplifier recovers; the external FET then settles to an equilibrium operating point determined by the power limiting circuit. Figure 15. Current Limit Onset Minimal input voltage overshoot appears in Figure 15 because a local 100-mF bypass capacitor and very short input leads were used. The input voltage would overshoot as the input current abruptly drops in a typical application due to the stored energy in the input distribution inductance. The exact waveforms seen in an application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the short itself. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Automatic Restart (Figure 16) The TPS2481 automatically initiates a restart after a fault has caused it to turn off the external FET. Internal control circuits use CT to count 16 cycles before re-enabling the external FET. This sequence repeats if the fault persists. The TIMER has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry duty cycle specification quantifies this behavior. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and reduces the need for additional protection devices. Figure 16. TPS2480/81 Restart Cycle Timing Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 19 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Low Voltage Application Design Example The following example illustrates the design and component selection process for a 12-V, 40-A hotswap application. Figure 17 shows the application circuit for this design example. VCC VOUT RS D1 RG CO A1 RPG 11 1kW C1 0.1mF CG Optional : Use with dV/dt control 10 GND PG OUT TIMER 9 12 13 GATE PROG 8 14 SENSE VREF 7 15 VCC EN 6 16 GND NC 5 17 VINP VS 4 18 VINM NC 3 A1 SCL 2 A0 TPS2480/1 SDA 1 19 A0 20 I2C Addresses VCC SDA REN1 SCL CT RPROG1 CEN 0.1mF REN2 RSDA 10kW RSDA 10kW RPROG2 CVS 0.1mF 3P3V_USB Figure 17. TPS2480/81 Low Voltage Design Example Schematic 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 1. Choose RS The following equation includes a factor of 1.2 (20%) for VSENSE and RS tolerance along with some additional margin. RS = • VSENSE 50mV = = 1.042mΩ 1.2 ´ ILIMIT 1.2 ´ 40A (5) Choose RS = 1 mΩ ILIMIT(MAX) = VSENSE( MAX ) RS = 55mV = 55 A 1mΩ (6) 2 RS Power = ILIMIT(MAX) ´ RS = 55 A2 ´ 1mW = 3.025W (7) Multiple sense resistors in parallel should be considered. 2. Choose M1 Select the M1 VDS rating allowing for maximum input voltage and transients. Then select an operating RDSON, package, and cooling to control the operating temperature. Most manufacturers list RDSON(MAX) at 25°C and provide a derating curve from which values at other temperatures can be derived. The next equation can be used to estimate desired RDSON(MAX) at the maximum operating junction temperature of TJ(MAX). (usually 125°C). TA(MAX) is the maximum expected ambient temperature. TJ(MAX) = 125C, TA(MAX) = 50C,Rq JA = 10 RDSON(MAX) = TJ(MAX) - TA(MAX) 2 LIMIT(NOM) Rq JA ´ I = C ,ILIMIT(NOM) = 50 A W (8) 125C - 50C = 3mΩ C 10 ´ (50A)2 W (9) The junction-to-ambient thermal resistance RqJA, depends upon the package style chosen and the details of heat-sinking and cooling including the PCB. Actual “in-system” temperature measurements will be required to validate heat-sinking and cooling performance. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 21 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com 3. Choose the Power Limit PLIM and the PROG Resistors, RPROG1 and RPROG2 M1 dissipates large amounts of power during power-up or output short circuit. Power limit, PLIM should be set to prevent M1 die temperature from exceeding a short term maximum temperature, TJ(MAX2). Short term TJ(MAX2) may be set as high as 150°C while still leaving ample margin for the typical manufacturer's rating of 175°C. PLIM can be estimated as follows: C C ,Rq JC = 0.2 ,RDS( on ) = 1.18mW W W 2 0.7*(TJ(MAX2) - Rq CA ´ ILIMIT(NOM) ´ RDSON - TA(MAX) ) = = 249W Rq JC TJ(MAX2) = 150C, TA(MAX) = 50C,Rq CA = 9.8 PLIM (10) (11) Where RqCA is M1+PCB case-to-ambient thermal resistance, RqJC is M1 junction-to-case thermal resistance, RDS(on) is M1 channel resistance at the maximum operating temperature, and the factor of 0.7 accounts for the tolerance of the constant power engine. The maximum power limit for the constant power engine, PLIM(MAX) and nominal power POUT(nom) settings for this circuit are calculated with the next equation: VREF = 4V ,RS = 1mW, VOUT(NOM) = 12V ,ILIMIT(NOM) = 50 A PLIM(MAX) = (12) 1V ´ VREF = 2kW 2 ´ RS (13) POUT(NOM) = VOUT(NOM) ´ ILIMIT(NOM) = 12V ´ 50 A = 600W (14) The PROG resistors should be chosen using the smallest of PLIM , PLIM(MAX), or PLIM(MAX) values. Choose RPROG2 = 20 kΩ . Choose RPROG1 as shown below. VPROG = 2 ´ PLIM(ACT) ´ RS 1V RPROG1 = RPROG2 ´ ( • = 2 ´ 249W ´ 1mΩ = 0.498V 1V (15) VREF - 1) = 140.6kΩ VPROG (16) Choose RPROG1 = 140 kΩ The power and current limit curve for this configuration is shown in Figure 18. Current Limit vs. Vout (Vvcc=12V) O u tp u t C u r r e n t ( A m p s ) 60 50 40 30 20 10 0 10 8 6 4 2 0 Output Voltage (V) Figure 18. TPS2480/81 Power and Current Limit Curve 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 4. Choose the Timer Capacitor, CT and Turn On Time The turn on time tON, represents the time it takes the circuit to charge up the output capacitance CO and load. CT programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of start up. The turn on time is a function of the type of control; current limit, power limit, or dV/dt control. The next equation calculates tON for both the power limit and current limit cases and assumes that only CO draws current during startup. For PLIM(ACT) < VVCC(MAX) ´ ILIMIT(NOM) : tON = CO ´ PLIM(ACT) For PLIM(ACT) ³ VVCC(MAX) ´ ILIMIT(NOM) : tON = tON = CO ´ PLIM(ACT) 2 LIMIT(NOM) 2´I 2 VCC(MAX) + CO ´ V 2 ´ PLIM(ACT) 2 2 ´ ILIMIT(NOM) + 2 CO ´ VVCC(MAX) 2 ´ PLIM(ACT) (17) CO ´ VVCC(MAX) ILIMIT(NOM) (18) 2 = 1000 m F ´ 249W 1000 m F ´ 13.5V + = 416 m s 2 ´ 502 A 2 ´ 249W (19) The next equation allows CT to be selected assuming that only CO draws current during startup. TPS2480/81 timer current source and capacitor tolerances are accounted for. CT = ISOURCE(MAX) VTMR-TH(MAX) ´ tON ´ ( 1 + CO-TOL + CT-TOL ) (20) 34 m A CT = ´ 416 m s ´ ( 1 + 0.2 + 0.1) = 4.48nF 4.1V • (21) Choose CT = 0.01 µF 5. Choose the Turn On Voltage, VON and the EN Resistors, REN1 and REN2 When the EN pin is used as an analog control, the desired turn on voltage, VON can be used to select the EN resistors. Select REN1 and REN2 taking into account device leakage currents. Choose REN2 =10 kΩ. REN 1 = REN 2 ´ ( • VON VEN_H(MAX) - 1) = 55.22k W (22) Choose REN2 = 54.9 kΩ The actual turn on and turn off voltages, VON(ACT) and VOFF(ACT) can be calculated as follows: VON = VEN_H(MAX) ´ REN 1 + REN 2 R + REN 2 ,VOFF = VEN_L(MIN) ´ EN 1 REN 2 REN 2 (23) VON = 1.38V ´ 54.9k W + 10k W = 8.96V 10k W VOFF = 1.22V ´ (24) 54.9k W + 10k W = 7.92V 10k W (25) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 23 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Alternative Inrush Designs Gate Capacitor (dV/dt) Control The TPS2480/81 can be configured to provide a linear dV/dt turn on characteristic. The load capacitor charging current ICHARGE, is controlled by a single capacitor from the GATE terminal to ground. M1 operates as a source follower (following the gate voltage) in this implementation. Choose a charge time, tON, based on the load capacitor, CO input voltage VI, and desired charge current. When power limiting is used (VPROG < VREF) choose ICHARGE to be less than PLIM /VVCC to prevent the fault timer from starting. The fault timer starts only if power or current limit is invoked. tON = CO ´ VVCC ICHARGE (26) Use the following equation to select the gate capacitance, CG. CISS is the gate capacitance of M1, and IGATE is the TPS2480/81 nominal gate charge current. As shown in Figure 17, a series resistor of about 1 kΩ should be used in series with CG. CG = IGATE ´ tON - CISS VVCC (27) If neither power nor current limit faults are invoked during turn on, CT can be chosen for fast transient turn off response using the M1 SOA curve. Choose the single pulse time conservatively from the M1 SOA curve using maximum operating voltage and maximum trip current. PROG Inrush Control A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 12. This method maintains a relatively fast turn-on time without the drawbacks of a gate-to-ground capacitor that include increased short circuit response time and less predictable gate clamping. 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 High Voltage Application Example The TPS2480/81 can be used to monitor current from a voltage source greater than 26 V by using the OPAMP circuit shown in Figure 19. M1 VIN 9V to 57V VCC VOUT RS RIN RMA C2 0.1mF D1 CO RG + D2 5.1V RMB RPG RB 1kW CVIN CG Optional : Use with dV/dt control A1 I2C Addresses 11 C1 0.1mF 10 GND PG 12 OUT TIMER 9 13 GATE PROG 8 14 SENSE VREF 7 15 VCC EN 6 16 NC 5 GND VINP VS 4 17 VINM NC 3 18 A1 SCL 2 19 A0 TPS2480/1 SDA 1 20 A0 VCC SDA REN1 SCL CT RPROG1 CEN 0.1mF REN2 RSDA 10kW 3P3V_USB RSDA 10kW RPROG2 CVS 0.1mF Figure 19. TPS2480/81 High Voltage Application The basic operating principle of U2, Q1, RMA, and RMB is to mirror the voltage seen across RS from a VCC referenced voltage to a GND referenced voltage. As load current flows through RS, the voltage input to U2-3 decreases and the output of U2/Q1 as seen at Q1-S follows this sense voltage. Ideally, the voltage drop across RMA mirrors the voltage drop across RS. Current flow through RMB will mirror current flow through RMA , and if RMA = RMB then the sense voltage across RS is mirrored at VINP. Since only a small voltage will be across RMA and RMB, their nominal value should be fairly low to offset input bias current effects (IVINP). TPS2480/1 input bias current sums with the current that flows through RMA increasing the voltage drop across RMB. To block the bias current from RMB, an additional buffer may be inserted between Q1-D and VINP. Using a network type resistor for RMA and RMB designed with temperature coefficient tracking will provide good voltage mirroring. U2 should be a high quality, low drift operational amplifier. The OPA333AID provides low input voltage offset and very low drift over time and temperature. U2 is referenced to VCC through D2 and RB and can operate from rail to rail. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 25 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Additional Design Considerations Use of PG Use the PG pin to control and sequence a downstream DC/DC converter. If this is not done a long time delay may be needed to allow CO to fully charge before the converter starts. Output Clamp Diode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during current limit. The OUT pin ratings can be maintained with a small diode such as an S1B, between the TPS2480/81 OUT to GND pins. Gate Clamp Diode The TPS2480/81 has a relatively well-regulated gate voltage of 12 V to 16 V, even at low supply voltages. A small clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if VGS of M1 is rated below this. High Gate Capacitance Applications Gate voltage overstress and large fault current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended if the total gate capacitance of M1 exceeds 4000 pF. When gate capacitor dV/dT control is used, a 1-kΩ resistor in series with CG is recommended, as shown in Figure 17. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is not required. Input Transient Protection The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on VINP and VINM solely to provide margin for transients on the bus. The TPS2480 will operate properly up to the absolute maximum voltage ratings on VINP and VINM. Hotswap systems experience positive transients on their input during hotplug or rapid turnoff with high current due to inductance in the input circuit. These same systems experience negative transients on the output during rapid turnoff with high current due to inductance in the output circuit. The TPS2480 may not require operational voltage margin below the absolute maximum if it is operated from a non-inductive input. An example is an application where the TPS2480 is used as an output protector with a large input capacitance located directly at the input terminals. Transient protection, e.g. a TVS diode (transient voltage suppressor, a type of Zener diode), may be required on the input in addition to a bypass capacitor if the system design does not inherently limit transient voltages below the absolute maximum ratings. An example of this is a system with significant input inductance. If a TVS is required, it must protect to the absolute maximum ratings at the worst case clamping current. An output voltage clamp diode may be required on the output to limit negative transients if the local output capacitance does not adequately control it. An example of this is a system with significant output bus inductance and little local capacitance. Select a schottky diode with low forward voltage at the anticipated current during an output short. 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Output Short Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to varying results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet since every setup differs. Applications using the retry feature (TPS2481) Applications using the retry feature may want to estimate fault retry time. The TPS2481 will retry (enable M1 to attempt turn on) once for every 16 timer charge/discharge cycles (15 cycles between 1 V and 4 V, 1 cycle between 0 V and 4 V). é ù 1 1 TRETRY = CT ´ éë VTMRHI(NOM) + 15 ´ (VTMRHI(NOM) - VTMRLO(NOM) )ùû ´ ê + ú ëê ISOURCE(NOM) ISINK(NOM) ûú TRETRY = CT ´ 21.56 ´ 10 (28) 6 (29) NOTE Equation 29 simplified - assumes no error. Layout Considerations Good layout practice places the power devices D1, RS, M1, and CO so power flows in a sequential, linear fashion. A ground plane under the power and the TPS2480/81 is desirable. The TPS2480/81 should be placed close to the sense resistor and MOSFET using a Kelvin type connection to achieve accurate current sensing across RS. A low-impedance GND connection is required because the TPS2480/81 can momentarily sink upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the GATE trace length short. The PROG, TIMER, and EN pins have high input impedances, therefore keep their input leads short. Oversize power traces and power device connections to assure low voltage drop and good thermal performance. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 27 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Power, Current, and Voltage Monitoring (PIV) The TPS2480/81 digital current-shunt monitor has an I2C / SMBus-compatible interface. It provides digital current, voltage, and power readings for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution, and continuous versus-triggered operation. Detailed register information appears in the Register Information Section. See the Register Block Diagram for a block diagram of the TPS2480 / 81 PIV monitoring circuits. PIV Monitoring - Typical Application Circuit Considerations Figure 17 shows a typical application circuit for the TPS2480/81. 0.1-mF ceramic capacitors must be placed as close as possible to the supply and ground pins for supply bypassing. The pull-up resistors shown on the SDA and SCL lines are not needed if there are pull-up resistors on these same lines elsewhere in the system. Resistor values shown are typical: consult the I2C or SMBus specification to determine acceptable values. I2C Bus Overview The I2C and SMBus protocols are essentially compatible with each other and the TPS2480/81 are compatible with both. This allows use of the I2C interface throughout this data sheet as the primary example, with SMBus protocol specified only when there is a difference. Two bidirectional lines, SCL and SDA, connect the TPS2480 / 81 to the bus. Both SCL and SDA are open-drain connections. The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls, the bus access, and generates START and STOP conditions. To address a specific device, the master initiates a START condition by pulling SDA from a HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH is interpreted as a START or STOP condition. Once all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The TPS2480/81 includes a 28-ms timeout on its interface to prevent locking up an SMBus. 28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Serial Bus Address To communicate with the TPS2480/81, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TPS2480/81 have two address pins, A0 and A1. Table 2 describes the pin logic levels for each of the 16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any activity on the interface occurs. The address pins are read at the start of each communication event. Table 2. TPS2480/81 Address Pins and Slave Addresses A1 A0 SLAVE ADDRESS GND GND 1000000 GND VS+ 1000001 GND SDA 1000010 GND SCL 1000011 VS+ GND 1000100 VS+ VS+ 1000101 VS+ SDA 1000110 VS+ SCL 1000111 SDA GND 1001000 SDA VS+ 1001001 SDA SDA 1001010 SDA SCL 1001011 SCL GND 1001100 SCL VS+ 1001101 SCL SDA 1001110 SCL SCL 1001111 Serial Interface The TPS2480/81 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TPS2480/81 support the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes are transmitted most significant byte first. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 29 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Writing To/Reading From The TPS2480/81 Accessing a particular register on the TPS2480/81 is accomplished by writing the appropriate value to the register pointer. Refer to Table 4 for a complete list of registers and corresponding addresses. The value for the register pointer as shown in Figure 20 is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the TPS2480/81 requires a value for the register pointer. Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit LOW. The TPS2480/81 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register to which data will be written. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The TPS2480/81 acknowledges receipt of each data byte. The master may terminate data transfer by generating a START or STOP condition. When reading from the TPS2480/81, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a START condition and sends the slave address byte with the R/W bit HIGH to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the TPS2480/81 retains the register pointer value until it is changed by the next write operation. Figure 20 and Figure 21 show write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte. Figure 22 shows the timing diagram for the SMBus Alert response operation. Figure 23 illustrates a typical register pointer configuration. 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 0 A3 A2 A1 A0 Frame 1 Two-Wire Slave Address Byte 0 (1) 1 P7 ACK By TPS2480/81 R/W 9 P6 P4 P3 P2 P1 Frame 2 Register Pointer Byte P5 1 D15 D14 ACK By TPS2480/81 P0 9 D13 Figure 20. Timing Diagram for Write Word Format Start By Master 1 1 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 0 A3 A2 A1 A0 D9 Frame 2 Data MSByte (2) D8 9 D6 ACK By TPS2480/81 D8 D7 1 ACK By Master NOTES: (1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. (2) Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 19. (3) ACK by Master can also be sent. (1) D11 D10 From D12 TPS2480/81 D13 ACK By D15 D14 1 TPS2480/81 R/W Frame 1 Two-Wire Slave Address Byte 0 9 D9 Frame 3 Data MSByte D12 D11 D10 9 D5 D7 1 D3 D3 D2 D1 D2 Frame 3 Data LSByte (2) D1 NoACK By Master 9 ACK By TPS2480/81 D0 D0 Frame 4 Data LSByte D4 From D5 TPS2480/81 D4 D6 9 (3) Stop Stop By Master www.ti.com SDA 1 1 NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Start By Master SCL SDA SCL TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Figure 21. Timing Diagram for Read Word Format Submit Documentation Feedback 31 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 0 0 R/W Start By Master 1 0 0 A3 A2 ACK By TPS2480/81 A1 A0 0 From TPS2480/81 Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte NACK By Master Stop By Master (1) NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure 22. Timing Diagram for SMBus ALERT 1 9 1 9 ¼ SCL SDA 1 0 0 A3 A2 A1 A0 R/W Start By Master P7 P6 P5 P4 P3 P2 P1 ACK By TPS2480/81 Frame 1 Two-Wire Slave Address Byte (1) P0 Stop ACK By TPS2480/81 Frame 2 Register Pointer Byte NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure 23. Typical Register Pointer Set 32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 High-Speed I2C Mode When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The TPS2480/81 does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 3.4-Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the TPS2480/81 to support the F/S mode. t(LOW) tF tR t(HDSTA) SCL t(HDSTA) t(HIGH) t(HDDAT) t(SUSTO) t(SUSTA) t(SUDAT) SDA t(BUF) P S S P Figure 24. Table 3. FAST MODE PARAMETER MIN HIGH-SPEED MODE MAX 0.001 MIN 0.4 UNITS MAX f(SCL) SCL operating frequency T(BUF) Bus free time between STOP and START condition 600 0.001 160 3.4 MHz ns T(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 100 100 ns T(SUSTA) Repeated START condition setup time 100 100 ns T(SUSTO) STOP condition setup time 100 100 ns T(HDDAT) Data hold time 0 0 ns T(SUDAT) Data setup time 100 10 ns T(LOW) SCL clock LOW period 1300 160 ns T(HIGH) SCL clock HIGH period 600 tF Clock/data fall time tR/ tR Clock/data rise time clock/data rise time for SCLK ≤ 100kHz 60 ns 300 160 ns 300/1000 160 ns/ns Power-Up Conditions Power-up conditions are caused by a software reset via the RST bit (bit 15) in the Configuration Register, or the I2C bus General Call Reset. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 33 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ADC Operation The two analog inputs to the TPS2480/81, VINP and VINM, connect to a shunt resistor in the bus of interest. The TPS2480/81 is typically powered by a separate supply from 3 V to 5 .5V. The bus being sensed can vary from 0 V to 26 V. There are no special considerations for power-supply sequencing (for example, a bus voltage can be present with the supply voltage off, and vice-versa). The TPS2480/81 senses the small drop across the shunt for shunt voltage, and senses the voltage with respect to ground from VIN– for the bus voltage. Figure 25 illustrates this operation. VSHUNT = VIN+ - VINTypically < 50mV + - Current Shunt Supply Load 3V to 5.5V 3.3V Supply VIN+ VS VIN- ´ Power Register Data (SDA) Clock (SCL) 2 VBUS = VIN- - GND Current Register Range of 0V to 26V Typical Application 12V PGA IC Interface A0 ADC Voltage Register A1 GND Figure 25. TPS2480/81 Configured For Current and Voltage Measurement When the TPS2480/81 is in the normal operating mode (that is, MODE bits of the Configuration Register are set to '111'), it continuously converts the shunt voltage up to the number set in the shunt voltage averaging function (Configuration Register, SADC bits). The device then converts the bus voltage up to the number set in the bus voltage averaging (Configuration Register, BADC bits). The Mode control in the Configuration Register also permits selecting modes to convert only voltage or current, either continuously or in response to an event (triggered). 34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 All current and power calculations are performed in the background and do not contribute to conversion time; conversion times shown in the Electrical Characteristics table can be used to determine the actual conversion time. Power-Down mode reduces the quiescent current and turns off current into the TPS2480/81 inputs, avoiding any supply drain. Full recovery from Power-Down requires 40 ms. ADC Off mode (set by the Configuration Register, MODE bits) stops all conversions. In triggered mode, the external Convert line becomes active. Convert commands are initiated by taking the Convert line low for a minimum of 4 ms. The Convert line may be connected high when unused. Any re-trigger of the Convert line during a conversion is ignored, and the Convert line state is disregarded until the conversion ends. There are several available triggered modes; however, all conversions are performed repeatedly up to the number set in the Averaging function (Configuration Register, BADC and SADC bits). If the Convert line is held low, writing any of the triggered convert modes into the Configuration Register (even if the desired mode is already programmed into the register) triggers a single-shot conversion. Although the TPS2480/81 can be read at any time, and the data from the last conversion remain available, the Conversion Ready bit (Status Register, CNVR bit) is provided to help co-ordinate one-shot or triggered conversions. The Conversion Ready bit is set after all conversions, averaging, and multiplication operations are complete. The Conversion Ready bit clears under these conditions: 1. Writing to the Configuration Register, except when configuring the MODE bits for Power Down or ADC off (Disable) modes; 2. Reading the Status Register; or 3. Triggering a single-shot conversion with the Convert pin. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 35 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Power Measurement Current and bus voltage are converted at different points in time, depending on the resolution and averaging mode settings. For instance, when configured for 12-bit and 128 sample averaging, up to 68 ms in time between sampling these two values is possible. Again, these calculations are performed in the background and do not add to the overall conversion time. PGA Function If larger full-scale shunt voltages are desired, the TPS2480/81 provides a PGA function that increases the full-scale range up to 2, 4, or 8 times (320 mV). Additionally, the bus voltage measurement has two full-scale ranges: 16 V or 32 V. Filtering and Input Considerations Measuring current can be noisy, and such noise can be difficult to define. The internal ADC has a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This architecture has good inherent noise rejection. However, transients that occur at or very close to the sampling rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be dealt with by incorporating filtering at the input of the TPS2480/81. The high frequency enables the use of low-value series resistors on the filter for reducing effects on measurement accuracy. In general, filtering the TPS2480/81 input is only necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate (>1 MHz). Filter using the lowest possible series resistance and ceramic capacitor. Recommended values are 0.1 mF to 1.0 mF. Overload conditions are another consideration for the TPS2480/81 inputs. The TPS2480/81 inputs are specified to tolerate 26 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long the power supply or energy storage capacitors support it). It must be remembered that removing a short to ground can result in inductive kickbacks that could exceed the 26-V differential and common-mode rating of the TPS2480/81. Inductive kickback voltages are best dealt with by zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficient energy storage capacitance. In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem occurs because an excessive dV/dt can activate the ESD protection in the TPS2480/81 in systems where large currents are available. Simple Current Shunt Monitor Usage (No Programming Necessary) The TPS2480/81 can be used without any programming if it is only necessary to read a shunt voltage drop and bus voltage with the default 12-bit resolution, 320-mV shunt full-scale range (PGA = ÷ 8), 32-V bus full-scale range, and continuous conversion of shunt and bus voltage. Without programming, current is measured by reading the shunt voltage. The Current Register and Power Register are only available if the Calibration Register contains a programmed value. Programming the TPS2480/81 The default power-up states of the registers are shown in the register information section. These registers are volatile, and if programmed to other than default values, must be re-programmed at every device power-up. Detailed information on programming the Calibration Register specifically is given in the Programming the TPS2480/81 Power Measurement Engine section. 36 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Programming The TPS2480/81 Power Measurement Engine Calibration Register and Scaling The Calibration Register makes it possible to set the scaling of the Current and Power Registers to whatever values are most useful for a given application. One strategy may be to set the Calibration Register such that the largest possible number is generated in the Current Register or Power Register at the expected full-scale point; this approach yields the highest resolution. The Calibration Register can also be selected to provide values in the Current and Power Registers that either provide direct decimal equivalents of the values being measured, or yield a round LSB number. After these choices have been made, the Calibration Register also offers possibilities for end user system-level calibration, where the value is adjusted slightly to cancel total system error. Below are two examples for configuring the TPS2480/81 calibration. Both examples are written so the information directly relates to the calibration setup found in the TPS2480/81EVM software. Calibration Example 1: Calibrating the TPS2480/81 With No Possibility for Overflow NOTE The numbers used in this example are the same used with the TPS2480/81EVM software as shown in Figure 26. This does not mean the input can go over 26 V! 1. Establish the following parameters: VBUS_MAX = 32, This does not mean the input can go over 26 V! VSHUNT_MAX = 0.32 RSHUNT = 0.5 2. Using Equation 30, determine the maximum possible current . VSHUNT_MAX MaxPossible_I = RSHUNT MaxPossible_I = 0.64 (30) 3. Choose the desired maximum current value. This value is selected based on system expectations. Max_Expected_I = 0.6 4. Calculate the possible range of current LSBs. To calculate this range, first compute a range of LSBs that is appropriate for the design. Next, select an LSB within this range. Note that the results will have the most resolution when the minimum LSB is selected. Typically, an LSB is selected to be the nearest round number to the minimum LSB value. Max_Expected_I Minimum_LSB = 32767 Minimum_LSB = 18.311 ´ 10-6 (31) Max_Expected_I 4096 Maximum_LSB = 146.520 ´ 10-6 Maximum_LSB = (32) Choose an LSB in the range: Minimum_LSB 320.00 2. Translate this number to a whole decimal number ==> 32000 3. Convert it to binary==> 111 1101 0000 0000 4. Complement the binary result : 000 0010 1111 1111 5. Add 1 to the Complement to create the Two’s Complement formatted result ==> 000 0011 0000 0000 6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h (Remember to extend the sign to all sign-bits, as necessary based on the PGA setting.) At PGA = ÷8, full-scale range = ±320 mV (decimal = 32000, positive value hex = 7D00, negative value hex = 8300), and LSB = 10 mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SD14_8 SD13_8 SD12_8 SD11_8 SD10_8 SD9_8 SD8_8 SD7_8 SD6_8 SD5_8 SD4_8 SD3_8 SD2_8 SD1_8 SD0_8 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At PGA = ÷4, full-scale range = ±160 mV (decimal = 16000, positive value hex = 3E80, negative value hex = C180), and LSB = 10 mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SIGN SD13_4 SD12_4 SD11_4 SD10_4 SD9_4 SD8_4 SD7_4 SD6_4 SD5_4 SD4_4 SD3_4 SD2_4 SD1_4 SD0_4 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At PGA = ÷2, full-scale range = ±80 mV (decimal = 8000, positive value hex = 1F40, negative value hex = E0C0), and LSB = 10 mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SIGN SIGN SD12_2 SD11_2 SD10_2 SD9_2 SD8_2 SD7_2 SD6_2 SD5_2 SD4_2 SD3_2 SD2_2 SD1_2 SD0_2 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At PGA = ÷1, full-scale range = ±40 mV (decimal = 4000, positive value hex = 0FA0, negative value hex = F060), and LSB = 10 mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SIGN SIGN SIGN SD11_1 SD10_1 SD9_1 SD8_1 SD7_1 SD6_1 SD5_1 SD4_1 SD3_1 SD2_1 SD1_1 SD0_1 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 47 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Table 8. Shunt Voltage Register Format (1) VSHUNT Reading (mV) Decimal Value PGA = ÷ 8 (D15…..................D0) PGA = ÷ 4 (D15…..................D0) PGA = ÷ 2 (D15…..................D0) PGA = ÷ 1 (D15…..................D0) 320.02 32002 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 320.01 32001 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 320.00 32000 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 319.99 31999 0111 1100 1111 1111 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 319.98 31998 0111 1100 1111 1110 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 - - - - - - 160.02 16002 0011 1110 1000 0010 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 160.01 16001 0011 1110 1000 0001 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 160.00 16000 0011 1110 1000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 159.99 15999 0011 1110 0111 1111 0011 1110 0111 1111 0001 1111 0100 0000 0000 1111 1010 0000 159.98 15998 0011 1110 0111 1110 0011 1110 0111 1110 0001 1111 0100 0000 0000 1111 1010 0000 - - - - - - 80.02 8002 0001 1111 0100 0010 0001 1111 0100 0010 0001 1111 0100 0000 0000 1111 1010 0000 80.01 8001 0001 1111 0100 0001 0001 1111 0100 0001 0001 1111 0100 0000 0000 1111 1010 0000 80.00 8000 0001 1111 0100 0000 0001 1111 0100 0000 0001 1111 0100 0000 0000 1111 1010 0000 79.99 7999 0001 1111 0011 1111 0001 1111 0011 1111 0001 1111 0011 1111 0000 1111 1010 0000 79.98 7998 0001 1111 0011 1110 0001 1111 0011 1110 0001 1111 0011 1110 0000 1111 1010 0000 - - - - - - 40.02 4002 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0000 40.01 4001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0000 40.00 4000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000 39.99 3999 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111 39.98 3998 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110 - - - - - - 0.02 2 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010 0.01 1 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 –0.01 –1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 –0.02 –2 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110 - - - - - - –39.98 –3998 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010 –39.99 –3999 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001 –40.00 –4000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000 –40.01 –4001 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0110 0000 –40.02 –4002 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0110 0000 - - - - - - –79.98 –7998 1110 0000 1100 0010 1110 0000 1100 0010 1110 0000 1100 0010 1111 0000 0110 0000 –79.99 –7999 1110 0000 1100 0001 1110 0000 1100 0001 1110 0000 1100 0001 1111 0000 0110 0000 –80.00 –8000 1110 0000 1100 0000 1110 0000 1100 0000 1110 0000 1100 0000 1111 0000 0110 0000 –80.01 –8001 1110 0000 1011 1111 1110 0000 1011 1111 1110 0000 1100 0000 1111 0000 0110 0000 –80.02 –8002 1110 0000 1011 1110 1110 0000 1011 1110 1110 0000 1100 0000 1111 0000 0110 0000 - - - - - - –159.98 –15998 1100 0001 1000 0010 1100 0001 1000 0010 1110 0000 1100 0000 1111 0000 0110 0000 –159.99 –15999 1100 0001 1000 0001 1100 0001 1000 0001 1110 0000 1100 0000 1111 0000 0110 0000 –160.00 –16000 1100 0001 1000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 –160.01 –16001 1100 0001 0111 1111 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 –160.02 –16002 1100 0001 0111 1110 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 - - - - - - –319.98 –31998 1000 0011 0000 0010 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 –319.99 –31999 1000 0011 0000 0001 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 –320.00 –32000 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 –320.01 –32001 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 –320.02 –32002 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000 (1) 48 Out-of-range values are shown in grey shading. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Bus Voltage Register 02h (Read-Only) The Bus Voltage Register stores the most recent bus voltage reading, VBUS. At full-scale range = 32 V (decimal = 8000, hex = 1F40), and LSB = 4 mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 At full-scale range = 16 V (decimal = 4000, hex = 0FA0), and LSB = 4 mV. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME 0 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVR: Conversion Ready Bit 1 Although the data from the last conversion can be read at any time, the TPS2480/81 Conversion Ready bit (CNVR) indicates when data from a conversion is available in the data output registers. The CNVR bit is set after all conversions, averaging, and multiplications are complete. CNVR will clear under the following conditions: 1) Writing a new mode into the Operating Mode bits in the Configuration Register (except for Power-Down or Disable) 2.) Reading the Power Register OVF: Math Overflow Flag Bit 0 The Math Overflow Flag (OVF) is set when the Power or Current calculations are out of range. It indicates that current and power data may be meaningless. Power Register 03h (Read-Only) Full-scale range and LSB are set by the Calibration Register. See the TPS2480/81 Power Measurement Engine section. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Power Register records power in watts by multiplying the values of the current with the value of the bus voltage according to the equation: Power = Current ´ BusVoltage 5000 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 49 TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Current Register 04h (Read-Only) Full-scale range and LSB depend on the value entered in the Calibration Register. See the TPS2480/81 Power Measurement Engine section. Negative values are stored in two's complement format. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The value of the Current Register is calculated by multiplying the value in the Shunt Voltage Register with the value in the Calibration Register according to the equation: ShuntVoltage ´ Calibration Register Current = 4096 Calibration Register Calibration Register 05h (Read/Write) Current and power calibration are set by bits D15 to D1 of the Calibration Register. Note that bit D0 is not used in the calculation. This register sets the current that corresponds to a full-scale drop across the shunt. Full-scale range and the LSB of the current and power measurement depend on the value entered in this register. See the TPS2480/81 Power Measurement Engine section. This register is suitable for use in overall system calibration. Note that the '0' POR values are all default. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (1) BIT NAME FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1) 50 D0 is a void bit and will always be '0'. It is not possible to write a '1' to D0. CALIBRATION is the value stored in D15:D1. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 REVISION HISTORY Changes from Revision A (April, 2010) to Revision B Page • Changed Increased the input range from 20-V to 26-V ........................................................................................................ 1 • Changed Simplified Application Diagram drawing on the first page. .................................................................................... 1 • Added Function column to the DEVICE INFORMATION Table. .......................................................................................... 2 • Changed RECOMMENDED OPERATING CONDITIONS Input Voltage range increase to 24.5 V. .................................... 2 • Added split Input bias current row and updated values. ....................................................................................................... 6 • Changed Design Example Schematic drawing. .................................................................................................................. 20 • Changed Figure 17 TPS2480/81 Low Voltage Design Example Schematic drawing ........................................................ 20 • Changed High Voltage Application drawing. ...................................................................................................................... 25 • Changed Figure 19 TPS2480/81 High Voltage Application drawing .................................................................................. 25 • Added Input Transient Protectionsection. ........................................................................................................................... 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS2480 TPS2481 51 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2480PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2480 TPS2480PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2480 TPS2481PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2481 TPS2481PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2481 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of