TPS2482PWR

TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 36-V Hotswap Controller with Precision I2C Power Monitoring Check for Samples: TPS2482, TPS2483 FEATURES DESCRIPTION • • • The TPS2482 and TPS2483 provide hotswap control and precision monitoring for 9-V to 36-V applications. Accurate voltage, current, and power monitoring is provided by a 16-bit A/D converter with a serial interface that is compatible with I2C and SMBus. Voltage and current measurements are interleaved and multiplied internally to provide concurrent power calculations. These devices have high current monitoring accuracy over temperature and a broad load range. This makes them well suited for applications where load identity and health is determined by current profile, such as remote radio heads or cellular antennae. 1 2 • • • • • • • 9-V to 36-V Input Range, 40 V Abs. Max Current, Voltage and Power Monitor ±0.5% Accurate Current Monitoring ( -25°C < TJ < 85°C) 16 Programmable I2C™ Addresses Configurable Averaging Options Programmable MOSFET SOA protection High Side Gate Drive for External N-FET Programmable Fault Timer Open-Drain Power-Good Output 20-Pin TSSOP Package APPLICATIONS • • • • • RRH (Remote Radio Heads) Storage Networks Plug-In Modules Base Station 24 V Antenna Power Industrial 24 V - 28 V Power The hotswap section drives N-channel MOSFETs, with timed inrush and fault-current limiting. Advanced MOSFET safe operating area (SOA) protection is achieved by programmable constant-power foldback and a fixed current limit. This results in an exponential inrush current profile as shown in the start-up figure below. As VOUT ramps up and the VDS of the MOSFET is reduced the current increases keeping MOSFET power dissipation within its SOA at all times. The TPS2482 latches off after a hard fault, while the TPS2483 automatically attempts to restart after a cool-off delay. The TPS2482 and TPS2483 can be dropped into existing TPS2480 and TPS2481 sockets to provide improved accuracy and operating voltage range. This can be accomplished with no PCB changes and minor software modifications. Simplified Application Diagram Example Start-Up Waveforms 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP B.V Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) While the standard monitoring function is limited to 36 V, with a few external components it is possible to monitor buses as high as 80 V. See special application description in High Voltage Application Example. DEVICE INFORMATION (1) (1) DEVICE AMBIENT TEMPERATURE PACKAGE FUNCTION MARKING TPS2482 -40°C to 85°C PW20 Latch Off on Fault TPS2482 TPS2483 -40°C to 85°C PW20 Auto Retry on Fault TPS2483 For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the TI web-site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) over recommended operating temperature range (unless otherwise noted) VALUES MIN MAX Input voltage range, VCC, SENSE, EN, OUT -0.3 100 Supply voltage, VS -0.3 6 Input voltage, common mode, VINP, VINM -0.3 40 Input voltage, differential, VINP, VINM -40 40 Input voltage range, PROG -0.3 6 Output voltage range, GATE, PG -0.3 100 Output voltage range, TIMER (3), VREF (3) -0.3 10 Source current, VREF 2 Sink current, PROG 2 SDA, ALERT -0.3 6 SCL -0.3 (VS + 0.3) -1 1 Current into SDA, SCL, VS, VINP, VINM, A0, A1, ALERT 5 Open-drain digital output current into SDA, ALERT 10 ESD rating, HBM 2000 ESD rating, CDM 500 Maximum operating junction temperature, TJ 150 Storage temperature range, Tstg (1) (2) (3) 2 -40 V 6 Sink current, PG Current into SENSE UNIT 150 mA V mA V °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND unless otherwise noted. Do not apply external voltage to these pins. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 RECOMMENDED OPERATING CONDITIONS over recommended junction temperature range (unless otherwise noted) MIN VCC Hotswap section bias-supply voltage range VS Monitor section bias-supply voltage range VINP, VINM Monitor section sensing input voltage range PROG Power-limit programming voltage range VREF Reference source current TJ Operating junction temperature (1) NOM MAX UNIT 9 80 2.7 5.5 0 36 0.4 (1) 4 V 0 1 mA -40 125 °C VPROG may be set below this minimum with reduced power-limit accuracy. THERMAL INFORMATION THERMAL METRIC (1) TPS2482 and TPS2483 PW UNITS 20 PINS θJA Junction-to-ambient thermal resistance 99.1 θJCtop Junction-to-case (top) thermal resistance 33.6 θJB Junction-to-board thermal resistance 50.4 ψJT Junction-to-top characterization parameter 2.2 ψJB Junction-to-board characterization parameter 49.8 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 3 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (Hotswap Section) Unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and voltage ranges, typical specifications are at TJ = 25°C, VVCC = 48 V, VPROG = 2 V, VTIMER = 0 V, all outputs unloaded. Voltages are with respect to GND and positive currents are into pins. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Hotswap Supply (VCC) IVCC Hotswap section enabled VEN = Hi, VSENSE = VVCC, VOUT = VVCC 450 1000 Hotswap section disabled VEN = Lo, VSENSE = VVCC, VOUT = 0 V 90 250 UVLO turn-on threshold VCC rising 8.4 8.8 UVLO turn-off threshold VCC falling 7.2 UVLO threshold hysteresis 8.3 75 μA V mV Current Sense Input (SENSE) ISENSE Input bias current VSENSE = VVCC, VOUT = VVCC 7.5 20 μA 4 4.1 V 5 μA 375 600 Ω 25 33 Reference Voltage Output (VREF) VVREF Reference voltage 0 mA < IVREF < 1 mA 3.9 Power Limiting Input (PROG) IPROG Input bias current; device enabled; sourcing or sinking 0 V < VPROG < 4 V, VEN = 48 V RPROG Pulldown resistance; device disabled IPROG = 200 μA, VEN = 0 V Power Limiting and Current Limiting (SENSE) VCL_PL Current-sense threshold V(VCC-SENSE), with power-limit active [VPROG = 2.4 V and VOUT = 0 V] or [VPROG = 0.9 V and VOUT = 30 V] VCL Current-sense threshold V(VCC-SENSE), with power-limit inactive VPROG = 4 V, VOUT = VSENSE tF_TRIP Response time, from large overload to GATE low VPROG = 4 V, VOUT = VSENSE, C(GATE-OUT) = 2 nF, V(VCC-SENSE) = 0 V → 200 mV, V(GATE-OUT) = 1 V 17 mV 45 50 55 1.2 μs Timer Operation (TIMER) ISOURCE Charge current (sourcing) ISINK Discharge current (sinking) VTMRHI TIMER upper threshold voltage VTMRLO TIMER lower threshold voltage DRETRY Fault retry duty-cycle VTIMER = 0 V 15 25 34 VTIMER = 0 V, TJ = 25°C 20 25 30 VTIMER = 5 V 1.5 2.5 3.7 VTIMER = 5 V, TJ = 25°C 2.1 2.5 3.1 3.9 4.0 4.1 TPS2483 only 0.96 1.0 1.04 TPS2483 only 0.5% 0.75% 1% μA V Gate Drive Output (GATE) IGATE GATE sourcing current GATE sinking current VEN = Hi, VSENSE = VVCC, V(GATE-OUT) = 7 V 15 22 35 VEN = Lo, VGATE = VVCC 1.8 2.4 2.8 VEN = Hi, VGATE = VVCC, V(VCC-SENSE) = 200 mV 75 125 250 12 VGATE-OUT GATE output voltage VGATE with respect to VOUT tD_ON Propagation delay: EN going true to GATE output high VEN = 0 V → 2.5 V (tRISE < 0.1 μs), 50% of VEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ 25 40 tD_OFF Propagation delay: EN going false to GATE output low VEN = 2.5 V → 0 V (tFALL < 0.1 μs), 50% of VEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ 0.5 1 Propagation delay: TIMER expires to GATE output low VTIMER = 0 V → 5 V (tRISE < 0.1 μs), 50% of VTIMER to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ 0.8 1 4 Submit Documentation Feedback 16 μA mA V μs Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS (Hotswap Section) (continued) Unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and voltage ranges, typical specifications are at TJ = 25°C, VVCC = 48 V, VPROG = 2 V, VTIMER = 0 V, all outputs unloaded. Voltages are with respect to GND and positive currents are into pins. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power-Good Output (PG) VPG_OL Output voltage (sinking), PG = false VOUT = 0 V, IPG = 2 mA 0.1 0.25 VOUT = 0 V, IPG = 4 mA 0.25 0.5 PG = true threshold voltage VSENSE = VVCC, VOUT rising, V(SENSE-OUT) decreasing 0.8 1.25 1.7 VPGTH PG = false threshold voltage VSENSE = VVCC, VOUT falling, V(SENSE-OUT) increasing 2.2 2.7 3.2 VHYST_PG PG threshold hysteresis VSENSE = VVCC tDPG PG deglitch delay, detection to output, rising and falling edges VSENSE = VVCC Output leakage current, PG = true VPG = VVCC VPGTL V 1.4 5 9 15 ms 10 μA Output Voltage Feedback Input (OUT) IOUT Input bias current VOUT = VVCC, VEN = Hi; (sinking) 8 20 VOUT = 0 V, VEN = Lo; (sourcing) 18 40 μA Enable Input (EN) VEN_H Threshold VEN rising 1.32 1.35 1.38 VEN_L Threshold VEN falling 1.20 1.25 1.30 EN threshold hysteresis IEN V 100 Input bias current mV VEN = 30 V μA 1 ELECTRICAL CHARACTERISTICS (Monitor Section) Boldface limits apply over the recommended junction temperature range, otherwise limits apply at TA = 25°C. Unless otherwise noted, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, default power-on mode. Voltages are with respect to GND and positive currents are into pins. PARAMETER CONDITIONS MIN TYP MAX UNIT Monitor Supply (VS) Operating supply range 5.5 V Quiescent current, default operating mode No SCL clock 2.7 330 420 μA Quiescent current, power-down mode No SCL clock 0.5 2 μA mV Monitor Sense Inputs (VINP, VINM) Shunt voltage input range -81.9175 81.9175 Bus voltage input range (1) 0 36 Common-mode rejection Shunt offset voltage, RTI (2) CMRR VVINP = 0 V to 36 V VOS vs Temperature vs Power supply Bus offset voltage, RTI (2) PSRR VS = 2.7 V to 5.5 V VOS vs Temperature vs Power supply Input bias current Input bias current, plus parallel resistance (1) (2) PSRR VS = 2.7 V to 5.5 V 126 V 140 dB ±2.5 ±10 μV 0.1 0.4 μV/°C μV/V 2.5 ±1.25 ±7.5 10 40 mV μV/°C 0.5 mV/V IVINP 10 μA IVINM + RVINM 10μA || 830kΩ While the input range is limited to 36 V, the full-scale range of the ADC scaling is 40.96 V. See the Basic ADC Functions section. Do not apply more than 36 V. RTI = Referred-to-input. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 5 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (Monitor Section) (continued) Boldface limits apply over the recommended junction temperature range, otherwise limits apply at TA = 25°C. Unless otherwise noted, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, default power-on mode. Voltages are with respect to GND and positive currents are into pins. PARAMETER CONDITIONS MIN TYP (VINP Pin) + (VINM Pin), Power-down mode, excluding VINM resistance Input leakage (3) MAX 0.1 UNIT 0.5 μA Conversion DC Accuracy ADC native resolution 16 1 LSB step size, Shunt voltage 2.5 μV 1 LSB step size, Bus voltage 1.25 mV Shunt voltage gain error 0.02 0.1 % 10 50 ppm/°C 0.02 0.1 % 10 50 ppm/°C vs Temperature Bus voltage gain error vs Temperature Differential nonlinearity Bits ±0.1 ADC conversion time, shunt or bus voltage LSB CT bits = 000 140 154 CT bits = 001 204 224 CT bits = 010 332 365 CT bits = 011 588 646 CT bits = 100 (default) 1.1 1.21 CT bits = 101 2.116 2.328 CT bits = 110 4.156 4.572 CT bits = 111 8.244 9.068 μs ms Serial-Bus Characteristics (SDA, SCL, ALERT, A0, A1) Input capacitance 3 0 ≤ VIN ≤ VS pF 1 μA Input logic high level VIH 0.7(VS) VS V Input logic low level VIL –0.3 0.3(VS) Input leakage current Input hysteresis level Output logic low level SDA, ALERT Bus timeout (3) (4) 6 0.1 Hysteresis VOL (4) 500 IOL = 3 mA VSCL = 0 V 0 28 V mV 0.4 V 35 ms Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur under different input conditions. Serial-Bus timeout in the TPS2482 and TPS2483 reset the bus interface any time SCL is low for more than the specified limit. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 FUNCTIONAL BLOCK DIAGRAM Register Block Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 7 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Pinout Diagram Table 1. PIN FUNCTIONS 8 NAME NUMBER I/O DESCRIPTION A0 20 I Serial-bus address input. Connect to GND, SCL, SDA, or VS. Table 8 shows pin settings and corresponding addresses. A1 19 I Serial-bus address input. Connect to GND, SCL, SDA, or VS. Table 8 shows pin settings and corresponding addresses. ALERT 3 O Serial-bus multi-function alert signal, open-drain output. EN 6 I Hotswap section enable input. GATE 13 O Pass-MOSFET gate-drive output. GND 10 - GND; common reference for all other input and output voltages. GND 16 - GND; common reference for all other input and output voltages. N/C 5 - No connection; tie to GND or float. OUT 12 I Input to sense pass-MOSFET source voltage for power-limit protection and PG state determination. PG 11 O Open-drain power-good output signal based on VSENSE - VOUT. PROG 8 I Pass-MOSFET power-limit programming input. Typically apply 0.4 to 4 V with a resistor divider from VREF. SCL 2 I Serial-bus clock line, high impedance input. SDA 1 I/O Serial-bus data line, open-drain input/output. SENSE 14 I Input to sense pass-MOSFET drain voltage for power-limit protection, and for sensing current-shunt voltage. TIMER 9 I Connect the fault timing capacitor from TIMER to GND. VCC 15 I Hotswap section bias-supply input and the positive reference for sensing current-shunt voltage. VINM 17 I Negative differential shunt voltage input. Connect to negative side of shunt resistor. Bus voltage is also measured from this pin to GND. VINP 18 I Positive differential shunt voltage input. Connect to positive side of shunt resistor. VREF 7 O Reference voltage output, used to set power-limit threshold on PROG input. VS 4 I Monitor section bias-supply input. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Pin Function Detailed Descriptions A0, A1: Address bits for setting the TPS2482 and TPS2483 serial-bus address. Each input may be tied to one of four pins (GND, SDA, SCL, VS) which provides a total of 16 different available addresses, as shown in Table 8. ALERT: The ALERT pin is associated with the serial bus, similar to the SMBus Alert function. ALERT is an opendrain multi-function logic signal that can be programmed to go low if a user-defined threshold has been exceeded. EN: The GATE driver is enabled when the internal POR2 and UVLO thresholds have been satisfied and the EN upper threshold is exceeded. Hysteresis between the upper and lower thresholds of EN helps to avoid enable/disable chatter if a slowly changing voltage is applied. EN can be used as a logic-level control input, an analog input voltage monitor as illustrated by REN1/REN2 in the Simplified Application Diagram, or it can be tied to VCC to always enable the TPS2482 and TPS2483. The hysteresis associated with the internal comparator makes this a stable method of detecting a low input voltage condition and shutting off the downstream circuit(s). A TPS2482 that has latched off can be reset by cycling EN below its lower threshold and back high. GATE: Provides the high-side (above VCC) gate drive for the external N-channel MOSFET pass-transistor (pass-MOSFET). It is controlled by the internal gate drive amplifier, which provides a pull-up current of 22 μA from an internal charge pump and a strong pull-down to ground of at least 75 mA. The pull-down current is a non-linear function of the amplifier overdrive; it provides less drive for small overloads, but higher overdrive for fast reaction to an output short-circuit. There is a separate pull-down of about 2.4 mA to shut off the passMOSFET when either EN or UVLO fall below their respective lower thresholds. An internal clamp protects the gate of the pass-MOSFET (to OUT) and generally eliminates the need for an external clamp in almost all cases for devices with a VGS(max) rating ≥ 20 V; an external Zener diode may be required to protect the gate of high-CGD devices with VGS(max) < 16 V. A small series resistance of 10 Ω should be inserted in the gate lead if the CISS of the pass-MOSFET > 200 pF, otherwise use 33 Ω for small MOSFETs. A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile without affecting the amplifier stability. Add a series resistor of about 1 kΩ to the gate capacitor to maintain the gate clamping and current limit response time. GND: These pins are connected to the system ground. OUT: This pin is an input used by the constant power-limit engine and the PG comparator to measure VDS of the pass-MOSFET as V(SENSE-OUT). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can drive OUT below ground, connect a clamp (or freewheel) diode from OUT (cathode) to GND (anode) to keep VOUT > -0.3 V. PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits to provide a "power-good" indication when load capacitor charge-up is essentially complete. PG goes open-drain (high voltage with a pull-up) after VDS of the pass-MOSFET has fallen below 1.25 V and a 9-ms deglitch time period has elapsed. PG is false (low or low-resistance to ground) whenever VDS of the pass-MOSFET is above 2.7 V or UVLO is active. PG can also be viewed as having an input and output voltage monitor function. The 9ms deglitch circuit serves to filter short events that could cause PG to go inactive (low) such as a momentary overload or input voltage step. However, the 9-ms delay is immediately reset whenever UVLO is active. VPG can be greater than VVCC because its ESD protection is only with respect to ground. PROG: The voltage applied to this pin (normally 0.4 V to 4.0 V) programs the power dissipation limit for the pass-MOSFET by the constant power-limit engine. Applying a voltage lower than 0.4 V may result in wide variations in power-limiting performance. Typically, a resistor divider RPROG1/RPROG2 is connected from VREF to PROG to set the power limit according to the following equation: VPROG = PLIM (10 ´ ILIM ) (1) where PLIM is the desired power dissipation limit for the pass-MOSFET and ILIM is the current limit setpoint (see SENSE). PLIM is determined by the allowable thermal stress on the pass-MOSFET: PLIM < TJ(max) - TS(max) RqJC(max) (2) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 9 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com where TJ(max) is the maximum desired transient junction temperature of the pass-MOSFET and TS(max) is its maximum case temperature just prior to a power-limiting event (such as a start or restart). RθJC(max) is the transient junction-to-case thermal resistance of the pass-MOSFET corresponding to the event interval. VPROG is used in conjunction with VDS to compute the (scaled) drain current, ID_ALLOWED, by the constant powerlimit engine. ID_ALLOWED is compared by the gate amplifier to the actual ID and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of the pass-MOSFET full on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship. A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 30 to look like a ramp. PROG is internally pulled to ground whenever EN, POR2, or UVLO are not satisfied, or the TPS2482 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor. SCL: This pin is the clock input for the serial-bus interface. SDA: This pin is the data input for the serial-bus interface. SENSE: Monitors the input voltage at the drain of the pass-MOSFET, and the downstream side of RS providing the constant power limit engine with feedback of both the pass-MOSFET current (ID) and voltage (VDS). Voltage is determined by the difference between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit at low VDS. The maximum current limit is set by the following equation: (3) Design the connections to SENSE to minimize RS voltage sensing errors. Don't drive SENSE to a large voltage difference from VCC because there is a non-linear internal impedance between them. The current limit function can be disabled by connecting SENSE to VCC. TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the allowable fault-time for both versions and the retry interval for the TPS2483. The timer charges at 25 μA whenever the TPS2482 and TPS2483 are in power limit or current limit and discharges at 2.5 μA otherwise. The charge-to-discharge current ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the TPS2482 pulls GATE to ground, latches off, and discharges CT. The TPS2483 pulls GATE to ground and attempts a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V followed by 15 more charge and discharge cycles. The TPS2482 can be reset by either cycling the EN pin or the UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or the internal POR2 (power-on reset) are active. The TIMER pin should be tied to ground if this feature is not used. The general equation for fault retry time as a function of CT and retry-application information is found in Applications Using the Retry Feature (TPS2483). VCC: Power supply input for the hotswap section, which provides three functions: 1. biasing power to the integrated circuit, 2. input to the hotswap section power-on reset (POR2) and under voltage lockout (UVLO) functions, and 3. voltage sense at one terminal of RS for the pass-MOSFET current measurement. The voltage must exceed the POR2 threshold (about 6 V for approximately 400 µs) and the internal UVLO turnon threshold (about 8.4 V) before normal operation (driving the GATE output) may begin. Connections to VCC should be designed to minimize RS voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RS rather than at the device pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR2 are active. VINM: This pin is Kelvin connected to the negative (load) side of the current sensing resistor. VINP: This pin is Kelvin connected to the positive (source) side of the current sensing resistor. VS: Power supply input for the monitoring section power-on reset (POR1), control logic, ADC, and serial-bus interface. Typically between 2.7 V and 5.5 V. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 VREF: Provides a 4.0-V reference voltage for use in conjunction with the resistor divider of a typical application circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR2 and UVLO turn-on thresholds have been met. It is not designed as a general-purpose supply voltage for other external circuitry, therefore ensure that no more than 1 mA is drawn from this output. Although not typically required, capacitance up to 1000 pF may be placed on this pin. TYPICAL CHARACTERISTICS At TA = 25°C, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, unless otherwise noted. VCC CURRENT vs VCC VOLTAGE 600 TJ = 1255C I VCC− Supply Current − mA 550 500 TJ = 255C 450 400 TJ = −405C 350 300 250 200 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 1. 79 CURRENT-LIMIT RESPONSE TIME vs VCC VOLTAGE (EN = 4 V, V(VCC – SENSE) = 200 mV) CURRENT-LIMIT THRESHOLD vs VCC VOLTAGE 55 1200 TJ = 1255C 54 T − Current Limit Response Time − nS − Current Limit Trip − mV V( VCC − Sense) 69 53 52 TJ = −405C 51 50 TJ = 255C 49 48 TJ = 1255C 47 1000 TJ = 255C 800 600 TJ = −405C 400 200 46 0 45 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 2. 69 79 9 14 19 24 29 34 39 VCC − Supply Voltage − V 44 Figure 3. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 49 11 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, unless otherwise noted. GATE PULLUP CURRENT vs VCC VOLTAGE GATE OUTPUT VOLTAGE vs VCC VOLTAGE 14.50 35 TJ = 1255C VGate − Gate Output Voltage − V I Gate − Gate Pullup Current − mA 33 31 29 27 TJ = 1255C 25 23 TJ = 255C 21 19 14.25 TJ = 255C 14 TJ = −405C 13.75 TJ = −405C 17 13.50 15 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 4. 69 9 79 69 79 69 79 GATE PULLDOWN CURRENT vs VCC VOLTAGE (EN = 4 V, V(VCC – SENSE) = 200 mV) 2.6 215 I Gate − Gate Pulldown Current − mA o TJ = 125 C 2.5 2.4 o TJ = 25 C 2.3 o TJ = −40 C 2.2 2.1 195 TJ = −405C 175 TJ = 255C 155 135 115 TJ = 1255C 95 2 9 19 29 39 49 59 69 79 75 9 19 VCC − Supply Voltage − V Figure 6. 12 29 39 49 59 VCC − Supply Voltage − V Figure 5. GATE PULLDOWN CURRENT vs VCC VOLTAGE (EN = 0 V) I Gate − Gate Pulldown Current − mA 19 Submit Documentation Feedback 29 39 49 59 VCC − Supply Voltage − V Figure 7. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, unless otherwise noted. TIMER PULLUP CURRENT vs VCC VOLTAGE TIMER CHARGE/DISCHARGE RATIO vs VCC VOLTAGE AND TEMPERATURE 9.80 32 ITimer − Charge/Discharge Ratio I Timer − Timer Pullup Current − µ A TJ = 1255C 30 28 TJ = 255C 26 24 TJ = −405C 22 9.75 TJ = 255C TJ = −405C 9.70 TJ = 1255C 9.65 20 18 9 19 29 39 49 59 69 9.60 79 9 19 VCC − Supply Voltage − V Figure 8. EN THRESHOLD VOLTAGE (RISING) vs VCC VOLTAGE 69 79 EN THRESHOLD VOLTAGE (FALLING) vs VCC VOLTAGE 1.351 1.255 VEN − EN Threshold Voltage (Falling) − V VEN − EN Threshold Voltage (Rising) − V 29 39 49 59 VCC − Supply Voltage − V Figure 9. TJ = 1255C 1.350 TJ = 255C 1.349 1.348 TJ = −405C 1.347 1.346 1.254 1.253 1.252 TJ = 1255C 1.251 TJ = 255C 1.250 1.249 TJ = −405C 1.248 1.247 1.246 1.345 9 19 29 39 49 59 VCC − Supply Voltage − V 69 79 1.245 9 19 Figure 10. 29 39 49 59 VCC − Supply Voltage − V Figure 11. 69 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 79 13 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, unless otherwise noted. SHUNT MEASUREMENT INPUT OFFSET VOLTAGE PRODUCTION DISTRIBUTION SHUNT MEASUREMENT INPUT OFFSET VOLTAGE vs TEMPERATURE −1 −1.2 Offset (µV) Population −1.4 −1.6 −1.8 −2 −2.4 −50 10 8 6 4 2 0 -2 -4 -6 -10 -8 −2.2 −25 0 25 50 Temperature (°C) 75 100 125 G003 Input Offset Voltage (mV) Figure 12. Figure 13. SHUNT MEASUREMENT INPUT GAIN ERROR PRODUCTION DISTRIBUTION SHUNT MEASUREMENT INPUT GAIN ERROR vs TEMPERATURE 600 Population Gain Error (m%) 500 400 300 200 0 −50 100 80 60 40 20 0 -20 -40 -60 -100 -80 100 −25 0 25 50 Temperature (°C) 75 100 125 G007 Input Gain Error (m%) Figure 14. Figure 15. SHUNT MEASUREMENT INPUT GAIN ERROR vs COMMON-MODE VOLTAGE SHUNT MEASUREMENT INPUT COMMON-MODE REJECTION RATIO vs TEMPERATURE 170 Common−Mode Rejection Ratio (dB) 300 Gain Error (m%) 250 200 150 100 50 0 −50 0 4 8 12 16 20 24 28 Common−Mode Input Voltage (V) 32 36 160 150 140 −50 −25 G008 Figure 16. 14 0 25 50 Temperature (°C) 75 100 125 G004 Figure 17. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, unless otherwise noted. BUS MEASUREMENT INPUT OFFSET VOLTAGE PRODUCTION DISTRIBUTION BUS MEASUREMENT INPUT OFFSET VOLTAGE vs TEMPERATURE −0.6 Population Offset (mV) −0.8 −1.0 −1.4 −50 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -7.5 -6 −1.2 −25 0 25 50 Temperature (°C) 75 100 125 G009 Input Offset Voltage (mV) Figure 18. Figure 19. BUS MEASUREMENT INPUT GAIN ERROR PRODUCTION DISTRIBUTION BUS MEASUREMENT INPUT GAIN ERROR vs TEMPERATURE 600 Population Gain Error (m%) 500 400 300 200 0 −50 100 80 60 40 20 0 -20 -40 -60 -100 -80 100 −25 0 25 50 Temperature (°C) 75 100 125 G012 Input Gain Error (m%) Figure 20. Figure 21. VINP+VINM INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE VINP+VINM INPUT BIAS CURRENT vs TEMPERATURE 24 20 Input Bias Current (µA) Input Bias Current (µA) 25 15 10 5 0 0 4 8 12 16 20 24 28 Common−Mode Input Voltage (V) 32 36 22 20 18 16 −50 −25 G012 Figure 22. 0 25 50 Temperature (°C) 75 100 125 G013 Figure 23. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 15 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VS = 3.3 V, VINP = 12 V, VSHUNT = (VINP – VINM) = 0 mV, unless otherwise noted. SAMPLING FREQUENCY RESPONSE (POR DEFAULT SETTINGS) 260 0 220 −10 180 −20 Gain (dB) Input Bias Current − Shutdown (nA) VINP+VINM INPUT BIAS CURRENT vs TEMPERATURE, POWER-DOWN MODE 140 100 −40 60 −50 20 −50 −25 0 25 50 Temperature (°C) 75 100 −60 125 10 100 1k Frequency (Hz) 10k Figure 25. ACTIVE IQ-VS vs I2C CLOCK FREQUENCY ACTIVE IQ-VS vs TEMPERATURE (NO I2C CLOCK) 500 Quiescent Current (µA) 400 350 100 1,000 400 300 200 100 −50 300 10 10,000 −25 0 25 50 Temperature (°C) 75 100 Figure 26. Figure 27. SHUTDOWN IQ-VS vs I2C CLOCK FREQUENCY SHUTDOWN IQ-VS vs TEMPERATURE (NO I2C CLOCK) 1.2 Quiescent Current − Shutdown (µA) 300 Shutdown IQ (mA) 250 200 150 100 50 0 10 100 1,000 10,000 1 0.8 0.6 0.4 0.2 −50 −25 0 25 50 Temperature (°C) Frequency (kHz) Figure 28. 16 125 G015 Frequency (kHz) 1 100k G001 Figure 24. 450 1 1 G014 500 IQ (mA) −30 75 100 125 G016 Figure 29. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 HOTSWAP APPLICATION INFORMATION Upgrading TPS2480 with TPS2482 and TPS2481 with TPS2483 The TPS2482 and TPS2483 are pin-compatible with the TPS2480 and TPS2481 with the exception that the VINP and VINM inputs are reversed in position. The TPS2482 and TPS2483 may be installed on a circuit board designed for the TPS2480/1 and operated successfully. The effect of the pin reversal will be to make the input current appear negative. This can be corrected in the interface software per the procedure discussed in Shunt Voltage Register 01h (Read-Only). This is not the only change required in the interface software as the data acquisition engine is different, requiring different configuration and calibration values. Basic TPS2482 and TPS2483 Operation The TPS2482 and TPS2483 provide all the features needed for a positive-voltage hotswap controller and monitor. These features include: 1. Under-voltage lockout; 2. Adjustable (system-level) enable; 3. Turn-on inrush limit; 4. High-side gate drive for an external N-channel MOSFET; 5. MOSFET over-current and power dissipation protection; 6. Adjustable overload timeout; 7. Charge-complete indicator for downstream converter sequencing; 8. Optional automatic restart mode; and 9. Serial-bus interface to monitor voltage, current, and power to the load. The TPS2482 and TPS2483 feature superior pass-MOSFET power-limiting protection that allows independent control of the current limit (to set maximum full-load current), power-limit and overload time (to keep the MOSFET within its SOA), and overload recovery time (to control case temperature rise). Oscilloscope waveforms from a typical 24-V application circuit, seen in Figure 30 through Figure 35, demonstrate many of the functions described above. EN can be used as a logic-level control input or as an analog input voltage monitor as illustrated by REN1/REN2 in the Simplified Application Diagram. The hysteresis associated with the internal comparator makes this a stable method of detecting a low input voltage condition and shutting off the pass-MOSFET. EN may also be tied directly to VCC to always enable the TPS2482 and TPS2483. Board Plug-In (Figure 30) Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. A startup cycle is ready to take place after POR2 stabilization. The TPS2482 and TPS2483 are held inactive and GATE, PROG, TIMER, and PG are held low for less than 1 ms while internal voltages stabilize. GATE, PROG, TIMER, and PG are released after stabilization if both the internal UVLO threshold and the external EN (enable) thresholds have been exceeded. After an RC-filter delay on EN passes, the device begins sourcing current from the GATE pin and M1 begins to turn on while the voltage across it, measured as V(SENSE–OUT), and current through it, measured as V(VCC–SENSE), are monitored and controlled. Once VGS has charged to the pass-MOSFET threshold voltage, current initially rises to the value which satisfies the power-limit engine, that is. (PLIM / VVCC), as seen on the trace labeled I-IN. The entire input voltage VCC is impressed across M1 since the output load capacitor, CO, was initially discharged. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 17 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Figure 30. Basic Board Insertion TIMER and PG Operation (Figure 30) The TIMER pin charges CT as long as limiting action continues, and discharges at 1/10 of the charge rate when all limiting stops (see trace labeled TMR). If the voltage on CT reaches 4 V while limiting is still active, the passMOSFET is turned off and either a latch-off or restart cycle commences, depending on the controller type. The open-drain PG output provides a deglitched end-of-charge indication which is based on the voltage across the pass-MOSFET. PG is useful to prevent a downstream DC-to-DC converter from starting while CO is still charging. PG goes active (open-drain) about 9 ms after CO is charged. This delay allows the pass-MOSFET to fully turn on and any transient disturbances in the power circuits to settle before the converter is allowed to start up. The resistor pull-up shown on pin PG in the typical application diagram illustrates an example operation only; the actual interface network to a converter depends on the specific application. CT charge can appear to terminate early in some designs (usually with high-CRSS MOSFETs) if operation transitions out of the power-limit mode into a gate-charge-limited mode at mid to low VDS values. This can occur when IGATE is insufficient to drive CISS of the MOSFET at a rate that would sustain operation in either PLIM or ILIM. In this situation, dVDS/dt is limited by IGATE/CRSS. 18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Action of the Constant Power-Limit Engine (Figure 31) The calculated power dissipated in the pass-MOSFET, VDS x ID, is computed under the startup conditions previously seen in Figure 30. The current of the pass-MOSFET, labeled I-IN, initially rises to the value that satisfies the constant power-limit engine; in this case it is 90 W / 24 V = 3.75A. The 90-W value is programmed into the engine by setting the PROG voltage using Equation 1. VDS of the pass-MOSFET, which is measured as V(SENSE-OUT) , decreases as CO charges, thus allowing the pass-MOSFET drain current to increase. This is the result of the internal constant-power engine adjusting the current-limit reference to the GATE amplifier as CO charges and VDS falls. The calculated device power dissipation shown in Figure 31 is flat-topped and constant within the limitations of circuit tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power-limit engine output to 50 mV when VDS is low. This protection technique can be viewed as a specialized form of foldback limiting; the benefit over a linear foldback technique is that it yields the maximum output current from a device over the full range of VDS and still protects the device. Figure 31. Computation of the Pass-MOSFET Stress During Startup Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 19 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Response to a Hard Output Short (Figure 32 and Figure 33) Figure 32 shows the short-circuit response over the full time-out interval. This interval begins when an output short-circuit is applied and ends when the pass-MOSFET is turned off. The pass-MOSFET current is actively controlled by the power-limit engine and gate amplifier circuit while the TIMER pin charges CT to the 4-V threshold. Once this threshold is reached, the TPS2482 and TPS2483 disable and shut off the pass-MOSFET. The TPS2482 remains latched off until either the VCC voltage drops below the UVLO threshold or EN is cycled through the false (low) state. The TPS2483 will automatically retry CO charging (attempt a restart) after going through a 16-count time-out cycle. Figure 32. Current Limit Overview 20 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 The TPS2482 and TPS2483 respond rapidly to the short-circuit as seen in Figure 33 (horizontal time base is 1 µs/div). The falling OUT voltage is the result of the pass-MOSFET and CO currents through the short-circuit impedance. The internal GATE diode clamp causes the GATE voltage to follow the output limits the negative VGS to 1~2 V. The rapidly rising fault current (not shown) overdrives the GATE amplifier causing it to overshoot and rapidly turn the pass-MOSFET off by sinking current to ground. The pass-MOSFET eventually turns back on as the GATE amplifier recovers and settles to an equilibrium operating point determined by the power-limit engine. Figure 33. Current Limit Onset Minimal input voltage overshoot appears in Figure 33 because a local 100-μF input bypass capacitor and very short input leads were used. In a typical application, as the input current abruptly drops, the input voltage may overshoot significantly due to stored energy in the input distribution inductance. The exact waveforms seen in an application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the nature of the overload or short-circuit itself. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 21 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Automatic Retry on Fault (Figure 34 and Figure 35) The TPS2483 automatically initiates a delayed restart attempt after a fault has caused it to turn off the passMOSFET. Internal control circuits use CT to count 16 charge/discharge cycles before re-enabling the passMOSFET. This sequence repeats if the fault persists. The TIMER has a 10:1 charge-to-discharge current ratio, and uses a 1-V lower threshold. TPS2483 will attempt to restart indefinitely, until a restart is successful or input power is removed. The fault-retry duty-cycle specification, DRETRY, quantifies this behavior. This small duty cycle often reduces the average short-circuit power dissipation in the MOSFET to levels associated with normal operation and reduces the need for additional thermal measures or derating. Figure 34. TPS2483 Retry-Cycle Timing Detail Figure 35. TPS2483 Full Retry-Cycle Timing 22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 24-V, 10-A Application Design Example The following example illustrates the design and component selection process for a 24-V, 10-A hotswap application. Figure 36 shows an example schematic for the TPS2482 and TPS2483 application. Figure 36. TPS2482 and TPS2483 Example Schematic 1. Choose Shunt Resistor RS The following equation includes a margin factor of 1.2 (20%) to account for current limit threshold (VCL) and RS tolerances along with some additional margin. IMAX is the maximum continuous load current. RS = • VSENSE 50mV = = 4.17 mΩ 1.2 ´ I MAX 1.2 ´ 10A (4) Where practical, select a standard value; choose RS = 4 mΩ. 2 PRS ( MAX ) = I MAX ´ RS = (10 A) 2 ´ 3mW = 0.3W (5) Pick a sense resistor with a power rating of 0.5 W or 1 W to allow some margin. Ensure sufficient heatsinking. 2. Choose Pass-MOSFET, M1 Select the VDS-rating of M1 allowing for peak input voltage, including transients and ringing. Then select an operating-RDS(on), device package, and cooling method to control the steady-state operating temperature. Most manufacturers list RDS(on)(MAX) at 25°C and provide an adjustment curve from which on-resistance at other temperatures can be derived. The next equation can be used to estimate desired RDS(on)(MAX) at the maximum operating junction temperature of TJ(MAX1) (usually 50°C below absolute maximum). TA(MAX) is the maximum expected ambient temperature. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 23 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 T J1(MAX) = 100C, T A(MAX) R DS(ON) < = 60C, R qJA = 31 TJ1(MAX) -TA(MAX) R θJA ×I = 2 MAX www.ti.com C ,I = 10A W (MAX) 100C-60C = 12.9 mΩ C 31 ×(10A) 2 W (6) The junction-to-ambient thermal resistance, RθJA, depends upon the package style chosen and the details of heat-sinking and cooling including the PCB. Actual “in-system” temperature measurements will be required to validate heat-sinking and cooling performance. Based on the above requirements CSD18503Q5A was chosen for M1. It has a VDS rating of 40 V and RDS(ON)(MAX) of 6.5 mΩ at 100°C meeting both the voltage and RDS(ON) requirements. 3. Choose the Power Limit, PLIM, and the PROG Resistors, RPROG1 and RPROG2 M1 dissipates large amounts of power during the brief power-up or output short-circuit events. Power limit, PLIM should be set to prevent M1 junction temperature from exceeding a short-term maximum temperature, TJ2(MAX). It is recommended to set TJ2(MAX) 25°C below the maximum junction temperature specified by the manufacturer to allow some margin. C C , R qJC = 1 , ZqJC = 0.3, R DS(ON)(MAX) = 6.45mW W W 2 0.7 ´ (TJ(MAX2) - R qCA ´ I MAX ´ R DSON(MAX) - TA(MAX) ) = = 106.5W R qJC ´ ZqJC TJ(MAX2) = 125C , TA(MAX) = 60C , R qCA = 30 PLIM (7) where, RθCA is M1 junction-to-case thermal resistance (computed by subtracting RθJC from RθJA), ZθJC is the normalized thermal impedance, RDS(ON)(MAX) is the channel resistance at the maximum operating temperature, and the factor of 0.7 accounts for the tolerance of the constant power engine. For CSD18503Q5A, ZθJC of 0.3 can be used for fault times below 10 ms. This assumption will be verified once the timer capacitor is chosen. The maximum power limit obtainable from the constant power-limit engine, PLIM(MAX), and nominal output power POUT(NOM) for this example system are calculated with the following equations: VREF = 4V,RS = 4mW,VOUT(NOM) = 24V, ILIMIT(NOM) = 12.5A PLIM(MAX) = 1V ´ VREF = 500W 2 ´ RS POUT(NOM) = VOUT(NOM) ´ ILIMIT(NOM) = 24V ´ 12.5A = 300W (8) The PROG resistors should be chosen using the smallest of PLIM, PLIM(MAX) , or POUT(NOM) values. Choose RPROG2 = 20kΩ. Choose RPROG1 as shown in Equation 9. PLIM(ACT) = 106.5W,RS = 4mW, RPROG2 = 20kΩ VPROG = 2 ´ PLIM(ACT) ´ RS 1V RPROG1 = RPROG2 ´ ( • = 2 ´ 106.5W ´ 4mΩ = 0.852V 1V VREF - 1) = 73.9kΩ VPROG (9) Choose RPROG1 = 73.2 kΩ, for a standard value. The current and power limit curve for this configuration is shown in Figure 37. 24 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Figure 37. Design Example Current and Power Limit Curve 4. Choose the Timer Capacitor, CT The turn on time tON, represents the time it takes the circuit to charge up the output capacitance CO. CT programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of start up. Assuming that all of the current is going towards charging CO, tON can be computed as follows: For PLIM(ACT) < VVCC(MAX) ´ ILIMIT(NOM) :tON = For PLIM(ACT) ³ VVCC(MAX) ´ ILIMIT(NOM) :tON = CO ´ PLIM(ACT) 2 2 ´ ILIMIT(NOM) + 2 CO ´ VVCC(MAX) 2 ´ PLIM(ACT) CO ´ VVCC(MAX) ILIMIT(NOM) (10) CT should be set to accommodate the worst case on time tON(MAX), which can be computed as follows: PLIM(MIN) = 0.7 ´ PLIM(ACT) = 75.1W , ILIMIT(MIN) = 0.9 ´ ILIMIT(ACT) = 11.25A , VVCC(MAX) = 2 6V, CO = 330mF tON(MAX) = = CO,MAX ´ PLIM(MIN) 2 2 ´ ILIMIT(MIN) + 2 CO,MAX ´ VVCC(MAX) 2 ´ PLIM(MIN) 330mF ´ 75.1W C330mF ´ (26V)2 + = 1.58ms 2 ´ (11.25A)2 2 ´ 75.1W (11) The next equation allows CT to be selected assuming that only CO draws current during startup. Account for the TPS2482 and TPS2483 timer current source and capacitor tolerances. ISOURCE(MAX) = 34mA,VTMR-TH(MIN) = 3.9V, CO-TOL = 20%,CT-TOL = 10% CT = CT = • ISOURCE(MAX) VTMR-TH(MIN) ´ t ON(MAX) ´ (1 + CO-TOL + CT-TOL ) 34mA ´1.58ms ´ (1 + 0.2 + 0.1) = 17.9nF 3.9V (12) Choose CT = 0.022 μF standard value. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 25 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Once CT is selected, it is prudent to back-calculate the longest fault-time which M1 must endure to validate that it remains properly within its SOA during a limiting event. If not, some previously-chosen system parameter(s) must be adjusted until M1 operates safely for both tON(max) and tFAULT(max), which can be computed as follows. ISOURCE(MIN) = 15mA,VTMR-TH(MAX) = 4.1V ,CT-TOL = 10% t FAULT(MAX) = VTMR-TH(MAX) ´ CT ISOURCE(MIN) ´ (1 + CT-TOL ) = 6.6ms (13) Note that tFAULT(MAX) is under 10 ms, supporting the use of ZθJC = 0.3. 5. Choose the Turn-On Voltage, VON, and the EN Resistors, REN1 and REN2 When the EN pin is used as an analog control, the desired input turn-on voltage, VON, can be used to select the EN resistors. The size of REN1 and REN2 need to be reasonable to avoid inaccuracy due to leakage current. First choose REN2 = 10 kΩ, and compute REN2 as follows: VON = 18V, VEN_H = 1.35V ,VEN_L = 1.25V , REN 2 = 10k W REN 1 = REN 2 ´ ( • VON - 1) = 123.33k W VEN_H (14) Choose REN1 = 124 kΩ standard value. The actual turn-on and turn-off voltages, VON and VOFF, can be calculated as follows: VON(MAX) = VEN_H ´ REN1 + REN2 = 18.09V REN2 VOFF(MIN) = VEN_L ´ REN1 + REN2 = 16.75V REN2 (15) Miscellaneous Design Considerations The serial bus will require pullup resistors (RSCL, RSDA, RALT). These are placed at the end of the bus. Typical values are 10 kΩ to a 3.3-V supply. CVS must be placed adjacent to the TPS2482 and TPS2483 to bypass noise at the VS input. 0.1 µF is a good choice. C1 provides a local source of bias currents and aids in controlling the dV/dt and overshoot on VCC. The size of C1 might be controlled by inrush energy considerations during board plug-in. PG and RPG are not necessary for TPS2482 and TPS2483 operation. However, the PG output can be used to minimize loading from downstream DC/DC circuits during inrush. RPG serves as a placeholder for some type of interface to those downstream circuits. D1 may be required for some systems. See Input and Output Transient Protection below. Note: In some cases, start-up may transition out of power-limited and current-limited operating modes before CO is fully charged, and CT begins to discharge as depicted in Figure 30. In such situations, VGS of the passMOSFET is held nearly constant by the output dV/dt and CO charging continues due to the high transconductance of the MOSFET. The circuit behaves like a source-follower, but the remaining time to fully charge CO is dependent on variable MOSFET parameters. The actual turn-on time used to determine CT (in Equation 12 ) may be longer than the time calculated by Equation 10. Prototype testing is necessary to identify this situation and validate the proper choice for CT. 26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Alternative Inrush Designs Gate Capacitor (dV/dt) Control The TPS2482 and TPS2483 can be configured to provide a controlled linear dVOUT/dt turn-on characteristic. The load-capacitor charging current, ICHARGE, is controlled by an R-C network (RG1 - CG1) from the GATE terminal to ground. M1 operates as a source follower (which follows the gate voltage) in this implementation. Choose a dV/dt-controlled charge time, tON_G1, based on the load capacitor, CO, input voltage VCC, and desired charge current. When power-limiting is used (VPROG < VVREF), choose ICHARGE to be less than PLIM /VVCC to prevent the fault timer from starting. The fault timer starts only if power limit or current limit is invoked. It is assumed there is no downstream load current during this charge-up time. (16) Use the following equation to select the external gate capacitance, CG. As shown in Figure 36, an RG1 of about 1 kΩ should be used in series with CG. æ Δt ö CG = ç IGATE ´ ÷ - CRS V è VCC ø (17) IGATE is the nominal gate charge current. This equation assumes that the MOSFET CGD is the controlling element as the gate and output voltage rise. Since, CGD is non-linear with applied VGD an averaged estimate (CRS) should be used when computing using CG. Divide the MOSFET QGD by VIN to obtain CRS. Since neither power nor current-limit faults are invoked during turn on, CT can be chosen for fast transient turn off response using the M1 SOA curve. Choose the single pulse time conservatively from the M1 SOA curve using maximum operating voltage and maximum trip current. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 27 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com High Voltage Application Example The TPS2482 and TPS2483 can be used to monitor current from a voltage source greater than 36 V by using a "high-side" Op-Amp circuit, as shown in Figure 38. This circuit translates the high-side current shunt voltage to a ground-referenced signal within the monitor section's operational rating. Voltage and power monitoring are lost in this configuration. Except for the high-side translation circuit, the system design and component selection process is the same as for the 24-V, 10-A Application Design Example. Figure 38. TPS2482 and TPS2483 High Voltage Application Diagram The basic operating principle of U2, M2, RMA, and RMB is to mirror the voltage seen across RS from a VCCreferenced voltage to a GND-referenced voltage. As load current flows through RS, the voltage at the (+) input of U2 decreases and U2 drives M2 to cause its source voltage at the (-) input to follow the (+) input. Ideally then, the voltage across RMA mirrors the voltage drop of RS. Current flow though RMB will mirror current through RMA, and if RMB = RMA, then the shunt voltage across RS is mirrored at VINP. Since only small voltages will be across RMA and RMB, their nominal values should be fairly low to avoid input bias-current effects (IVINP). While discrete resistors may provide acceptable performance, well-matched networktype resistors with temperature coefficient tracking for RMA and RMB will provide the most accurate solution. 28 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 U2 should be a high-quality, low-drift operational amplifier, such as the OPA333, which provides low input voltage offset and very low drift over time and temperature. U2 is referenced to VCC through D2 and RB and its output can operate from rail to rail. P-channel MOSFET M2 can be a small-signal device rated for the maximum input voltage, such as Si2325DS or similar. Additional Design Considerations Use of PG Output Use the PG pin to control and sequence a downstream DC/DC converter. If this is not done, a long time delay may be needed on the converter to allow CO to fully charge before the converter starts. Output Clamp Diode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during sudden current limit. Protect the OUT pin from excessive negative voltage excursions with a clamp diode from OUT to GND. The diode must be sized to carry the peak fault current . Gate Clamp Diode The TPS2482 and TPS2483 have a relatively well-regulated gate voltage of 12 V to 16 V, even at low supply voltages. If VGS of the pass-MOSFET is rated below 20 V, an external Zener clamp-diode, such as a BZX84C7V5, is recommended from gate to source. High Gate Capacitance Applications An external gate clamp Zener diode is recommended if the total gate capacitance of M1 exceeds 4000 pF, to aid in controlling the MOSFET peak VGS if the source is abruptly pulled to ground. without the external clamp, excess VGS voltage may occur as a result of the CDG/CGS divider in M1. When gate-capacitor dV/dt control is used, a 1kΩ resistor in series with CG1 is recommended, as shown in Figure 36. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then an external Zener diode is usually not required. Input and Output Transient Protection Hotswap systems experience positive-going transients on their input during hotswap or rapid turn-off events due to inductance in the input circuit. These same systems experience negative-going transients on the output during rapid turn-off due to inductance in the output circuit. The location of transients experienced by the TPS2482 and TPS2483 will depend on the application; one example is a hotswap input protector, and a second example is short circuit protection for an output cable. When used as an input hotswap protector, input voltage overshoots are a primary concern. Absolute Maximum Voltage (VABS) ratings of the VINM and VINP pins will control the maximum operating voltage and the choice of transient protection. The use of a transient voltage suppressor (TVS) across the input power line is recommended to sink the over-current. Consider the SMCJ28A TVS as an example. The breakdown voltage is 31.1 V to 34.4 V at 1 mA, and its clamp voltage is 45 V at 33.1 A. Considering the worst case, the TVS can be modeled as an ideal 34.4 V diode in series with a 0.32 Ω resistor. The model indicates the SMCJ28A will conduct at least 17.5 A of current at 40 V. This device can provide sufficient protection from an inductive current spike that is less than 17.5 A. Overall, the magnitude of these spikes is very system dependent and should be evaluated in a real system. As a rule of thumb, pick a TVS to support a current spike twice the operating current. Then test the circuit in a fully loaded system, observe the maximum transient voltage (VMAX), and ensure that the difference between VMAX and VABS is at least 3 volts to account for variation in the break down voltage of the TVS. If this difference is too small, pick a TVS with a larger die area or use two in parallel. When the TPS2482 and TPS2483 are used as an output protector with sufficient input capacitance these transient spikes are not as big of a concern. In this case, a 4 V margin between the VINP and VINM operating voltage and absolute max should be sufficient. An output voltage clamp to GND may be required to limit negative transients if the local output capacitance does not provide adequate control. An example of this is a system with significant output bus inductance and little local capacitance. In this case, select a schottky diode with low forward voltage drop at the anticipated current during an output short-circuit shut-down event. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 29 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Output Short-Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short-circuit, and instrumentation all contribute to varying results. The actual short-circuit itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in test configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet since every setup differs. Applications Using the Retry Feature (TPS2483) Applications using the retry feature may want to estimate fault retry time. The TPS2483 will retry (enable M1 to attempt turn-on to restart the load) once for every 16 TIMER charge/discharge cycles (1 segment between 0 V and 1 V, and 16 cycles from 1 V to 4 V back to 1V). However, in the case of an immediate fault upon each retry attempt, the minimum retry interval is found by Equation 18, when the voltage on CT does not fall appreciably below 1V at the end of each retry interval. Although most retry intervals are likely to be slightly longer, using this retry equation in thermal analysis will help achieve conservative results. (18) (19) NOTE Equation 19 is simplified - assumes no error, nominal conditions, and immediate fault on retry. Resistance shown is an effective mathematical value, not a true resistance. PCB Layout Considerations Good layout practice arranges the power devices D1, RS, M1, and CO so that power flows in a sequential, linear fashion. A ground plane under the positive current path and the TPS2482 and TPS2483 are desirable. The TPS2482 and TPS2483 should be placed close to the sense resistor and MOSFET, using Kelvin-type connections to achieve accurate voltage sensing across RS. A low-impedance GND connection is required because the TPS2482 and TPS2483 can momentarily sink current greater than 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the GATE trace-length short. The PROG, TIMER, and EN pins have high input impedances, therefore keep their input leads short. Oversize power traces and powerdevice connections to assure low voltage drop and good thermal performance. 30 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 MONITORING APPLICATION INFORMATION The TPS2482 and TPS2483 incorporate a digital monitor with a serial-bus interface compatible with I2C and SMBus. It provides digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution as well as continuous-versus-triggered operation. Detailed register information appears at the end of this data sheet, beginning with Table 3. See the Register Block Diagram for a high-level overview of the TPS2482 and TPS2483 monitoring section. Each data register contains a value stored as a binary number (often abbreviated in the hexadecimal format in the text) which represents the magnitude of the respective register measurement or calculation. Each of these registers also has a corresponding unit weighting for the least significant bit (LSB) of the respective register, which is used to scale that register's decimal equivalent value to the actual real-world magnitude in the units for that parameter. The Shunt Voltage Register and the Bus Voltage Register have fixed internal LSB-weights of 2.5 µV/bit and 1.25 mV/bit, respectively. The Current Register's LSB-weight is determined using the process discussed in PROGRAMMING THE TPS2482 and TPS2483 MONITOR SECTION. The Power Register's LSBweight is internally determined based on the Current Register's LSB-weight. Reading a register via the serial-bus for a particular parameter of interest returns the value stored in that register. Multiplying the register's decimal value by its corresponding LSB-weight yields the actual magnitude of that register's measured or calculated parameter. BASIC ADC FUNCTIONS The TPS2482 and TPS2483 monitoring section performs two measurements on the input power-supply bus of interest. The load current that flows through a shunt resistor develops a shunt voltage that is measured at the VINP and VINM pins. The shunt resistor is used by both the hotswap and monitoring sections. The device also measures the input bus voltage at the VINM input with respect to ground. The monitoring section is typically powered by a separate power supply that can range from 2.7 V to 5.5 V. The input bus can be monitored over a range of 0 V to 36 V. It is important to note here that based on the fixed 1.25mV LSB for the Bus Voltage Register, a full-scale register would result in a value of 40.96 V. The actual voltage that is applied to the VINP and VINM pins of the TPS2482 and TPS2483 should not exceed 36 V. There are no special considerations for power-supply sequencing because the common-mode input range and powersupply voltage are independent of each other; therefore, the bus voltage can be present with the supply voltage off, and vice-versa. As noted, the TPS2482 and TPS2483 take two measurements, shunt voltage and bus voltage. It then converts the shunt measurement to current based on the Calibration Register value, and thereafter calculates power. Refer to the Configure/Measure/Calculate Example section for additional information on programming the Calibration Register. Monitoring can operate in one of two conversion modes, continuous or triggered, which determine how the ADC proceeds following a measurement conversion. When the TPS2482 and TPS2483 are in the normal continuous operating mode (that is, MODE bits of the Configuration Register are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage reading. After each shunt voltage reading, the current value is calculated (based on Equation 22). This current value is then used to calculate the power result (using Equation 23). These values are subsequently stored in an accumulator, and the measurement/calculation sequence repeats until the number of averaging samples set in the Configuration Register is reached. Following every sequence, the present set of values measured and calculated are appended to previously collected values. Once all of the averaging has been completed, the final values for shunt voltage, bus voltage, current, and power are updated in the corresponding registers that can then be read. These values remain in the data output registers until they are replaced by the next fully-averaged conversion results. Reading the data output registers does not affect a conversion in progress. The Mode control in the Configuration Register also permits selecting modes to convert only the shunt voltage or only the bus voltage in order to allow the user to configure the monitoring function to fit the specific application requirements. All current and power calculations are performed in the background and do not contribute to conversion time. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 31 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com To operate in triggered mode, writing any of the triggered-convert modes into the Configuration Register (that is, MODE bits of the Configuration Register are set to ‘001’, ‘010’, or ‘011’) triggers a single-shot conversion. This action produces a single set of measurements; thus, to trigger another single-shot conversion, the Configuration Register must be written to a subsequent time, even if the mode does not change. In addition to the two operating modes (continuous and triggered), the TPS2482 and TPS2483 also have a power-down mode that reduces the section quiescent current and turns off the bias currents into VINP and VINM (except for the 830 kΩ on VINM), reducing the impact of supply drain when the monitoring section is not being used. The registers of the TPS2482 and TPS2483 can be written to and read from while the device is in powerdown mode. The device remains in power-down mode until one of the active modes settings are written into the Configuration Register. Power-on reset for the monitoring section (POR1) configures continuous shunt and bus monitoring as default. Full recovery from POR1 or power-down mode requires about 40 µs. Although the TPS2482 and TPS2483 can be read at any time, and the data from the last conversion remain available, the Conversion Ready Flag bit (Mask/Enable Register, CVRF bit) is provided to help coordinate oneshot or triggered conversions. The Conversion Ready Flag bit is set after all conversions, averaging, and multiplication operations are complete. The Conversion Ready Flag bit clears under these conditions: 1. Writing to the Configuration Register, except when configuring the MODE bits for power-down mode; or 2. Reading the Status Register. Power Calculation The Current and Power values are calculated following shunt voltage and bus voltage measurements as shown in Figure 39. Current is calculated following each shunt voltage measurement based on the value set in the Calibration Register. If there is no value loaded into the Calibration Register, the current value stored is zero. Power is calculated following each bus voltage measurement based on the previous current calculation and that bus voltage measurement. If there is no value loaded in the Calibration Register, the power value stored is also zero. Again, these calculations are performed in the background and do not add to the overall conversion time. These current and power values are considered intermediate results (unless the averaging is set to '1') and are stored in an internal accumulation register set, not the corresponding output registers. Following every measured sample, the newly-calculated values for current and power are appended to this accumulation register set until all of the samples have been measured and averaged based on the number of samples set in the Configuration Register. Bus and Power Limit Detect Following Every Bus Voltage Conversion Current Limit Detect Following Every Shunt Voltage Conversion I V I P V I P V I P V I P V I P V I P V I P V I P V I V P I V P I P V I P V I P V I P V I P V P Power Average Bus Voltage Average Shunt Voltage Average Figure 39. Power Calculation Scheme In addition to the current and power values accumulating after every sample, the shunt and bus voltage measurements are also collected. Once all of the samples have been measured and the corresponding current and power calculations have been made, the accumulated average for each of these parameters is then loaded to their corresponding output registers, where they can then be read. Figure 39 illustrates an averaging of 16 samples. Also indicated in Figure 39 is the relative timing of the various current, voltage, and power limit detection functions associated with the ALERT pin. Details of the Alert functions can be found in the ALERT PIN section. 32 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Averaging and Conversion Time Considerations The TPS2482 and TPS2483 have programmable conversion times for both the shunt voltage and bus voltage measurements. The conversion times for these measurements can be selected from as fast as 140 μs to as long as 8.244 ms. The conversion time settings, along with the programmable averaging mode, allow the TPS2482 and TPS2483 to be configured to optimize the available timing requirements in a given application. For example, if a system requires that data be read every 5 ms, the TPS2482 and TPS2483 could be configured with the conversion times set to 588 μs and the averaging mode set to '4'. This configuration results in the data updating approximately every 4.7 ms. The TPS2482 and TPS2483 could also be configured with a different conversion time setting for the shunt and bus voltage measurements. This type of approach is common in applications where the bus voltage tends to be relatively stable. This situation can allow for the time focused on the bus voltage measurement to be reduced relative to the shunt voltage measurement. The shunt voltage conversion time could be set to 4.156 ms with the bus voltage conversion time set to 588 μs, with the averaging mode set to '1'. This configuration also results in data updating approximately every 4.7 ms. There are trade-offs associated with the settings for conversion time and the averaging mode used. The averaging feature can significantly improve the measurement accuracy by effectively filtering the signal. This approach allows the TPS2482 and TPS2483 to reduce any noise in the measurement that may be caused by noise coupling into the signal. A greater number of averages enables the TPS2482 and TPS2483 to be more effective in reducing the noise component of the measurement. The conversion times selected can also have an impact on the measurement accuracy. This effect can seen in Figure 40. Multiple conversion times are shown here to illustrate the impact of noise on the measurement. In order to achieve the highest accuracy measurement possible, a combination of the longest allowable conversion times and highest number of averages should be used, based on the timing requirements of the system. 10mV/div Conversion Time: 140ms Conversion Time: 1.1ms Conversion Time: 8.244ms 0 200 400 600 800 1000 Number of Conversions Figure 40. Noise vs Conversion Time Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 33 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Filtering and Input Considerations Measuring current is often noisy, and such noise can be difficult to define. The TPS2482 and TPS2483 offer several options for filtering by allowing the conversion times and number of averages to be selected independently in the Configuration Register. The conversion times can be set independently for the shunt voltage and bus voltage measurements to allow added flexibility in configuring the monitoring of the power-supply bus. The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500 kHz (±30%) typical sampling rate. This architecture has good inherent noise rejection; however, transients that occur at or very close to the sample-rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be managed by incorporating simple R-C filtering at VINP and VINM. The high frequency enables the use of low-value series resistors on the filter with negligible effects on measurement accuracy. In general, filtering the TPS2482 and TPS2483 monitoring input is only necessary if there are transients at exact harmonics of the 500 kHz (±30%) sampling rate (greater than 1 MHz). Filter using the lowest possible series resistance (typically 10 Ω for RFLTR) and a ceramic capacitor, CFLTR. Recommended values for CFLTR are 0.1 μF to 1.0 μF. Figure 41 shows the TPS2482 and TPS2483 with an additional filter added at the input. A short circuit on the hotswap output can create an input voltage overshoot. This occurs as the input circuit inductance discharges when the MOSFET, M1, turns off. These transients could exceed the 40-V common-mode rating of VINP and VINM if not controlled. See Input and Output Transient Protection for guidance. In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to VINP and VINM. A hard physical short is the most likely cause of this event. This problem occurs because an excessive dV/dt can activate the ESD protection. The addition of 10-Ω resistors in series with VINP and VINM will protect the monitor inputs against this dV/dt failure up to their maximum 40-V ratings. Figure 41. TPS2482 and TPS2483 with Input Filtering 34 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 ALERT PIN The TPS2482 and TPS2483 have a single Alert Limit Register, 07h, that allows the ALERT pin to be programmed to respond to a single user-defined event or to a conversion ready notification if desired. The Mask/Enable Register allows the user to select from one of the five available functions to monitor and/or set the conversion ready bit to control the response of the ALERT pin. Based on the function being monitored, the user would then enter a value into the Alert Limit Register to set the corresponding threshold value that asserts the ALERT pin. The ALERT pin allows for one of several available Alert functions to be monitored to determine if a user-defined threshold has been exceeded. The five Alert functions that can be monitored are: • • • • • Shunt Voltage Over Limit (SOL) Shunt Voltage Under Limit (SUL) Bus Voltage Over Limit (BOL) Bus Voltage Under Limit (BUL) Power Over Limit (POL) The ALERT pin is an open-drain output. This pin is asserted when the value of the Alert function selected in the Mask/Enable Register exceeds the value programmed into the Alert Limit Register. Only one of these Alert functions can be enabled and monitored at a time. If multiple Alert functions are enabled, the selected function in the highest significant bit position takes priority and exclusively responds to the Alert Limit Register value. For example, if the Shunt Voltage Over Limit and the Shunt Voltage Under Limit are both selected, the ALERT pin asserts only when the Shunt Voltage Over Limit Register exceeds the value in the Alert Limit Register. The Conversion Ready state of the device can also be monitored at the ALERT pin to inform the user when the device has completed the previous conversion and is ready to begin a new conversion. Conversion Ready can be monitored at the ALERT pin simultaneously with one of the Alert functions. If an Alert function and the Conversion Ready are both enabled to be monitored at the ALERT pin, after the ALERT pin is asserted, the Mask/Enable Register must be read following the Alert to determine the source of the Alert. By reading the Conversion Ready Flag (CVRF), bit D3, and the Alert Function Flag (AFF), bit D4 in the Mask/Enable Register, the source of the Alert can be determined. If the Conversion Ready feature is not desired and the CNVR bit is not set, the ALERT pin only responds to an exceeded Alert limit based on the Alert function enabled. If the Alert function is not used, the ALERT pin can be left floating without affecting the operation of the device. Refer to Figure 39 to see the relative timing of when the value in the Alert Limit Register is compared to the corresponding Alert function value. For example, if the Alert function that is enabled is Shunt Voltage Over Limit (SOL), following every shunt voltage conversion the value in the Alert Limit Register is compared to the measured shunt voltage to determine if the measurement has exceeded the programmed limit. The AFF, bit 4 of the Mask/Enable Register, asserts high any time the measured voltage exceeds the value programmed into the Alert Limit Register. In addition to the AFF being asserted, the ALERT pin logic polarity is asserted based on the Alert Polarity Bit (APOL, bit 1 of the Mask/Enable Register). If the Alert Latch is enabled, the AFF and ALERT pin remain asserted until either the Configuration Register is written to or the Mask/Enable Register is read. The Shunt Voltage Alert functions compare the measured Shunt Voltage Register value to the Alert Limit Register value following every shunt voltage conversion and assert the AFF bit and ALERT pin if the programmed limit threshold is exceeded. The Bus Voltage Alert functions compare the measured Bus Voltage Register value to the Alert Limit Register value following every bus voltage conversion and assert the AFF bit and ALERT pin if the programmed limit threshold is exceeded. The Power Over Limit Alert function compares the calculated Power Register value to the Alert Limit Register value following every bus voltage conversions and asserts the AFF bit and ALERT pin if the programmed limit threshold is exceeded. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 35 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com PROGRAMMING THE TPS2482 and TPS2483 MONITOR SECTION An important aspect of the TPS2482 and TPS2483 is that they do not measure current or power directly. The TPS2482 and TPS2483 measure both the differential shunt voltage applied between the VINP and VINM input pins and the bus voltage applied from the VINM pin to GND. In order for the TPS2482 and TPS2483 to report both current and power values, the user must program the resolution of the Current Register and the value of the shunt resistor used in the application. The Power_LSB, corresponding to the Power Register, is internally set to be 25 times the programmed Current_LSB. Both the Current_LSB and shunt-resistor value are used in the calculation of the Calibration Register value which the TPS2482 and TPS2483 use to calculate the corresponding current and power values based on the shunt and bus voltage measurements. The Calibration Register value is calculated using Equation 21. CAL(ibration) is the factor used to convert the value in the Shunt Voltage Register to the value representing current in the Current Register. This equation includes the Current_LSB term, which is a rounded value for the LSB-weight of the Current Register. The highest resolution for the Current Register can be obtained by using the exact Current_LSB value, based on the maximum expected current, as determined by Equation 20. While this value will yield the highest resolution, it is common practice to select a value for the Current_LSB to the nearest round number above this value to simplify the conversion of the Current Register and Power Register values to amperes and watts, respectively. The RSHUNT term is the value of the external shunt resistor used to generate the differential voltage across the input pins. The 0.00512 term in Equation 21 is a constant factor used to scale the external values to the proper internal levels. (20) (21) Once the Calibration Register has been programmed, the Current Register and Power Register will be updated accordingly based on the corresponding shunt voltage and bus voltage averaged measurements. Until the Calibration Register is programmed, the Current and Power Registers remain at zero. 36 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 CONFIGURE/MEASURE/CALCULATE EXAMPLE In this example, shown in Figure 42, a nominal 40-A load current creates a differential voltage of 40 mV across a 1-mΩ shunt resistor. The bus voltage for the TPS2482 and TPS2483 is measured from VINM to GND. In this case, the VINM pin measures 11.96 V as a consequence of the voltage drop across the shunt resistor. Figure 42. Example Circuit Configuration For this example, assuming a maximum expected current of 55 A (based on the ILIM tolerance), the exact Current_LSB is calculated to be 1.679 mA/bit using Equation 20. Choosing a rounded-up Current_LSB value of 2 mA/bit would significantly simplify the mental conversion of the Current Register and Power Register values to amperes and watts. Using a rounded value for the Current_LSB does trade off a small amount of resolution for having a simpler calculation process on the part of the user. With a Current_LSB of 2 mA/bit and a shunt resistance of 1-mΩ in this example, using Equation 21 results in a Calibration Register value of 2560, or A00h. The Current Register value is then calculated by multiplying the decimal value of the Shunt Voltage Register contents by the decimal value of the Calibration Register and dividing by 2048 (another internal scaling factor), as shown in Equation 22. For this example, the Shunt Voltage Register contains a value of 16000, which is multiplied by the Calibration Register value of 2560 and then divided by 2048 to yield a decimal value for the Current Register of 20000, or 4E20h. Multiplying this value by 2 mA/bit results in the original 40-A current level stated at the beginning of this example. (22) The LSB for the Bus Voltage Register is internally fixed at 1.25 mV/bit, which means that the 11.96 V present at the VVINM pin results in a register representation value of 2560h, or a decimal equivalent of 9568. Note that the MSB of the Bus Voltage Register is always zero because the VVINM pin is only able to measure positive voltages. The Power_LSB has a fixed ratio to the Current_LSB of 25 W/bit to 1 A/bit. For this example, a programmed Current_LSB of 2 mA/bit automatically results in a Power_LSB of 50 mW/bit ( ((25 W/bit) / (1 A/bit)) * 2 mA/bit ). The 25-W/A ratio is internally programmed to ensure that the results of the power calculation falls within an acceptable representation range for the Power Register. The Power Register value is calculated by multiplying the decimal value of the Current Register, 20000, by the decimal value of the Bus Voltage Register, 9568, and then dividing by 20000, as defined in Equation 23. For this example, the result for the Power Register is 2560h, or a decimal equivalent of 9568. Multiplying this value by the Power_LSB results in a calculation of (9568 × 50 mW/bit), or 478.4 W of actual power. To verify the example, a manual calculation for the power being delivered to the load uses the bus voltage of 11.96 V (12 V source – 40 mV shunt drop) multiplied by the load current of 40 A to give a result of 478.4 W. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 37 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com (23) Table 2 shows the steps for configuring, measuring, and calculating the values for current and power for this device. Table 2. Configure/Measure/Calculate Example (1) CONTENT REPRESENTATION (1) STEP # REGISTER NAME ADDRESS HEXADECIMAL DECIMAL LSB-WEIGHT Step 1 Configuration 00h 4127h — — ACTUAL VALUE — Step 2 Shunt Voltage 01h 3E80h 16000 2.5 µV/bit 40 mV Step 3 Bus Voltage 02h 2560h 9568 1.25 mV/bit 11.96 V Step 4 Calibration 05h A00h 2560 — — Step 5 Current 04h 4E20h 20000 2 mA/bit 40 A Step 6 Power 03h 2560h 9568 50 mW/bit 478.4W Conditions: RSHUNT = 1 mΩ, load current = 40 A, VCM = 12 V, and VVINM = 12 V. PROGRAMMING THE TPS2482 and TPS2483 POWER MEASUREMENT ENGINE Calibration Register and Scaling The Calibration Register makes it possible to set the scaling of the Current and Power Registers to whatever values are most useful for a given application. One strategy may be to set the Calibration Register such that the largest possible number is generated in the Current Register or Power Register at the expected full-scale point. This approach would yield the highest resolution based on using the previously-calculated exact Current_LSB in the equation for the Calibration Register. The Calibration Register value can also be selected to produce values in the Current and Power Registers that either provide direct decimal equivalents of the values being measured, or yield a rounded LSB-value for each respective register. After these choices have been made, the programmable Calibration Register also offers possibilities for end-user system-level calibration. By physically measuring the current with an accurate external ammeter, the exact current is known. The calculated value for the Calibration Register can then be adjusted, based on the measured-current result of the TPS2482 and TPS2483, to cancel the total system error as shown in Equation 24. Store the Corrected_CAL value (rounded to the nearest whole number) in place of the previously-stored (exact or rounded) CAL value. If necessary, iterate this process until the current reported by the TPS2482 and TPS2483 is equal to the ammeter measurement. (24) 38 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Simple Current Shunt Monitor Usage (No Programming Necessary) The TPS2482 and TPS2483 can be used without any programming if it is only necessary to read a shunt voltage drop and bus voltage with the default power-on reset configuration and continuous conversion of shunt and bus voltage. Without programming the TPS2482 and TPS2483 Calibration Register, the device is unable to provide either a valid current or power value, because these outputs are both derived using the values loaded into the Calibration Register. Default TPS2482 and TPS2483 Settings The default power-up states of the registers are shown in the REGISTER DETAILS section of this data sheet. These registers are volatile, and if programmed to a value other than the default values shown in Table 3, they must be re-programmed at every device power-up. Detailed information on programming the Calibration Register specifically is given in the Configure/Measure/Calculate Example section and calculated based on Equation 21. REGISTER INFORMATION The TPS2482 and TPS2483 monitoring section uses a bank of registers for programming and holding configuration settings, measurement results, minimum/maximum limits, and status information. Table 3 summarizes all of the TPS2482 and TPS2483 registers. Refer to the Register Block Diagram for a simplified illustration of the measurement data registers. Table 3. Summary of Register Set POINTER ADDRESS (1) (2) POWER-ON RESET DEFAULT SETTINGS BINARY HEX TYPE (1) Configures all-register reset, shunt voltage and bus voltage ADC conversion times and averaging, operating mode. 01000001 00100111 4127 R/W Shunt voltage averaged measurement data. 00000000 00000000 0000 R Bus Voltage Bus voltage averaged measurement data. 00000000 00000000 0000 R 3 Power (2) Contains the value of the calculated power being delivered to the load. 00000000 00000000 0000 R 4 Current (2) Contains the value of the calculated current flowing through the shunt resistor. 00000000 00000000 0000 R 5 Calibration Sets full-scale range and LSB value of current and power measurements. Overall system calibration. 00000000 00000000 0000 R/W 6 Mask/Enable Alert configuration and Conversion Ready flag. 00000000 00000000 0000 R/W 7 Alert Limit Contains the limit value to compare to the selected Alert function. 00000000 00000000 0000 R/W FF Die ID ASCII ASCII R HEX REGISTER NAME 0 Configuration Register 1 Shunt Voltage 2 FUNCTION Contains unique die identification number. Type: R = Read-Only, R/W = Read/Write. The Current Register defaults to '0' because the Calibration Register defaults to '0', yielding zero current and power values until the Calibration Register is programmed. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 39 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com REGISTER DETAILS All 16-bit registers in the TPS2482 and TPS2483 comprise two 8-bit bytes via the serial-bus interface. Configuration Register 00h (Read/Write) BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME RST — — — AVG2 AVG1 AVG0 VBUSCT2 VBUSCT1 VBUSCT0 VSHCT2 VSHCT1 VSHCT0 MODE3 MODE2 MODE1 POR1 VALUE 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 1 The Configuration Register bit settings control the operating modes for the TPS2482 and TPS2483. This register controls the conversion time settings for both the shunt and bus voltage measurements as well as the averaging mode used. The operating mode that controls which signals are selected to be measured is also programmed in the Configuration Register. The Configuration Register can be read from at any time without impacting or affecting the device settings or a conversion in progress. However, writing to the Configuration Register will halt any conversion in progress until the write sequence is completed, resulting in a new conversion starting based on the new contents of the Configuration Register. This prevents any uncertainty in the conditions used for the next completed conversion. Configuration Register Bit Descriptions RST: Reset Bit Bit 15 Setting this bit to '1' generates a system reset that is the same as power-on reset (POR1). Resets all registers to default values; this bit self-clears. (RESERVED): Undefined and Reserved Bits 12-14 These bits are preset to '100', perform no defined function, and are not programmable by the user. Reserved for future use. AVG: Averaging Mode Bits 9–11 Sets the number of samples that will be collected and averaged together. Table 4 summarizes the AVG bit options and related number of samples averaged for each bit combination. Applies to both shunt and bus voltage measurements. Table 4. AVG Bit Settings [11:9] (1) (1) 40 AVG2 D11 AVG1 D10 AVG0 D9 NUMBER OF SAMPLES AVERAGED 0 0 0 1 0 0 1 4 0 1 0 16 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 1024 Shaded values are POR1 default. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 VBUS CT: Bus Voltage Conversion Time Bits 6–8 Sets the conversion time for each bus voltage measurement. Table 5 shows the VBUS CT bit options and related conversion times for each bit combination. Applies to VBUS measurement only. (1) Table 5. Bus Voltage CT Bit Settings [8:6] (1) VBUS CT2 D8 VBUS CT1 D7 VBUS CT0 D6 CONVERSION TIME 0 0 0 140µs 0 0 1 204µs 0 1 0 332µs 0 1 1 588µs 1 0 0 1.1ms 1 0 1 2.116ms 1 1 0 4.156ms 1 1 1 8.244ms Shaded values are POR1 default. VSHUNT CT: Shunt Voltage Conversion Time Bits 3–5 Sets the conversion time for each shunt voltage measurement. Table 6 shows the VSHUNT CT bit options and related conversion times for each bit combination. Applies to VSHUNT measurement only. Table 6. Shunt Voltage CT Bit Settings [5:3] (1) (1) VSHUNT CT2 D5 VSHUNT CT1 D4 VSHUNT CT0 D3 CONVERSION TIME 0 0 0 140µs 0 0 1 204µs 0 1 0 332µs 0 1 1 588µs 1 0 0 1.1ms 1 0 1 2.116ms 1 1 0 4.156ms 1 1 1 8.244ms Shaded values are POR1 default. MODE: Operating Mode Bits 0–2 Selects continuous, triggered, or power-down mode of operation. These bits default to continuous shunt and bus measurement mode. The mode-setting options are shown in Table 7. Table 7. Operating Mode Settings [2:0] (1) (1) MODE3 D2 MODE2 D1 MODE1 D0 0 0 0 Power-Down 0 0 1 Shunt Voltage, Triggered 0 1 0 Bus Voltage, Triggered 0 1 1 Shunt and Bus, Triggered 1 0 0 Power-Down 1 0 1 Shunt Voltage, Continuous 1 1 0 Bus Voltage, Continuous 1 1 1 Shunt and Bus, Continuous OPERATING MODE Shaded values are POR1 default. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 41 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com DATA OUTPUT REGISTERS Shunt Voltage Register 01h (Read-Only) The Shunt Voltage Register stores the most recent, fully-averaged shunt voltage measurement, VSHUNT, represented by the LSB-weighted magnitude of that value. Negative numbers are represented in twos complement format. Generate the twos complement of a negative number by complementing the absolute value binary number and adding '1'. Extend the sign, denoting a negative number by setting the MSB = '1'. Example: For a value of VSHUNT = –80 mV: 1. Take the absolute value: 80 mV 2. Translate this number to a whole decimal number (80 mV ÷ 2.5 µV) = 32000 3. Convert this number to binary = 111 1101 0000 0000 4. Complement the binary result = 000 0010 1111 1111 5. Add '1' to the complement to create the twos complement result = 000 0011 0000 0000 6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h Full-scale range = 81.9175 mV (hexadecimal = 7FFF); LSB-weight = 2.5 μV/bit. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SIGN SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bus Voltage Register 02h (Read-Only) (1) The Bus Voltage Register stores the most recent, fully-averaged input bus voltage measurement, VBUS, represented by the LSB-weighted magnitude of that value. Full-scale range = 40.96 V (hexadecimal = 7FFF); LSB-weight = 1.25 mV/bit. However, do not apply more than 36 V to the input. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME — BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1) D15 is always zero because bus voltage can only be positive. Power Register 03h (Read-Only) The Power Register stores the product of the most recent current and bus voltage values, represented by the LSB-weighted magnitude of that calculation. The Power_LSB is internally programmed to equal 25 times the programmed value of the Current_LSB. The Power Register records power by multiplying the decimal values of the Current Register and the Bus Voltage Register and dividing by a scale-factor, according to Equation 23. LSB-weight = Power_LSB. If measurement averaging is enabled, this register displays the final averaged value. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Current Register 04h (Read-Only) The Current Register stores the most recent input current calculation, represented by the LSB-weighted magnitude of that calculation. The Current Register records current by multiplying the decimal values of the Shunt Voltage Register and the Calibration Register and dividing by a scale-factor, according to Equation 22. LSB-weight = Current_LSB. If measurement averaging is enabled, this register displays the final averaged value. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Calibration Register 05h (Read/Write) This register provides the TPS2482 and TPS2483 with the value of the shunt resistor which generates the measured differential voltage combined with the resolution of the Current Register and internal scaling. The Current_LSB and Power_LSB are set by the programming of this register. This register is also suitable for use in overall system calibration. See the Configure/Measure/Calculate Example for additional information on programming the Calibration Register. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME — FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mask/Enable Register 06h (Read/Write) The Mask/Enable Register selects the function that is enabled to control the ALERT pin, as well as how that pin functions. If multiple functions are enabled, the highest significant bit position Alert Function (D15-D11) takes priority and responds to the Alert Limit Register. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME SOL SUL BOL BUL POL CNVR — — — — — AFF CVRF OVF APOL LEN POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL: Shunt Voltage Over-Voltage Bit 15 Setting this bit high configures the ALERT pin to be asserted when the Shunt Voltage Register exceeds the value in the Alert Limit Register. SUL: Shunt Voltage Under-Voltage Bit 14 Setting this bit high configures the ALERT pin to be asserted when the Shunt Voltage Register drops below the value in the Alert Limit Register. BOL: Bus Voltage Over-Voltage Bit 13 Setting this bit high configures the ALERT pin to be asserted when the Bus Voltage Register exceeds the value in the Alert Limit Register. BUL: Bus Voltage Under-Voltage Bit 12 Setting this bit high configures the ALERT pin to be asserted when the Bus Voltage Register drops below the value in the Alert Limit Register. POL: Power Over-Limit Bit 11 Setting this bit high configures the ALERT pin to be asserted when the Power Register exceeds the value in the Alert Limit Register. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 43 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com CNVR: Conversion Ready Bit 10 Setting this bit high configures the ALERT pin to be asserted (independently of any Alert Function) when the Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready for the next conversion. AFF: Alert Function Flag Bit 4 While only one Alert Function can be monitored at the ALERT pin at a time, the Conversion Ready can also be simultaneously enabled to assert the ALERT pin. Reading the Alert Function Flag following an Alert allows the user to determine if the Alert Function was the source of the Alert. When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag clears only when the Mask/Enable Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag is cleared following the next conversion that does not result in an Alert condition. CVRF: Conversion Ready Flag Bit 3 Although the TPS2482 and TPS2483 can be read at any time, and the data from the last conversion is available, the Conversion Ready bit is provided to help coordinate one-shot or triggered conversions. The Conversion bit is set after all conversions, averaging, and multiplications are complete. Conversion Ready clears under the following conditions: 1.) Writing to the Configuration Register (except for Power-Down or Disable selections) 2.) Reading the Mask/Enable Register OVF: Math Overflow Flag Bit 2 This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid. This bit is cleared by the next operation which does not result in an overflow error. APOL: Alert Polarity bit; sets the ALERT pin logic polarity. Bit 1 1 = Inverted (active-high open-drain) 0 = Normal (active-low open-drain) (POR1 default) LEN: Alert Latch Enable bit; configures the latching feature of the ALERT pin and Alert Function Flag bit. Bit 0 1 = Latch enabled 0 = Transparent (POR1 default) When the Alert Latch Enable bit is cleared to Transparent mode, the ALERT pin and Alert Function Flag bit will automatically reset to their idle states when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the ALERT pin and Alert Function Flag bit will remain active following a fault until the Mask/Enable Register has been read. Alert Limit Register 07h (Read/Write) The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register to determine if a limit has been exceeded. BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME AUL15 AUL14 AUL13 AUL12 AUL11 AUL10 AUL9 AUL8 AUL7 AUL6 AUL5 AUL4 AUL3 AUL2 AUL1 AUL0 POR1 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SERIAL-BUS OVERVIEW The TPS2482 and TPS2483 serial-bus offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another. The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the TPS2482 and TPS2483 to the bus. Both SCL and SDA are open-drain connections. The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates START and STOP conditions. 44 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA low. Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit (slave generated). During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition. Once all data have been transferred, the master generates a stop condition, indicated by pulling SDA from low to high while SCL is high. The TPS2482 and TPS2483 includes a 28-ms timeout on its interface to prevent locking up the bus. Serial-Bus Address To communicate with the TPS2482 and TPS2483, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation. The TPS2482 and TPS2483 has two address pins, A0 and A1. Table 8 describes the pin logic levels for each of the 16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any activity on the interface occurs. Table 8. TPS2482 and TPS2483 Address Pin Connections and Corresponding Slave Addresses A1 A0 SLAVE ADDRESS GND GND 1000000 GND VS 1000001 GND SDA 1000010 GND SCL 1000011 VS GND 1000100 VS VS 1000101 VS SDA 1000110 VS SCL 1000111 SDA GND 1001000 SDA VS 1001001 SDA SDA 1001010 SDA SCL 1001011 SCL GND 1001100 SCL VS 1001101 SCL SDA 1001110 SCL SCL 1001111 Serial-Bus Interface The TPS2482 and TPS2483 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. While there is spike suppression integrated into the digital I/O lines, proper layout should be used to minimize the amount of coupling into the communication lines. This noise introduction could occur from capacitively coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielding communication lines in general is recommended to reduce to possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands. The TPS2482 and TPS2483 supports the transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 3.4 MHz) modes. All data bytes are transmitted most significant byte first. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 45 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com WRITING TO/READING FROM THE TPS2482 and TPS2483 Accessing a specific register on the TPS2482 and TPS2483 is accomplished by writing the appropriate value to the register pointer. Refer to Table 3 for a complete list of registers and corresponding addresses. The value for the register pointer (as shown in Figure 46) is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TPS2482 and TPS2483 requires a value for the register pointer. Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit low. The TPS2482 and TPS2483 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register which data will be written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The TPS2482 and TPS2483 acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop condition. When reading from the TPS2482 and TPS2483, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register pointer byte. No additional data are required. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a NotAcknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the TPS2482 and TPS2483 retain the register pointer value until it is changed by the next write operation. Figure 43 and Figure 44 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte. (1) The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 8. Figure 43. Timing Diagram for Write Word Format (1) The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 8. (2) Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 23. (3) ACK by Master can also be sent. Figure 44. Timing Diagram for Read Word Format 46 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 Figure 45 shows the timing diagram for the SMBus Alert Response operation. Figure 46 illustrates a typical register pointer configuration. (1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 8. Figure 45. Timing Diagram for SMBus ALERT (1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 8. Figure 46. Typical Register Pointer Set Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 47 TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com High-Speed I2C Mode When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The TPS2482 and TPS2483 do not acknowledge the HS master code, but does recognize it and switches its internal filters to support 3.4 MHz operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 MHz are allowed. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the TPS2482 and TPS2483 to support the F/S mode. t(LOW) tF tR t(HDSTA) SCL t(HDSTA) t(HIGH) t(SUSTO) t(SUSTA) t(HDDAT) t(SUDAT) SDA t(BUF) P S S P Figure 47. Bus Timing Diagram Bus Timing Diagram Definitions FAST MODE PARAMETER HIGH-SPEED MODE MIN MAX MIN MAX UNITS SCL operating frequency f(SCL) 0.001 0.4 0.001 3.4 MHz Bus free time between STOP and START conditions t(BUF) 600 160 ns Hold time after repeated START condition. After this period, the first clock is generated. t(HDSTA) 100 100 ns Repeated start condition setup time t(SUSTA) 100 100 ns STOP condition setup time t(SUSTO) 100 100 ns Data hold time t(HDDAT) 0 0 ns Data setup time t(SUDAT) 100 10 ns SCL clock low period t(LOW) 1300 160 ns SCL clock high period t(HIGH) 600 60 Clock/data fall time tF Clock/data rise time Clock/data rise time for SCLK ≤ 100 kHz ns 300 160 ns tR 300 160 ns tR 1000 ns SMBus Alert Response The TPS2482 and TPS2483 are designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides a quick fault identification for simple slave devices. When an Alert occurs, the master can broadcast the Alert Response slave address (0001 100) with the Read/Write bit set high, as seen in Figure 45. Following this Alert Response, any slave devices that generated an Alert will identify themselves by acknowledging the Alert Response and sending their respective address on the bus. The Alert Response can activate several different slave devices simultaneously, similar to the I2C General Call. If more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an Acknowledge and continues to hold the ALERT line low until the interrupt is cleared. spacer 48 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 TPS2482 TPS2483 www.ti.com SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 REVISION HISTORY Changes from Original (December 2012) to Revision A • Page Changed Shunt offset voltage, RTI vs Temperature TYP value From: 0.02 To: 0.1 and the MAX value From: 0.1 To: 0.4 ......................................................................................................................................................................................... 5 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 49 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2482PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TPS2482 TPS2482PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TPS2482 TPS2483PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TPS2483 TPS2483PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TPS2483 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of