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TPS254900-Q1
SLUSCO9A – SEPTEMBER 2016 – REVISED OCTOBER 2016
TPS254900-Q1 Automotive USB Host Charger With Short-to-VBATT Protection
1 Features
•
1
•
•
•
•
•
•
•
•
The TPS254900-Q1 45-mΩ power switch has two
selectable, adjustable current limits that support port
power management by changing to a lower current
limit when adjacent ports are experiencing heavy
loads. This is important in systems with multiple ports
and upstream power supplies with limited capacity.
AEC-Q100 Qualified With the Following Results:
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C5
4.5-V to 6.5-V Input Operating Range
Integrated 45-mΩ (typ.) High-Side MOSFET
3-A Maximum Continuous Output Current
VBUS ±5% Cable Compensation Accuracy at
Connector
Supports USB BC 1.2 CDP and SDP Modes
Short-to-Battery Protection on OUT, DP_IN, and
DM_IN Pins
DP_IN and DM_IN IEC 61000-4-2 Rated
– ±8-kV Contact and ±15-kV Air Discharge
20-Pin QFN (3-mm × 4-mm) Package
The TPS254900-Q1 has a current-sense output that
is able to control an upstream supply, which allows it
to maintain 5 V at the USB port even with heavy
charging currents. This feature is important in
systems with long USB cables where significant
voltage drops can occur with fast-charging portable
devices.
A current monitor allows a system to monitor the load
current in real time by monitoring the IMON voltage.
The current monitor is very useful and can be used
for dynamic port-power management.
The TPS254900-Q1 device also provides ESD
protection capability per IEC 61000-4-2, level 4 on
DP_IN and DM_IN.
2 Applications
•
•
Automotive USB Charging Ports (Host and Hubs)
Automotive USB Protection
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
3 Description
TPS254900-Q1
The TPS254900-Q1 device is a USB charging-port
controller and power switch with short-to-battery
protection. This feature provides protection on OUT,
DM_IN and DP_IN. These three pins withstand
voltage up to 18 V. The internal MOSFET turns off
quickly when the short-to-battery condition occurs.
Rapid turnoff is very important to protect the
upstream dc-dc converter, processor, or hub data
lines.
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
WQFN (20)
3.00 mm × 4.00 mm
10 µF
DM_OUT
DP_OUT
EN
EN
VBUS
OUT
DM_IN
D–
DP_IN
D+
5.1 kΩ
FAULT
FAULT
STATUS
BIAS
CTL1
Mode
Select I/O
SMAJ18
STATUS
GND
2.2 µF
CTL2
OVP_SEL
CS
IMON
2.55 kΩ
ADC
ILIM_LO
ILIM_HI
GND
19.1 kΩ
Logic I/O
Upstream DC-DC
80.6 kΩ
100 kΩ
100 kΩ
100 kΩ
IN
To Host
Controller
USB Connector
5V
TPS254900-Q1
SMAJ18
0.1 µF
10 µF
Schematic
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS254900-Q1
SLUSCO9A – SEPTEMBER 2016 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 23
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application ................................................. 26
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
Changes from Original (September 2016) to Revision A
•
2
Page
Changed data sheet from PRODUCT PREVIEW to PRODUCTION DATA .......................................................................... 1
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SLUSCO9A – SEPTEMBER 2016 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
ILIM_HI
ILIM_LO
FAULT
STATUS
20
19
18
17
RVC Package
20-Pin WQFN
Top View
IMON
1
16
OUT
IN
2
15
OUT
IN
3
14
DM_IN
DM_OUT
4
13
DP_IN
DP_OUT
5
12
BIAS
CS
6
11
GND
Thermal
10
OVP_SEL
8
9
CTL2
CTL1
EN
7
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
Used for IEC protection. Typically, connect a 2.2-µF capacitor and a transient-voltage
suppressor (TVS) to ground and 5.1 kΩ to OUT.
BIAS
12
PWR
CS
6
O
Linear cable compensation current. Connect to divider resistor of front-end dc-dc converter.
CTL1
8
I
Logic-level control input for controlling the charging mode and the signal switches; see the
Device Truth Table (TT).
CTL2
9
I
Logic-level control input for controlling the charging mode and the signal switches; see the
Device Truth Table (TT).
DM_IN
14
I/O
D– data line to downstream connector
DM_OUT
4
I/O
D– data line to upstream USB host controller
DP_IN
13
I/O
D+ data line to downstream connector
DP_OUT
5
I/O
D+ data line to upstream USB host controller
EN
7
I
Logic-level control input for turning the power and signal switches on or off. When EN is low,
the device is disabled, and the signal and power switches are OFF.
FAULT
18
O
Active-low, open-drain output, asserted during overtemperature, overcurrent, and
overvoltage conditions.
GND
11
—
Ground connection; should be connected externally to the thermal pad.
ILIM_HI
20
I
External resistor used to set the high current-limit threshold.
ILIM_LO
19
I
External resistor used to set the low current-limit threshold and the load-detection current
threshold.
IMON
1
O
This pin sources a scaled-down ratio of current through the internal FET. A resistor from this
pin to GND converts current to proportional voltage; used as an analog current monitor.
2,3
PWR
Input supply voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close
to the IC as possible.
15,16
PWR
Power-switch output
OVP_SEL
10
I
Logic-level control input for choosing the OUT overvoltage threshold. When OVP_SEL is low,
V(OV_OUT_LOW) is active. When OVP_SEL is high, V(OV_OUT_HIGH) is active.
STATUS
17
O
Active-low open-drain output, asserted in load-detect conditions
Thermal pad
—
—
Thermal pad on the bottom of the package
IN
OUT
(1)
I = Input, O = Output, I/O = Input and output, PWR = Power
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SLUSCO9A – SEPTEMBER 2016 – REVISED OCTOBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
Voltages are with respect to GND unless otherwise noted (1)
Voltage range
Continuous current
ISRC
Continuous output source
current
ISNK
Continuous output sink current
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
MIN
MAX
CS, CTL1, CTL2, EN, FAULT, ILIM_HI, ILIM_LO, IN,
IMON, OVP_SEL, STATUS
–0.3
7
DM_OUT, DP_OUT
–0.3
5.7
BIAS, DM_IN, DP_IN, OUT
–0.3
18
DM_IN to DM_OUT or DP_IN to DP_OUT
–100
100
OUT
Internally limited
ILIM_HI, ILIM_LO, IMON
Internally limited
V
mA
A
FAULT, STATUS
CS
UNIT
25
mA
–40
Internally limited
°C
–65
150
°C
Internally limited
A
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
Electrostatic
discharge
V(ESD)
(1)
±2 000
±750 (3)
Charged-device model (CDM), per AEC Q100-011
IEC 61000-4-2 contact discharge, DP_IN and DM_IN
(4)
V
±8 000
IEC 61000-4-2 air discharge, DP_IN and DM_IN (4)
(1)
(2)
(3)
(4)
UNIT
(2)
±15 000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The passing level per AEC-Q100 Classification H2.
The passing level per AEC-Q100 Classification C5
Surges per IEC 61000-4-2, level 4, 1999 applied from DP_IN and DM_IN to output ground of the TPS254900Q1EVM-817 (SLUUBI0)
evaluation module.
6.3 Recommended Operating Conditions
Voltages are with respect to GND unless otherwise noted.
MIN
V(IN)
Supply voltage
Input voltage
I(OUT)
Output continuous current
Continuous output sink current
IN
NOM
MAX
UNIT
4.5
6.5
V
CTL1, CTL2, EN, OVP_SEL
0
6.5
V
DM_IN, DM_OUT, DP_IN, DP_OUT
0
3.6
V
3
A
–30
30
mA
OUT (–40°C ≤ TA ≤ 85°C)
DM_IN to DM_OUT or DP_IN to DP_OUT
10
mA
R(ILIM_xx)
Current-limit-set resistors
14.3
1000
kΩ
TJ
Operating junction temperature
–40
125
°C
4
FAULT, STATUS
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SLUSCO9A – SEPTEMBER 2016 – REVISED OCTOBER 2016
6.4 Thermal Information
TPS254900-Q1
THERMAL METRIC (1)
RVC (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
37.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.9
°C/W
RθJB
Junction-to-board thermal resistance
11.9
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
11.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(CTL1) = V(CTL2) = V(IN), R(FAULT) = R(STATUS) =
10 kΩ, R(IMON) = 2.55 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C.
All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ = 25°C
45
55
–40°C ≤ TJ ≤ 85°C
45
69
–40°C ≤TJ ≤ 125°C
45
77
0.01
2
µA
400
500
630
Ω
Input pin rising logic
threshold voltage
1
1.35
2
V
Input pin falling logic
threshold voltage
0.85
1.15
1.65
V
OUT – POWER SWITCH
rDS(on)
Ilkg
On-resistance (1)
Reverse leakage current
VOUT = 6.5 V, VIN = VEN = 0 V, –40°C ≤ TJ ≤ 85°C,
measure I(IN)
mΩ
OUT – DISCHARGE
R(DCHG)
Discharge resistance
(mode change)
CTL1, CTL2, EN, OVP_SEL INPUTS
Hysteresis (2)
Input current
200
Pin voltage = 0 V or 6.5 V
–1
mV
1
µA
CURRENT LIMIT
OUT short-circuit current
limit
IOS
R(ILIM_LO) = 210 kΩ
190
240
R(ILIM_LO) = 80.6 kΩ
555
620
290
680
R(ILIM_LO) = 21.5 kΩ
2145
2300
2460
R(ILIM_LO) = 19.1 kΩ
2420
2590
2760
R(ILIM_HI) = 18.2 kΩ
2545
2720
2895
R(ILIM_HI) = 14.3 kΩ
3240
3455
3670
R(ILIM_HI) shorted to GND
5000
6500
8000
V(EN) = 0 V, V(OUT) = 0 V, –40°C ≤ TJ ≤ 85°C, no
5.1-kΩ resistor (open) between BIAS and OUT
0.1
5
SDP mode (CTL1, CTL2 = 0, 1)
170
250
CDP mode (CTL1, CTL2 = 1, 1)
200
280
Client mode (CTL1, CTL2 = 0, 0)
120
210
mA
SUPPLY CURRENT
I(IN_OFF)
Disabled IN supply current
I(IN_ON)
Enabled IN supply current
(1)
(2)
µA
µA
Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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Electrical Characteristics (continued)
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(CTL1) = V(CTL2) = V(IN), R(FAULT) = R(STATUS) =
10 kΩ, R(IMON) = 2.55 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C.
All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.9
4.15
4.3
UNIT
UNDERVOLTAGE LOCKOUT, IN
V(UVLO)
UVLO threshold voltage
Hysteresis
(3)
IN rising
TJ = 25°C
100
V
mV
FAULT
Output low voltage
I(FAULT) = 1 mA
100
mV
Off-state leakage
V(FAULT) = 6.5 V
2
µA
Output low voltage
I(STATUS) = 1 mA
100
mV
Off-state leakage
V(STATUS) = 6.5 V
2
µA
STATUS
THERMAL SHUTDOWN
T(OTSD2)
Thermal shutdown
threshold
155
°C
T(OTSD1)
Thermal shutdown
threshold in current-limit
135
°C
Hysteresis
(3)
20
°C
LOAD DETECT (VCTL1 = VCTL2 = VIN)
IOUT load detection
threshold
I(LD)
R(ILIM_LO) = 80.6 kΩ, rising load current
585
Hysteresis (3)
650
715
50
mA
mA
DM_IN AND DP_IN OVERVOLTAGE PROTECTION
V(OV_Data)
Protection trip threshold
DP_IN and DM_IN rising
3.7
Hysteresis (3)
R(DCHG_Data)
Discharge resistor after
OVP(2)
3.9
4.15
100
DP_IN = DM_IN = 18 V, IN = 5 V or 0 V
200
DP_IN = DM_IN = 5 V, IN = 5 V
370
DP_IN = DM_IN = 5 V, IN = 0
390
V
mV
kΩ
OUT OVERVOLTAGE PROTECTION
V(OV_OUT_LOW)
Protection trip threshold
OUT rising
5.65
Hysteresis (3)
V(OV_OUT_HIGH)
Protection trip threshold
Hysteresis
R(DCHG_OUT)
OUT rising
6.6
(3)
Discharge resistor
6
6.35
90
6.95
V
mV
7.3
130
V
mV
OUT = 18 V, IN = 5 V
55
85
OUT = 18 V, IN = 0
80
120
kΩ
CABLE COMPENSATION
I(CS)
Sink current
Load = 3 A, 2.5 V ≤ V(CS) ≤ 6.5 V
234
246
258
Load = 2.4 A, 2.5 V ≤ V(CS) ≤ 6.5 V
187
197
207
Load = 2.1 A, 2.5 V ≤ V(CS) ≤ 6.5 V
163
172
181
77
82
87
Load = 3 A, 0 ≤ V(IMON) ≤ 2.5 V
287
312
337
Load = 2.4 A, 0 ≤ V(IMON) ≤ 2.5 V
230
250
270
Load = 2.1 A, 0 ≤ V(IMON) ≤ 2.5 V
201
218
235
Load = 1 A, 0 ≤ V(IMON) ≤ 2.5 V
94
104
114
Load = 0.5 A, 0 ≤ V(IMON) ≤ 2.5 V
44
52
60
Load = 1 A, 2.5 V ≤ V(CS) ≤ 6.5 V
µA
CURRENT MONITOR OUTPUT (IMON)
I(IMON)
(3)
6
Source current
µA
This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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Electrical Characteristics (continued)
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(CTL1) = V(CTL2) = V(IN), R(FAULT) = R(STATUS) =
10 kΩ, R(IMON) = 2.55 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C.
All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) =
30 mA
3.2
6.5
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) =
–15 mA
3.8
7.6
0.05
0.15
0.05
0.15
UNIT
HIGH-BANDWIDTH ANALOG SWITCH
R(HS_ON)
|ΔR(HS_ON)|
DP and DM switch onresistance
Ω
V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) =
Switch resistance mismatch 30 mA
between DP and DM
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) =
channels
–15 mA
Ω
C(IO_OFF)
DP and DM switch off-state
capacitance (4)
VEN = 0 V, V(DP_IN) = V(DM_IN) = 0.3 V, Vac = 0.03
VPP , f = 1 MHz
8.8
pF
C(IO_ON)
DP and DM switch on-state
capacitance (4)
V(DP_IN) = V(DM_IN) = 0.3 V, Vac = 0.03 VPP, f = 1
MHz
10.9
pF
Off-state isolation(3)
V(EN) = 0 V, f = 250 MHz
8
dB
On-state cross-channel
isolation (4)
f = 250 MHz
30
dB
Ilkg(OFF)
Off-state leakage current
VEN = 0 V, V(DP_IN) = V (DM_IN) = 3.6 V, V(DP_OUT)
= V(DM_OUT) = 0 V, measure I(DP_OUT) and
I(DM_OUT)
0.1
BW
Bandwidth (–3 dB) (4)
R(L) = 50 Ω
940
1.5
µA
MHz
CHARGING DOWNSTREAM PORT DETECT
V(DM_SRC)
DM_IN CDP output voltage
V(DAT_REF)
DP_IN rising lower window
threshold for V(DM_SRC)
activation
V(DP_IN) = 0.6 V, –250 µA < I(DM_IN) < 0 µA
0.5
0.36
Hysteresis (4)
V(LGC_SRC)
DP_IN rising upper window
threshold for VDM_SRC
de-activation
V(LGC_SRC_HYS)
Hysteresis (4)
I(DP_SINK)
DP_IN sink current
(4)
0.6
0.7
V
0.4
V
50
0.8
mV
0.88
100
V(DP_IN) = 0.6 V
40
75
V
mV
100
µA
This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.6 Switching Characteristics
Unless otherwise noted –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(IN). R(FAULT) = R(STATUS)
= 10 kΩ, R(IMON) = 2.55 KΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at
25°C. All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω
1.05
1.75
3.1
UNIT
ms
0.27
0.47
0.82
ms
7.5
11
ms
2.7
5
ms
2
2.9
tr
OUT voltage rise time
tf
OUT voltage fall time
ton
OUT voltage turnon time
toff
OUT voltage turnoff time
t(DCHG_S)
Discharge hold time (mode
change)
Time V(OUT) < 0.7 V
t(IOS)
OUT short-circuit response
time (1)
V(IN) = 5 V, R(SHORT) = 50 mΩ
t(OC_OUT_FAULT)
OUT FAULT deglitch time
Bidirectional deglitch applicable to current-limit
condition only (no deglitch assertion for OTSD)
tpd
Analog switch propagation
delay (1)
V(IN) = 5 V
0.14
ns
t(SK)
Analog switch skew
between opposite
transitions of the same port
(tPHL – tPLH) (1)
V(IN) = 5 V
0.02
ns
t(LD_SET)
Load-detect set time
V(IN) = 5 V
120
210
280
t(LD_RESET)
Load-detect reset time
V(IN) = 5 V
1.8
3
4.2
t(OV_Data)
DP_IN and DM_IN
overvoltage protection
response time
t(OV_OUT)
OUT overvoltage protection
response time
t(OV_D_FAULT)
DP_IN and DM_IN FAULTasserted degltich time
11
16
23
ms
OUT FAULT-asserted
degltich time
11
16
23
ms
(1)
V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω
1.1
s
2
5.5
8.5
µs
11.5
ms
ms
s
5
µs
0.3
µs
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
6.7 Typical Characteristics
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
41
OUT Reverse Leakage Current (PA)
Power Switch On Resistance (m:)
70
65
60
55
50
45
40
35
30
-40
-25
-10
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
40.6
40.4
40.2
40
39.8
39.6
-40
-25
-10
D001
V(IN) = 5 V
V(OUT) = 5 V
Figure 1. Power Switch On-Resistance vs Temperature
8
40.8
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
D002
Measure I(OUT)
Figure 2. Reverse Leakage Current vs Temperature
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Typical Characteristics (continued)
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
570
100
OUT Discharge Resistance (:)
560
550
OUT Discharge Resistance (:)
VIN = 4.5 V
VIN = 5.0 V
VIN = 6.5 V
540
530
520
510
500
VIN = 5 V
VIN = 0 V
90
80
70
60
50
490
480
-40
-25
-10
5
20 35 50 65 80
Junction Temperature (qC)
95
40
-40
110 125
-25
A
3400
600
RILIM_HI = 21.5 K
RILIM_HI = 19.1 K
OUT Short Circuit Limit (mA)
OUT Short Circuit Limit (mA)
700
RILIM_HI = 18.2 K
RILIM_HI = 14.3 K
2800
2600
2400
2000
-40
-25
95
110 125
D004
500
400
300
200
100
2200
-10
5
20 35 50 65 80
Junction Temperature (qC)
95
RILIM_LO = 210 k:
RILIM_LO = 80.6 k:
0
-40
110 125
-25
-10
5
D005
V(IN) = 5 V
20 35 50 65 80
Junction Temperature (qC)
95
110 125
D006
V(IN) = 5 V
Figure 5. OUT Short-Circuit Current Limit vs Temperature I
Figure 6. OUT Short-Circuit Current Limit vs Temperature II
6
240
4
220
IIN_ON (PA)
IIN_OFF (PA)
20 35 50 65 80
Junction Temperature (qC)
Figure 4. OUT Discharge Resistance (OVP) vs Temperature
3600
3000
5
A
Figure 3. OUT Discharge Resistance (Mode Change) vs
Temperature
3200
-10
D003
2
200
180
0
VIN = 4.5 V
VIN = 5 V
VIN = 6.5 V
VIN = 4.5 V
VIN = 5 V
VIN = 6.5 V
-2
-40
-25
-10
CTL1 = 1
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
160
-40
-25
-10
D007
CTL2 = 1
CTL1 = 1
Figure 7. Disabled IN Supply Current vs Temperature
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
D008
CTL2 = 1
Figure 8. Enabled IN Supply Current – CDP (11) vs
Temperature
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Typical Characteristics (continued)
660
4.2
650
4.1
DP_IN Over-voltage
Protection Threshold (V)
Current (PA)
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
640
630
620
610
4
3.9
3.8
3.7
LLD IOUT Rising Load Detect Threshold
IOS IOUT Short Circuit Current Limit
600
-40
-25
-10
5
V(IN) = 5 V
20 35 50 65 80
Junction Temperature (qC)
95
3.6
-40
110 125
R(ILIM_LO) = 80.6 kΩ
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
D012
Figure 10. DP_IN Overvoltage Protection Threshold vs
Temperature
7.3
300
7.2
250
7.1
ICS (PA)
200
7
6.9
150
100
6.8
50
6.7
IOUT = 1 A
IOUT = 2.1 A
6.6
-40
-25
-10
5
20 35 50 65 80
Junction Temperature (qC)
95
0
-40 -25 -10
110 125
5
V(IN) = 5 V
Figure 11. OUT Overvoltage Protection Threshold vs
Temperature
IOUT = 2.4 A
IOUT = 3 A
20 35 50 65 80 95 110 125 140
Junction Temperature (qC)
D016
D014
V(IN) = 5 V
V(CS) = 25 V
Figure 12. I(CS) vs Temperature
300
340
250
320
300
ICS (PA)
200
ICS (PA)
-10
V(IN) = 5 V
Figure 9. I(OUT) Rising Load-Detect Threshold and OUT
Short-Circuit Limit vs Temperature
DP_IN Over-voltage Protection Threshold (V)
-25
D011
150
IOUT = 2.1 A
280
IOT = 2.4 A
IOUT = 3 A
260
100
240
50
IOUT = 1 A
IOUT = 2.1 A
0
2.5
3
3.5
220
IOUT = 2.4 A
IOUT = 3 A
4
4.5
5
5.5
Junction Temperature (qC)
VIN = 6.5 V
6
6.5
200
-40
-25
VIN = 5 V
Figure 13. I(CS) vs V(CS) Voltage
10
-10
D017
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20 35 50 65 80
Junction Temperature (qC)
95
110 125
D018
V(IMON) = 25 V
Figure 14. I(IMON) vs Temperature
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Typical Characteristics (continued)
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
320
300
ICS (PA)
280
IOUT = 2.1 A
IOUT = 2.4 A
IOUT = 3 A
260
240
220
200
180
0
0.5
1
1.5
VCS Voltage (V)
2
2.5
D020
VIN = 4.5 V
Figure 15. I(IMON) vs V(CS) Voltage
Measured on EVM with 10-cm cable
Measured on EVM with 10-cm cable
Figure 16. Bypassing the TPS254900-Q1 Data Switch
Figure 17. Through the TPS254900-Q1 Data Switch
VEN
5 V/div
VOUT
2 V/div
IOUT
0.5 A/div
R(LOAD) = 5 Ω
C(LOAD) = 10 µF
t = 2 ms/div
R(LOAD) = 5 Ω
Figure 18. Turnon Response
C(LOAD) = 10 µF
t = 1 ms/div
Figure 19. Turnoff Response
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Typical Characteristics (continued)
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
R(ILIM_LO) = 80.6 kΩ
R(ILIM_HI) = 19.1 kΩ
t = 4 ms/div
Figure 21. Enable Into Short (CDP) – Thermal Cycling
Figure 20. Enable Into Short (SDP)
R(ILIM_LO) = 80.6 kΩ
R(ILIM_HI) = 19.1 kΩ
t = 2 ms/div
Figure 22. Short Circuit to No Load (SDP)
R(ILIM_HI) = 19.1 kΩ
R(short) = 50 mΩ
t = 2 ms/div
t = 4 ms/div
Figure 23. Short Circuit to No Load (CDP)
R(ILIM_LO) = 80.6 kΩ
t = 100 ms/div
Figure 25. Load-Detection Set Time
Figure 24. Hot Short
12
t = 4 ms/div
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Typical Characteristics (continued)
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
R(ILIM_LO) = 80.6 kΩ
t = 1 s/div
t = 4 ms/div
Figure 26. Load-Detection Reset Time
t = 100 ms/div
Figure 27. OUT Short to Battery
t = 4 ms/div
Figure 28. OUT Short-to-Battery Recovery
R(BIAS) = 5.1 kΩ
Figure 29. DP_IN Short to Battery
t = 100 ms/div
Figure 30. DP_IN Short-to-Battery Recovery
R(BIAS) = 5.1 kΩ
t = 4 ms/div
Figure 31. DP_IN Short to VBUS
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Typical Characteristics (continued)
TA = 25°C, V(IN) = 5 V, V(EN) = 5 V, V(CTL1) = V(CTL2) = 5 V, FAULT and STATUS connect to V(IN) via a 10-kΩ pullup resistor
(unless stated otherwise)
R(BIAS) = 5.1 kΩ
t = 200 ms/div
Figure 32. DP_IN Short-to-VBUS and Recovery
Figure 33. Data Transmission Characteristics vs Frequency
Figure 34. Off-State Data-Switch Isolation vs Frequency
14
Figure 35. On-State Cross-Channel Isolation vs Frequency
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7 Parameter Measurement Information
10 cm AWG18
0.5 m AWG28
Manually Hot-short
0.5 m AWG22
ICABLE
0.5 m AWG28
18 V
TPS254900-Q1
LMR14030
DC Power Supply
27 mF
35 V
DM_IN
DP_IN
Voltage Test Point
OUT
5V
GND
GND
PWR817A
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Figure 36. Short-to-Battery System Test Setup
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8 Detailed Description
8.1 Overview
The TPS254900-Q1 device is a USB charging controller and power switch which integrates D+ and D– short-tobattery protection, cable compensation, current monitor (IMON), and IEC ESD protection suitable for automotive
USB charging and USB port protection applications.
The integrated power distribution switch uses N-channel MOSFETs suitable for applications where short circuits
or heavy capacitive loads will be encountered. The device allows the user to adjust the current-limit thresholds
using external resistors. The device enters constant-current mode when the load exceeds the current-limit
threshold.
The TPS254900-Q1 device provides VBUS, D+, and D– short-to-battery protection. This protects the upstream
voltage regulator, automotive processor, and hub when these pins are exposed to fault conditions.
The device also integrates CDP mode, defined in the BC1.2 specification, to enable up to 1.5-A fast charging of
most portable devices during data communication.
The TPS254900-Q1 device integrates a cable compensation (CS) feature to compensate for long-cable voltage
drop. This keeps the remote USB port output voltage constant to enhance the user experience under highcurrent charging conditions.
The TPS254900-Q1 device provides a current-monitor function (IMON) by connecting a resistor from the IMON
pin to GND to provide a positive voltage linearly with load current. This can be used for system power or dynamic
power management.
Additionally, the device provides ESD protection up to ±8 kV (contact discharge) and ±15 kV (air discharge) per
IEC 61000-4-2 on DP_IN and DM_IN.
16
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8.2 Functional Block Diagram
Current
Sense
CS
IN
ILIM_HI
OUT
Disable + UVLO +
Discharge + OVP
Current
Limit
ILIM_LO
OVP1
(Short to BAT)
OVP_SEL
Charge
Pump
8-ms
Deglitch
Driver
EN
GND
OC
UVLO
CS
FAULT
Thermal
Sense
´82 µA/A
OTSD
IEC ESD
Protection
OVP2/3 (Short to BAT)
IMON
´104 µA/A
BIAS
DM_IN
DM_OUT
DP_IN
DP_OUT
CDP
Detection
CTL1
STATUS
Logic
Control
CTL2
Discharge
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8.3 Feature Description
8.3.1 FAULT Response
The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault
detection includes overtemperature, overcurrent, or overvoltage on VBUS, DP_IN and DM_IN. Connect a 10-kΩ
pullup resistor from FAULT to IN.
Table 1 summarizes the conditions that generate a fault and actions taken by the device.
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Feature Description (continued)
Table 1. Fault Conditions
EVENT
CONDITION
ACTION
Overvoltage on the data lines
V(DP_IN) or V(DM_IN) > 3.9 V
The device immediately shuts off the USB data switches and
the internal power switch. The fault indicator asserts with a
16-ms deglitch, and deasserts without deglitch.
Overvoltage on V(OUT)
V(OUT) > 6 V or 6.95 V
The device immediately shuts off the internal power switch
and the USB data switches. The fault indicator asserts with a
16-ms deglitch and deasserts without deglitch.
Overcurrent on V(OUT)
I(OUT) > I(OS)
The device regulates switch current at I(OS) until thermal
cycling occurs. The fault indicator asserts and deasserts with
an 8-ms deglitch (the device does not assert FAULT on
overcurrent in SDP1 mode).
Overtemperature
TJ > OTSD2 in non-current-limited or TJ
> OTSD1 in current-limited mode.
The device immediately shuts off the internal power switch
and the USB data switches. The fault indicator asserts
immediately when the junction temperature exceeds OTSD2
or OTSD1 while in a current-limiting condition. The device
has a thermal hysteresis of 20°C.
8.3.2 Cable Compensation
V(OUT) (V)
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to
the load. In the vehicle from the voltage regulator 5-V output to the VPD_IN (input voltage of portable device), the
total resistance of power switch rDS(on) and cable resistance causes an IR drop at the PD input. So the charging
current of most portable devices is less than their expected maximum charging current.
V(OUT) With Compensation
5.x
V(DROP)
VBUS With Compensation
VBUS Without Compensation
0
0.5
1
1.5
2
2.5
3
I(OUT) (A)
Figure 37. Voltage Drop
TPS254900-Q1 device detects the load current and applies a proportional sink current that can be used to adjust
the output voltage of the upstream regulator to compensate for the IR drop in the charging path. The gain G(CS)
of the sink current proportional to load current is 82 µA/A.
18
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rDS(on)
V(OUT)
R(FA)
To Regulator OUT
IN
OUT
R3
C(COMP)
R1
R2
To Load
R(WIRE)
R(LOAD)
C(BUS)
R(FB)
FB
To Regulator
Resistor Divider
CS
R(G)
Figure 38. Cable Compensation Equivalent Circuit
8.3.2.1 Design Procedure
To start the procedure, the total resistance, including the power switch rDS(on) and wire resistance R(WIRE), must
be known.
1. Choose R(G) following the voltage-regulator feedback resistor-divider design guideline.
2. Calculate R(FA) according to Equation 1.
R FA = (r DS(on) + R (WIRE) ) / G (CS)
(1)
3. Calculate R(FB) according to Equation 2.
V(OUT)
R (FB) =
- R (G) - R (FA)
V(FB) / R (G)
(2)
4. C(COMP) in parallel with R(FA) is required to stablilize V(OUT) when C(BUS) is large. Start with C(COMP) ≥ 3 × G(CS)
× C(OUT), then adjust C(COMP) to optimize the load transient of the voltage regulator output. V(OUT) stability
should always be verified in the end application circuit.
8.3.3 D+ and D– Protection
D+ and D– protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins provide
ESD protection up to ±15 kV (air discharge) and ±8 kV (contact discharge) per IEC 61000-4-2 (see the ESD
Ratings section for test conditions).
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors, like the parasitic resistance
and inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and
humidity of the environment can cause some difference, so the IEC performance should always be verified in the
end-application circuit.
The IEC ESD performance of the TPS254900-Q1 device depends on the capacitance connected from BIAS to
GND. A 2.2-µF capacitor placed close to the BIAS pin is recommended. Connect the BIAS pin to OUT using a
5.1-kΩ resistor as a discharge path for the ESD stress.
OVP protection is provided for short-to-VBUS or short-to-battery conditions in the vehicle harness, preventing
damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9 V (typical),
the TPS254900-Q1 device quickly responds to block the high-voltage reverse connection to DP_OUT and
DM_OUT. Overcurrent short-to-GND protection for D+ and D– is provided by the upstream USB transceiver.
8.3.4 VBUS OVP Protection
The TPS254900-Q1 OUT pin can withstand up to 18 V. The internal MOSFET turns off quickly when a short-tobattery condition occurs.
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The TPS254900-Q1 device has two OVP thresholds; one is 6 V (typical) and the other is 6.95 V (typical). Set the
OVP threshold using the external OVP_SEL pin.
8.3.5 Output and D+ or D– Discharge
To allow a charging port to renegotiate current with a portable device, the TPS254900-Q1 device uses the OUT
discharge function. During mode change, the TPS254900-Q1 device turns off the power switch while discharging
OUT with a 500-Ω resistance, then turning back on the power switches to reassert the OUT voltage.
When an OVP condition occurs on DP_IN or DM_IN, the TPS254900-Q1 device enables an internal 200-kΩ
discharge resistance from DP_IN to ground and from DM_IN to ground. The analog switches are also turned off.
The TPS254900-Q1 device automatically disables the discharge paths and turns on the analog switches once
the OVP condition is removed.
When an OVP condition occurs on OUT, the TPS254900-Q1 device turns on an internal discharge path (see
Table 2 for the discharge resistance). The TPS254900-Q1 device automatically turns off the discharge path and
turns on the power switch once the OVP condition is removed.
Table 2. OUT Discharge Resistance
EN (1)
OVP (1)
OUT Discharge
Resistance (2)
0
0
0
—
0
0
1
80 kΩ
0
1
0
—
0
1
1
80 kΩ
1
0
0
500 Ω
1
0
1
500 Ω or 55 kΩ
1
1
0
—
1
1
1
55 kΩ
VIN
(1)
(2)
(1)
0 = inactive, 1 = active
— = no discharge resistance
8.3.6 Port Power Management (PPM)
PPM is the intelligent and dynamic allocation of power. PPM is for systems that have multiple charging ports but
cannot power them all simultaneously.
8.3.6.1 Benefits of PPM
The benefits of PPM include the following:
• Delivers better user experience
• Prevents overloading of system power supply
• Allows for dynamic power limits based on system state
• Allows every port potentially to be a high-power charging port
• Allows for smaller power-supply capacity because loading is controlled
8.3.6.2 PPM Details
All ports are allowed to broadcast high-current charging. The current limit is based on ILIM_HI. The system
monitors the STATUS pin to see when high-current loads are present. Once the allowed number of ports asserts
STATUS, the remaining ports are toggled to a non-charging port. The current limit of the non-charging port is
based on the ILIM_LO setting. The non-charging ports are automatically toggled back to charging ports when a
charging port deasserts STATUS.
STATUS asserts in a charging port when the load current is above ILIM_LO + 30 mA for 210 ms (typical).
STATUS deasserts in a charging port when the load current is below ILIM_LO – 20 mA for 3 seconds (typical).
20
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8.3.6.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
Figure 39 shows the implementation of the two charging ports with data communication, each with a
TPS254900-Q1 device and configured in CDP mode. In this example, the 5-V power supply for the two charging
ports is rated at less than 3.5 A. Both TPS254900-Q1 devices have R(ILIM) chosen to correspond to the low (1-A)
and high (2.4-A) current-limit setting for the port. In this implementation, the system can support only one of the
two ports at 2.4-A charging current, whereas the other port is set to the SDP1 mode and IOS corresponds to 1 A.
USB Charging
Port 1
TPS254900-Q1 Port 1
5V
IN
OUT
EN1
DM_IN
EN
DP_IN
FAULT1
FAULT
STATUS
ILIM_LO
100 kW
GND
RILIM_LO
CTL1
RILIM_HI
ILIM_HI
CTL2
USB Charging
Port 2
TPS254900-Q1 Port 2
IN
OUT
EN2
EN
FAULT2
DM_IN
DP_IN
FAULT
STATUS
ILIM_LO
ILIM_HI
RILIM_LO
GND
100 kW
RILIM_HI
CTL1
CTL2
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Figure 39. PPM Between CDP and SDP1
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8.3.7 Overcurrent Protection
When an overcurrent condition is detected, the device maintains a constant output current and reduces the
output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is
shorted before the device is enabled or before the application of V(IN). The TPS254900-Q1 device senses the
short and immediately switches into a constant-current output. In the second condition, a short or an overload
occurs while the device is enabled. At the instant the overload occurs, high currents flow for 1 to 2 μs (typical)
before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit
has responded. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.
The device remains off until the junction temperature cools approximately 20°C and then restarts. The device
continues to cycle on and off until the overcurrent condition is removed.
8.3.8 Undervoltage Lockout
The undervoltage-lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from
large current surges.
8.3.9 Thermal Sensing
Two independent thermal-sensing circuits protect the TPS254900-Q1 device if the temperature exceeds
recommended operating conditions. These circuits monitor the operating temperature of the power-distribution
switch and disable operation. The power dissipation in the package is proportional to the voltage drop across the
power switch, so the junction temperature rises during an overcurrent condition. The first thermal sensor turns off
the power switch when the die temperature exceeds 135ºC and the device is in current limit. The second thermal
sensor turns off the power switch when the die temperature exceeds 155ºC regardless of whether the power
switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on after the device
has cooled by approximately 20°C. The switch continues to cycle off and then on until the fault is removed. The
open-drain false-reporting output, FAULT, is asserted (low) during an overtemperature shutdown condition.
8.3.10 Current-Limit Setting
The TPS254900-Q1 has two independent current-limit settings that are each adjusted externally with a resistor.
The ILIM_HI setting is adjusted with R(ILIM_HI) connected between ILIM_HI and GND. The ILIM_LO setting is
adjusted with R(ILIM_LO) connected between ILIM_LO and GND. Consult the device truth table (Table 3) to see
when each current limit is used. Both settings have the same relation between the current limit and the adjusting
resistor.
The following equation calculates the value of resistor for adjusting the typical current limit:
48 687 V
I OS(nom) (mA) =
R (ILIM _ xx)0.9945 kW
(3)
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance
limits, both the tolerance of the TPS254900-Q1 current limit and the tolerance of the external adjusting resistor
must be taken into account. The following equations approximate the TPS254900-Q1 minimum and maximum
current limits to within a few milliamperes and are appropriate for design purposes. The equations do not
constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations
assume an ideal—no variation—external adjusting resistor. To take resistor tolerance into account, first
determine the minimum and maximum resistor values based on its tolerance specifications and use these values
in the equations. Because of the inverse relation between the current limit and the adjusting resistor, use the
maximum resistor value in the IOS(min) equation and the minimum resistor value in the IOS(max) equation.
46 464 V
I OS(min) (mA) =
- 32
R (ILIM _ xx)0.9974 kW
(4)
I OS(max) (mA) =
22
51 820 V
R (ILIM _ xx)0.9987 kW
+ 38
(5)
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4000
600
Current-Limit Threshold (mA)
3500
Current-Limit Threshold (mA)
IOS, Min
IOS, Max
IOS, Typ
3000
2500
2000
1500
1000
500
0
10
20
30
40
50
60
70
Adjusting Resistor (kW)
80
90
IOS, Min
IOS, Max
IOS, Typ
500
400
300
200
100
0
100
100
200
300
D022
Figure 40. Current-Limit Setting vs Adjusting Resistor I
400 500 600 700
Adjusting Resistor (kW)
800
900
1000
D023
Figure 41. Current-Limit Setting vs Adjusting Resistor II
The routing of the traces to the R(ILIM_xx) resistors should have a sufficiently low resistance so as not to affect the
current-limit accuracy. The ground connection for the R(ILIM_xx) resistors is also very important. The resistors must
reference back to the TPS254900-Q1 GND pin. Follow normal board layout practices to ensure that current flow
from other parts of the board does not impact the ground potential between the resistors and the TPS254900-Q1
GND pin.
8.4 Device Functional Modes
8.4.1 Device Truth Table (TT)
The device truth table (Table 3) lists all valid combinations for both control pins (CTL1 and CTL2), and the
corresponding charging mode. The TPS254900-Q1 device monitors the CTL inputs and transitions to the
charging mode to which it is commanded.
Table 3. Truth Table
(1)
(2)
(3)
CTL1
CTL2
CURRENT LIMIT
SELECTED
MODE
STATUS
for Load
Detect
CS FOR CABLE
COMPENSATION
IMON FOR
CURRENT
MONITOR
FAULT
REPORT
NOTES
0
0
N/A
Client
mode (1)
OFF
OFF
OFF
OFF
Power switch
is disabled,
only analog
switch is on.
0
1
ILIM_LO
SDP
OFF
ON
ON
ON
Standard
SDP
1
0
ILIM_LO
SDP1 (2)
OFF
ON
ON
ON (3)
1
1
ILIM_HI
CDP (2)
ON
ON
ON
ON
No OUT
discharge
between CDP
and SDP1 for
PPM
No 5.1-kΩ resistor from BIAS to OUT (open between the pins), or OUT still has 5-V voltage from an external downstream port; client
mode is still active.
No OUT discharge when changing from 10 to 11 or from 11 to 10.
A fault only trips OTSD, OUT, DP_IN, DM_IN, and OVP.
8.4.2 USB BC1.2 Specification Overview
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP)
• Charging downstream port (CDP)
• Dedicated charging port (DCP)
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BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable
equipment. Under this definition, CDP and DCP are defined as charging ports.
Table 4 lists the difference between these port types.
Table 4. Operating Modes Table
PORT TYPE
SUPPORTS USB2.0 COMMUNICATION
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
SDP (USB 2.0)
YES
0.5
SDP (USB 3.0)
YES
0.9
CDP
YES
1.5
DCP
NO
1.5
8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
An SDP is a traditional USB port that follows the USB 2.0 or USB 3.0 protocol. An SDP supplies a minimum of
500 mA per port for USB 2.0 and 900 mA per port for USB 3.0. USB 2.0 and USB 3.0 communication is
supported, and the host controller must be active to allow charging.
8.4.4 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows the USB BC1.2 specification and supplies a minimum of 1.5 A per port. A CDP
provides power and meets the USB 2.0 requirements for device enumeration. USB 2.0 communication is
supported, and the host controller must be active to allow charging. The difference between CDP and SDP is the
host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2
client device and allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During the first step, the portable equipment outputs a
nominal 0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the
connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device
detects the connection to a CDP if the D– voltage is greater than the nominal data-detect voltage of 0.3 V and
optionally less than 0.8 V.
The second step is necessary for portable equipment to determine whether the equipment is connected to a CDP
or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input on the
D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read remains
less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a DCP if
the data line being read is greater than the nominal data-detect voltage of 0.3 V.
The TPS254900-Q1 integrates CDP detection protocol, used at a downstream port as the CDP controller to
support CDP portable-device fast charge up to 1.5 A.
8.4.5 Client Mode
The TPS254900-Q1 device integrates client mode as shown in Figure 42. The internal power switch is OFF to
block current flow from OUT to IN, and the signal switches are ON. This mode can be used for software
upgrades from the USB port.
OUT
IN
OFF
DP_OUT
DP_IN
DM_OUT
DM_IN
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Figure 42. Client-Mode Equivalent Circuit
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Passing the IEC 61000-4-2 test for DP_IN and DM_IN requires connecting a discharge resistor to OUT during
USB 2.0 high-speed enumeration. In client mode, because the power switch is OFF, OUT must be 5 V so that
the device can work normally (usually powered by an external downstream USB port). If the OUT voltage is low,
the communication may not work properly.
8.4.6 High-Bandwidth Data-Line Switch
The D+ and D– data lines pass through the device to enable monitoring and handshaking while supporting the
charging operation. A wide-bandwidth signal switch allows data to pass through the device without corrupting
signal integrity. The data-line switches are turned on in any of the CDP, SDP or client operating modes. The EN
input must be at logic high for the data-line switches to be enabled.
•
•
•
NOTE
While in CDP mode, the data switches are ON, even during CDP handshaking.
The data switches are only for the USB-2.0 differential pair. In the case of a USB-3.0
host, the super-speed differential pairs must be routed directly to the USB connector
without passing through the TPS254900-Q1 device.
Data switches are OFF during OUT (VBUS) discharge.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS254900-Q1 device is a USB charging-port controller and power switch with cable compensation and
short-to-battery protection for VBUS, D+, and D–. The device is typically used for automotive USB port protection
and as a USB charging controller. The following design procedure can be used to select components for the
TPS254900-Q1. This section presents a simplified discussion of how to choose external components for VBUS,
D+, and D– short-to-battery protection. For cable-compensation design information, see the data sheet
(SLUSCE3) for the TPS2549-Q1 device, which has features and design considerations very similar to those of
the TPS254900-Q1 device.
9.2 Typical Application
100 kΩ
100 kΩ
100 kΩ
IN
To Host
Controller
SMAJ18
10 µF
1210
35 V
X7R
TPS254900-Q1
VBUS
OUT
DM_OUT
DP_OUT
DM_IN
D–
DP_IN
D+
5.1 kΩ
EN
EN
FAULT
GND
BIAS
SMAJ18
FAULT
USB Connector
5V
0.1 µF
10 µF
For an automotive USB charging port, the VBUS, D+, and D– pins are exposed and require a protection device.
The protection required includes VBUS overcurrent, D+ and D– ESD protection, and short-to-battery protection.
This charging-port device protects the upstream dc-dc converter (bus line) and automotive SOC or hub chips (D+
and D– data lines). An application schematic of this circuit with short-to-battery protection is shown in Figure 43.
2.2 µF
0805
50 V
X7R
STATUS
STATUS
CTL1
OVP_SEL
Logic I/O
Upstream DC-DC
Converter
ILIM_LO
ILIM_HI
CS
GND
ADC
80.6 kΩ
CTL2
19.1 kΩ
Mode
Select I/O
2.55 kΩ
IMON
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Figure 43. Typical Application Schematic: USB Port Charging With Cable Compensation
26
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
DESIGN PARAMETER
EXAMPLE VALUE
Battery voltage, V(BAT)
18 V
Short-circuit cable
0.5 m
9.2.2 Detailed Design Procedure
To
•
•
•
•
•
begin the design process, the designer must know the following:
The battery voltage
The short-circuit cable length
The maximum continuous output current for the charging port. The minimum current-limit setting of
TPS254900-Q1 device must be higher than this current.
The maximum output current of the upstream dc-dc converter. The maximum current-limit setting of
TPS254900-Q1 device must be lower than this current.
For cable compensation, the total resistance including power switch rDS(on), cable resistance, and connector
contact resistance must be specified.
9.2.2.1 Input Capacitance
Consider the following application situations when choosing the input capacitors.
For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed
as close as possible to the device for local noise decoupling.
During output short or hot plug-in of a capacitive load, high current flows through the TPS254900-Q1 device back
to the upstream dc-dc converter until the TPS254900-Q1 device responds (after t(IOS)). During this response time,
the TPS254900-Q1 input capacitance and the dc-dc converter output capacitance source current to keep VIN
above the UVLO of the TPS254900-Q1 device and any shared circuits. Size the input capacitance for the
expected transient conditions and keep the path between the TPS254900-Q1 device and the dc-dc converter
short to help minimize voltage drops.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power-bus inductance and input capacitance when the IN pin is in the highimpedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second
cause is due to the abrupt reduction of output short-circuit current when the TPS254900-Q1 device turns off and
energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for
example, a connection between the evaluation board and the bench power supply through long cables) may
require large input capacitance to prevent the voltage overshoot from exceeding the absolute-maximum voltage
of the device.
During the short-to-battery (EN = HIGH) condition, the input voltage follows the output voltage until OVP
protection is triggered (t(OV_OUT)). After the TPS254900-Q1 device responds and turns off the power switch, the
stored energy in the input inductance can cause ringing.
Based on the three situations described, 10-µF and 0.1-µF low-ESR ceramic capacitors, placed close to the
input, are recommended.
9.2.2.2 Output Capacitance
Consider the following application situations when choosing the output capacitors.
After an output short occurs, the TPS254900-Q1 device abruptly reduces the OUT current, and the energy stored
in the output power-bus inductance causes voltage undershoot and potentially reverse voltage as it discharges.
Applications with large output inductance (such as from a cable) benefit from the use of a high-value output
capacitor to control the voltage undershoot.
For USB port applications, because the VBUS pin is exposed to IEC61000-4-2 level-4 ESD, use a low-ESR
capacitance to protect OUT.
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The TPS254900-Q1 device is capable of handling up to 18-V battery voltage. When VBUS is shorted to the
battery, the LCR tank circuit formed can induce ringing. The peak voltage seen on the OUT pin depends on the
short-circuit cable length. The parasitic inductance and resistance varies with length, causing the damping factor
and peak voltage to differ. Longer cables with larger resistance reduce the peak current and peak voltage.
Consider high-voltage derating for the ceramic capacitor, because the peak voltage can be higher than twice the
battery voltage.
Based on the three situations described, a 10-µF, 35-V, X7R, 1210 low-ESR ceramic capacitor placed close to
OUT is recommended. If the battery voltage is 16 V and a 16-V transient voltage suppressor (TVS) is used, then
the capacitor voltage can be reduced to 25 V. Considering temperature variation, placing an additional 35-V
aluminum electrolytic capacitor can lower the peak voltage and make the system more robust.
9.2.2.3 BIAS Capacitance
The capacitance on the BIAS pin helps the IEC ESD performance on the DM_IN and DP_IN pins.
When a short to battery on DP_IN, DM_IN and/or OUT occurs, high voltage can be seen on the BIAS pin. Place
a 2.2-µF, 50-V, X7R, 0805, low-ESR ceramic capacitor close to the BIAS pin. The whole current path from BIAS
to GND should be as short as possible. Additionally, use a 5.1-kΩ discharge resistor from BIAS to OUT.
9.2.2.4 Output and BIAS TVS
The TPS254900-Q1 device can withstand high transient voltages due to LCR tank ringing, but in order to make
OUT, DP_IN, and DM_IN robust, place one TVS close to the OUT pin, and another TVS close to the BIAS pin.
When choosing the TVS, the reverse standoff voltage VR depends on the battery voltage (16 V or 18 V).
Considering the peak pulse power capability, a 400-W device is recommended such as an SMAJ16 for a 16-V
battery or an SMAJ18 for an 18-V battery.
9.2.3 Application Curves
VBAT = 14 V
t = 10 µs/div
VBAT = 18 V
Figure 44. Disabled, 25-V, 1206, X7R COUT Capacitor
Without SMAJ18
28
t = 10 µs/div
Figure 45. Disabled, 35-V, 1210, X7R COUT Capacitor
Without SMAJ18
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t = 10 µs/div
t = 10 µs/div
Figure 46. Disabled, 25-V, 1206, X7R COUT Capacitor With
SMAJ18, OUT Shorted to Battery
t = 10 µs/div
Figure 47. Disabled, 35-V, 1210, X7R COUT Capacitor With
SMAJ18, OUT Shorted to Battery
t = 10 µs/div
Figure 48. DC-DC Input Is Floating, OUT Shorted to Battery
t = 10 µs/div
Figure 49. Enabled With OVP_SEL = High, OUT Shorted to
Battery
RBIAS = 5.1 kΩ
Figure 50. Enabled With OVP_SEL = Low, OUT Shorted to
Battery
t = 2 µs/div
Figure 51. Disabled, DP_IN Shorted to Battery
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RBIAS = 5.1 kΩ
t = 2 µs/div
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R(BIAS) = 5.1 kΩ
Figure 52. DC-DC Input Is Floating, DP_IN Shorted to
Battery
t = 2 µs/div
R(DP_OUT) = 15 kΩ
Figure 53. Enabled, DP_IN Shorted to Battery
10 Power Supply Recommendations
The TPS254900-Q1 device is designed for a supply voltage range of 4.5 V ≤ VIN ≤ 6.5 V, with its power switch
used for protecting the upstream power supply when a fault such as overcurrent or short to ground occurs on the
USB port. Therefore, the power supply should be rated higher than the current-limit setting to avoid voltage drops
during overcurrent or short-circuit conditions.
11 Layout
11.1 Layout Guidelines
Layout best practices for the TPS254900-Q1 are listed as follows.
• Considerations for input and output power traces
– Make the power traces as short as possible.
– Make the power traces as wide as possible.
• Considerations for input-capacitor traces
– For all applications, 10-µF and 0.1-µF low-ESR ceramic capacitors are recommended, placed close to the
IN pin.
• The resistors attached to the ILIM_HI and ILIM_LO pins of the device have several requirements.
– It is recommended to use 1% low-temperature-coefficient resistors.
– The trace routing between these two pins and GND should be as short as possible to reduce parasitic
effects on current limit. These traces should not have any coupling to switching signals on the board.
• Locate all TPS254900-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup
resistors should be 100 kΩ.
– If a particular open-drain output is not used or needed in the system, tie it to GND.
• ESD considerations
– The TPS254900-Q1 device has built-in ESD protection for DP_IN and DM_IN. Keep trace lengths minimal
from the USB connector to the DP_IN and DM_IN pins on the TPS254900-Q1 device, and use minimal
vias along the traces.
– The capacitor on BIAS helps to improve the IEC ESD performance. A 2.2-µF capacitor should be placed
close to BIAS, and the current path from BIAS to GND across this capacitor should be as short as
possible. Do not use vias along the connection traces.
– A 10-µF output capacitor should be placed close to the OUT pin and TVS.
– See the ESD Protection Layout Guide (SLVA680) for additional information.
• TVS Considerations
– For OUT, a TVS like SMAJ18 should be placed near the OUT pin.
– For BIAS, a TVS like SMAJ18 should be placed close to the BIAS pin, but behind the 2.2-µF capacitor.
30
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Layout Guidelines (continued)
•
•
– The whole path from OUT to GND or BIAS to GND across the TVS should be as short as possible.
DP_IN, DM_IN, DP_OUT, and DM_OUT routing considerations
– Route these traces as microstrips with nominal differential impedance of 90 Ω.
– Minimize the use of vias on the high-speed data lines.
– Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance
discontinuities.
– For more USB 2.0 high-speed D+ and D– differential routing information, see the High Speed USB
Platform Design Guideline from Intel.
Thermal Considerations
– When properly mounted, the thermal-pad package provides significantly greater cooling ability than an
ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane
directly under the device. The thermal pad is at GND potential and can be connected using multiple vias
to inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase
heat sinking in higher-current applications. See the PowerPad™ Thermally Enhanced Package application
report (SLMA002) and PowerPAD™ Made Easy application brief (SLMA004) for more information on
using this thermal pad package.
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11.2 Layout Example
Top Layer Signal Trace
Top Layer Signal Ground Plane
Bottom Layer Signal Trace
Via to Bottom layer Signal Ground Plane
Via to Bottom layer Signal
IMON
17
18
x
1
16
2
15
OUT
Thermal
Pad
IN
3
x
14
DM_IN
x
DM_OUT
4
13
DP_OUT
5
12
BIAS
10
GND
9
xx
xx
xxxx
xxxx
xx
DP_IN
11
6
8
CS
7
xx
19
x
20
x
FAULT
ILIM_HI
ILMI_LO
STATUS
x
x
x
x
x
OVP_SEL
CTL2
CLT1
x
EN
x
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Figure 54. TPS254900-Q1 Layout Diagram
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
High Speed USB Platform Design Guidelines, Intel
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS254900IRVCRQ1
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
254900Q
TPS254900IRVCTQ1
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
254900Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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