TPS2553DDBVT

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 TPS255xD Precision Adjustable Current-Limited Power-Distribution Switches 1 Features 3 Description • • • • • • • The TPS2552D and TPS2553D power-distribution switches are intended for applications where precision current limiting is required or heavy capacitive loads and short circuits are encountered and provide up to 1.5 A of continuous load current. These devices offer a programmable current-limit threshold between 75 mA and 1.7 A (typ) via an external resistor. Current-limit accuracy as tight as ±6% can be achieved at the higher current-limit settings. The power-switch rise and fall times are controlled to minimize current surges during turn on/off. 1 • • • • • • • • Up to 1.5 A Maximum Load Current ±6% Current-Limit Accuracy at 1.7 A (Typ) Meets USB Current-Limiting Requirements Backwards Compatible with TPS2550/51 Adjustable Current Limit, 75 mA–1700 mA (Typ) Constant-Current (TPS2552D and TPS2553D) TPS2552D (Enable Low) and TPS2553D (Enable High) Fast Overcurrent Response - 2 μs (Typ) 85-mΩ High-Side MOSFET (DBV Package) Reverse Input-Output Voltage Protection Operating Range: 2.7 V to 6.5 V Built-in Soft-Start 15 kV ESD Protection per IEC 61000-4-2 (With External Capacitance) UL Listed – File No. E169910 and NEMKO IEC60950-1-am1 ed2.0 See the TI Switch Portfolio The TPS2552D/3D devices limit the output current to a safe level by using a constant-current mode when the output load exceeds the current-limit threshold. An internal reverse-voltage comparator disables the power-switch when the output voltage is driven higher than the input to protect devices on the input side of the switch. The FAULT output asserts low during overcurrent and reverse-voltage conditions. Device Information(1) 2 Applications • • • • USB Ports/Hubs Digital TV Set-Top Boxes VOIP Phones PART NUMBER PACKAGE BODY SIZE (NOM) TPS2552D SOT-23 (6) 2.90 mm × 1.60 mm TPS2553D SOT-23 (6) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic TPS2552D/53D 5V USB Input 0.1 mF USB Data IN OUT USB Port RFAULT 100 kW 120 mF Fault Signal Control Signal FAULT EN ILIM GND Power Pad RILIM 20 kW USB requirement only* *USB requirement that downstream facing ports are bypassed with at least 120 mF per hub 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 10 Application and Implementation........................ 17 10.1 Application Information.......................................... 17 10.2 Typical Applications .............................................. 17 11 Power Supply Recommendations ..................... 25 11.1 Self-Powered and Bus-Powered Hubs ................. 25 11.2 Low-Power Bus-Powered and High-Power BusPowered Functions .................................................. 25 11.3 Power Dissipation and Junction Temperature ...... 25 12 Layout................................................................... 26 12.1 Layout Guidelines ................................................. 26 12.2 Layout Example .................................................... 26 13 Device and Documentation Support ................. 27 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Parameter Measurement Information ................ 11 Detailed Description ............................................ 13 9.1 9.2 9.3 9.4 9.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 13 13 13 14 15 Device Support...................................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 27 27 14 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES September 2016 * Initial Release Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 5 Device Comparison Table Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 3 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com 6 Pin Configuration and Functions TPS2552D/3D DBV Package Top View 1 2 3 IN GND EN 6 5 4 OUT ILIM FAULT EN = Active Low for the TPS2552D EN = Active High for the TPS2553D Pin Functions PIN NAME TPS2552D TPS2553D I/O DESCRIPTION DBV DBV EN 3 – I Enable input, logic low turns on power switch EN – 3 I Enable input, logic high turns on power switch GND 2 2 IN 1 1 I Input voltage; connect a 0.1 μF or greater ceramic capacitor from IN to GND as close to the IC as possible. FAULT 4 4 O Active-low open-drain output, asserted during overcurrent, overtemperature, or reverse-voltage conditions. OUT 6 6 O Power-switch output ILIM 5 5 O External resistor used to set current-limit threshold; recommended 15 kΩ ≤ RILIM ≤ 232 kΩ. PowerPAD ™ – – 4 Ground connection; connect externally to PowerPAD Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect PowerPAD to GND pin externally. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) Voltage range on IN, OUT, EN , ILIM, FAULT Voltage range from IN to OUT IO Continuous output current (2) UNIT 7 V –7 7 V See the Thermal Information Continuous FAULT sink current 0 25 mA ILIM source current 0 1 mA –40 150 °C –65 150 °C Maximum junction temperature Tstg Storage temperature (1) MAX Internally Limited Continuous total power dissipation TJ MIN –0.3 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are referenced to GND unless otherwise noted. 7.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 IEC 61000-4-2 contact discharge (3) ±8000 IEC 61000-4-2 air-gap discharge (3) ±15000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Surges per EN61000-4-2. 1999 applied to output terminals of EVM. These are passing test levels, not failure threshold. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage, IN VEN Enable voltage VEN NOM MAX 2.7 6.5 TPS2552D 0 6.5 TPS2553D 0 6.5 0 6.5 VEN Enable voltage VIH High-level input voltage on EN VIL Low-level input voltage on EN IOUT Continuous output current, OUT 1.1 0.66 UNIT V V V V –40 °C ≤ TJ ≤ 125 °C 0 1.2 –40 °C ≤ TJ ≤ 105 °C 0 1.5 RILIM Current-limit threshold resistor range (nominal 1%) from ILIM to GND 15 232 KΩ IO Continuous FAULT sink current 0 10 mA Input de-coupling capacitance, IN to GND TJ (1) Operating virtual junction temperature (1) 0.1 A μF IOUT ≤ 1.2 A –40 125 IOUT ≤ 1.5 A –40 105 °C See "Dissipation Rating Table" and "Power Dissipation and Junction Temperature" sections for details on how to calculate maximum junction temperature for specific applications and packages. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 5 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com 7.4 Thermal Information TPS2552D THERMAL METRIC (1) TPS2553D DBV DBV 6 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 182.6 182.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.2 122.2 °C/W RθJB Junction-to-board thermal resistance 29.4 29.4 °C/W ψJT Junction-to-top characterization parameter 20.8 20.8 °C/W ψJB Junction-to-board characterization parameter 28.9 28.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 7.5 Electrical Characteristics over recommended operating conditions, VEN = VIN, RFAULT = 10 kΩ (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH DBV package, TJ = 25°C 85 DBV package, –40°C ≤TJ ≤125°C rDS(on) Static drain-source on-state resistance DRV package, TJ = 25°C 100 DRV package, –40°C ≤TJ ≤105°C Rise time, output tf Fall time, output mΩ 150 VIN = 6.5 V 1.1 VIN = 2.5 V 0.7 VIN = 6.5 V 115 140 DRV package, –40°C ≤TJ ≤125°C tr 95 135 CL = 1 μF, RL = 100 Ω, (see Figure 20) VIN = 2.5 V 1.5 1 ms 0.2 0.5 0.2 0.5 0.66 1.1 V –0.5 0.5 μA 3 ms 3 ms ENABLE INPUT EN OR EN Enable pin turn on/off threshold IEN Input current ton Turnon time toff Turnoff time VEN = 0 V or 6.5 V, VEN = 0 V or 6.5 V CL = 1 μF, RL = 100 Ω, (see Figure 20) CURRENT LIMIT RILIM = 15 kΩ RILIM = 20 kΩ Current-limit threshold (Maximum DC output current IOUT delivered to load) and Short-circuit current, OUT connected to GND IOS RILIM = 49.9 kΩ –40°C ≤TJ ≤105°C 1610 1700 1800 TJ = 25°C 1215 1295 1375 –40°C ≤TJ ≤125°C 1200 1295 1375 TJ = 25°C 490 520 550 –40°C ≤TJ ≤125°C 475 520 565 110 130 150 50 75 100 RILIM = 210 kΩ ILIM shorted to IN tIOS Response time to short circuit VIN = 5 V (see Figure 21) 2 mA μs REVERSE-VOLTAGE PROTECTION Reverse-voltage comparator trip point (VOUT – VIN) Time from reverse-voltage condition to MOSFET turn off VIN = 5 V 95 135 190 mV 3 5 7 ms SUPPLY CURRENT IIN_off Supply current, low-level output VIN = 6.5 V, No load on OUT, VEN = 0 V IIN_on Supply current, high-level output VIN = 6.5 V, No load on OUT IREV Reverse leakage current VOUT = 6.5 V, VIN = 0 V 0.1 1 μA RILIM = 20 kΩ 120 150 μA RILIM = 210 kΩ 100 130 μA TJ = 25 °C 0.01 1 μA 2.35 2.45 UNDERVOLTAGE LOCKOUT UVLO Low-level input voltage, IN Hysteresis, IN VIN rising TJ = 25 °C 25 V mV FAULT FLAG VOL Output low voltage, FAULT I/FAULT = 1 mA Off-state leakage V/FAULT = 6.5 V FAULT deglitch 180 mV 1 μA FAULT assertion or de-assertion due to overcurrent condition 5 7.5 10 ms FAULT assertion or de-assertion due to reverse-voltage condition 2 4 6 ms THERMAL SHUTDOWN Thermal shutdown threshold 155 °C Thermal shutdown threshold in current-limit 135 °C Hysteresis (1) 10 °C Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 7 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com 7.6 Typical Characteristics TPS2552D 10 mF VIN IN VOUT OUT RFAULT 10 kW 150 mF ILIM Fault Signal Control Signal FAULT RILIM GND EN Power Pad 8 Figure 1. Typical Characteristics Reference Schematic Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time Figure 4. Device Enabled into Short-Circuit Figure 5. Full-Load to Short-Circuit Transient Response Figure 6. Short-Circuit to Full-Load Recovery Response Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 Typical Characteristics (continued) Figure 7. No-Load to Short-Circuit Transient Response Figure 8. Short-Circuit to No-Load Recovery Response Figure 9. No Load to 1-Ω Transient Response Figure 10. 1-Ω to No Load Transient Response Figure 11. Reverse-Voltage Protection Response Figure 12. Reverse-Voltage Protection Recovery Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 9 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Typical Characteristics (continued) 0.40 2.40 RILIM = 20 kW RILIM = 20 kW 0.36 IIN - Supply Current, Output Disabled - mA UVLO - Undervoltage Lockout - V 2.39 2.38 2.37 UVLO Rising 2.36 2.35 2.34 UVLO Falling 2.33 2.32 0.32 0.28 0.24 0.16 0.12 0.08 VIN = 2.5 V 0.04 2.31 2.30 -50 0 50 TJ - Junction Temperature - °C 100 0 -50 150 Figure 13. UVLO – Undervoltage Lockout – V 135 0 50 TJ - Junction Temperature - °C 100 150 Figure 14. IIN – Supply Current, Output Disabled – μA 150 20 RILIM = 20 kW VIN = 6.5 V VIN = 5 V, 18 VIN = 5 V 120 RILIM = 20 kW, TA = 25°C 16 Current Limit Response - ms IIN - Supply Current, Output Enabled - mA VIN = 6.5 V 0.20 105 90 75 VIN = 2.5 V VIN = 3.3 V 60 45 14 12 10 8 6 30 4 15 2 0 -50 0 50 TJ - Junction Temperature - °C 100 150 0 0 1.5 Figure 15. IIN – Supply Current, Output Enabled – μA 6 1400 1300 1200 125 DRV Package IDS - Static Drain-Source Current - mA rDS(on) - Static Drain-Source On-State Resistance - mW 4.5 Figure 16. Current Limit Response – μs 150 100 DBV Package 75 50 25 TA = -40°C 1100 1000 TA = 25°C 900 TA = 125°C 800 700 600 500 400 300 VIN = 6.5 V, 200 RILIM = 20 kW 100 0 -50 0 0 50 TJ - Junction Temperature - °C 100 150 Figure 17. MOSFET rDS(on) Vs. Junction Temperature 10 3 Peak Current - A 0 100 200 300 400 500 600 VIN - VOUT - 100 mV/div 700 800 900 1000 Figure 18. Switch Current Vs. Drain-Source Voltage Across Switch Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 Typical Characteristics (continued) 150 140 IDS - Static Drain-Source Current - mA 130 120 TA = 25°C TA = -40°C 110 TA = 125°C 100 90 80 70 60 50 40 30 20 VIN = 6.5 V, 10 RILIM = 200 kW 0 0 100 200 300 400 500 600 VIN - VOUT - 100 mV/div 700 800 900 1000 Figure 19. Switch Current Vs. Drain-Source Voltage Across Switch 8 Parameter Measurement Information OUT tf tr CL RL 90% 90% VOUT 10% 10% TEST CIRCUIT VEN 50% 50% VEN ton VOUT toff toff ton 90% 50% 50% toff 90% VOUT 10% 10% VOLTAGE WAVEFORMS Figure 20. Test Circuit and Voltage Waveforms IOS IOUT tIOS Figure 21. Response Time to Short Circuit Waveform Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 11 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Parameter Measurement Information (continued) Decreasing Load Resistance VOUT Decreasing Load Resistance IOUT IOS Figure 22. Output Voltage Vs. Current-Limit Threshold 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 9 Detailed Description 9.1 Overview The TPS2552D and TPS2553D are current-limited, power-distribution switches using N-channel MOSFETs for applications where short circuits or heavy capacitive loads will be encountered and provide up to 1.5 A of continuous load current. These devices allow the user to program the current-limit threshold between 75 mA and 1.7 A (typ) via an external resistor. Additional device shutdown features include overtemperature protection and reverse-voltage protection. The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. The driver controls the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges and provides built-in soft-start functionality. There are two device families that handle overcurrent situations differently. The TPS255xD family enters constant-current mode when the load exceeds the current-limit threshold. 9.2 Functional Block Diagram - Reverse Voltage Comparator + IN OUT 4-ms Deglitch CS Current Sense Charge Pump Driver EN Current Limit (Note A) FAULT UVLO GND Thermal Sense 8-ms Deglitch ILIM Copyright © 2016, Texas Instruments Incorporated A. TPS255x parts enter constant current mode during current limit condition 9.3 Feature Description 9.3.1 Overcurrent Conditions The TPS2552D and TPS2553D respiond to overcurrent conditions by limiting their output current to the IOS levels shown in Figure 23. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur. The first condition is when a short circuit or partial short circuit is present when the device is powered-up or enabled. The output voltage is held near zero potential with respect to ground and the TPS2552D and TPS2553D ramps the output current to IOS. The TPS2552D and TPS2553D devices limits the current to IOS until the overload condition is removed or the device begins to thermal cycle. The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is enabled and powered on. The device responds to the overcurrent condition within time tIOS (see Figure 21). The current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit MOSFET. The current-sense amplifier recovers and limits the output current to IOS. Similar to the previous case, the TPS2552D and TPS2553D devices limit the current to IOS until the overload condition is removed or the device begins to thermal cycle. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 13 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Feature Description (continued) The TPS2552D/53D thermal cycles if an overload condition is present long enough to activate thermal limiting in any of the above cases. The device turns off when the junction temperature exceeds 135°C (typ) while in current limit. The device remains off until the junction temperature cools 10°C (typ) and then restarts. The TPS2552D/53D cycle on/off until the overload is removed (see Figure 6 and Figure 8) . 9.3.2 Reverse-Voltage Protection The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds the input voltage by 135 mV (typ) for 4-ms (typ).A reverse current of (VOUT – VIN)/rDS(on)) are present when this occurs. This prevents damage to devices on the input side of the TPS2552D/53D by preventing significant current from sinking into the input capacitance. The TPS2552D/53D devices allow the N-channel MOSFET to turn on once the output voltage goes below the input voltage for the same 4-ms deglitch time. The reversevoltage comparator also asserts the FAULT output (active-low) after 4-ms. 9.3.3 FAULT Response The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or reverse-voltage condition. The TPS2552D/53D asserts the FAULT signal until the fault condition is removed and the device resumes normal operation. The TPS2552D/53D are designed to eliminate false FAULT reporting by using an internal delay "deglitch" circuit for overcurrent (7.5-ms typ) and reverse-voltage (4-ms typ) conditions without the need for external circuitry. This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving fault conditions. Overtemperature conditions are not deglitched and assert the FAULT signal immediately. 9.3.4 Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current surges. 9.3.5 ENABLE The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce the supply current. The supply current is reduced to less than 1-μA when a logic high is present on EN or when a logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver,A logic high input on EN enables the driver, control circuits, and power switch. The enable input is compatible with both TTL and CMOS logic levels. 9.3.6 Thermal Sense The TPS2552D/53D self-protection features use two independent thermal sensing circuits that monitor the operating temperature of the power switch and disable operation if the temperature exceeds recommended operating conditions. The TPS2552D/53D devices operate in constant-current mode during an overcurrent conditions, which increases the voltage drop across power-switch. The power dissipation in the package is proportional to the voltage drop across the power switch, which increases the junction temperature during an overcurrent condition. The first thermal sensor turns off the power switch when the die temperature exceeds 135°C (min) and the part is in current limit. Hysteresis is built into the thermal sensor, and the switch turns on after the device has cooled approximately 10°C. The TPS2552D/3D also have a second ambient thermal sensor. The ambient thermal sensor turns off the powerswitch when the die temperature exceeds 155°C (min) regardless of whether the power switch is in current limit and will turn on the power switch after the device has cooled approximately 10°C. The TPS2552D/53D families continue to cycle off and on until the fault is removed. The open-drain fault reporting output FAULT is asserted (active low) immediately during an overtemperature shutdown condition. 9.4 Device Functional Modes There are no other functional modes. 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 9.5 Programming 9.5.1 Programming the Current-Limit Threshold The overcurrent threshold is user programmable via an external resistor. The TPS2552D/53D use an internal regulation loop to provide a regulated voltage on the ILIM pin. The current-limit threshold is proportional to the current sourced out of ILIM. The recommended 1% resistor range for RILIM is 15 kΩ ≤ RILIM ≤ 232 kΩ to ensure stability of the internal regulation loop. Many applications require that the minimum current limit is above a certain current level or that the maximum current limit is below a certain current level, so it is important to consider the tolerance of the overcurrent threshold when selecting a value for RILIM. The following equations and Figure 23 can be used to calculate the resulting overcurrent threshold for a given external resistor value (RILIM). Figure 23 includes current-limit tolerance due to variations caused by temperature and process. However, the equations do not account for tolerance due to external resistor variation, so it is important to account for this tolerance when selecting RILIM. The traces routing the RILIM resistor to the TPS2552D/53D should be as short as possible to reduce parasitic effects on the current-limit accuracy. RILIM can be selected to provide a current-limit threshold that occurs 1) above a minimum load current or 2) below a maximum load current. To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current limit above a minimum threshold is important to ensure start up into full load or heavy capacitive loads. The resulting maximum current-limit threshold is the intersection of the selected value of RILIM and the IOS(max) curve. To design below a maximum current-limit threshold, find the intersection of RILIM and the maximum desired load current on the IOS(max) curve and choose a value of RILIM above this value. Programming the current limit below a maximum threshold is important to avoid current limiting upstream power supplies causing the input voltage bus to droop. The resulting minimum current-limit threshold is the intersection of the selected value of RILIM and the IOS(min) curve. Current-Limit Threshold Equations (IOS): IOSmax (mA) = 22980V RILIM0.94kW IOSnom (mA) = 23950V RILIM0.977kW IOSmin (mA) = 25230V RILIM1.016kW (1) where 15 kΩ ≤ RILIM ≤ 232 kΩ. While the maximum recommended value of RILIM is 232 kΩ, there is one additional configuration that allows for a lower current-limit threshold. The ILIM pin may be connected directly to IN to provide a 75 mA (typ) current-limit threshold. Additional low-ESR ceramic capacitance may be necessary from IN to GND in this configuration to prevent unwanted noise from coupling into the sensitive ILIM circuitry. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 15 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Programming (continued) 1800 1700 1600 Current Limit Threshold - mA 1500 1400 1300 1200 1100 1000 900 IOS(max) 800 700 600 IOS(nom) 500 400 300 IOS(min) 200 100 0 15 25 35 45 55 65 75 85 95 105 115 125 135 145 155 165 175 185 195 205 215 225 235 RILIM - Current Limit Resistor - kW Figure 23. Current-Limit Threshold vs RILIM 16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information 10.1.1 Constant-Current and Impact on Output Voltage During normal operation the N-channel MOSFET is fully enhanced, and VOUT = VIN - (IOUT x rDS(on)). The voltage drop across the MOSFET is relatively small compared to VIN, and VOUT ≉ VIN. The TPS2552D/53D devices limit current to the programmed current-limit threshold set to RILIM by operating the N-channel MOSFET in the linear mode. During current-limit operation, the N-channel MOSFET is no longer fullyenhanced and the resistance of the device increases. This allows the device to effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the MOSFET is that the voltage drop across the device is no longer negligible (VIN ≠ VOUT), and VOUT decreases. The amount that VOUT decreases is proportional to the magnitude of the overload condition. The expected VOUT can be calculated by IOS × RLOAD, where IOS is the current-limit threshold and RLOAD is the magnitude of the overload condition. For example, if IOS is programmed to 1 A and a 1 Ω overload condition is applied, the resulting VOUT is 1 V. The TPS2552D/53D devices assert the FAULT flag after the deglitch period and continue to regulate the current to the current-limit threshold indefinitely. In practical circuits, the power dissipation in the package will increase the die temperature above the overtemperature shutdown threshold (135°C min), and the device will turn off until the die temperature decreases by the hysteresis of the thermal shutdown circuit (10°C typ). The device will turn on and continue to thermal cycle until the overload condition is removed. The TPS2552D/53D devices resume normal operation once the overload condition is removed. 10.2 Typical Applications 10.2.1 Two-Level Current-Limit Circuit Some applications require different current-limit thresholds depending on external system conditions. Figure 24 shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit threshold is set by the total resistance from ILIM to GND (see the Programming the Current-Limit Threshold section). A logiclevel input enables/disables MOSFET Q1 and changes the current-limit threshold by modifying the total resistance from ILIM to GND. Additional MOSFET/resistor combinations can be used in parallel to Q1/R2 to increase the number of additional current-limit levels. NOTE ILIM should never be driven directly with an external signal. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 17 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Typical Applications (continued) Input 0.1 mF Output IN OUT RFAULT 100 kW ILIM Fault Signal FAULT Control Signal RLOAD CLOAD R1 210 kW R2 22.1 kW GND EN Power Pad Q1 2N7002 Current Limit Control Signal Copyright © 2016, Texas Instruments Incorporated Figure 24. Two-Level Current-Limit Circuit 10.2.1.1 Design Requirements For this example, use the parameters shown in Table 1. Table 1. Design Requirements PARAMETER VALUE Input voltage 5V Output voltage 5V Above a minimum current limit 1000 mA Below a maximum current limit 500 mA 10.2.1.2 Detailed Design Procedures 10.2.1.2.1 Designing Above a Minimum Current Limit Some applications require that current limiting cannot occur below a certain threshold. For this example, assume that 1 A must be delivered to the load so that the minimum desired current-limit threshold is 1000 mA. Use the IOS equations and Figure 23 to select RILIM. IOSmin (mA) = 1000mA IOSmin (mA) = 25230V RILIM1.016 k W 1 æ 25230V ÷ö1.016 RILIM (k W ) = ççç ÷÷ çè I mA ÷ø OSmin RILIM (k W ) = 24k W (2) Select the closest 1% resistor less than the calculated value: RILIM = 23.7 kΩ. This sets the minimum current-limit threshold at 1 A . Use the IOS equations, Figure 23, and the previously calculated value for RILIM to calculate the maximum resulting current-limit threshold. RILIM (kW) = 23.7kW IOSmax (mA) = IOSmax (mA) = 22980V RILIM0.94kW 22980V 23.70.94kW IOSmax (mA) = 1172.4mA (3) The resulting maximum current-limit threshold is 1172.4 mA with a 23.7 kΩ resistor. 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 10.2.1.2.2 Designing Below a Maximum Current Limit Some applications require that current limiting must occur below a certain threshold. For this example, assume that the desired upper current-limit threshold must be below 500 mA to protect an up-stream power supply. Use the IOS equations and Figure 23 to select RILIM. IOSmax (mA) = 500mA IOSmax (mA) = 22980V RILIM0.94kW 1 æ 22980V ÷ö0.94 ÷ RILIM (kW) = ççç çèIOSmax mA ÷÷ø RILIM (kW) = 58.7kW (4) Select the closest 1% resistor greater than the calculated value: RILIM = 59 kΩ. This sets the maximum currentlimit threshold at 500 mA . Use the IOS equations, Figure 23, and the previously calculated value for RILIM to calculate the minimum resulting current-limit threshold. RILIM (kW) = 59kW IOSmin (mA) = IOSmin (mA) = 25230V RILIM1.016kW 25230V 591.016kW IOSmin (mA) = 400.6mA (5) The resulting minimum current-limit threshold is 400.6 mA with a 59 kΩ resistor. 10.2.1.2.3 Accounting for Resistor Tolerance The previous sections described the selection of RILIM given certain application requirements and the importance of understanding the current-limit threshold tolerance. The analysis focused only on the TPS2552D/53D performance and assumed an exact resistor value. However, resistors sold in quantity are not exact and are bounded by an upper and lower tolerance centered around a nominal resistance. The additional RILIM resistance tolerance directly affects the current-limit threshold accuracy at a system level. The following table shows a process that accounts for worst-case resistor tolerance assuming 1% resistor values. Step one follows the selection process outlined in the application examples above. Step two determines the upper and lower resistance bounds of the selected resistor. Step three uses the upper and lower resistor bounds in the IOS equations to calculate the threshold limits. It is important to use tighter tolerance resistors, e.g. 0.5% or 0.1%, when precision current limiting is desired. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 19 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com Table 2. Common RILIM Resistor Selections DESIRED NOMINAL CURRENT LIMIT (mA) IDEAL RESISTOR (kΩ) CLOSEST 1% RESISTOR (kΩ) 120 226.1 226 200 134.0 300 88.5 400 65.9 500 RESISTOR TOLERANCE ACTUAL LIMITS 1% HIGHT (kΩ) IOS MIN (mA) IOS NOM (mA) IOS MAX (mA) 223.7 228.3 50.0 75.0 100.0 101.3 120.0 142.1 133 131.7 134.3 88.7 87.8 89.6 173.7 201.5 233.9 262.1 299.4 66.5 65.8 342.3 67.2 351.2 396.7 52.5 52.3 448.7 51.8 52.8 448.3 501.6 562.4 600 43.5 700 37.2 43.2 42.8 43.6 544.3 604.6 673.1 37.4 37.0 37.8 630.2 696.0 800 770.8 32.4 32.4 32.1 32.7 729.1 800.8 882.1 75 1% LOW (kΩ) SHORT ILIM to IN 900 28.7 28.7 28.4 29.0 824.7 901.5 988.7 1000 25.8 26.1 25.8 26.4 908.3 989.1 1081.0 1100 23.4 23.2 23.0 23.4 1023.7 1109.7 1207.5 1200 21.4 21.5 21.3 21.7 1106.0 1195.4 1297.1 1300 19.7 19.6 19.4 19.8 1215.1 1308.5 1414.9 1400 18.3 18.2 18.0 18.4 1310.1 1406.7 1517.0 1500 17.0 16.9 16.7 17.1 1412.5 1512.4 1626.4 1600 16.0 15.8 15.6 16.0 1512.5 1615.2 1732.7 1700 15.0 15.0 14.9 15.2 1594.5 1699.3 1819.4 10.2.1.2.4 Input and Output Capacitance Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. For all applications, a 0.1μF or greater ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local noise de-coupling. This precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy transient conditions. This is especially important during bench testing when long, inductive cables are used to connect the evaluation board to the bench power-supply. Placing a high-value electrolytic capacitor on the output pin is recommended when large transient currents are expected on the output. 10.2.1.3 Application Curves Figure 25. Turn on Delay and Rise Time 20 Figure 26. Reverse-Voltage Protection Recovery Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 10.2.2 Auto-Retry Functionality Some applications require that an overcurrent condition disables the part momentarily during a fault condition and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and capacitor. During a fault condition, FAULT pulls low disabling the part. The part is disabled when EN is pulled low, and FAULT goes high impedance allowing CRETRY to begin charging. The part re-enables when the voltage on EN reaches the turnon threshold, and the auto-retry time is determined by the resistor/capacitor time constant. The device continues to cycle in this manner until the fault condition is removed. TPS2553D 0.1 mF Input Output IN OUT RLOAD RFAULT CLOAD 100 kW ILIM FAULT GND EN RILIM 20 kW CRETRY Power Pad 0.1 mF Figure 27. Auto-Retry Functionality Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal. Figure 28 shows how an external logic signal can drive EN through RFAULT and maintain auto-retry functionality. The resistor/capacitor time constant determines the auto-retry time-out period. TPS2553D 0.1 mF Input Output IN OUT RLOAD CLOAD External Logic Signal & Driver RFAULT 100 kW ILIM RILIM FAULT 20 kW GND EN CRETRY 0.1 mF Power Pad Figure 28. Auto-Retry Functionality With External EN Signal 10.2.2.1 Design Requirements For this example, use the parameters shown in Table 3. Table 3. Design Requirements PARAMETER VALUE Input voltage 5V Output voltage 5V Current 1200 mA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D 21 TPS2552D, TPS2553D SLVSDL7 – SEPTEMBER 2016 www.ti.com 10.2.2.2 Detailed Design Procedure Refer to Programming the Current-Limit Threshold section for the current limit setting. For auto-retry functionality, once FAULT asserted, EN pull low, TPS2553D is disabled, FAULT des-asserted, CRETRY is slowly charged to EN logic high via RFAULT, then enable, after deglitch time, FAULT asserted again. In the event of an over-load, TPS2553D cycles and has output average current. ON-time with output current is decided by FAULT deglitch time. OFF-time without output current is decided by RFAULT x CRETRY constant time to EN logic high and ton time. Therefore, set the RFAULT × CRETRY to get the desired output average current during overload. 22 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS2552D TPS2553D TPS2552D, TPS2553D www.ti.com SLVSDL7 – SEPTEMBER 2016 10.2.3 Typical Application as USB Power Switch TPS2552D/53D 5V USB Input 0.1 mF USB Data IN OUT USB Port RFAULT 100 kW 120 mF FAULT EN Fault Signal Control Signal ILIM GND Power Pad RILIM 20 kW USB requirement only* *USB requirement that downstream facing ports are bypassed with at least 120 mF per hub Figure 29. Typical Application as USB Power Switch 10.2.3.1 Design Requirements For this example, use the parameters shown in Table 4. Table 4. Design Requirements PARAMETER VALUE Input voltage 5V Output voltage 5V Current 1200 mA 10.2.3.1.1 USB Power-Distribution Requirements USB can be implemented in several ways regardless of the type of USB device being developed. Several powerdistribution features must be implemented. • SPHs must: – Current limit downstream ports – Report overcurrent conditions • BPHs must: – Enable/disable power to downstream ports – Power up at