TPS2559
TPS2559
SLVSCL5A – JUNE 2014 – REVISED NOVEMBER
2020
SLVSCL5A – JUNE 2014 – REVISED NOVEMBER 2020
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TPS2559 Precision Adjustable Current-Limited Power-Distribution Switch
1 Features
3 Description
•
•
•
•
•
•
•
•
The TPS2559 power-distribution switch is intended for
applications where a low resistance, precision current
limit switch is required or heavy capacitive loads are
encountered. The TPS2559 provides up to 5.5 A of
continuous load current with a precise current limit set
by a single resistor to ground. Output current is
maintained at a safe level by switching into a
constant-current mode when the output load exceeds
the current-limit threshold. During overload events the
output current is limited to the level set by R (ILIM). If a
persistent overload occurs, the device goes into
thermal shutoff to prevent damage to the TPS2559.
Operating range: 2.5 V to 6.5 V
Adjustable 1.2-A to 4.7-A I(LIMIT) (±4.4% at 4.7 A)
Short-circuit shutoff (typical): 3.5 µs
High-side MOSFET: 13 mΩ
Maximum standby supply current: 2 µA
Built-in soft-start
System-level ESD capable: 8 kV / 15 kV
UL 2367 recognition pending
2 Applications
•
•
•
•
USB ports, hubs
Digital TVs
Set-top boxes
VOIP phones
The power-switch rise and fall times are controlled to
minimize current surges during turn on or off. The
FAULT logic output asserts low during overcurrent or
overtemperature conditions.
Device Information (1)
PART NUMBER
TPS2559
(1)
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
TPS2559DRC
2.5V-6.5V
0.1PF
2/3/ 4
FAULT
Signal
IN
OUT
VOUT
7/8/ 9
COUT
RFAULT
10
Control
Signal
FAULT
ILIM
5
EN
Power
PAD
6
GND
R ILIM
1
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements.................................................. 6
7.7 Timing Diagrams......................................................... 7
7.8 Typical Characteristics................................................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................20
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Receiving Notification of Documentation Updates..22
12.2 Support Resources................................................. 22
12.3 Trademarks............................................................. 22
12.4 Electrostatic Discharge Caution..............................22
12.5 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2014) to Revision A (November 2020)
Page
• Updated the numbering format for tables and figures throughout the document............................................... 1
• Added OUT row to Voltage range parameter in Absolute Maximum Ratings table............................................ 4
• Added Tstg row to Absolute Maximum Ratings table, moved from ESD Ratings table.......................................4
• Changled title of ESD Ratings table and updated to current standards............................................................. 4
• Added Timing Diagrams title to section, moved from Parameter Measurement Information section to match
current standards................................................................................................................................................7
2
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5 Device Comparison Table
RDS(on) (mΩ)
IOS
TOLERANCE
PACKAGE:
SON-8 (DRB)
SOT-23 (DBV)
SON-10 (DRC)
SON-6 (DRV)
5.5
13
±4.4% at 4.7 A
DRC
±6% at 1.7 A
DBV, DRV
DEVICE
OPERATING
RANGE (V)
OCP MODE
ICONT.
ADJ. RANGE
(A)
TPS2559
2.5 - 6.5
Auto retry
TPS2552/3
2.5 - 6.5
Auto retry
1.2
85 (DBV)
100 (DRV)
TPS2552/3-1
2.5 - 6.5
Latch off
1.2
85 (DBV)
100 (DRV)
±6% at 1.7 A
DBV, DRV
TPS2554/5
(dual Adjustable)
4.5 - 5.5
Auto retry
2.5
73
±9.7% at 2.8 A
DRC
TPS2556/7
2.5 - 6.5
Auto Retry
5
22
±6.5% at 4.5 A
DRB
TPS2560/61
(dual Channels)
2.5 - 6.5
Auto retry
2.5
44
±7.5% at 2.8 A
DRC
TPS2560A/61A
(dual Channels)
2.5 - 6.5
Auto retry
2.5
44
2.1 A to 2.5 A
including ±1% R
DRC
TPS25200
(with OVP protection)
2.5 - 6.5
(withstand up to 20 V)
(ILIM)
Auto retry
2.5
60
±6% at 2.9 A
DRV
6 Pin Configuration and Functions
GND
IN
IN
IN
EN
1
2
3
4
5
10
9
PAD 8
7
6
FAULT
OUT
OUT
OUT
ILIM
Figure 6-1. DRC Package, 10-Pin VSON, Top View
Table 6-1. Pin Functions
PIN
NAME
GND
NO.
1
Ground connection, connect externally to PowerPAD.
Input voltage, connect a 0.1 μF or greater ceramic capacitor from IN to GND as close to the device as
possible.
5
I
Enable input, logic high turns on power switch.
6
O
External resistor used to set current-limit threshold; recommended. 24.9 kΩ ≤ R(ILIM) ≤ 100 kΩ.
7, 8, 9
O
Power-switch output.
10
O
Active-low open-drain output, asserted during over-current or overtemperature conditions.
PAD
—
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect PowerPAD
to GND pin externally.
2, 3, 4
EN
ILIM
OUT
PowerPAD™
DESCRIPTION
I
IN
FAULT
TYPE
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Voltage range
MIN
MAX
UNIT
IN, EN, ILIM, FAULT
–0.3
7
V
OUT
–0.8
7
V
–7
7
V
IN to OUT
Continuous output current, IOUT
OUT
Internally limited
Continuous FAULT sink current
ILIM source current
–40
Storage temperature range, Tstg
(2)
mA
Internally limited
Maximum junction temperature, TJ
(1)
mA
20
mA
OTSD2
–62
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Voltages are referenced to GND unless otherwise noted.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
±500
V
±8000
System level (contact/air) (3)
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Surges per EN61000-4-2, 1999 applied between USB and output ground of the TPS2559EVM-624 Evaluation Module user guide
(documentation available on the web.) These were the test levels, not the failure threshold.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Input voltage, IN
VEN
Input voltage, EN
IOUT
Continuous output current of OUT
MIN
MAX
2.5
6.5
V
0
6.5
V
5.5
A
Continuous FAULT sink current
R(ILIM)
Recommended resistor limit range (1)
TJ
Operating junction temperature
(1)
4
UNIT
10
mA
24.9
100
kΩ
-40
125
°C
R(ILIM) is the resistor from ILIM pin to GND and ILIM pin can be shorted to GND.
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7.4 Thermal Information
TPS2559
THERMAL
METRIC(1)
UNIT
DRC (VSON)
10 PINS
RθJA
Junction-to-ambient thermal resistance
40.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.5
°C/W
RθJB
Junction-to-board thermal resistance
15.9
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
15.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
conditions are –40°C ≤ TJ ≤ 125°C, 2.5 V ≤ VIN ≤ 6.5 V, V(EN) = VIN, R(ILIM) = 49.9kΩ; positive current are into pins; typical
value is at 25°C; all voltages are with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
RDS(on)
Input/output resistance(1)
TJ = 25°C
13
-40°C ≤ TJ ≤ 125°C
16
21
mΩ
ENABLE INPUT EN
EN turn-on/off threshold
0.66
I(EN)
Input current
1.1
55(2)
Hysteresis
V(EN) = 0 V or V(EN) = 6.5 V
–1
V
mV
1
µA
CURRENT LIMIT
IOS
OUT short-circuit current limit
R(ILIM) = 24.9 kΩ
4490
4731
4900
R(ILIM) = 44.2 kΩ
2505
2665
2775
R(ILIM) = 49.9 kΩ
2215
2360
2460
R(ILIM) = 61.9 kΩ
1780
1902
1990
R(ILIM) = 100 kΩ
1080
1176
1245
ILIM pin short to GND (R(ILIM) = 0)
5860
6650
7460
0.1
2
mA
SUPPLY CURRENT
I(IN_OFF) Disabled, IN supply current
V(EN) = 0 V, no load on OUT
µA
R(ILIM) = 100 kΩ, no load on OUT
97
125
R(ILIM) = 24.9 kΩ, no load on OUT
107
135
VOUT = 6.5 V, VIN = 0 V, TJ = 25°C,
measure IOUT
0.01
1
µA
IN rising UVLO threshold voltage
2.36
2.45
V
Hysteresis
35(2)
I(IN_ON)
Enabled, IN supply current
I(REV)
Reverse leakage current
µA
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO
mV
FAULT
VOL
Output low voltage
IFAULT = 1 mA
Off-state leakage
VFAULT = 6.5 V
180
mV
1
µA
THERMAL SHUTDOWN
OTSD2
Thermal shutdown threshold
155
OTSD1
Thermal shutdown threshold in current-limit
135
°C
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7.5 Electrical Characteristics (continued)
conditions are –40°C ≤ TJ ≤ 125°C, 2.5 V ≤ VIN ≤ 6.5 V, V(EN) = VIN, R(ILIM) = 49.9kΩ; positive current are into pins; typical
value is at 25°C; all voltages are with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
(2)
MAX
UNIT
20 (2)
Hysteresis
Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
7.6 Timing Requirements
conditions are –40°C ≤ TJ = ≤ 125°C, 2.5 V ≤ VIN ≤ 6.5 V, V(EN) = VIN, R(ILIM) = 49.9kΩ; positive current are into pins; typical
value is at 25°C; all voltages are with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.6
3.65
5.2
1.3
2.6
3.9
0.7
0.95
1.3
0.42
0.78
1.04
UNIT
POWER SWITCH
tr
OUT voltage rise time
tf
OUT voltage fall time
VIN = 6.5 V
VIN = 2.5 V
VIN = 6.5 V
CL = 1 µF, RL = 100 Ω, see Figure 7-2
VIN = 2.5 V
ms
ENABLE INPUT EN
ton
OUT voltage turn-on time
toff
OUT voltage turn-off time
15
CL = 1 µF, RL = 100 Ω, see Figure 7-3
8
ms
CURRENT LIMIT
tIOS
Short-circuit response time(1)
VIN = 5 V, RSHORT = 50 mΩ, see Figure 7-4
3.5(1)
FAULT deglitch
FAULT assertion or de-assertion resulting from overcurrent
condition
µs
FAULT
(1)
6
6
9.5
13
ms
This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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7.7 Timing Diagrams
OUT
RL
CL
Figure 7-1. Output Rise/Fall Time Test Load
90%
VOUT
tf
tr
10%
Figure 7-2. Power-On and Off Timing
VEN
50%
ton
50%
toff
90%
VOUT
10%
Figure 7-3. Enable Timing, Active High Enable
IOUT
120% x IOS
IOS
0A
tIOS
Figure 7-4. Output Short-Circuit Parameters
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7.8 Typical Characteristics
0.6
0.5
2.4
0.4
IIN_OFF ( A)
Undervoltage Lockout (V)
2.5
2.3
2.2
0.3
0.2
2.1
0.1
Rising
Falling
2.0
±50
0
50
100
0.0
150
Junction Temperature (ƒC)
±50
0
50
100
150
Junction Temperature (ƒC)
C001
C002
VIN = 6.5 V
Figure 7-5. Undervoltage Lockout (UVLO) vs Temperature
Figure 7-6. Supply Current, Output Disabled (IIN_OFF) vs
Temperature
120
140
100
120
100
IIN_ON ( A)
IIN_ON ( A)
80
60
40
80
60
40
20
V
VIN=2.5
IN = 2.5 V
VIN=6.5
V
IN = 6.5 V
0
±50
0
50
100
VIN=6.5
V
IN = 6.5 V
0
150
Junction Temperature (ƒC)
V
VIN=2.5
IN = 2.5 V
20
±50
0
50
100
150
Junction Temperature (ƒC)
C003
R(ILIM) = 100 kΩ
C004
R(ILIM) = 24.9 kΩ
Figure 7-7. Supply Current, Output Enabled (IIN_ON) vs
Temperature
Figure 7-8. Supply Current, Output Enabled (IIN_ON) vs
Temperature
0.7
18
0.6
16
0.4
RDS(on) (m )
IREV ( A)
0.5
0.3
0.2
0.1
14
12
10
0.0
8
±0.1
±50
0
50
100
Junction Temperature (ƒC)
150
±50
VOUT = 6.5 V
50
100
150
C006
VIN = 5 V
Figure 7-9. Reverse Leakage Current (IREV) vs Temperature
8
0
Junction Temperature (ƒC)
C005
Figure 7-10. Input/Output Resistance (RDS(on)) vs Temperature
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7.8 Typical Characteristics (continued)
8.0
13
7.5
12
11
tFAULT (ms)
IOS (A)
7.0
6.5
6.0
10
9
8
5.5
7
6
5.0
±50
0
50
100
150
Junction Temperature (ƒC)
0
±50
100
150
C008
V( FAULT) = 2.5 V
VIN = 6.5 V, ILIM pin short to GND
Figure 7-12. Deglitch Time (tFAULT) vs Temperature
Figure 7-11. Short-Circuit Current (IOS) vs Temperature
4.0
1.0
3.5
0.9
0.8
3.0
0.7
tF (ms)
2.5
tR (ms)
50
Junction Temperature (ƒC)
C007
2.0
1.5
0.6
0.5
0.4
0.3
1.0
0.2
V
VIN=2.5
IN = 2.5 V
0.5
0.0
±50
0
50
100
VVIN=6.5V
IN = 6.5 V
0.0
150
Junction Temperature (ƒC)
VVIN=2.5V
IN = 2.5 V
0.1
VIN=6.5
V
IN = 6.5 V
50
100
Junction Temperature (ƒC)
COUT = 1 µF, R(LOAD) = 100 Ω
150
C010
COUT = 1 µF, R(LOAD) = 100 Ω
Figure 7-13. Output Rise Time (tR) vs Temperature
Figure 7-14. Output Fall Time (tF) vs Temperature
6
R
24.9
k
RILIM
24.9K
ILIM = =
R
RILIM=44.2K
ILIM = 44.9 k
R
RILIM=49.9K
ILIM = 49.9 k
R
RILIM=61.9K
ILIM = 61.9 k
R
RILIM=100K
ILIM = 100 k
5
4
IOS (A)
0
±50
C009
3
2
1
0
±50
0
50
100
Junction Temperature (ƒC)
150
C011
VIN = 6.5 V
Figure 7-15. Short-Circuit Current (IOS) vs Temperature
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8 Detailed Description
8.1 Overview
The TPS2559 is a current-limited, power-distribution switch using N-channel MOSFETs for applications where
short circuits or heavy capacitive loads will be encountered. This device allows the user to program the currentlimit via an external resistor and the maximum continuous output current up to 5.5 A. This device incorporates an
internal charge pump and the gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump
supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the
source. The charge pump operates from input voltages as low as 2.5 V and requires little supply current. The
driver controls the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall
times of the output voltage to limit large current and voltage surges and provides built-in soft-start functionality.
The TPS2559 limits the output current to the programmed current-limit threshold IOS during an overcurrent or
short-circuit event by reducing the charge pump voltage driving the N-channel MOSFET and operating it in the
linear range of operation. The result of limiting the output current to IOS reduces the output voltage at OUT
because N-channel MOSFET is no longer fully enhanced.
8.2 Functional Block Diagram
IN
2/ 3/4
Current
Sense
Charge
Pump
EN
CS
7/8/ 9
Current
Limit
Driver
5
10
UVLO
ILIM
6
GND
1
OUT
Thermal
Sense
FAULT
9.5-ms
Deglitch
8.3 Feature Description
8.3.1 Thermal Sense
The TPS2559 self protects by using two independent thermal sensing circuits that monitor the operating
temperature of the power switch and disable operation if the temperature exceeds recommended operating
conditions. The TPS2559 device operates in constant-current mode during an over-current condition, which
increases the voltage drop across power switch. The power dissipation in the package is proportional to the
voltage drop across the power switch, which increases the junction temperature during an over-current condition.
The first thermal sensor (OTSD1) turns off the power switch when the die temperature exceeds 135°C (min) and
the part is in current limit. Hysteresis is built into the thermal sensor, and the switch turns on after the device has
cooled approximately 20°C.
The TPS2559 also has a second ambient thermal sensor (OTSD2). The ambient thermal sensor turns off the
power switch when the die temperature exceeds 155°C (min) regardless of whether the power switch is in
current limit and will turn on the power switch after the device has cooled approximately 20°C. The TPS2559
continues to cycle off and on until the fault is removed.
10
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8.3.2 Overcurrent Protection
The TPS2559 responds to overcurrent conditions by limiting their output current to IOS. When an overload
condition is present, the device maintains a constant output current, with the output voltage determined by (IOS ×
RLOAD). Two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered-up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS2559 ramps the
output current to IOS. The TPS2559 limits the current to IOS until the overload condition is removed or the device
begins to thermal cycle (see Figure 9-9).
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time tIOS (see Figure 7-4). The
response speed and shape will vary with the overload level, input circuit, and rate of application. The current-limit
response will vary between simply settling to I OS, or turnoff and controlled return to IOS. Similar to the previous
case, the TPS2559 limits the current to I OS until the overload condition is removed or the device begins to
thermal cycle.
The TPS2559 thermal cycles if an overload condition is present long enough to activate thermal limiting in any of
the above cases. The device turns off when the junction temperature exceeds 135°C (min) while in current limit.
The device remains off until the junction temperature cools 20°C (typ) and then restarts. The TPS2559 cycles
on/off until the overload is removed (see Figure 9-10).
8.3.3 FAULT Response
The FAULT open-drain output is asserted (active low) during an over-current or over-temperature condition. The
TPS2559 asserts the FAULT signal until the fault condition is removed and the device resumes normal
operation. The TPS2559 is designed to eliminate false FAULT reporting by using an internal delay "deglitch"
circuit for over-current (9-ms typ.) conditions without the need for external circuitry. This ensures that FAULT is
not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch
circuitry delays entering and leaving current-limit induced fault conditions. The FAULT signal is not deglitched
when the MOSFET is disabled due to an over-temperature condition but is deglitched after the device has
cooled and begins to turn on. This unidirectional deglitch prevents FAULT oscillation during an over-temperature
event.
8.4 Device Functional Modes
8.4.1 Operation with VIN Undervoltage Lockout (UVLO) Control
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage droop during turn on.
8.4.2 Operation with EN Control
The logic enable controls the power switch and device supply current. The supply current is reduced to less than
2-μA when a logic low is present on EN. A logic high input on EN enables the driver, control circuits, and power
switch. The enable input is compatible with both TTL and CMOS logic levels.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS2559 current limited power switch uses N-channel MOSFETs in applications requiring up to 5.5 A of
continuous load current. The device enters constant-current mode when the load exceeds the current limit
threshold.
The TPS2559 power switch is used to protect the up-stream power supply when the output is overloaded.
9.2 Typical Application
TPS2559
5V
0.1PF
2/ 3/4
Fault
Signal
OUT
IN
VOUT
7/ 8/9
150µF
10kŸ
10
FAULT
5
EN
ILIM
Control
Signal
Power
Pad
6
GND
RILIM *
1
Figure 9-1. Typical TPS2559 Power Switch
Use the IOS in the Electrical Characteristics table or IOS in Equation 1 to select the RILIM.
9.2.1 Design Requirements
Table 9-1 lists the input parameters for this design example.
Table 9-1. Design Requirements
DESIGN PARAMETERS
EXAMPLE VALUE
Input operation voltage
5V
Rating current
3 A or 4.5 A
Minimum current limit
3A
Maximum current limit
5A
When choosing a power switch, there are several general steps:
1. Determine what is the power rail, 3.3 V or 5 V, and then choose the operation range of the power switch that
can cover the power rail voltage range.
2. Determine what is the normal operation current. For example, the maximum allowable current drawn by
portable equipment for a USB 2.0 port is 500 mA, so the normal operation current is 500 mA and the
minimum current limit of power switch must exceed 500 mA to avoid false trigger during normal operation.
3. Determine what is the maximum allowable current provided by up-stream power, and then decide the
maximum current limit of the power switch that must lower it to ensure the power switch can protect the upstream power when an overload is encountered at the output of the power switch.
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Note
Choosing power switch with tighter current limit tolerance can loosen the up-stream power-supply
design.
9.2.2 Detailed Design Procedure
9.2.2.1 Step-by-Step Design Procedure
To begin the design process a few parameters must be decided upon. The designer must know the following:
•
•
•
•
Normal input operation voltage
Rating current
Minimum current limit
Maximum current limit
9.2.2.2 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, a 0.1μF or greater ceramic bypass capacitor
between IN and GND is recommended as close to the device as possible for local noise decoupling. This
precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be
needed on the input to reduce voltage undershoot from exceeding the UVLO of other load share one power rail
with TPS2559 or overshoot from exceeding the absolute-maximum voltage of the device during heavy transient
conditions. This is especially important during bench testing when long, inductive cables are used to connect the
evaluation board to the bench power supply.
Output capacitance is not required, but placing a high-value electrolytic capacitor on the output pin is
recommended when large transient currents are expected on the output to reduce the undershoot, which caused
by the inductance of the output power bus just after a short has occurred and the TPS2559 has abruptly reduced
OUT current. Energy stored in the inductance will drive the OUT voltage down and potentially negative as it
discharges.
9.2.2.3 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable via an external resistor. The TPS2559 uses an internal
regulation loop to provide a regulated voltage on the ILIM pin. The current-limit threshold is proportional to the
current sourced out of ILIM. The recommended 1% resistor range for R (ILIM) is 24.9 kΩ ≤ R (ILIM) ≤ 100 kΩ to
ensure stability of the internal regulation loop.
When ILIM pin short to GND (single point failure), maximum current limit is less than 8 A over temperature and
process variation.
Many applications require that the minimum current limit is above a certain current level or that the maximum
current limit is below a certain current level, so it is important to consider the tolerance of the overcurrent
threshold when selecting a value for R (ILIM). The equations and the graph below can be used to estimate the
minimum and maximum variation of the current-limit threshold for a predefined resistor value within R (ILIM) is
24.9 kΩ ≤ R (ILIM) ≤ 100 kΩ. This variation is an approximation only and does not take into account, for example,
the resistor tolerance. For examples of more-precise variation of I OS refer to the current-limit section of the
Electrical Characteristics table.
IOSmax (mA) =
IOSnom (mA) =
IOSmin (mA) =
121635 V
R(ILIM)1.0013kW
+ 36
118079 V
R(ILIM)1.0008kW
113325 V
R(ILIM)1.0010kW
- 47
(1)
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24.9 kΩ ≤ R(ILIM) ≤ 100 kΩ
6000
IIos(Min)
OS (Min)
IOS (Typ)
IOS (Max)
Current Limit Threshold (mA)
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
20
30
40
50
60
70
80
Current Limit Resistor (k
90
100
C012
Figure 9-2. Current-Limit vs R(ILIM)
9.2.2.4 Design Above a Minimum Current Limit
Some applications require that current limiting cannot occur below a certain threshold. For this example, assume
that 3 A must be delivered to the load so that the minimum desired current-limit threshold is 3000 mA. Use the I
OS equations and Figure 9-2 to select R(ILIM).
IOSmin (mA) = 3000 mA
113325 V
IOSmin (mA) =
- 47
R(ILIM)1.0010kW
1
1
æ 113325 ö 1.0010 æ 113325 ö 1.0010
R(ILIM) (kW) = ç
=ç
= 37.06 kW
÷
÷
ç IOS(min) + 47 ÷
è 3000 + 47 ø
è
ø
(2)
Select the closest 1% resistor less than the calculated value: R (ILIM) = 36.5 kΩ. This sets the minimum currentlimit threshold at 3016 A.
IOSmin (mA) =
113325 V
R(ILIM)1.0010kW
- 47 =
113325
(36.5 ´ 1.01)1.0010
- 47 = 3016 mA
(3)
Use the I OS equations, Figure 9-2, and the previously calculated value for R (ILIM) to calculate the maximum
resulting current-limit threshold.
IOSmax (mA) =
121635
R(ILIM)1.0013
+ 36 =
121635
(36.5 ´ 0.99)1.0013
+ 36 = 3387 mA
(4)
The resulting maximum current-limit threshold minimum is 3016 mA and maximum is 3387 mA with a 36.5 kΩ ±
1%.
9.2.2.5 Design Below a Maximum Current Limit
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that 5A must be delivered to the load so that the minimum desired current-limit threshold is 5000 mA. Use the I
OS equations and Figure 9-2 to select R(ILIM).
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IOSmax (mA) = 5000 mA
IOSmax (mA) =
121635
R(ILIM)1.0013kW
+ 36
1
1
æ 121635 ö 1.0013 æ 121635 ö 1.0013
R(ILIM) (kW) = ç
=ç
= 24.4 kW
÷
÷
ç
÷
è 5000 - 36 ø
è IOS(max) ø
(5)
Select the closest 1% resistor less than the calculated value: R ILIM = 24.9 kΩ. This sets the maximum currentlimit threshold at 4950 A.
IOSmax (mA) =
121635
R(ILIM)1.0013kW
+ 36 =
121635
(24.9 ´ 0.99 )1.0013
+ 36 = 4950 mA
(6)
Use the I OS equations, Figure 9-2, and the previously calculated value for R (ILIM) to calculate the minimum
resulting current-limit threshold.
IOSmin (mA) =
113325
R(ILIM)1.0010
- 47 =
113325
(24.9 ´ 1.01)1.0010
- 47 = 4445 mA
(7)
The resulting minimum current-limit threshold minimum is 4445 mA and maximum is 4950 mA with a 24.9 kΩ ±
1%.
9.2.2.6 Accounting for Resistor Tolerance
The previous sections described the selection of R (ILIM) given certain application requirements and the
importance of understanding the current-limit threshold tolerance. The analysis focused only on the TPS2559 is
bounded by an upper and lower tolerance centered on a nominal resistance. The additional R ILIM resistance
tolerance directly affects the current-limit threshold accuracy at a system level. Table 9-2 lists a process that
accounts for worst-case resistor tolerance assuming 1% resistor values.
Step one follows the selection process outlined in the application examples above.
Step two determines the upper and lower resistance bounds of the selected resistor.
Step three uses the upper and lower resistor bounds in the IOS equations to calculate the threshold limits.
It is important to use tighter tolerance resistors, that is, 0.5% or 0.1%, when precision current limiting is desired.
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Table 9-2. Common R(ILIM) Resistor Selections
DESIRED NOMINAL
CURRENT LIMIT
(mA)
IDEAL
RESISTOR
(kΩ)
CLOSEST 1%
RESISTOR
(kΩ)
1250
94.1
1500
1750
2000
2250
RESISTOR TOLERANCE
ACTUAL LIMITS
1% LOW
(kΩ)
1% HIGH
(kΩ)
IOS MIN
(mA)
IOS NOM
(mA)
IOS MAX
(mA)
93.1
92.2
94
1153
1264
1348
78.4
78.7
77.9
79.5
1372
1495
1588
67.2
66.5
65.8
67.2
1633
1770
1874
58.8
59
58.4
59.6
1847
1995
2107
52.3
52.3
51.8
52.8
2090
2551
2373
2500
47.1
47.5
47
48
2306
2478
2610
2750
42.8
43.2
42.8
43.6
2541
2725
2866
3000
39.2
39.2
38.8
39.6
2805
3003
3155
3250
36.2
36.5
36.1
36.9
3016
3226
3386
3500
33.6
34
33.7
34.3
3241
3463
3633
3750
31.4
31.6
31.3
31.9
3491
3726
3907
4000
29.4
29.4
29.1
29.7
3757
4005
4197
4250
27.7
28
27.7
28.3
3947
4206
4405
4500
26.1
26.1
25.8
26.4
4238
4512
4724
4750
24.8
24.9
24.7
25.1
4445
4730
4950
9.2.2.7 Power Dissipation and Junction Temperature
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The below analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system level factors in addition to individual component
analysis. Begin by determining the r DS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r DS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
PD = rDS(on) × IOUT 2
Where:
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD × θJA + TA
Where:
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" r DS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance θ JA and thermal resistance is highly dependent on the individual package and board
layout.
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9.2.2.8 Auto-Retry
Some applications require that an overcurrent condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor
and capacitor. During a fault condition, FAULT pulls low EN. The part is disabled when EN is pulled below the
turn-off threshold, and FAULT goes high impedance allowing C (RETRY) to begin charging. The part re-enables
when the voltage on EN reaches the turn-on threshold. The part will continue to cycle in this manner until the
fault condition is removed. The auto-retry cycling time is determined by the resistor/capacitor time constant,
TPS2559 turn on time and FAULT deglitch time (see Figure 9-13).
TPS2559
VIN
0.1PF
2/3/4
VOUT
OUT
IN
7/8/9
C OUT
R FAULT
100k:
10
FAULT
5
EN
ILIM
C RETRY
PF
Power
Pad
6
GND
100 kŸ
1
Figure 9-3. Auto-Retry Circuit
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
Figure 9-4 shows how an external logic signal can drive EN through R ( FAULT) and maintain auto-retry
functionality. The resistor, capacitor time constant determines the auto-retry time-out period.
TPS2559
VIN
0.1PF
2/ 3/4
IN
OUT
VOUT
7/ 8/9
C OUT
External Logic
Signal and Driver
R FAULT
100 k:
10
ILIM
5
C RETRY
PF
FAULT
EN
Power
Pad
GND
6
100kŸ
1
Figure 9-4. Auto-Retry Circuit with External EN Signal
See the A Power-Distribution Switch With Latched OvercurrentProtection application report for how to implement
latch-off.
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9.2.2.9 Two-Level Current-Limit
Some applications require different current-limit thresholds depending on external system conditions. Figure 9-5
shows an implementation for an externally-controlled, two-level current-limit circuit. The current-limit threshold is
set by the total resistance from ILIM to GND (see the Programming the Current-Limit Threshold section). A logiclevel input enables/disables MOSFET Q1 and changes the current-limit threshold by modifying the total
resistance from ILIM to GND (see Figure 9-14 and Figure 9-15). Additional MOSFET/resistor combinations can
be used in parallel to Q1/R2 to increase the number of additional current-limit levels.
Note
ILIM must never be driven directly with an external signal.
TPS2559
5V
0.1PF
2/3/ 4
OUT
IN
VOUT
7/8/ 9
10kŸ
Control
Signal
C OUT
10
FAULT
5
EN
ILIM
Power
Pad
R1
100 kŸ
6
R2
100 kŸ
Current Limit
Control Signal
GND
1
Q1
Figure 9-5. Two-Level Current-Limit Circuit
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9.2.3 Application Curves
6
3.0
5
6
2.5
3.0
V
VEN
EN
V
VOUT
OUT
5
2.5
4
2.0
3
1.5
3
1.5
2
1.0
1
0.5
2
1.0
1
0.5
0.0
0
0.0
±0.5
±1
IOUT (A)
2.0
VEN, VOUT (V)
4
IOUT (A)
VEN, VOUT (V)
IIOUT
OUT
V
VEN
EN
IIOUT
OUT
±1
±4
0
4
8
12
16
Time (ms)
16
C014
Figure 9-7. Output Fall With 150 µF // 5 Ω
6
6
VFAULT
Vfault
V
VOUT
OUT
4
IIOUT
OUT
5
5
4
4
3
3
2
2
2
2
1
1
1
1
0
0
0
0
±1
±1
±1
0
8
16
24
VOUT , VFAULT (V)
3
IOUT (A)
32
±1
±40
Time (ms)
±20
0
20
40
Figure 9-8. Enable Into Output Short
6
60
80
100 120 140 160
Time (ms)
C015
C016
Figure 9-9. Full Load to Output Short Transient
Response
6
6
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
±1
±1
VFAULT
Vfault
±1
±80
±60
±40
±20
Time (ms)
0
20
5
±1
0
±2
2
4
6
Time (ms)
C017
Figure 9-10. Output Short to Full Load Recovery
Response
6
Vout
V
OUT
IIout
OUT
IIOUT
OUT
IOUT (A)
V
VOUT
OUT
VOUT (V)
VEN, VFAULT (V)
12
3
±8
VOUT , VFAULT (V)
8
Time (ms)
5
VEN
V
EN
Vfault
V
FAULT
IIOUT
OUT
4
4
C013
Figure 9-6. Output Rise With 150 µF // 5 Ω
5
±0.5
0
±4
IOUT (A)
V
VOUT
OUT
IOUT (A)
0
8
C019
Figure 9-11. 50-mΩ Hot-Short
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TPS2559
3.0
1.2
50
2.5
1.0
2.0
0.8
1.5
0.6
1.0
0.4
0.5
0.2
4
40
3
30
2
20
1
10
0
0
±1
±2
±20
±5
±4
±3
±2
0
±1
1
2
3
4
VOUT
Vfault
VFAULT
VOUT
±0.5
5
0
±40
Time ( s)
40
80
120
160
IIOUT
OUT
±0.2
200
240
280
320
360
Time (ms)
C020
Figure 9-12. 50-mΩ Hot-Short Response Time
C021
Figure 9-13. Auto-Retry Cycle
2.5
6
4
2.0
5
2.5
3
1.5
4
2.0
3
1.5
2
1.0
2
1.0
1
0.5
1
0.5
0
0.0
0
0.0
V
VOUT
OUT
±1
±2.0
±1.5
±1.0
V
Vgate
GATE
±0.5
0.0
Vfault
V
FAULT
0.5
1.0
VOUT ,VGATE, VFAULT (V)
5
IOUT (A)
VOUT ,VGATE, VFAULT (V)
0.0
0.0
±10
V
Vout
OUT
VFAULT
Vfault
VGATE
Vgate
IOUT
Iout
3.0
IOUT (A)
VOUT (V)
60
VOUT , VFAULT (V)
VOUT
VOUT
IOUT
IOUT
5
IOUT (A)
6
IOUT (A)
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IIOUT
OUT
±0.5
1.5
±1
±0.5 ±0.4 ±0.3 ±0.2 ±0.1
2.0
Time (s)
Time (s)
C022
Figure 9-14. Two-Level Current Limit With RLOAD =
2.5 Ω
±0.5
0.0
0.1
0.2
0.3
0.4
0.5
C023
Figure 9-15. Two-Level Current Limit With RLOAD =
1Ω
10 Power Supply Recommendations
Design of the devices is for operation from an input voltage supply range of 2.5 V to 6.5 V. The current capability
of the power supply should exceed the maximum current limit of the power switch.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a lowinductance trace.
Placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin is recommended
when large transient currents are expected on the output.
The traces routing the RILIM resistor to the device should be as short as possible to reduce parasitic effects
on the current limit accuracy.
The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.
11.2 Layout Example
VIA to Power Ground Plane
Power Ground
High Frequency
Bypass Capacitor
IN
FAULT
1
108
2
9
3
8
4
7
5
6
OUT
ILIM
Figure 11-1. TPS2559 Board Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2559DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2559
TPS2559DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2559
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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