TPS25762CQRQLRQ1

TPS25762-Q1 SLVSGL9 – DECEMBER 2022 TPS25762-Q1 Automotive USB Type-C® Power Delivery Controller with Buck-Boost Regulator 1 Features 3 Description • The TPS25762-Q1 is a fully integrated USB TypeC® Power Delivery (PD) solution with integrated Buck-Boost converter for automotive single USB port applications. Functionality includes: integrated Buck-Boost converter with 4 power switches; an ARM® Cortex®-M0; USB port controller with Type-C cable plug and orientation detection; USB Battery Charging Specification Version 1.2 (BC1.2) detection; USB Endpoint PHY; device power management and supervisory circuitry; and connector pin protection over-voltage and short-circuit protection. • • • Device Information PART NUMBER TPS25762-Q1 PACKAGE BODY SIZE RQL (QFN-29) 6.00 mm × 5.00 mm IN ON OFF EN LDO5V LDO3V3 LDO1V5 AGND TVSP E2PROM (32kB) IRQ SCL1 SDA1 PGND PA_CC1 PA_CC2 PA_DP PA_DM CSN/BUS CSP OUT 3-21V 3V3 LS_GD NTC GPIO0 GPIO1 TPS25762-Q1 2 Applications • • • • PORT A VBAT TYPE-C CONNECTOR • Device configuration settings are selected through an intuitive graphical user interface (GUI). SCL2 SDA2 SYNC • An intelligent System Policy Manager maximizes delivered USB power while protecting the system from automotive battery transient and over-temperature conditions. Battery • AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature range – Device HBM ESD classification level 2 – Device CDM ESD classification level C2b – Enhanced connector pin ESD protection USB Power Delivery (PD) controller with Programmable Power Supply (PPS) support – Wide VIN: 5.5 V to 18 V (40-V maximum) – Integrated buck-boost 4 power switches supporting up to 65-W USB PD output power – VBUS output: 3–21 V with ±20-mV step size – IBUS output: 0–3 A with ±50-mA current limit step size – VBUS short circuit to VBAT and GND protection – VBUS cable droop compensation – MFi overcurrent protection – Switching frequency: 300, 400, 450 kHz – DC/DC sync in/out with dithering USB port configurations options – 1 USB-PD Port (TPS25762-Q1) – 2 USB-PD Ports (TPS25772-Q1) Compliant to USB – USB Type-C® Power Delivery Rev 3.1 • CC logic, VCONN source and discharge • USB cable polarity detection – Battery charging specification rev 1.2 • DCP: Dedicated Charging Port Legacy Fast Charging – 2.7-V divider-3 mode – 1.2-V divider mode – High Voltage DCP Protocol Microcontroller core allows – Firmware updates – Supply voltage and temperature-dependent power management Short to VBUS and VBAT protection – VBUS – Px_ DP and Px_DM – Px_CC1 and Px_CC2 Automotive USB Charge Automotive Media Hub Automotive Head Unit Automotive Rear Seat Entertainment An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings .............................................................. 7 7.3 Recommended Operating Conditions.........................7 7.4 Recommended Components...................................... 8 7.5 Thermal Information....................................................9 7.6 Buck-Boost Regulator................................................. 9 7.7 CC Cable Detection Parameters...............................13 7.8 CC VCONN Parameters........................................... 13 7.9 CC PHY Parameters.................................................14 7.10 Thermal Shutdown Characteristics......................... 15 7.11 Oscillator Characteristics........................................ 15 7.12 ADC Characteristics................................................15 7.13 TVS Parameters..................................................... 16 7.14 Input/Output (I/O) Characteristics........................... 16 7.15 BC1.2 Characteristics............................................. 17 7.16 I2C Requirements and Characteristics................... 18 7.17 Typical Characteristics............................................ 21 8 Parameter Measurement Information.......................... 29 9 Detailed Description......................................................31 9.1 Overview................................................................... 31 9.2 Functional Block Diagram......................................... 32 9.3 Feature Description...................................................32 9.4 Device Functional Modes..........................................63 10 Application and Implementation................................ 65 10.1 Application Information........................................... 65 10.2 Typical Application.................................................. 65 11 Power Supply Recommendations..............................80 12 Layout...........................................................................81 12.1 Layout Guidelines................................................... 81 12.2 Layout Example...................................................... 82 13 Device and Documentation Support..........................83 13.1 Documentation Support.......................................... 83 13.2 Receiving Notification of Documentation Updates..83 13.3 Support Resources................................................. 83 13.4 Trademarks............................................................. 83 13.5 Electrostatic Discharge Caution..............................83 13.6 Glossary..................................................................83 14 Mechanical, Packaging, and Orderable Information.................................................................... 84 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES December 2022 * Initial Release Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 5 Device Comparison Table PART NUMBER TPS25762-Q1 TPS25772-Q1 Port A USB-PD Port B Port A Output Power Port B Output Power n/a 65 W n/a USB-PD 65 W 65 W Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 3 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO_3V3 GPIO3 | I2C_SDA2 27 26 IN SW1 PGND SW2 CSP 28 OUT CSN/BUS 29 6 Pin Configuration and Functions I2C_SDA1 4 22 TVSP AGND 5 21 LDO_5V EN/UVLO 6 20 PA_CC1 LDO_1V5 7 19 PA_CC2 GPIO5 | NTC 8 18 PA_DP | GPIO8 PA_DM | GPIO7 17 GPIO0 BOOT1 16 23 IN 15 I2C_SCL1 3 SW1 14 GPIO1 | IRQ2(o) PGND 13 24 SW2 12 GPIO9 | IRQ 2 OUT 11 GPIO2 | I2C_SCL2 BOOT2 10 25 PA_LSGD 9 GPIO6 | SYNC 1 Figure 6-1. RQL Package 29-Pin (VQFN) Top View 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 6-1. Pin Descriptions PIN NAME DESCRIPTION NO. EN/UVLO 6 Enable pin. For EN/UVLO < 0.3 V, the TPS25762-Q1 is in a low current shutdown mode. For EN/UVLO > 1.3 V, the full functionality is enabled, provided LDO_5V exceeds the LDO_5V UVLO threshold. IN 15 The input supply pin to the IC. Connect VIN to a supply voltage between 5.5 V and 18 V (40-V ABS MAX transient). PGND 13 Power ground of the IC. The high current ground connection to the low-side gate drivers. SW1 14 The buck side switching node. SW2 12 The boost side switching node. BOOT1 16 An external capacitor is required between the BOOT1 and the SW1 pins to provide bias to the high-side MOSFET gate drivers. BOOT2 10 An external capacitor is required between the BOOT2 and the SW2 pins to provide bias to the high-side MOSFET gate drivers. AGND 5 Analog ground of the IC. OUT 11 Output of the buck-boost regulator. Connect to bulk capacitance. CSP 28 Positive input of the current sense amplifier. CSN/BUS 29 Negative input of the current sense amplifier. This is the PA_VBUS supply. LDO_5V 21 Output of internal 5 V LDO for buck-boost low-side FET drivers, and Px_VCONN supply. Connect bypass capacitor to PGND. May be overdriven from external 5-V supply. LDO_3V3 27 Output of internal 3.3-V LDO for analog circuitry and GPIO drivers. Connect bypass capacitor to AGND. LDO_1V5 7 Output of internal 1.5-V LDO for digital circuitry. Connect bypass capacitor to AGND. I2C_SCL1 3 Controller I2C Clock Input/Output. I2C_SDA1 4 Controller I2C Data Input/Output. GPIO2 (I2C_SCL2) 25 Multifunction pin. GPIO; or target I2C Clock Input. GPIO3 (I2C_SDA2) 26 Multifunction pin. GPIO; or target I2C Data Input. IRQ (GPIO9) 2 Multifunction pin. Interrupt I/O and fault flag for I2C1 or I2C2; or GPIO depending upon firmware configuration. Reports fault conditions set by application configuration firmware. PA_CC1 20 Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem. Connect to Port A Type-C connector CC1 pin. PA_CC2 19 Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem. Connect to Port A Type-C connector CC2 pin. PA_DP (GPIO8) 18 Multifunction pin. BC1.2 USB 2.0 D+ data line input/output. Connect to Port A Type-C USB data line DP connector pins. May also be used as GPIO depending upon firmware configuration. PA_DM (GPIO7) 17 Multifunction pin. BC1.2 USB 2.0 D- data line input/output. Connect to Port A Type-C USB data line DM connector pins. May also be used as GPIO depending upon firmware configuration. GPIO0 23 GPIO GPIO1 or IRQ2(o) 24 Multifunction pin. GPIO or Interrupt I/O depending upon firmware configuration. GPIO5 (NTC) 8 Multifunction pin. GPIO; thermistor input (can use either negative temperature coefficient resistor or positive temperature coefficient resistor). GPIO6 (SYNC) 1 Multifunction pin. GPIO; SYNC(o) - clock out to synchronize slave DC/DC regulators to internal DC/DC switching frequency; SYNC(i) - clock input to synchronize internal DC/DC to an external clock. PA_LSGD 9 Charge pump output for external NFET for VBUS bulk capacitance blocking. TVSP 22 Transient voltage protection and firmware setting pin. See Table 9-3 for boot configuration. See Table 9-2 for R-C network component values. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 5 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7 Specifications 7.1 Absolute Maximum Ratings Over the recommended operating junction temperature range of -40°C to 150°C and AGND = PGND (unless otherwise noted)(1) (2) 6 MIN MAX Input voltage range IN (3) (4) to PGND –0.3 40 V Input voltage range IN with respect to SW1 –0.3 25 V Input voltage range EN/UVLO (5) to AGND –0.3 internally limited V Input voltage range BOOT1 with respect to SW1 –0.3 6 V Input voltage range BOOT2 with respect to SW2 (6) –0.3 6 V Input voltage range SW1 (7) to PGND –0.3 24 V (8) Input voltage range SW2 Input voltage range SW2 to OUT to PGND –0.3 Input voltage range CSP to PGND Input voltage range CSN/BUS to PGND Input voltage range Input voltage range UNIT 24 V 17.5 V –0.3 24 V –0.3 24 V CSP to CSN -0.3 0.3 V AGND to PGND –0.3 0.3 V Output voltage range OUT to PGND –0.3 24 V Output voltage range LDO_5V to PGND –0.3 6 V Output voltage range LDO_3V3 to AGND –0.3 6 V Output voltage range LDO_1V5 to AGND –0.3 2 V I/O voltage range TVSP to PGND –0.3 30 V I/O voltage range I2C_SCL1 to AGND –0.3 6 V I/O voltage range I2C_SDA1 to AGND –0.3 6 V I/O voltage range GPIO9, IRQ1 to AGND –0.3 6 V I/O voltage range PA_CC1 to AGND –0.3 30 V I/O voltage range PA_CC2 to AGND –0.3 30 V I/O voltage range PA_DM to AGND –0.3 30 V I/O voltage range GPIO7 to AGND –0.3 6 V I/O voltage range PA_DP to AGND –0.3 30 V I/O voltage range GPIO8 to AGND –0.3 6 V I/O voltage range GPIO0 to AGND –0.3 6 V I/O voltage range GPIO1, IRQ2 to AGND –0.3 6 V I/O voltage range GPIO2, I2C_SCL2 to AGND –0.3 6 V I/O voltage range GPIO3, I2C_SDA2 to AGND –0.3 6 V I/O voltage range PA_LSGD to PGND –0.3 30 V I/O voltage range GPIO5, NTC to AGND –0.3 6 V I/O voltage range GPIO6, SYNC to AGND –0.3 6 V I/O voltage range PA_LSGD to CSN/BUS –0.3 10 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.1 Absolute Maximum Ratings (continued) Over the recommended operating junction temperature range of -40°C to 150°C and AGND = PGND (unless otherwise noted)(1) (2) Input current EN/UVLO Output current Positive source current on PA_CC1, PA_CC2 Output current GPIO 2, 3, 5, 6, 7, 8 Output current GPIO 0, 1, 4, 9 Output current positive sink current for I2C_SDA1, I2C_SCL1, I2C_SDA2, I2C2_SCL2 Output current positive source current for LDO_5V, LDO_3V3, LDO_1V5 MIN MAX 0 2 UNIT mA internally limited A 0.0010 A 0.005 A internally limited A internally limited A TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C TSTG Storage temperature –55 150 °C (1) (2) (3) (4) (5) (6) (7) (8) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to PGND or AGND. Connect the PGND pin directly to the Ground plane of the board. The PGND and AGND traces can be connected near the AGND pin. When the buck-boost is operating and VIN exceeds 18 V, the positive slew rate dVIN/dt must not exceed 200V/ms. When applying VIN, the time from VIN exceeding 5 V to VIN exceeding 25 V must not be less than 2 µs. This is normally achieved by properly sizing the input EMI filter. EN/UVLO pin is internally clamped to 10V. Ensure input current rating is not exceeded by connecting current limit resistor. BOOT2 with respect to SW2 during OUT overvoltage conditions can be -15 V due to internal clamp. SW1 can undershoot PGND by -1 V during negative switching transients as up to 10A (peak) may flow through the body diode. Typical duration ~20 ns. SW1 can overshoot OUT by 1 V during positive transients. Typical duration ~ 20 ns. SW2 can undershoot PGND by -2 V during switching transients as up to 10A (peak) may flow through the body diode. Typical duration ~20 ns. SW2 can overshoot OUT by 1 V during positive transients. Typical duration ~20 ns. 7.2 ESD Ratings VALUE UNIT ±2000(1) V ±750(2) V V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 V(ESD) Electrostatic discharge IEC61000-4-2 Contact discharge 150 pF, 330 Ω. OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM ±2000(3) V V(ESD) Electrostatic discharge IEC61000-4-2 Contact discharge 150 pF, 330 Ω. OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM ±2000(3) V V(ESD) Electrostatic discharge ISO 10605 Contact discharge 330 pF, 330 Ω. OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM ±2000(3) V V(ESD) Electrostatic discharge ISO 10605 Air-gap discharge 330 pF, 330 Ω. OUT, CSP, CSN/BUS, PA_CC1, PA_CC2, PA_DP, PA_DM ±2000(3) V (1) (2) (3) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification. The passing level per AEC-Q100 Classification C2b. Test conducted on Texas Instruments evaulation board. 7.3 Recommended Operating Conditions Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) MIN MAX UNIT VI Input voltage range (up to 65W output) IN 6.8 18 V VI Input voltage range (up to 30W output) IN 5.5 18 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 7 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.3 Recommended Operating Conditions (continued) Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) MIN MAX UNIT VI Input voltage range EN/UVLO 0 7 (2) V II Input current EN/UVLO 0 1 VI Input voltage range LDO_5V when overdriven by external supply 4.75 5.5 V VI Input voltage range CSP, CSN/BUS 0 22 V VI Input voltage range PB_VBUS (GPIO4 when configured as PB_VBUS) 3 22 V VO Output voltage range OUT 0 21 V VIO I/O voltage range PA_CC1, PA_CC2, PB_CC1, PB_CC2 0 5.5 V VIO I/O voltage range PA_DP, PA_DM, PB_DP, PB_DM 0 3.6 V VIO I/O voltage range I2C_SDAn, I2C_SCLn, IRQn (n=1 or 2) 0 5.5 V VIO I/O voltage range GPIOn (n = 0 - 9) 0 3.6 V VIO I/O voltage range NTC monitor (GPIO5), SYNC (GPIO6) 0 3.6 V IO Output current(1) IOUT 5 A IO Output current PA_CC1, PA_CC2, PB_CC1, PB_CC2 IO Output current (from LDO_3V3) GPIOn (n = 0 - 9) fsw Buck-boost converter switching frequency driven from SYNC pin TA TJ (1) (2) mA 225 mA 10 mA 250 500 kHz Ambient operating temperature –40 125 °C Operating junction temperature –40 150 °C Average LC filtered output current from buck-boost power stage. Operation with IOUT > 3A with VOUT > 10 V may result in thermal shutdown. EN/UVLO MAX specification specification applies when current into pin is not externally limited. 7.4 Recommended Components over operating free-air temperature range (unless otherwise noted) PARAMETER (1) MIN TYP CIN Capacitance on VIN 40 V 22 47 CLDO_5V Capacitance on LDO_5V (supplied 10 V internally) 4.7 CLDO_5V Capacitance on LDO_5V (supplied 10 V externally) 10 CLDO_3V3 Capacitance on LDO_3V3 6.3 V CLDO_1V5 Capacitance on LDO_1V5 6.3 V pins(2) MAX UNIT µF 10 µF 100 µF 4.7 10 µF 4.7 10 µF 47 CPx_CCy Capacitance on Px_CCy 6.3 V 200 330 480 pF CBOOT1, CBOOT2 Boot charge capacitance 10 V 0.08 0.1 0.3 µF RSnubber_SW1 RC snubber resistor on SW1 35 V, 0.25 W CSnubber_SW1 RC snubber capacitor on SW1 35 V RSnubber_SW2 RC snubber resistor on SW2 35 V, 0.25 W 1.1 Ω CSnubber_SW2 RC snubber capacitor on SW2 35 V 3.3 nF COUT Capacitance on OUT (4) 35 V 30 33 40 µF CBUS Capacitance on PA_VBUS 35 V 100 120 150 µF 3.3 4.7 5.6 µH L 8 VOLTAGE RATING Inductor (4) Submit Document Feedback 1.1 Ω 1 nF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 over operating free-air temperature range (unless otherwise noted) PARAMETER (1) VOLTAGE RATING MIN TYP MAX UNIT 100 kΩ NTC Thermistor 47 REN/UVLO Enable/UVLO pull up resitance 47 TVPS pin components (CTVSP || (DamperR + C)) CTVSP Capacitance on TVSP pin (3) 40 V TVPS pin components (CTVSP || (DamperR + C)) Damper resistor R of R + C network in Parallel with CTVSP 0.25W TVPS pin components (CTVSP || (DamperR + C)) Damper capacitor C of R + C network in Parallel with CTVSP 40 V ESRCTVSP TVSP Capacitor ESR (eq series resistance) 10 mΩ ESLCTVSP TVSP Capacitor ESL (eq series inductance) 1 nH (1) (2) (3) (4) kΩ 0.08 0.1 0.12 µF 8 10 12 Ω 0.376 0.47 0.564 µF Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by 50% at the required operating voltage, then the required external capacitor value would be 10 µF. This includes all capacitance to the Type-C receptacle. Maximum capacitance allowed on TVSP pin to ensure propoer decode of device configuration during boot. See applications section for recommended L and COUT combinations. 7.5 Thermal Information TPS25762-Q1 THERMAL METRIC(1) Hot Rod UNIT 29 PINS RθJA Junction-to-ambient thermal resistance 33.3 RθJC(top) Junction-to-case (top) thermal resistance 13.1 RθJB Junction-to-board thermal resistance 7.3 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 7.2 (1) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.6 Buck-Boost Regulator Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT 130 µA SUPPLY VOLTAGE (VIN) IQ VIN shutdown current VEN/UVLO = 0 V IQ VIN operating current VEN/UVLO = 2V, VOUT = 5 V, IOUT = 0 A IQ VIN operating current VEN/UVLO = 1V, VOUT = 0 V, IOUT = 0 A 4.5 mA IQ VIN operating current VEN/UVLO = 2V, VOUT = 0 V, IOUT = 0 A 8 mA VIN(OVP_R) VIN rising overvoltage threshold VIN rising. 18.4 19.2 20 V VIN(OVP_F) VIN falling overvoltage threshold VIN falling. 18.0 18.8 19.6 V 8 hysteresis mA 0.4 V VIN(UVLO_R) VIN undervoltage lockout rising VIN rising. 5.14 5.30 5.46 V VIN(UVLO_F) VIN undervoltage lockout falling VIN falling. 5.04 5.20 5.36 V hysteresis 0.1 V LDO_5V OUTPUT VLDO_5V LDO_5V Output Regulation voltage 7V ≤ VIN ≤ 18 V, 0 < ILDO_5V < 125mA, VEN = 2 V. 4.5 4.63 4.75 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 9 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1) MIN TYP MAX UNIT VLDO_5V(UVLO_R) PARAMETER LDO_5V Undervoltage lockout rising TEST CONDITION 4.29 4.4 4.51 V VLDO_5V(UVLO_F) LDO_5V Undervoltage lockout falling 4.09 4.2 4.31 V Undervoltage hysteresis VLDO_5V_DO 200 mV drop out voltage VIN = 5.5 V; ILDO_5V = 125mA 4.3 LDO_5V current limit VLDO_V5V = 0 to 3.5 V, RLDO_V5V_LOAD = 1 Ω 125 200 400 mA VLDO_3V3 LDO_3V3 Output regulation voltage 7V ≤ VIN ≤ 18 V, VEN = 2 V, VLDO_5V(UVLO) < VLDO_5V < 5.5 V, 0 < ILDO_3V3 < 25mA 3.4 3.5 3.6 V VLDO_3V3(UVLO_R) LDO_3V3 Undervoltage lockout rising 3.2 3.3 3.4 V VLDO_3V3(UVLO_F) LDO_3V3 Undervoltage lockout falling 3.05 3.15 3.25 V ILDO_5V(ILIMIT) V LDO_3V3 OUTPUT Undervoltage hysteresis VLDO_3V3_DO 150 mV drop out voltage VIN = 4.5 V, ILDO_3V3 = 30mA 3.3 LDO_3V3 current limit VLDO_3V3 = 0 to 2.5 V, RLDO_3V3_LOAD =1Ω 35 50 80 VLDO_1V5 LDO_1V5 Output Regulation voltage 4.5 < VLDO_5V < 5.5V, 0 < ILDO_1V5 < 10 mA 1.49 1.55 1.65 V VLDO_1V5(UVLO_R) LDO_1V5 Undervoltage lockout rising 1.44 1.49 1.54 V VLDO_1V5(UVLO_F) LDO_1V5 Undervoltage lockout falling 1.37 1.42 1.47 V ILDO_3V3(ILIMIT) V mA LDO_1V5 OUTPUT Undervoltage hysteresis 70 mV LDO_1V5 current limit VLDO_1V5 = 0 to 1.2 V, RLDO_1V5_LOAD =1Ω VEN(LDO_V5V_R) EN input level required to turn on internal LDOs EN/UVLO rising VEN(LDO_V5V_F) EN input level required to turn off internal LDOs EN/UVLO falling 0.3 VEN(OPER) EN input level required to start operation EN/UVLO rising Precision EN 1.2 1.25 1.3 V VEN(STBY) EN input level required to stop operation EN/UVLO falling 1.1 1.15 1.2 V VEN(HYS) Hysteresis ILDO_1V5(ILIMIT) 15 20 28 mA EN/UVLO 1.05 V V 100 mV VEN(CLAMP) EN input clamp voltage VEN/UVLO > VEN(CLAMP), 10 µA < IEN/ UVLO < 1 mA IEN(LEAK) Leakage current into EN pin 0 V < VEN < 6 V VCSN/BUS(3V) VCNS/BUS regulation accuracy at 3V 0 ≤ IOUT ≤ 3A 2.9 VCSN/BUS(5V) VCNS/BUS regulation accuracy at 5V 0 ≤ IOUT ≤ 3A 4.85 VCSN/BUS(21V) VCNS/BUS regulation accuracy at 21V 0 ≤ IOUT ≤ 3A 20.48 VCSN/BUS_STP Output voltage step size (12-bit DAC) VDAC Resolution Resolution of VBUS DAC IDISCHG CSN/BUS discharge current when transitioning to VSafe0V VCSP = VCSN/BUS. VCSN/BUS = 3V. Measure current into BUS. tDISCHG CSN/BUS discharge time when transitioning to VSafe5V VBUS = 21 V (max), CBULK = 220 µF, time to discharge BUS to < 5.5 V (per USB PD specification) 275 ms tDISCHG CSN/BUS discharge time when transitioning to VSafe0V VBUS = 21 V (max), CBULK = 220 µF, time to discharge BUS to < 0.8 V (per USB PD specification) 650 ms 6 9 12 V 1 µA 3 3.1 V 5 5.15 V 21 21.53 V OUTPUT VOLTAGE 10 Submit Document Feedback 10 mV 12 Bits 40 mA Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1) PARAMETER TEST CONDITION RDISCHG Weak discharge resistance on BUS pin when not sourcing VBUS EN = 2V; measure BUS to PGND resistance. RBUS-GND(PWR) BUS to GND resistance, RDISCH disabled, not sourcing VBUS EN = 2V measure BUS to PGND resistance. RBUS-GND(UNPWR) BUS to GND resistance, unpowered VIN = EN = 0V measure BUS to PGND resistance. MIN TYP MAX UNIT 60 135 kΩ 120 500 kΩ 2 kΩ CABLE VOLTAGE DROP COMPENSATION VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.1V/A: VCSP VCSN/BUS = 50 mV 465 500 535 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.1V/A: VCSP VCSN/BUS = 10 mV 85 100 115 mV VOUT_CDC ΔVOUT increase vs IOUT Gain stetting = 0.075V/A: VCSP VCSN/BUS = 50 mV 346 375 404 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.075V/A: VCSP VCSN/BUS = 10 mV 61 75 89 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.05V/A: VCSP VCSN/BUS = 50 mV 227 250 273 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.05V/A: VCSP VCSN/BUS = 10 mV 37 50 63 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.025V/A: VCSP VCSN/BUS = 50 mV 109 125 141 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0.025V/A: VCSP VCSN/BUS = 10 mV 14 25 36 mV VOUT_CDC ΔVOUT increase vs IOUT Gain setting = 0V/A: 0 mV ≤ VCSP VCSN/BUS ≤ 50 mV -5 20 mV BUCK-BOOST PEAK CURRENT LIMITS IPEAK(BOOST) Boost peak current limit (in boost mode) 12.3 14.5 16.7 A IPEAK(BOOST) Boost peak current limit (in boost mode) 10.8 12.8 14.7 A IPEAK(BOOST) Boost peak current limit (in boost mode) 9.3 11.0 12.6 A IPEAK(BOOST) Boost peak current limit (in boost mode) 7.9 9.3 10.6 A IPEAK(BOOST) Boost peak current limit (in boost mode) 6.3 7.5 8.6 A IPEAK(BOOST) Boost peak current limit (in boost mode) 4.8 5.7 6.5 A IPEAK(BUCK) Buck peak current limit (in buck mode) 8.2 9.7 11.2 A IPEAK(BUCK) Buck peak current limit (in buck mode) 9.0 10.6 12.1 A IPEAK(BUCK) Buck peak current limit (in buck mode) 9.7 11.4 13.1 A IPEAK(BUCK) Buck peak current limit (in buck mode) 10.4 12.3 14.1 A IPEAK(BUCK) Buck peak current limit (in buck mode) 5.3 6.2 7.2 A IPEAK(BUCK) Buck peak current limit (in buck mode) 6 7.1 8.2 A IPEAK(BUCK) Buck peak current limit (in buck mode) 6.8 8.0 9.1 A IPEAK(BUCK) Buck peak current limit (in buck mode) 7.5 8.8 10.1 A INEG(BUCK) Buck negative current limit (in buck mode) -4.6 - 3.8 -3 A OUT CURRENT DAC IDAC_Resolution 8 Bits Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 11 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT CURRENT LIMIT ILIMIT_LO Current limit accuracy 1 A ≤ IOUT ≤ 3 A, VCSN/BUS < 2.5 V; RS = 10 mΩ. -250 250 mA ILIMIT_LO Current limit accuracy < 1 A 1 A ≤ IOUT ≤ 3 A, VCSN/BUS ≥ 2.5 V; RS = 10 mΩ -150 150 mA ILIMIT_HI Current limit accuracy > 3 A IOUT > 3 A, VCSN/BUS < 2.5 V; RS = 10 mΩ -20 20 % ILIMIT_HI Current limit accuracy > 3 A IOUT > 3 A, VCSN/BUS ≥ 2.5 V; RS = 10 mΩ -5 5 % ILIMIT_MIN Minimum programmable current limit ICL_STEP Current limit step size 1 1 A ≤ IOUT ≤ 5 A; RS = 10 mΩ A 50 mA FREQUENCY fSW(1) Switching Frequency 1 285 300 315 kHz fSW(2) Switching Frequency 2 380 400 420 kHz fSW(3) Switching Frequency 3 428 450 473 kHz 8 10 12 % -12 -10 -8 % FREQUENCY DITHER Positive frequency deviation during dither FSSS Negative frequency deviation during dither FSSS_MOD Modulation frequency of dither DITHER_FREQ = 0 9 10 11 kHz FSSS_MOD Modulation frequency of dither DITHER_FREQ = 1 22.5 25 27.5 kHz OVERVOLTAGE PROTECTION VCSN/BUS_OVP_R Fixed output overvoltage threshold at CSN/BUS pin 22.0 23 24 V VCSN/BUS_OVP_F Falling 20.5 21.5 22.5 V Hysteresis 1.5 V POWER SWITCHES RDS(ON) M1 VIN = 12V; (VBOOT1 - VSW1) = 4.5V; ISW1 = -1 A 4.5 mΩ RDS(ON) M2 VIN = 12V; ISW1 = 1 A 20 mΩ RDS(ON) M4 VIN = 12V; ISW2 = 1 A 6 mΩ RDS(ON) M3 + M5 VIN = VOUT = 12V: (VBOOT2 - VSW2) = 4.5V, ISW2 = -1 A 18 mΩ VUV_BOOT1_R BOOT1 to SW1 rising UVLO threshold 3.5 4 4.4 V VUV_BOOT1_F BOOT1 to SW1 falling UVLO threshold 2.9 3.4 3.7 V BOOT1 to SW1 UVLO hysteresis 680 mV VOV_BOOT1_R BOOT1 to SW1 rising OVP threshold 4.6 5.3 5.9 V VOV_BOOT1_F BOOT1 to SW1 falling OVP threshold 4.3 5 5.6 V BOOT 1 OVP hysteresis 250 300 350 mV VUV_BOOT2_R BOOT2 to SW2 rising UVLO threshold 3.5 4 4.4 V VUV_BOOT2_F BOOT2 to SW2 falling UVLO threshold 2.9 3.4 3.7 V BOOT2 to SW2 UVLO hysteresis 680 mV VOV_BOOT2_R BOOT2 to SW1 rising OVP threshold 4.6 5.3 5.9 V VOV_BOOT2_F BOOT2 to SW1 falling OVP threshold 4.3 5 5.6 V BOOT2 OVP hysteresis 250 300 350 mV BUCK-BOOST CHARACTERISTICS 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1) PARAMETER tSS (1) TEST CONDITION MIN TYP Soft-start time MAX 6 UNIT ms All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical processcontrol. 7.7 CC Cable Detection Parameters Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Type-C Source (Rp pull-up) VOC_3.3 Unattached Px_CCy open circuit voltage while Rp enabled, no load RCC = 47 kΩ 1.85 V VOC_5 Attached Px_CCy open circuit voltage while Rp enabled, no load RCC = 47 kΩ 2.95 V IRev Unattached reverse current on Px_CCy VCCy = 5.5V, VCCx = 0V, measure current into CCy IRpStd current source - Standard 0 < VCCy < 1.0 V, measure ICCy 64 IRp1.5 current source - 1.5A 0 < VCCy < 1.5 V, measure ICCy IRp3.0 current source - 3.0A 0 < VCCy < 2.45 V, measure ICCy 10 µA 80 96 µA 166 180 194 µA 304 330 356 µA Type-C Sink (Rd pull-down) RSNK Rd pulldown resistance 0V ≤ VPx_CCy ≤ 2.1 V, measure resistance on Px_CCy 4.6 5.6 kΩ RVCONN_DIS VCONN discharge resistance 0V ≤ VPx_CCy ≤ 5.5 V, measure resistance on Px_CCy 4.0 6.6 kΩ Common (Source and Sink) tCC deglitch time for comparators on Px_CCy, this applies for VSRC1, VSRC2, VSRC3, VSNK1, VSNK2, VSNK3, and VSNK4. 2.56 ms 7.8 CC VCONN Parameters Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN = 2 V unless otherwise stated. PARAMETER RPP_CABLE ILIMVC Rdson of the VCONN path short circuit current limit TEST CONDITIONS MIN TYP VLDO_5V = 5V, IL = 200 mA, measure resistance from LDO_5V to Px_CCy MAX 1.2 UNIT Ω setting 0, VLDO_5V = 5V, RL=10mΩ , measure IPx_CCy 30 50 70 setting 1, VLDO_5V = 5V, RL=10mΩ , measure IPx_CCy 235 275 315 -1 0 10 µA mA ICCyLKG Leakage current into Px_Cy pins VCONN disabled, TJ ≤ 125 oC, VPx_CCy = 5.5 V, measure IPx_CCy VVC_OVP Over-voltage protection threshold for Px_CCy VLDO_5V rising 5.6 5.9 6.2 V VVC_RCP Reverse current protection threshold for Px_CCy, sourcing VCONN through CCx VLDO_5V = 5 V, VCCx rising, setting 1. 230 310 390 mV Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 13 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN = 2 V unless otherwise stated. PARAMETER TEST CONDITIONS VVC_RCP Reverse current protection threshold for Px_CCy, sourcing VCONN through CCx tPP_CABLE_FSD Time to disable Px_Cy VCONN after VLDO_5V > CL=0 VVC_OVP or VCCx - VLDO_5V > VVC_RCP tPP_CABLE_off from disable signal to Px_CCy at 10% of final value tiOS_PP_CABLE tiOS_PP_CABLE VLDO_5V = 5 V, VCCx rising, setting 2. IL = 200 mA, VLDO_5V = 5V, CL=0 MIN TYP MAX UNIT 60 155 250 mV 1.5 100 225 µs 300 µs External VLDO_5V = 5V, for response time to short circuit short circuit RL = 10mΩ. Set VCONILIM = 1. 2 µs Internal VLDO_5V = 5V, for response time to short circuit short circuit RL = 10mΩ. Set VCONILIM = 0. 0.3 µs 7.9 CC PHY Parameters Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN = 2V unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.125 1.2 V Transmitter VTXHI Transmit high voltage on Px_CCy Standard External load 1.05 VTXLO Transmit low voltage on Px_CCy Standard External load -75 75 mV ZDRIVER Transmit output impedance while driving the CC line using Px_CCy measured at 750 kHz 33 75 Ω tRise Rise time. 10 % to 90 % amplitude points on Px_CCy, minimum is under an unloaded condition. Maximum set by TX mask CPx_CCy= 520 pF 300 ns tFall Fall time. 90 % to 10 % amplitude points on Px_CCy, minimum is under an unloaded condition. Maximum set by TX mask CPx_CCy= 520 pF 300 ns VPHY_OVP OVP detection threshold for USB PD PHY. Initially VCC1 ≤ 5.5 V and VCC2 ≤ 5.5 V, then VCCx rises. 5.5 Receiver input impedance on Px_CCy Does not include pull-up or pulldown resistance from cable detect. Transmitter is Hi-Z. CCC Receiver capacitance on Px_CCy(1) Capacitance looking into the CC pin when in receiver mode VRX_SNK_R Rising threshold on Px_CCy sink mode (rising) for receiver comparator 499 VRX_SRC_R Rising threshold on Px_CCy source mode (rising) for receiver comparator 784 8.5 V Receiver ZBMCRX 14 (2) Submit Document Feedback 1 MΩ 120 pF 525 551 mV 825 866 mV Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN = 2V unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRX_SNK_F Falling threshold on Px_CCy sink mode (falling) for receiver comparator 230 250 270 mV VRX_SRC_F Falling threshold on Px_CCy source mode (falling) for receiver comparator 523 550 578 mV (1) (2) CCC includes only the internal capacitance on a Px_CCy pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends adding CPx_CCy externally. Guaranteed, but not production tested. 7.10 Thermal Shutdown Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TSD_BB Temperature shutdown threshold Temperature rising TSD_HYS Temperature shutdown hysteresis hysteresis TSD_PA_VCONN Temperature shutdown threshold Temperature rising TSD_HYS Temperature shutdown hysteresis hysteresis TSD_PA_VBUS_DISCH Temperature shutdown threshold Temperature rising TSD_HYS Temperature shutdown hysteresis hysteresis TSD_LDO5V Temperature shutdown threshold Temperature rising TSD_HYS Temperature shutdown hysteresis hysteresis MIN TYP MAX UNIT 160 167 175 °C 18 152 166 °C 179 20 155 166 °C 177 20 165 177 °C °C °C 188 15 °C °C 7.11 Oscillator Characteristics Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER FOSC(100K) TEST CONDITIONS 100KHz oscillator Trimmed. FOSC(24M) 24MHz oscillator Trimmed. 0 ℃ ≤ TA ≤ 70 ℃ FOSC(24M) 24MHz oscillator Trimmed. -40 ℃ ≤ TA ≤ 150 ℃ MIN TYP MAX 89 103 111 UNIT kHz 23.64 24.2 24.36 MHz 23.3 24.2 24.5 MHz 7.12 ADC Characteristics Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LSB least significant bit 3.6V max scaling, voltage divider of 3 LSB least significant bit 25.2V max scaling, voltage divider of 21 98 mV LSB least significant bit (VCSP - VCSN/BUS)= 10 mV, 30 mV 27 mA EG Gain error 0 A ≤ ITVSP ≤ 0.9 mA –2.7 14 mV 2.7 % Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 15 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EG Gain error 0.05V ≤ VGPIOx ≤ 3.6V, VGPIOx ≤ VLDO_3V3 –2.7 2.7 % EG Gain error 2.7V ≤ VLDO_3V3 ≤ 3.6V –2.4 2.4 % EG Gain error 0.6V ≤ VPx_VBUS ≤ 22V –2.4 2.4 % EG Gain error, current sense (VCSP - VCSN/BUS)= 10 mV, 30 mV –2.4 2.4 % EG Gain error VIN –2.4 2.4 % EG Gain error 4.3 V ≤ VLDO_5V ≤ 5.5V –2.4 2.4 % VOS(E) Offset error(1) 0 A ≤ ITVSP ≤ 0.9 mA –4.1 15 mV VOS(E) Offset error(1) 0.05V ≤ VGPIOx ≤ 3.6V, VGPIOx ≤ VLDO_3V3 –4.1 4.1 mV VOS(E) Offset error(1) 2.7V ≤ VLDO_3V3 ≤ 3.6V -4.1 4.1 mV VOS(E) Offset error(1) 0.6V ≤ VPx_VBUS ≤ 22V -4.1 4.1 mV VOS(E) Offset error(1) (VCSP - VCSN/BUS)= 10 mV, 30 mV -4.5 4.5 mA VOS(E) Offset error(1) VIN -4.1 4.1 mV VOS(E) Offset error(1) 4.3 V ≤ VLDO_5V ≤ 5.5V -4.1 4.1 mV (1) The offset error is specified after the voltage divider. 7.13 TVS Parameters VIN = 13.5V, EN = 2V. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.3 5.5 5.7 V 1 µA TVSP VTVSP_PU Pull up voltage for configuration (1) Decode 0 Device configuration decode RTVS = Open Decode 1 Device configuration decode RTVS = 93.1 kΩ 56.9 61.2 µA Decode 2 Device configuration decode RTVS = 47.5 kΩ 111.6 120 µA Decode 3 Device configuration decode RTVS = 29.4 kΩ 180.3 193.9 µA Decode 4 Device configuration decode RTVS = 20.0 kΩ 265 285 µA Decode 5 Device configuration decode RTVS = 14.7 kΩ 360.5 387.8 µA Decode 6 Device configuration decode RTVS = 11.0 kΩ 481.8 518.2 µA Decode 7 Device configuration decode RTVS = 8.45 kΩ 627.2 674.6 µA Decode 8 Device configuration decode RTVS = 6.65 kΩ 797 857.1 µA ITVSP(ILIMIT) Current limit when TVSP is sourcing. 1.83 mA (1) 0 < ITVSP < 1 mA CTVSP = open; RTVSP = open. All Px_Dy = 0 V and Px_CCy = 0 V. VTVSP = 0 V. Measure current flowing out of TVSP. 1.1 1.44 For proper device configuration, VIN must be ≥ 7.6 V at time of configuration read. 7.14 Input/Output (I/O) Characteristics Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GPIO0-9 (Inputs) (1) VIH GPIOx high-Level input voltage VIL GPIOx low-level input voltage 16 Submit Document Feedback 1.3 V 0.54 V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS GPIOx input hysteresis voltage MIN TYP MAX 0.09 II(LEAKAGE) GPIOx leakage current VGPIOx = 5.5 V –8 RPU GPIOx internal pull-up pull-up enabled 50 RPD GPIOx internal pull-down pull-down enabled 50 tDG GPIOx input deglitch UNIT V 8 µA 100 150 kΩ 100 150 kΩ 20 ns GPIO 2, 3, 5, 6 (Outputs) VOH GPIOx output high voltage IGPIOx= -5mA VOL GPIOx output low voltage IGPIOx=5mA GPIO 0, 1, 4, 7, 8, 9 (Outputs) 2.9 V 0.4 V (2) VOH GPIOx output high voltage IGPIOx= -2mA 2.9 V VOL GPIOx output low voltage IGPIOx=2mA ϕ shift_00 GPIOx when configured as phase shifted DC/DC fsw clock output Phase difference between fsw and GPIO6 when configured as SYNC(O). 0 degrees ϕ shift_90 GPIOx when configured as phase shifted DC/DC fsw clock output Phase difference between fsw and GPIO6 when configured as SYNC(O). 90 degrees ϕ shift_120 GPIOx when configured as phase shifted DC/DC fsw clock output Phase difference between fsw and GPIO6 when configured as SYNC(O). 120 degrees ϕ shift_180 GPIOx when configured as phase shifted DC/DC fsw clock output Phase difference between fsw and GPIO6 when configured as SYNC(O). 180 degrees 0.4 V SYNC OUT SYNC IN fSYNC(300kHz) Valid external clock frequency (fSW_internal = 300kHz) 250 353 kHz fSYNC(400kHz) Valid external clock frequency (fSW_internal = 400kHz) 334 470 kHz fSYNC(450kHz) Valid external clock frequency (fSW_internal = 450kHz) 376 530 kHz 16 µA 8 V LSGD ILSGD_ON NFET driver sourcing current 0 V ≤ VCSN/BUS ≤ 21 V; 0 V ≤ (VLSGD - VCSN/BUS) ≤ 4 V VLSGD_ON Sourcing voltage while enabled (VLSGD - VCSN/BUS) 0 V ≤ VCSN/BUS ≤ 21 V; ILSGD ≤ 4 µA. Measure voltage between LSGD and CSN/BUS. RLSGD_OFF Sinking resistance when disabled VLSGD = VCSN/BUS = 5 V (1) (2) 10 13 6 160 300 kΩ GPIO9 is normally configured as I2C_IRQ1m (master): input pin. I2C specification requires use of external pullup resistor. Input thresholds (VIH; VIL) leakage current (II(LEAKAGE))and deglitch timing (tDG) specifications are apply when used as I2C_IRQ1m. Internal pullup and pulldown resistors are not used during this mode of operation. GPIO9 or GPIO1 may be configured as I2C_IRQ2s (slave): open-drain output pin. I2C specification requires use of external pullup resistor. Output threshold (VOL) applies. Internal pullup and pulldown resistors are not used during this mode of operation. 7.15 BC1.2 Characteristics Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 Ω BC1.2 RESISTANCES RDCP_DAT Dedicated Charging Port Resistance between Px_DP and Px_DM VPx_DP = 0.6 V, VPx_DM = 0V, measure DP to DM shorted resistance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 17 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RDM_DWN_15k Px_DM line pulldown resistance VPx_DM = 3.6V 12 15 18 kΩ RDM_DWN_20k Px_DM line pulldown resistance VPx_DM = 3.6V 14.25 19.53 24.8 kΩ V DIVIDER MODES V2.7V Output Voltage on DPy pin No load on DPy pin 2.57 2.7 2.83 V2.7V Output Voltage on DMy pin No load on DMy pin 2.57 2.7 2.83 V R2.7V Output Impedance on DPy 5µA pulled from DPy pin 24 30 36 kΩ R2.7V Output Impedance on DMy 5µA pulled from DMy pin V1.2V Output Voltage on DMy No load on DMy R1.2V Output Impedance on DMy 5µA pulled from DMy 24 30 36 kΩ 1.12 1.2 1.28 V 80 102 130 kΩ 0.25 0.325 0.4 V 1.8 2 2.2 V 8.5 V HVDCP THRESHOLD VOLTAGES VDAT_REF Data detection voltage on DP or DM pin VSEL_REF Output selection voltage DP or DM pin DP AND DM OVERVOLTAGE PROTECTION VDy_OVP OVP detection threshold for USB Px_DP and Px_DM pins Initially VPxDy ≤ 3.6 V, then VPx_Dy rises. 5.5 7.16 I2C Requirements and Characteristics Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.54 V I2C_IRQ1s, I2C_IRQ2 I2C_IRQ1m SDA and SCL Characteristics (Standard, Fast, Fast-mode Plus) VIL Input low signal VIH Input high signal 1.3 V VDD = 3.3 V INPUT LOGIC THRESHOLDS VIL Input low signal 0.9 V VIH Input high signal 2.31 V VHYS Input hysteresis 0.165 V VOL Output low voltage VDD = 1.8V, IOL=2 mA 0.36 VOL Output low voltage VDD = 3.3V, IOL=3 mA 0.4 IOL Max output low current VOL=0.4 V 12 ILEAK Input leakage current Voltage on pin = 3.3V –5 CI pin capacitance (internal) Cb Capacitive load for each bus line (external). Applies in Standardmode and Fast-mode. Cb Capacitive load for each bus line (external). Applies in Fast-mode Plus. V mA 5 µA 10 pF 400 pF 550 pF 50 ns 100 kHz COMMON TIMING tSP I2C pulse width surpressed SDA and SCL Characteristics (Standard Mode) fSCLS Clock frequency (slave) VDD = 1.8V or 3.3V tHD;STA Start or repeated start condition hold time VDD = 1.8V or 3.3V 18 Submit Document Feedback 4 µs Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tLOW SCL Clock low time VDD = 1.8V or 3.3V 4.7 µs tHIGH SCL Clock high time VDD = 1.8V or 3.3V 4 µs tSU;STA Start or repeated start condition setup time VDD = 1.8V or 3.3V 4.7 µs tHD;DAT Serial data hold time (1) VDD = 1.8V or 3.3V 0 (2) tSU;DAT Serial data setup time VDD = 1.8V or 3.3V 250 tr VDD = 1.8V or 3.3V; RPU = 2.8 kΩ; Rise time of SCL and SDA signals Cb = 400pF; measure 0.3 × VDD to 0.7 × VDD tof Output fall time from VIH(MIN) to VIL(MAX) - (3) ns ns 1000 ns VDD = 1.8V or 3.3V; measure 0.3 × VDD to 0.7 × VDD 250 (4) ns Fall time of SCL and SDA signals VDD = 1.8V, RPU = 2.8 kΩ; 10 pF ≤ Cb ≤ 400 pF 300 ns Fall time of SCL and SDA signals (2) (4) (5) VDD = 3.3V, RPU = 2.8 kΩ; 10 pF ≤ Cb ≤ 400 pF 300 ns tSU;STO Stop condition setup time VDD = 1.8V or 3.3V 4 µs tBUF Bus free time between stop and start VDD = 1.8V or 3.3V 4.7 µs tVD;DAT Valid data time (6) Transmitting Data; VDD = 1.8V or 3.3V, SCL low to SDA output valid 3.45 (3) µs tVD;ACK Valid data time of ACK condition Transmitting Data; VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA valid 3.45 (3) µs tf tf (2) (4) (5) SDA and SCL Characteristics (Fast Mode) fSCLS Clock frequency (slave) VDD = 1.8V or 3.3V tHD;STA Start or repeated start condition hold time 400 VDD = 1.8V or 3.3V 0.6 µs tLOW SCL Clock low time VDD = 1.8V or 3.3V 1.3 µs tHIGH SCL Clock high time VDD = 1.8V or 3.3V 0.6 µs tSU;STA Start or repeated start condition setup time VDD = 1.8V or 3.3V 0.6 µs tHD;DAT Serial data hold time (1) VDD = 1.8V or 3.3V 0 (2) tSU;DAT Serial data setup time VDD = 1.8V or 3.3V 100 (7) tr VDD = 1.8V or 3.3V; RPU = 850 Ω; Rise time of SCL and SDA signals Cb = 400 pF; measure 0.3 × VDD to 0.7 × VDD tof Output fall time from VIH(MIN) to VIL(MAX) tof - (3) kHz ns ns 20 300 ns VDD = 1.8V; measure 0.3 × VDD to 0.7 × VDD 6.55 250 (4) ns Output fall time from VIH(MIN) to VIL(MAX) VDD = 3.3V; measure 0.3 × VDD to 0.7 × VDD 12 250 (4) ns Fall time of SCL and SDA signals VDD = 1.8V; RPU = 850 Ω; 10 pF ≤ Cb ≤ 400 pF 6.55 300 ns Fall time of SCL and SDA signals (2) (4) (5) VDD = 3.3V; RPU = 850 Ω; 10 pF ≤ Cb ≤ 400 pF 12 300 ns tSU;STO Stop condition setup time VDD = 1.8V or 3.3V 0.6 µs tBUF Bus free time between stop and start VDD = 1.8V or 3.3V 1.3 µs tVD;DAT Valid data time (6) Transmitting Data; VDD = 1.8V or 3.3V, SCL low to SDA output valid tf tf (2) (4) (5) 0.9 (3) µs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 19 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V) PARAMETER tVD;ACK (1) (2) (3) (4) (5) (6) (7) 20 TEST CONDITIONS Valid data time of ACK condition Transmitting Data; VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low MIN TYP MAX UNIT 0.9 (3) µs tHD;DAT = the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD;DAT could be 3.45 µs and 0.9 µs for Standard-mode and Fast-mode, but must be less than the maximum tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the setup time before it releases the clock. The maximum tf for the SDA and SCL bus lines is stated in these tables as 300 ns is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (RS) to be connected between the SDA and SCL pins and the SDA and SCL bus lines without exceeding the maximum specified tf. In Fast-mode Plus, fall time is specified the same for both ouput stage and bus timing. If series resistors (RS) are used, designers should allow for this when considering bus timing. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. IQ VIN Shutdown Current (A) 60 55 50 45 40 -40 -20 0 20 40 60 80 100 Temperature (C) 120 140 160 EN = 2 V EN = 0 V USB Port(s) not connected Figure 7-1. IQ VIN Shutdown Current vs Temperature Figure 7-2. IQ VIN Standby Current vs Temperature 9 8.7 VEN(CLAMP) 8.4 8.1 VIN = 6.8 V VIN = 13.5 V VIN = 18 V 7.8 7.5 7.2 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 Figure 7-3. ENABLE/UVLO Thresholds vs Temperature Figure 7-4. EN Clamp Voltage vs Temperature Figure 7-5. EN Leakage Current vs Temperature Figure 7-6. VIN(UVLO) vs Temperature 160 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 21 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. 19.5 4.71 4.7 4.69 4.68 Voltage (V) Voltage (V) 19 18.5 4.67 4.66 4.65 4.64 4.63 VIN VIN VIN VIN 4.62 RISING FALLING 18 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 4.61 4.6 -40 160 0 20 40 60 80 Temperature (C) 6.8 V, 125 mA 6.8 V, 0 mA 13.5 V, 0 mA 18 V, 0 mA 100 120 140 Figure 7-7. VIN(OVP) vs Temperature Figure 7-8. LDO_5V vs VIN and Temperature Figure 7-9. LDO_5V Current Limit vs VIN and Temperature Figure 7-10. LDO_3V3 vs VIN and Temperature 58 1.59 1.58 1.57 55 Voltage (V) ILIMIT (mA) 56 54 53 1.56 1.55 1.54 1.53 52 VIN VIN VIN VIN 1.52 51 50 -40 160 1.6 VIN = 6.8 V VIN = 13.5 V VIN = 18 V 57 1.51 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 7-11. LDO_3V3 Current Limit vs VIN and Temperature 22 -20 = = = = 1.5 -40 -20 0 20 40 60 80 Temperature (C) 100 = = = = 6.8 V, 10 mA 6.8 V, 0 mA 13.5 V, 0 mA 18 V, 0 mA 120 140 160 Figure 7-12. LDO_1V5 vs VIN and Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. 22 ILIMIT (mA) 21.5 21 20.5 20 19.5 -40 VIN = 6.8 V VIN = 13.5 V VIN = 18 V -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 7-13. LDO_1V5 Current Limit vs VIN and Temperature Figure 7-14. VTVSP_PU vs Temperature 40 1.51 35 30 RDS(ON) (m) ITVSP(ILIMIT) (mA) 1.5 1.49 1.48 25 M1 M2 M4 M3+M5 20 15 10 1.47 5 1.46 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 0 -40 -20 0 20 40 60 80 100 Temperature (C) 120 140 160 Figure 7-15. ITVSP(ILIMIT) vs Temperature Figure 7-16. Buck-Boost Power FET RDS(ON) vs Temperature Figure 7-17. Boost Peak Current Limit vs Temperature (upper settings) Figure 7-18. Boost Peak Current Limit vs Temperature (lower settings) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 23 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. Figure 7-19. Buck Peak Current Limit vs Temperature (upper settings) Figure 7-20. Buck Peak Current Limit vs Temperature (lower settings) -3.8 -3.85 INEG(BUCK) (A) -3.9 -3.95 -4 -4.05 -4.1 -4.15 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 7-21. Buck Negative Current Limit vs Temperature Figure 7-22. BOOTx UVLO vs Temperature 5.6 1.4 5.55 1.2 5.5 VOV_BOOT (V) 5.4 VOV_BOOT1_R VOV_BOOT1_F VOV_BOOT2_R VOV_BOOT2_F 5.35 5.3 5.25 fsw variation (%) 1 5.45 0.8 0.6 0.4 0.2 5.2 0 5.15 -0.2 5.1 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 -0.4 -40 -20 Figure 7-23. BOOTx OVP vs Temperature 0 20 40 60 80 Temperature (C) 100 120 140 160 Percentage Change from Nominal Figure 7-24. Buck-Boost Switching Frequency Variation vs Temperature 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. VSNS = (VCSP - VCSN) (mV) 11.5 VSNS = 10 mV, VBUS = 3 V VSNS = 10 mV, VBUS = 12 V VSNS = 10 mV, VBUS = 20 V 11 10.5 10 9.5 9 8.5 -40 -20 Figure 7-25. fSW Dither Modulation Frequency vs Temperature 0 20 40 60 80 Temperature (C) 100 120 140 160 Target VSNS for Current Limit = 10 mV Current Limiting Engaged Figure 7-26. Current Loop Regulation Voltage vs VBUS and Temperature 52.5 VSNS = 30 mV, VBUS = 3 V VSNS = 30 mV, VBUS = 12 V VSNS = 30 mV, VBUS = 20 V 31 30.5 30 29.5 29 VSNS = 50 mV, VBUS = 3 V VSNS = 50 mV, VBUS = 12 V VSNS = 50 mV, VBUS = 20 V 52 VSNS = (VCSP - VCSN) (mV) VSNS = (VCSP - VCSN) (mV) 31.5 51.5 51 50.5 50 49.5 49 48.5 48 28.5 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 47.5 -40 160 -20 Target VSNS for Current Limit = 30 mV Current Limiting Engaged 20 40 60 80 Temperature (C) 100 120 140 160 Target VSNS for Current Limit = 50 mV Current Limiting Engaged Figure 7-27. Current Loop Regulation Voltage vs VBUS and Temperature Figure 7-28. Current Loop Regulation Voltage vs VBUS and Temperature 150 500 Gain Gain Gain Gain = = = = 0.025V/A; 0.050V/A; 0.075V/A; 0.100V/A; VSNS = VSNS = VSNS = VSNS = 10 10 10 10 mV mV mV mV 100 50 Gain = 0.025V/A; VSNS = 50 mV Gain = 0.050V/A; VSNS = 50 mV 450 VOUT vs (VCSP - VCSN) (mV) VOUT vs (VCSP - VCSN) (mV) 0 400 350 300 250 200 150 0 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 Figure 7-29. Cable Voltage Droop Compensation vs Temperature 160 100 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 7-30. Cable Voltage Droop Compensation vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 25 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. 25 500 20 400 350 VBUS (V) VOUT vs (VCSP - VCSN) (mV) 450 300 250 15 10 200 5 150 100 -40 Gain = 0.075V/A; VSNS = 50 mV Gain = 0.100V/A; VSNS = 50 mV -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 7-31. Cable Voltage Droop Compensation vs Temperature 0 0 0.5 VIN = 13.5 V 1 1.5 2 IBUS (A) VBUS = 20 V (CV) 2.5 3 3.5 ILIMIT = 3.15 A (CC) Figure 7-32. Constant Voltage to Constant Current Transition Figure 7-34. VBUS Discharge Current vs Temperature IBUS = 0 A Figure 7-33. Buck-boost Output Voltage Regulation vs Temperature 24.45 Frequency (MHz) 24.35 24.25 24.15 24.05 23.95 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 Figure 7-35. (M0) 24 MHz Oscillator vs Temperature 26 160 Figure 7-36. (M0) 100 kHz Oscillator vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. Figure 7-37. Type-C Cable Detect: IRp vs Temperature Figure 7-38. Type-C Cable Detect: RSNK vs Temperature Figure 7-39. VCONN Power Path: RDS(ON) vs Temperature Figure 7-40. VCONN Power Path: Current Limit vs Temperature Figure 7-41. Type-C Cable Detect & VCONN: Over-voltage Protection Thresholds vs Temperature Figure 7-42. USB BC1.2: DP to DM Shorting Resistance, RDCP_DAT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 27 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 7.17 Typical Characteristics (continued) At VIN = 12 V, fsw = 400 kHz, unless otherwise stated. 23 22 Resistance (k) 21 20 19 18 17 16 -40 Figure 7-43. USB BC1.2: DM to AGND 15 kΩ Resistance, RDM_DWN_15k -20 0 20 40 60 80 Temperature (C) 100 120 140 Figure 7-44. USB BC1.2: DM to AGND 20 kΩ Resistance, RDM_DWN_20k 4 3.5 Output Voltage (V) 3 2.5 VOH VOL 2 1.5 1 0.5 0 -40 -20 Figure 7-45. USB BC1.2: DP and DM Pin Over-voltage Protection Thresholds vs Temperature 0 20 40 60 80 Temperature (C) 100 120 140 GPIO 0, 1, 4, 7, 8, 9 IO = ±2 mA Figure 7-46. GPIO: Output Voltage vs Output Current and Temperature Figure 7-48. GPIO: Input Voltage Thresholds vs Temperature GPIO 2, 3, 5, 6 IO = ±5 mA Figure 7-47. GPIO: Output Voltage vs Output Current and Temperature 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 8 Parameter Measurement Information tf SDA tr tSU;DAT 70 % 30 % 70 % 30 % cont. tHD;DAT tf tVD;DAT tHIGH tr 70 % 30 % SCL 70 % 30 % 70 % 30 % tHD;STA 70 % 30 % cont. tLOW 9th clock 1 / fSCL S 1st clock cycle tBUF SDA tSU;STA tHD;STA tVD;ACK tSP tSU;STO 70 % 30 % SCL Sr P S 9th clock Figure 8-1. I2C 002aac938 Slave Interface Timing VPU From Output Under Test 1 M PU 1M CL Push-Pull Load Circuit  V  5.5 V RPU From Output Under Test CL 1.65 V Open-Drain Load Circuit Internal Signal from M0 Internal Signal from M0 tprop_delay 90% GPIOx Output VOH 90% GPIOx Output 10% 10% tr tprop_delay_z tprop_delay 90% 90% 10% VOL tf tf GPIO Push-Pull Output Timing Diagram 10% VPU
0V tr GPIO Open-Drain Output Timing Diagram GPIO Input tsu th VOH Internal Signal to M0 VOL GPIO Input Timing Diagram Figure 8-2. GPIO Output Timing Diagram (rise/fall vs capacitive load) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 29 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 tFALL_EP tRISE_EP VOH 90% 10% VOL 90% 10% Figure 8-3. USB Endpoint Transmitter Rise and Fall Time V OH Differential Data Lines VCRS VCRS VOL (a) Output Crossover Voltage 2.0 V Differential Data Lines VCRS VCRS 0.8 V (b) Input Crossover Voltage Figure 8-4. USB Endpoint Crossover Voltages 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 9 Detailed Description 9.1 Overview The TPS25762-Q1 is a fully-integrated AEC-Q100 USB Power Delivery (USB-PD) source intended for use in 12-V automotive battery systems. Input supply pin, VIN, must be connected to a load dump clamped battery supply, VBAT, and never exceed 40 V (ABS MAX). The device consists of seven sub-blocks: USB-PD controller; Type-C cable plug and orientation detection circuitry; USB Endpoint; USB Battery Charging Specification Version 1.2 (BC1.2) detection circuitry; digital core; device power management and supervisory circuitry; and a buck-boost converter integrated with 4 power switches. The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the Px_CC1 pin or the Px_CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and more detailed circuitry, see USB-PD Physical Layer. The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features and more detailed circuitry, see Cable Plug and Orientation Detection. A USB Endpoint is included for downloading configuration information and firmware updates. When enabled by firmware, the USB Endpoint connects to the Port A DP and DM pins. The USB BC1.2 sub-block contains circuitry to support legacy USB charging methods which signal on the USB DP and DM data lines including: DCP, Divider-3, 1.2 V mode, and HVDCP. See BC 1.2, legacy and fast charging modes (Px_DP, Px_DM). The power management and supervisory circuitry generates the LDO_5V, LDO_3V3, and LDO_1V5 voltage rails used by the device. LDO_5V supplies the LDO_3V3 and LDO_1V5 rails. For a high-level block diagram of the power management circuitry, a description of its features and more detailed operation, see Internal LDO Regulators section. The digital core contains an ARM Cortex-M0 with 160-kB ROM and 27-kB RAM memory. The ROM contains firmware code to execute device functionality. RAM stores application configuration code created using the Graphical User Interface (GUI) and post-manufacturing firmware updates. The digital core is the engine for autonomously managing the system including: USB port connection status and communication; system power budget and allocation; system thermal monitoring and load shedding; and fault detection and reporting. All devices contain one controller I2C port (I2C1) for controlling external peripherals such as external EEPROM memory; DC/DC converters; USB data multiplexers/redrivers; GPIO expanders; and additional temperature sensors. Some devices include an I2C target port (I2C2) for connection to an external processor, HUB or embedded controller. An integrated 8-bit analog-to-digital converter ADC (see the ADC section), monitors USB port telemetry information. USB port connection status, voltage, current and fault information can be read from I2C2 target port. For a high-level block diagram of the digital core and a description of its features, see the Digital Core section. The integrated buck-boost converter is the PA_VBUS power source. It operates in buck mode when VIN is greater than VOUT and boost mode when VIN is less than VOUT. When VIN and VOUT are nearly the same, it operates in transition mode. Single Port Device TPS25762-Q1 is a single USB-PD port device. Refer to Device Comparison Table for dual port options. The TPS25762-Q1 device consists of a single 3 to 21 V output internal buck-boost converter, one USB-PD port controller providing cable plug and orientation detection, one internal VCONN source path, legacy USB Battery Charging Specification v1.2 Dedicated Charging Port (DCP) as well as legacy (non-USB compliant) charger detection including: Divider-3, 1.2 V, and HVDCP modes. The TPS25762-Q1 device communicates with its connected USB Type-C cable and downstream USB device at the opposite end of the cable to determine connection state and enables VBUS sourcing as appropriate. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 31 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 9.2 Functional Block Diagram BOOT1 SW2 SW1 BOOT2 BUCK BOOST IN OUT CSP LDO_5V ENABLE, LDOs, BIAS, VCONN SUPPLY PA_CABLE DET & VCONN LDO_1V5 MUXes I/O BUFFERS, PD PHY (Port A) CSN/VBUS PA_CC1 PA_CC2 PA_DP | GPIO8 PA_DM | GPIO7 LDO_3V3 SYNC | GPIO6 M0 NFET CHARGE PUMPS TVSP LDO_3V3 NTC ADC CONFIG, ESD, STBUS/STBAT IRQ | GPIO9 I2C_SCL1 I2C_SDA1 Type-C Connector CURRENT SENSE, CURRENT LIMIT, CABLE COMPENSATION EN/UVLO NTC | GPIO5 GPIO0 MUXes, I/O BUFFERS I2C PORT 1 CONTROLLER IRQ2(o) | GPIO1 GPIO2 | I2C_SCL2 GPIO3 | I2C_SDA2 PA_LSGD AGND I2C PORT 2 TARGET PGND 9.3 Feature Description 9.3.1 Device Power Management and Supervisory Circuitry 9.3.1.1 VIN UVLO and Enable/UVLO The TPS25762-Q1 has one internally fixed VIN UVLO and one user programmable UVLO using the EN/UVLO pin. Both thresholds must be cleared for the device to start up. • The fixed VIN(UVLO) has a rising threshold between 5 and 5.5 V to ensure internal circuits have sufficient headroom for proper operation. • The EN/UVLO pin provides the user with a resistor programmable UVLO threshold and master enable / disable for the device. The EN/UVLO pin has three distinct voltage ranges: shutdown, standby, and operating. When the EN/UVLO pin is below the standby threshold VEN(STBY), the device is disabled in a low power shutdown. When EN/UVLO voltage is greater than the standby threshold VEN(STBY) but less than the operating threshold VEN(OPER), the internal bias rails, LDO_5V, LDO_3V3, and LDO_1V5 regulators are enabled but remaining device functions are disabled. When EN/UVLO is greater than the operating threshold VEN(OPER) and LDO_5V, LDO_3V3 and LDO_1V5 regulators are above their respective undervoltage threshold UVLO thresholds, the device is fully functional. The EN/UVLO pin includes fixed hysteresis between the shutdown mode and the standby mode. 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 EN/UVLO VEN(OP) VLDO_5V(UVLO_R) LDO_5V VLDO_3V3(UVLO_R) LDO_3V3 VLDO_1V5(UVLO_R) LDO_1V5 3-4 ms M0 Disabled Enabled trim enabled Figure 9-1. EN/UVLO and LDO Sequencing Table 9-1. EN/UVLO and LDO_UVLO Operation EN/UVLO (1) LDOs DEVICE OPERATION VEN/UVLO < VEN(LDO_V5V_F) — Shutdown: LDO_5V, LDO_3V3 and LDO_1V5 OFF. M0 (MCU) is OFF. VEN(LDO_V5V_R) < VEN/UVLO < VEN(STBY) — Standby: LDO_5V, LDO_3V3 and LDO_1V5 ON. M0 (MCU) is OFF. VEN/UVLO > VEN(OPER) LDO_5V < VLDO_5V(UVLO_R), or LDO_3V3 < VLDO_3V3(UVLO_R); or LDO_1V5 < VLDO_1V5(UVLO_R) LDO_5V, LDO_3V3 and LDO_1V5 ON, M0 (MCU) is OFF. VEN/UVLO > VEN(OPER) LDO_5V > VLDO_5V(UVLO_R), and LDO_3V3 > VLDO_3V3(UVLO_R), and LDO_1V5 > VLDO_1V5(UVLO_R) Operating: M0 (MCU) is ON. (1) Valid when VIN > VIN(UVLO_R). In some cases an input UVLO level different than that provided by the internal VIN(UVLO) is needed. This can be accomplished by using the circuit shown in UVLO Threshold Programming. The input voltage at which the device turns on is designated VON; while the turnoff voltage is VOFF. First a value for RENB is chosen in the range of 13 kΩ to 22 kΩ. Use Equation 1 and Equation 2 to calculate RENT and VOFF. V RENT = V ON − 1 × RENB EN OPER (1) The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by: VEN HYS VOFF = 1 − V EN OPER × VON (2) VIN RENT EN/UVLO RENB AGND Figure 9-2. UVLO Threshold Programming Where • VON = VIN turn-on voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 33 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 • VOFF = VIN turn-off voltage Note: Ensure RENT ≥ 47 kΩ If the programmable UVLO is not required, the EN/UVLO pin can be connected to the IN pin with a 47 kΩ, or larger, resistor. 9.3.1.2 Internal LDO Regulators Three internal LDOs provide regulated supplies for operation of internal circuitry. • LDO_5V: Supplies buck-boost gate drive circuitry, LDO_3V3, LDO_1V5, and PA and PB VCONN power paths. External bypass capacitance, CLDO_5V is required for proper operation. It is highly recommended to include an additional high frequency 0.1 μF capacitor in parallel with CLDO_5V. CLDO_5V and the parallel high frequency should be placed as close to the LDO_5V pin as possible. This capacitance: 1) provides energy storage for the buck-boost internal FET gate drivers, and 2) is required to stabilize the internal 5-V LDO in applications where an external 5-V supply is not connected. The TPS25762-Q1 will not operate (release reset) until VLDO_5V(UVLO_R) threshold is met. Hard reset occurs when VLDO_5V < VLDO_5V(UVLO_F) threshold. Current from LDO_5V returns to PGND pin. The LDO_5V output may be used to supply a small external loads such as indicator LEDs. When supplying external components, it is recommended that the total external load current not exceed 25 mA (MAX). – 0.1W VCONN: when enabled in the application configuration GUI, LDO_5V is capable of sourcing 20 mA each to PA_VCONN and PB_VCONN. – 1W VCONN: when enabled in the application configuration GUI, this mode of operation requires an external 4.75 - 5.5 V, 500-mA capable supply connected to LDO_5V. Back-feeding of LDO_5V is allowed. • LDO_3V3: Supplies internal analog circuits, GPIO buffers, USB PD and the USB Endpoint PHYs. External bypass capacitance of CLDO_3V3 is required for proper operation. An additional 0.1 μF capacitor in parallel with CLDO_3V3 is highly recommended to filter high frequency noise from the I/O buffers and PHYs. The LDO_3V3 can supply external circuits at up to 25 mA. Expected loads include: EEPROM (5mA), NTC resistor divider network (< 1 mA). Current may be drawn up to ILDO_3V3(ILIMIT). Note: the USB PD and Endpoint PHYs draw current from LDO_3V3. If a CCx or Dx pin is shorted to GND during a transmission the current drawn may reach the current limit threshold. Similarly, if any GPIO pins are configured as push-pull outputs and a GPIO short to GND event occurs, the LDO_3V3 current limit may be reached. Current returns to AGND pin. • LDO_1V5: Supplies digital core. External bypass capacitance of CLDO_1V5 is required for proper operation. An additional 0.1 μF capacitor in parallel with CLDO_1V5 is highly recommended to filter noise generated by the digital core. The M0 is held in reset until all three UVLO_R (rising) thresholds are met. Current returns to AGND pin. 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VIN LDO_5V (125mA) LDO_5V PGND LDO_3V3 (25 mA) LDO_3V3 GND LDO_1V5 (10 mA) LDO_1V5 GND Note: LDO_5V max regulation current includes LDO_3V3 (25 mA) and LDO_1V5 (10 mA) Figure 9-3. Internal LDO Connection Diagram 9.3.2 TVSP Device Configuration and ESD Protection The Transient Voltage protection and firmware Setting Pin (TVSP) has three functions: 1) Boot configuration settings; 2) USB connector pin short to VBUS or VBAT protection; and 3) USB connector pin enhanced ESD protection. • RTVSP: At power on, the resistance between the TVSP pin and PGND determines the boot method, USB PD port I2C addresses and I2C logic thresholds. Refer to Table 9-3. The most common configuration is shown in Figure 9-4 with RTVSP open, corresponding to TVSP Index 0. During device initialization and boot, typically within 4 seconds after power on, VIN must be above 7.6 V to ensure proper bias of the TVSP pin to 5.5 V. Once boot is complete the device can operate over the full VIN range. • CTVSP: A 0.1-µF capacitor (CTVSP) must be connected to PGND. Place CTVSP as close to the TVSP pin as possible to minimize parasitic inductance. CTVSP is part of the centralized protection circuitry fortifying connector pins Px_CCy, Px_DP and Px_DM from damage during short to VBUS, VBAT and ESD events. A 40-V 0.1-µF capacitor is recommended for proper operation of the internal TVSP regulator circuit. • TVSP Damper Network: Capacitance, CDAMP, and resistance, RDAMP, form an RC network preventing excessive current from flowing inside the device durging connector pin over-voltage and ESD events. – CDAMP: A 0.47-µF capacitor must be connected in series with RDAMP to PGND. A 40-V 0.47-µF capacitor is recommended. – RDAMP: A 10-Ω resistor must be connected in series with CDAMP to PGND. A 0.25-W rating is recommended. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 35 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO5V Px_DP ESD BC1.2 Functions Bias ~5.5V PGND ESD Px_DM RDAMP CTVSP Px_CC1 ESD I mirror to ADC 1 k: TVSP_PD_EN CDAMP 0.47 PF 0.1 PF RTVSP 10 : TVSP USB PD Functions ESD Px_CC2 Recommended component values PGND Figure 9-4. Basic TVSP Pin Connection Table 9-2. Recommended TVSP Components CTVSP RDAMP CDAMP 0.1 μF 10 Ω 0.47 μF Table 9-3. RTVSP Configuration Settings TVSP Index ADC Value I2C Target Port (2) Addresses (A | B) I2C Logic (VDD) Open 0 ≤ 10 (0x0A) 0x22 | 0x26 3.3 V EEPROM 93.1 1 ≤ 24 (0x18) 0x23 | 0x27 3.3 V External HUB/MCU 47.5 2 ≤ 42 (0x2A) 0x22 | 0x26 1.8 V EEPROM 29.4 3 ≤ 63 (0x3F) 0x23 | 0x27 1.8 V External HUB/MCU 20.0 4 ≤ 89 (0x59) 0x23 | 0x27 3.3 V EEPROM 14.7 5 ≤ 119 (0x77) 0x22 | 0x26 3.3 V External HUB/MCU RTVSP (kΩ) (1) (2) (1) Boot Mode 11.0 6 ≤ 156 (0x9C) 0x23 | 0x27 1.8 V EEPROM 8.45 7 ≤ 201 (0xC9) 0x22 | 0x26 1.8 V External HUB/MCU 6.65 8 ≤ 255 (0xFF) 0x22 | 0x26 3.3 V Firmware Update 1% resistor required. 0x22h = 0100010; 0x26h = 0100110; 0x23h = 0100011; 0x27 = 0100111 Device firmware can be updated using the USB Endpoint on the PA_DP and PA_DM pins. To enable firmware update mode, boot the device with a resistance corresponding to Index 8 between TVPS and PGND. A boot cycle can be performed by power cycling the device or by pulling the EN/UVLO pin momentarily below VEN(OPER) threshold. An example circuit to enable USB Endpoint firmware update mode is shown in Figure 9-5 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO5V Px_DP ESD PGND USB Endpoint Firmware Update Mode TVSP ESD Px_DM Px_CC1 CTVSP RDAMP CDAMP RTVSP = {index 8} BC1.2 Func
ons Bias ~5.5V ESD I mirror to ADC TVSP_PD_EN 1 k
USB PD Func ons ESD Px_CC2 PGND Figure 9-5. Example Circuit to Enable USB Endpoint Firmware Update Mode 9.3.3 Buck-Boost Regulator 9.3.3.1 Buck-Boost Regulator Operation The TPS25762-Q1 devices utilize a fixed frequency, current mode control buck-boost converter. This converter operates in forced continuous conduction mode (CCM) and therefore allows inductor current to flow in either direction at light loads. The power train consists of five N-Channel power MOSFETs. See Figure 9-6. Transistors M1 and M2 are the high-side and low-side buck FETs. Transistors M3 and M4 are the high-side and low-side boost FETs. Transistor M5 blocks reverse conduction from OUT to SW2 during input overvoltage transients as explained in VIN Supply and VIN Over-Voltage Protection. • IN: Receives power from the battery. The input bulk capacitor must be connected between IN and PGND. • OUT: Delivers power from the switching converter. The output bulk capacitor connects between OUT to PGND. • PGND: Ground return for the switching converter power train. • AGND: Ground return for everything except the power train. The voltage feedback divider returns to AGND. PGND and AGND must connect together on the circuit board. • LDO_5V: Provides gate drive for M2 and M4 and current for the bootstrap circuits feeding BOOT1 and BOOT2. A bypass capacitor must connect from LDO_5V to PGND. See Internal LDO Regulators for more information on LDO_5V. • LDO_3V3: Analog circuitry power supply. A bypass capacitor must connect from LDO_3V3 to AGND. See Internal LDO Regulators for more information on LDO_3V3. • BOOT1: Provides gate drive for M1. A bootstrap capacitor must connect from BOOT1 to SW1. • BOOT2: Provides gate drive for M3. A bootstrap capacitor must connect from BOOT2 to SW2. • SW1: Connects M1 and M2 to external inductor. • SW2: Connects M3 and M4 to external inductor. • CSP: Positive terminal of average current sense amplifier. Connects to positive terminal of output bulk capacitor. • CSN/BUS: Negative terminal of average current sense amplifier. A 10-mΩ current sense resistor is externally connected from CSP to CSN/BUS. Depending upon the input voltage VIN and the output voltage VOUT, the converter can operate in one of four different states, each of which is described in following sections. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 37 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 M1 M3 M5 IN OUT M2 M4 PGND Figure 9-6. Buck-Boost Internal Power FETs Buck State When the input voltage VIN significantly exceeds the output voltage VOUT, the converter enters the buck region of operation in which it performs an endless series of buck switching cycles Buck State. M3 and M5 are constantly on and M4 is constantly off. When the clock signals that a switching cycle has begun, the controller turns on M2 and turns off M1. This switch configuration corresponds to the off-time interval of a traditional buck converter. The voltage difference VSW1 – VSW2 across the inductor equals –VOUT. The inductor current IL ramps down until it reaches a threshold IVALLEY set by the error amplifiers. The controller then turns off M2 and turns on M1. This switch configuration corresponds to the on-time interval of a traditional buck converter. The voltage difference VSW1 – VSW2 now equals VIN – VOUT. The inductor current now ramps up until the converter clock signals that the end of the switching cycle has been reached. The on-time ton equals the time interval during which M1 conducts. The off-time toff equals the time interval during which M2 conducts. Because the converter operates in FCCM, the period τ equals the sum of ton and toff. During the buck state, the controller regulates power flow by adjusting the buck duty cycle D, which equals the ratio ton/τ. 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VSW1 t VSW2 VIN t VOUT t t VOUT IL IVALLEY t toff ton • Figure 9-7. Buck State Buck Transition State When the input voltage VIN is only slightly larger than the output voltage VOUT, the converter enters the buck transition region of operation in which it alternately performs buck and boost switching cycles Buck Transition. M5 is always on. When the clock signals that a buck switching cycle has begun, the controller turns on M2 and M3, and it turns off M1 and M4. This switch configuration corresponds to the off-time of a traditional buck converter. The inductor current IL ramps down until it reaches a threshold IVALLEY set by the error amplifiers. The controller then turns off M2 and turns on M1. This switch configuration corresponds to the on-time of a traditional buck converter. The inductor current now ramps up slowly until the clock signals the end of the buck switching cycle. The next switching cycle is a boost switching cycle. When this cycle begins, the controller turns M3 off and turns M4 on. M2 remains off, and both M1 and M5 remain on. This switch configuration corresponds to the on-time of a traditional boost converter. The inductor current IL now ramps up rapidly until the fixed on-time expires. The controller then turns off M4 and turns on M3. The inductor current now ramps down until the clock signals the end of the boost switching cycle. The next switching cycle will be another buck cycle. During the buck transition state, the controller regulates power flow by adjusting the buck duty cycle. The boost duty cycle remains fixed. If the converter had remained in the buck state rather than move to the buck transition Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 39 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 state, the buck on-time would have become so short that it would have become impossible to regulate power flow without pulse skipping. VSW1 t VSW2 VIN VIN t VOUT t t VOUT IL IVALLEY t toff ton • Buck tB • Boost Figure 9-8. Buck Transition Boost Transition State When the input voltage VIN is only slightly smaller than the output voltage VOUT, the converter enters the boost transition region of operation in which it alternately performs boost and buck switching cycles Boost Transition. M5 is always on. When the clock signals that a boost switching cycle has begun, the controller turns on M1 and M4, and it turns off M2 and M3. This switch configuration corresponds to the on-time of a traditional boost converter. The inductor current IL ramps up until it reaches a threshold IPEAK set by the error amplifiers. The controller then turns off M4 and turns on M3. This switch configuration corresponds to the off-time of a traditional boost converter. The inductor current now ramps down slowly until the clock signals the end of the boost switching cycle. The next switching cycle is a buck switching cycle. When this cycle begins, the controller turns M1 off and turns M2 on. M4 remains off, and both M3 and M5 remain on. This switch configuration corresponds to the off-time of a traditional buck converter. The inductor current IL now ramps down rapidly until the fixed off-time expires. The controller then turns off M2 and turns on M1. The inductor current now ramps up until the clock signals the end of the buck switching cycle. The next switching cycle will be another boost cycle. 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 During the boost transition state, the controller regulates power flow by adjusting the boost duty cycle. The buck duty cycle remains fixed. If the converter had remained in the boost state rather than move to the boost transition state, the boost on-time would have become so short that it would have become impossible to regulate power flow without pulse skipping. VSW1 t VSW2 VIN t VIN t VOUT t VOUT IL IPEAK t ton toff • Boost tE • Buck Figure 9-9. Boost Transition Boost State When the input voltage VIN is significantly less than the output voltage VOUT, the converter enters the boost region of operation in which it performs an endless series of boost switching cycles Boost State. M1 and M5 are constantly on and M2 is constantly off. When the clock signals that a switching cycle has begun, the controller turns on M4 and turns off M3. This switch configuration corresponds to the on-time interval of a traditional boost converter. The voltage difference VSW1 – VSW2 across the inductor equals VIN. The inductor current IL ramps up until it reaches a threshold IPEAK set by the error amplifiers. The controller then turns off M4 and turns on M3. This switch configuration corresponds to the off-time interval of a traditional boost converter. The voltage difference VSW1 – VSW2 now equals VIN – VOUT, which is negative. The inductor current now ramps down until the converter clock signals that the end of the switching cycle has been reached. The on-time ton equals the time interval during which M4 conducts. The off-time toff equals the time interval during which M3 conducts. Because the converter operates in FCCM, the period τ equals the sum of ton and toff. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 41 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 During the boost state, the controller regulates power flow by adjusting the boost duty cycle D, which equals the ratio ton/τ. VSW1 t VSW2 VIN t VIN t VOUT IL IPEAK t ton toff • Figure 9-10. Boost State Boundaries of the Regions of Operation Regions of Operation graphically depicts the four regions of operation and the boundaries between them. When VBUS > kVIN, the converter remains in the boost region of operation. The value k is 1.2. When VIN < VBUS < kVIN, the converter enters the boost transition region of operation. When VIN/k < VBUS < VIN, the converter enters the buck transition region of operation. When VBUS < VIN/k, the converter enters the buck region of operation. The converter will cease operating if VIN exceeds the OVP threshold, which lies between 18 and 20 V. Similarly, the converter will also cease operating if VIN drops below either the internal UVLO threshold, which lies between 5 and 5.5 V, or the user programmed EN/UVLO threshold (see VIN UVLO and ENABLE/UVLO, whichever is greater). 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VBUS=kVIN VBUS VIN=VBUS ion 21V Bo o st tra n si t Boost n ra i si t on VIN=kVBUS kt uc B Buck VIN UVLO OVP Figure 9-11. Regions of Operation 9.3.3.2 Switching Frequency, Frequency Dither, Phase-Shift and Synchronization The PWM oscillator frequency (fsw) is programmed by firmware using the application configuration GUI. The switching converter is intended for operation below the AM radio band (520 kHz - 1730 kHz). Three nominal fsw settings below are available: 300 kHz, 400 kHz and 450 kHz. Frequency dithering can be enabled by firmware via the application GUI. When enabled, the nominal oscillator frequency is dithered by ±FSSS (approximately ±10%) using triangular waveform modulation (see Dithering using triangular waveform modulation). The dither period τM is the reciprocal of the dither modulation frequency FSSS_MOD. Two firmware selectable dither modulation frequencies FSSS_M are available: 10 and 25 kHz. Dithering spreads the spectral peaks generated by switching, thereby reducing the peak harmonic levels and easing EMI filter design. f 1.1fs fs 0.9fs t WM Figure 9-12. Dithering Using Triangular Waveform Modulation Multiple converters can be synchronized using the SYNC pin. This pin can be firmware-configured as either an output SYNC(o) or an input SYNC(i). • SYNC(o): The switching clock is placed on the SYNC(o) pin. This waveform will have a duty cycle of approximately 50%. If frequency dithering is configured by firmware, this signal will also exhibit dithering. Four phase settings are available by firmware configuration to shift the SYNC(o) output relative to the internal switching clock by 0°, 90°, 120°, or 180°. SYNC(o) is used to slave other DC/DC converter clocks to the switching converter clock inside the TPS25762-Q1. When two dc/dc converters operate out of phase, peak input current from the battery is reduced and total input bulk capacitance requirements decrease. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 43 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Internal PWM Clock Falling SWx edge triggers on rising edge of internal PWM clock Internal SWx node(s) period ~50% duty SYNC(o) 0º phase shift 90º SYNC(o) 90º phase shift 120º SYNC(o) 120º phase shift 180º SYNC(o) 180º phase shift Figure 9-13. SYNC(o) Phase Shift SYNC(o) Other DC/DC Converter TPS257xx-Q1 • Figure 9-14. Using SYNC(o) to slave DC/DC Converter SYNC(i): The internal clock is synchronized to the pulse train on the SYNC(i) pin. This feature is used to slave the TPS25762-Q1 to an external clock. The period of this clock must meet synchronization requirements in SYNC(i) frequency ranges or the TPS25762-Q1 will instead use its internal switching clock. If an external clock deviates outside of the acceptable frequency range and then returns to within the acceptable frequency range, the TPS25762-Q1 will resume operation from the external clock after counting 8 consecutive clocks meeting the criteria of Table 9-4. When SYNC(i) is configured, frequency dithering is disabled when operating from the internal clock following a failure of the external clock. Table 9-4. SYNC(i) Frequency Ranges fSW Firmware Setting Allowed SYNC(i) Frequency Range MIN 44 Submit Document Feedback MAX Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 9-4. SYNC(i) Frequency Ranges (continued) fSW Firmware Setting Allowed SYNC(i) Frequency Range 300 kHz 250 kHz 353 kHz 400 kHz 334 kHz 470 kHz 450 kHz 376 kHz 530 kHz 9.3.3.3 VIN Supply and VIN Over-Voltage Protection VIN Supply The voltage VIN at the input supply pin IN, measured with respect to AGND, must meet the following requirements: • Overvoltage: The voltage VIN must never exceed an absolute maximum of 40 V, and should not exceed 36 V under anticipated operating conditions. Automotive applications will typically require an external transient suppressor to meet this requirement. • Load dump: When the converter is running and VIN exceeds 18 V, the positive slew rate dVIN/dt must not exceed 200 V/ms. • Double battery: When the converter is not running, the positive slew rate dVIN/dt must not exceed 10 V/µs. The input EMI filter can help mitigate input voltage slew rates. • Reverse battery: The voltage VIN must never go below –0.3 V. Automotive applications will typically require external reverse voltage blocking circuitry. The buck-boost switching converter is capable of delivering its full rated output power of 65 W over an input supply range 6.8 V < VIN < 18 V . The input voltage can dip down to the UVLO threshold providing that the output power level is appropriately derated. VIN Overvoltage Protection Circuitry The TPS25762-Q1 contains circuitry that protects the power train against load dump and double battery conditions. When VIN exceeds about 19 V, a comparator determines that an input overvoltage condition has occurred. This comparator sends a signal that shuts the switching converter down. Transistors M1, M2, and M3 in Buck-Boost Internal Power FETs are turned off, and transistor M4 is turned on. However, current is still flowing through the inductor. Two cases may exist: the current may flow forward (from SW1 to SW2) or in reverse (from SW2 to SW1). Reverse current flow will forward-bias the body diode of M1. The voltage across the inductor will then equal the sum of the forward voltage of this diode plus the input voltage, which is sufficient to cause the inductor voltage to rapidly ramp down to zero. Forward current flow will forward-bias the body diode of M2. After the inductor current is released, a small linear regulator biases SW1 to about 15 V. When the overvoltage condition is removed, the switching regulator may resume operation. 9.3.3.4 Feedback Paths and Error Amplifiers The TPS25762-Q1 includes not only a programmable voltage feedback path, but also a programmable average current feedback path that can be used to limit the average current provided by the switching converter to the USB cable. The voltage feedback path also includes provision for cable droop compensation. Figure 9-15 shows a simplified block diagram of the relevant portions of the integrated circuit. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 45 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 CSN/BUS A1 A2 RF1 CSP CSN/BUS Avg Current Ampli
er RF2 Voltage EA I1 I1 A3 Vcomp I2 A4 8 icode MAX COMP 1V IDAC RC1 Current EA CC2 12 vcode CC1 VDAC RF3 Figure 9-15. Simplified block diagram of feedback paths and error amplifiers. 9.3.3.5 Transconductors and Compensation The TPS25762-Q1 is internally compensated. The overall slope compensation and loop compensation is internally fixed based on inductor and capacitance values shown in Table 10-1. 9.3.3.6 Output Voltage DAC, Soft-Start and Cable Droop Compensation The buck-boost output voltage is regulated at the CSN/VBUS pin. A 12-bit digital-to-analog converter, VDAC, provides ±20-mV step voltage adjustments of VCSP/BUS as commanded by device firmware. After a successful cable detect event, firmware sets the VDAC to output 5 V as measured on the VCSN/BUS output. An internal clock steps up the VDAC codes from an initial 0 V to final 5-V setting producing a monotonic ramp of VCSN/BUS to 5 V at tSS. In some applications, the USB-PD controller may be located 1 m, or more, from the USB receptacle. When configured and enabled by firmware, cable droop compensation will increase the VCSP/BUS linearly with increasing load current independent of the VDAC setting. Four selectable VOUT_CDC ranges are available. 500 mV is the maximum supported cable droop voltage and it is disabled by default during USB-PD PPS contracts. 9.3.3.7 VBUS Overvoltage Protection A fixed threshold overvoltage comparator monitors the CSN/BUS pin for overvoltage conditions. When the VCSN/BUS_OVP_R threshold is exceeded, output OV protection circuitry turns off the internal MOSFETs. Switching resumes when VCSN/BUS decreases below VCSN/BUS_OVP_F. 46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 + Buck-Boost State Machine – CSN/BUS VCSN/BUS_OVP ADC M0 Figure 9-16. VBUS OVP and UVP 9.3.3.8 VBUS Undervoltage Protection PA_VBUS undervoltage conditions are monitored by the internal ADC. In accordance with USB Power Delivery specifications, the TPS25762-Q1 firmware configures the threshold based on USB PD contract with the attached sink device. 9.3.3.9 Current Sense Resistor (RSNS) and Current Limit Operation The CSP and CSN/BUS pins are the positive and negative inputs to the average current sense amplifier (CSA). The TPS25762-Q1 devices sense port A load current across sense resistor, RSNS, located between the CSP and CSN/BUS pins. A 10-mΩ, 1%, power resistor provides a 0 - 50-mV sense voltage over the range 0 ≤ IOUT ≤ 5 A. A seven bit digital-to-analog converter, IDAC, provides ±50-mA step current limit adjustments and is automatically programmed by device firmware. 9.3.3.10 Buck-Boost Peak Current Limits The buck and boost peak current limits are adjustable by firmware using the application configuration GUI. Refer to the BUCK-BOOST PEAK CURRENT LIMITS in Section 7.6 of the Electrical Characteristics tables for selectable values. In most applications it is desirable to limit input current to the automotive USB module to protect module components, connectors and wiring from over-current conditions. The worst case input current condition occurs when VIN is minimum and VCSN/BUS is maximum (21 V) while supplying maximum 3.25 A output current. When VIN < VBUS, the internal DC/DC converter is operating in boost mode. Refer to the Table 10-6 tables in the Inductor Currents section to estimate the peak current versus recommended inductor value for the application. The buck peak current limit setting selection should be just lower than the boost peak current limit. Set as close to the boost peak current limit as selections allow to prevent the possibility of limit cycling between the two peak current limits under extreme transients. IPEAK(BUCK) ≅ IPEAK(BOOST). When selecting an inductor, it is important select one with an appropriate saturation current rating, IL(SAT). The inductor IL(SAT) rating should larger than the maximum (MAX) IPEAK(BOOST) limit from the Electrical Characteristics tables to avoid excessive current flow in the TPS25762-Q1 or the inductor. 9.3.4 USB-PD Physical Layer Figure 9-17 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block. This block applies to Port A. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 47 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO_3V3 IRp RSNK Px_CC1 Digital Core USB-PD PHY (Rx/Tx) Px_CC2 LDO_3V3 IRp RSNK Figure 9-17. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry USB-PD messages are transmitted in a USB Type-C system using a BMC (Biphase Mark Coding) signaling. The BMC signal is output on the same pin (Px_CC1 or Px_CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism discussed in the USB-PD BMC Transmitter section. 9.3.4.1 USB-PD Encoding and Signaling Figure 9-18 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 9-19 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Encoder Data BMC Encoder to PD_TX CRC Figure 9-18. USB-PD Baseband Transmitter Block Diagram from PD_RX BMC Decoder SOP Detect Data 4b5b Decoder CRC Figure 9-19. USB-PD Baseband Receiver Block Diagram 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 9.3.4.2 USB-PD Bi-Phase Marked Coding The USB-PD physical layer implemented in the TPS25762-Q1 is compliant to the USB-PD Specifications. The encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity (limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 9-20 illustrates Biphase Mark Coding. 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 Data in BMC Figure 9-20. Biphase Mark Coding Example The USB PD baseband signal is driven onto the Px_CC1 or Px_CC2 pin with a tri-state driver. The tri-state driver controls slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the final bit of EOP. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise and fall times. Refer to the USB-PD Specifications for more details. 9.3.4.4 USB-PD BMC Transmitter The TPS25762-Q1 transmits and receives USB-PD data over one of the Px_CCy pins for a given CC pin pair (one pair per USB Type-C port). The Px_CCy pins are also used to determine the cable orientation (see the Cable Plug and Orientation Detection section) and maintain cable/device attach detection. Thus, a DC bias exists on the Px_CCy pins. The transmitter driver overdrives the Px_CCy DC bias while transmitting, but returns to a Hi-Z state allowing the DC voltage to return to the Px_CCy pin when not transmitting. While either Px_CC1 or Px_CC2 may be used for transmitting and receiving, during a given connection only the one that mates with the CC pin of the plug is used; so there is no dynamic switching between Px_CC1 and Px_CC2. Figure 9-21 shows the USB-PD BMC TX and RX driver block diagram. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 49 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO_3V3 PD_TX Level Shifter Driver Px_CC1 + PD_RX Level Shifter Px_CC2 ± Digitally Adjustable VREF (VRXHI, VRXLO) USB-PD Modem Figure 9-21. USB-PD BMC TX/Rx Block Diagram Figure 9-22 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere between the minimum threshold for detecting a UFP attach and the maximum threshold for detecting a Sink attach to a Source. This means that the DC bias can be above or below the VOH of the transmitter driver. VOH DC Bias DC Bias VOL DC Bias VOH DC Bias VOL Figure 9-22. TX Driver Transmission with DC Bias The transmitter drives a digital signal onto the Px_CCy lines. The signal peak, VTXHI, is set to meet the TX masks defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable. When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the noise ingression in the cable. RDRIVER ZDRIVER Driver CDRIVER Figure 9-23. ZDRIVER Circuit 9.3.4.5 USB-PD BMC Receiver The receiver block of the TPS25762-Q1 receives a signal that falls within the allowed Rx masks defined in the USB PD specification. The receive thresholds and hysteresis come from this mask. 50 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Figure 9-24 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has the typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one system can be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach detection. Source System Sink System Pullup for Attach Connector Detection Connector Cable CC wire Tx Tx CRECEIVER CRECEIVER Rx Rx CCablePlug_CC CCablePlug_CC RD for Attach Detection Rx Tx 623¶ 3' communication only (eMarker #1) Rx Tx 623¶¶ 3' communication only (eMarker #2) Figure 9-24. Example USB-PD Multi-Drop Configuration 9.3.4.6 Squelch Receiver The TPS25762-Q1 has a squelch receiver to monitor for the bus idle condition as defined by the USB PD specification. The squelch receiver output reflects the state of the CC pin regardless of the source of the transmission. 9.3.5 VCONN Internal VCONN sourcing power paths are firmware configurable. Using only the internal LDO_5V supply, PortA is able to draw 20 mA continuously. If an external 5-V regulator is connected to the LDO_5V pin and the application GUI settings are enabled, PortA is able to draw 200 mA continuously. When disabled, blocking FETs in the PortA VCONN paths protect the LDO_5V rail from high-voltage and reverse current. When VCONN power is enabled and provided, the internal VCONN power switches have a current limit of ILIMVC. If the VCONN load current exceeds ILIMVC, the current clamping circuit activates within tiOS_PP_CABLE and the switch behaves as a constant current source. Reverse current blocking is disabled when current is flowing to Px_CC1 or Px_CC2. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 51 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Px_CC1 Gate Control TSD_Px_VCONN Fast current limit, ILIMVC LDO_5V Px_CC1 Px_CC2 Gate Control Temp Sensor Px_CC2 Figure 9-25. VCONN Power Switches When operating in current limit, the VCONN FET temperature rises. Local temperature sensors disable the Px_VCONN path in current limit when Tsensor > TSD_Px_VCONN within tPP_CABLE_off. The application firmware enters USB Type-C Error Recovery on the affected port. LDO_5V must remain above its under voltage lock out threshold (VLDO_5V(UVLO_F)) for Px_VCONN operation. If the VLDO_5V(UVLO_F) threshold is reached, Px_VCONN paths are automatically disabled within tPP_CABLE_off. 9.3.6 Cable Plug and Orientation Detection Figure 9-26 shows the plug and orientation detection block at each Px_CCy pin (PA_CC1, PA_CC2, PB_CC1, PB_CC2). Each CC pin has identical detection circuitry. When the port is operating as a Type-C source, the VREFx nodes are multiplexed to the VSRC thresholds corresponding to the advertised Type-C source capability current, IRp_. When the port is operating as a Type-C sink, the VREFx nodes are multiplexed to the VSNK thresholds corresponding to sink detection. 52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO_5V LDO_3V3 IRpSTD IRp1.5 IRpSTD_5 IRp1.5 IRp3.0 VREF1 Px_CCy VREF2 RSNK VREF3 Figure 9-26. Plug and Orientation Detection Block 9.3.6.1 Configured as a Source When either of the PA or PB ports is configured as a Source, the device detects when a cable or a Sink is attached using the Px_CC1 and Px_CC2 pins. When in a disconnected state, the device monitors the voltages on these pins to determine what, if anything, is connected. See USB Type-C Specification for more information. Table 9-5 shows the Cable Detect States for a Source. Table 9-5. Cable Detect States for a Source Px_CC1 Px_CC2 CONNECTION STATE RESULTING ACTION Open Open Nothing attached Continue monitoring both Px_CCy pins for attach. Power is not applied to Px_VBUS or VCONN. Rd Open Sink attached Monitor Px_CC1 for detach. Power is applied to Px_VBUS but not to VCONN (Px_CC2). Open Rd Sink attached Monitor Px_CC2 for detach. Power is applied to Px_VBUS but not to VCONN (Px_CC1). Ra Open Powered Cable-No UFP attached Monitor Px_CC2 for a Sink attach and Px_CC1 for cable detach. Power is not applied to Px_VBUS or VCONN (Px_CC1). Open Ra Powered Cable-No UFP attached Monitor Px_CC1 for a Sink attach and Px_CC2 for cable detach. Power is not applied to Px_VBUS or VCONN (Px_CC2). Ra Rd Powered Cable-UFP Attached Provide power on Px_VBUS and VCONN (Px_CC1) then monitor Px_CC2 for a Sink detach. Px_CC1 is not monitored for a detach. Rd Ra Powered Cable-UFP attached Provide power on Px_VBUS and VCONN (Px_CC2) then monitor Px_CC1 for a Sink detach. Px_CC2 is not monitored for a detach. When a port is configured as a Source, a current IRp1.5A, is driven out of each Px_CCy pin and each pin is monitored for different states. When a Sink is attached to the pin a pull-down resistance of Rd to GND exists. The current IRp1.5A is then forced across the resistance Rd generating a voltage at the Px_CCy pin. The device applies the configured IRp1.5A until the buck-boost regulator is enabled and operating at 5 V, at which time application firmware may remain at IRp1.5A or change to IRp3.0A. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 53 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 When the Px_CCy pin is connected to an electronically marked cable VCONN input, the pull-down resistance is different (Ra). In this case the voltage on the Px_CCy pin will pull below VRDstd and the system recognizes the electronically marked cable. The VDstd1.5 or VD3.0 threshold is monitored to detect a disconnection depending upon which Rp current source is active. When a connection has been recognized and the voltage on Px_CCy subsequently rises above the disconnect threshold for tCC, the system registers a disconnection. Source monitors for connection Sink monitors for orientation USB Type-C Cable + IRp Rd CC IRp Ra Ra GND Rd GND GND TPS257xx-Q1 (Type-C source) Type-C Sink Figure 9-27. Type-C Cable 9.3.6.2 Configured as a Sink When the TPS25762-Q1 port is configured as a Sink, such as in Firmware Update Mode with TVSP Index 8, the device presents a pull-down resistance RSNK on each PA_CCy pin and waits for a Source to attach and pull-up the voltage on the pin. The Source pulls-up the PA_CCy pin by applying either a resistance or a current. The Sink detects an attachment by the presence of VBUS. The Sink determines the advertised current from the Source by the pull-up applied to the PA_CCy pin. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2) Comparators on the Px_CCy pins detect when the voltage on CC1 or CC2 is too high, or there is reverse current into the LDO_5V output. During an overvoltage event, VCONN is disabled within tPP_CABLE_FSD and the associated USB PD transmitter is disabled. max(VCC1, VCC2) ± VLDO_5V VVC_RCP LDO_5V Control Logic Disable PP_CABLE And USB PD PHY VVC_OVP Px_CC1 VPHY_OVP Px_CC2 VPHY_OVP Figure 9-28. Over-voltage and Reverse Current Protection 9.3.7 ADC The ADC is shown in Figure 9-29. The ADC is an 8-bit successive approximation ADC. The input to the ADC is an analog input mux that supports multiple inputs from various voltages and currents in the device. The output from the ADC is available to be read and used by application firmware. 54 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 IN Voltage Divider 4 PA_VBUS Voltage Divider 2 PB_VBUS | GPIO4 Voltage Divider 2 LDO_5V Voltage Divider 3 LDO_3V3 Voltage Divider 1 8 bits Input Mux ADC PA_DM | GPIO7 PA_DP | GPIO8 Buffers & Voltage Divider 1 PB_DP | GPIO2 PB_DM | GPIO3 NTC | GPIO5 I_PA_VBUS I-to-V I_TVSP I-to-V Figure 9-29. SAR ADC ADC output 8h 7h 6h 5h 4h 3h 2h LSB 1h 0h VIN Figure 9-30. ADC Conversion 9.3.7.1 ADC Divider Ratios The ADC voltage inputs are each divided down to the full-scale input of 1.2 V. The ADC current sensing elements are not divided. Table 9-6 shows the divider ratios for each ADC input. The application firmware may select any group of channels to be auto-sequenced in the round robin automatic readout mode. Table 9-6. ADC Inputs CHANNEL SIGNAL TYPE DIVIDER RATIO BUFFERED 0 1 I_TVSP Current n/a No IN Voltage 17 No 2 LDO_3V3 Voltage 3 No 3 PA_VBUS Voltage 21 No Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 55 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 9-6. ADC Inputs (continued) CHANNEL SIGNAL TYPE DIVIDER RATIO BUFFERED 4 GPIO4 | PB_VBUS Voltage 21 No 5 IPA_VBUS Current n/a No 6 GPIO2 | PB_DP Voltage 3 Yes 7 GPIO3 | PB_DM Voltage 3 Yes 8 GPIO5 | NTC Voltage 3 Yes 9 GPIO7 | PA_DM Voltage 3 Yes 10 GPIO8 | PA_DP Voltage 3 Yes 11 LDO_5V Voltage 5 No 9.3.8 BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM) BC 1.2 downstream port charger emulation is application GUI configurable. The following charging modes can be enabled or disabled: • • • • DCP (Dedicated Charging Port) Shorted Mode Divider-3 Mode 1.2-V Mode HVDCP (High Voltage Dedicated Charging Port) Mode The following table shows voltage sources, resistors and comparator hardware used in each mode. Symbol "X" represents that the corresponding module is implemented. Application 2.7-V SRC 1.2-V SRC RDCP_DAT DCP RDM_DWN (20 kΩ) VDAT_REF VSEL_REF X X X X Divider-3 X 1.2 V X X HVDCP BC1P2 DCP & Legacy Charging HVDCP OVP COMPARATORS VDAT_REF + VSEL_REF dp_ovp + RDCP_DAT dm_ovp + SW Px_DP Digital Core MUX dm_ovp SW Px_DM R_2.7V R_2.7V + R_1.2V dm_ovp VSEL_REF + VDAT_REF + RDM_DWN (20k) V_2.7V V_1.2V Figure 9-31. BC1P2 Functional Diagram 9.3.9 USB2.0 Low-Speed Endpoint The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based accesses. The TPS25762-Q1 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 host during firmware update mode. Firmware update mode is entered with when the device is powered on with an RTVSP corresponding to TVSP Index 8. Figure 9-32 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the Serial Interface Engine, and the Endpoint FIFOs and supports low-speed USB operation. 56 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO_3V3 SW RPU_EP To Digital Core 32 EP_TX_DP EP0 TX/RX FIFO Serial Interface Engine Digital Core Interrupts and Control RX/TX Status Control EP_TX_DM RS_EP + PA_DP RS_EP - PA_DM + EP_RX_RCV EP_RX_DP EP_RX_DM Transceiver Figure 9-32. USB Endpoint PHY The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– through a source resistance RS_EP. RPU_EP is disconnected during transmit mode of the transceiver. When the endpoint is in receive mode, the resistance RPU_EP is connected to the PA_DM pin. The RPU_EP resistance advertises low speed mode only. 9.3.10 Digital Interfaces The TPS25762-Q1 contains one I2C controller which used for communicating with I 2C target devices. Depending upon application GUI firmware configuration, an I2C target and GPIOs may be available. 9.3.10.1 General GPIO An application configuration GUI manages the multi-function pins which contain General Purpose Input/Output functionality. Each buffer is configurable to be a push-pull output or open drain output. When configured as an input, the signal can be a de-glitched digital input or an analog input to the ADC (only designated pins). The push-pull output is a simple CMOS totem-pole structure. Independent pull-up and pull-down enables can be configured using the application GUI. When interfacing with non 3.3-V I/O devices the output buffer should be configured as an open drain output and an external pull-up resistor attached to the GPIO pin. 9.3.10.2 I2C Buffer The TPS25762-Q1 features two I2C interfaces that each use an I2C I/O driver like the one shown in Figure 9-33. This I/O consists of an open-drain output and an input comparator with de-glitching. deglitch SCL/SDA Digital Core GND Figure 9-33. I2C Driver Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 57 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 9.3.11 I2C Interface The TPS25762-Q1 has two I2C ports. I2C1 is a controller interface. I2C2 is a target interface. I2C1 is used to read from or write to external target devices. During boot I2C1 is configured to read firmware patch and application configuration data from an external EEPROM with target address 0x50. Depending upon application configuration, the TPS25762-Q1 may expose target port, I2C2, using multi-function pins: GPIO2 (I2C_SCL2), GPIO3 (I2C_SDA2). When the TPS257xx-Q1 is used in systems with a HUB or MCU, the I2C2 port can provide connection status and telemetry information as well as transfer firmware updates from the HUB or MCU to an EEPROM connected on I2C1. IRQ functionality depends upon firmware application configuration. IRQ is not always available on both I2C1 and I2C2 simultaneously. the IRQ is available as follows: • Multi-function pin GPIO9: IRQ1(i), IRQ1(o), IRQ2(o) • Multi-function pin GPIO1: IRQ2(o) Where (i) = operates as an input, and (o) = operates as output. In HUB applications where I2C control is not used, GPIO9 can be configured as a simple FAULT pin reporting port over-current conditions as required by the USB 2.0 specifications. Table 9-7. I2C Summary I2C Bus Type Typical Usage Max Bus Frequency I2C I2C1c I2C2t Connect to EEPROM, USB Type-C mux, I2C temperature sensor, I2C Controller GPIO expander, or other I2C target. Use LDO_5V or LDO_3V3 pin as the pull-up voltage. Multi-controller configuration is not supported. Target Connect to I2C capable USB HUB, MCU or automotive processor. 1 MHz (Fast Mode Plus) 1 MHz (Fast Mode Plus) 9.3.11.1 I2C Interface Description The I2C1 and I2C2 ports support Standard, Fast Mode, and Fast Mode Plus I2C interfaces. The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor. Data transfer may be initiated only when the bus is not busy. A controller sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as changes in the data line at this time are interpreted as control commands (Start or Stop). The controller sends a Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high. Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met to ensure proper operation. A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the target. The controller receiver holding the SDA line high does this. In this event, the target transmitter must release the data line to enable the controller to generate a Stop condition. Figure 9-34 shows the start and stop conditions of the transfer. Figure 9-35 shows the SDA and SCL signals for transferring a bit. Figure 9-36 shows a data transfer sequence with the ACK or NACK at the last clock pulse. 58 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 SDA SCL S P Start Condition Stop Condition Figure 9-34. I2C Definition of Start and Stop Conditions SDA SCL Data Line Figure 9-35. Change I2C Bit Transfer Data Output by Transmitter Nack Data Output by Receiver SCL From Master Ack 1 2 8 9 S Clock Pulse for Acknowledgement Start Condition Figure 9-36. I2C Acknowledgment 9.3.11.2 I2C Clock Stretching Clock stretching for I2C2. The target I2C port may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The controller communicating with the target must not finish the transmission of the current bit and must wait until the clock line actually goes high. When the target is clock stretching, the clock line remains low. The controller must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for standard 100-kbps I2C) before pulling the clock low again. Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit. 9.3.11.3 I2C Address Setting A HUB, MCU, or automotive processor host should only use I2C_SCL2 and I2C_SDA2 for loading a firmware patches or general status communication. Once the boot process is complete, each I2C port is assigned a unique target address as determined by the TVSP pin. The target address used by each port on the I2C2s bus are determined from the application configuration. 9.3.11.4 Unique Address Interface The Unique Address Interface allows for complex interaction between an I2C controller and a single TPS25762Q1. The I2C target sub-address is used to receive or respond to Host Interface protocol commands. Figure 9-37 and Figure 9-38 show the write and read protocol for the I2C target interface, and a key is included in Figure Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 59 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 9-39 to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part. 1 7 1 1 8 1 8 1 8 1 S Unique Address Wr A Register Number A Byte Count = N A Data Byte 1 A 8 1 8 1 Data Byte 2 A Data Byte N A P Figure 9-37. I2C Unique Address Write Register Protocol 1 7 1 1 8 1 1 7 1 1 8 1 S Unique Address Wr A Register Number A Sr Unique Address Rd A Byte Count = N A 8 1 8 1 8 1 Data Byte 1 A Data Byte 2 A Data Byte N A P 1 Figure 9-38. I2C Unique Address Read Register Protocol 1 7 1 1 8 1 1 S Slave Address Wr A Data Byte A P x x S Start Condition SR Repeated Start Condition Rd Read (bit value of 1) Wr Write (bit value of 0) x Field is required to have the value x A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK) P Stop Condition Master-to-Slave Slave-to-Master Continuation of protocol Figure 9-39. I2C Read/Write Protocol Key 9.3.11.5 I2C Pullup Resistor Calculation Typical value for RP, the I2C pullup resistor is given by: RP = tr / (0.8473 × Cb) Refer to Table 9-8 for values of tr, Cb and VOL. Table 9-8. Parametrics from I2C Specifications Standard Mode (Max) Fast Mode (Max) Fast Mode Plus (Max) Unit SCL clock frequency 100 400 1000 kHz Rise time of both SDA and SCL signals 1000 300 120 ns Capacitive load for each bus line 400 400 550 pF Parameter fSCL tr Cb 60 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 9-8. Parametrics from I2C Specifications (continued) Standard Mode (Max) Fast Mode (Max) Fast Mode Plus (Max) Unit Low-level output voltage (at 3-mA current sink, VDD > 2 V) 0.4 0.4 0.4 V Low-level output voltage (at 2-mA current sink, VDD ≤ 2 V) – 0.2 × VDD 0.2 × VDD V Parameter VOL For additional background regarding I2C pullup resistor calculations, please refer to application report, I2C Bus Pullup Resistor Calculation. 9.3.12 Digital Core Figure 9-40 shows a simplified block diagram of the digital core. GPIO0-9 I2C to HUB, MCU, or Automotive processor Memory I2C_SDA2 I2C Port 2 (target) I2C_SCL2 Processor IRQ MUX I2C_IRQx Digital Core I2C to EEPROM, PB_DC/DC, USB redrivers I2C_SDA1 CBL_DET Bias CTL and USB-PD USB PD Phy I2C Port 1 (controller) I2C_SCL1 Buck-Boost Control OSC Buck-Boost Converter ADC Read Thermal Shutdown Temp Sense ADC Figure 9-40. Digital Core Simplified Block Diagram 9.3.12.1 Device Memory The digital core contains a combination of ROM, SRAM, and OTP. ROM and SRAM function as the storage and operational space for application firmware. OTP contains boot configuration settings. There are 27 kBytes of SRAM, 160 kBytes of ROM, and 512 bytes of OTP. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 61 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 9.3.12.2 Core Microprocessor The digital core is an ARM M0+ clocked at 24MHz with zero wait states. 9.3.13 NTC Input The NTC pin is used by the device firmware to monitor system temperature. Rising or falling voltages on the NTC pin indicate increasing or decreasing system temperatures, respectively. To achieve a positive temperature slope on the TPS25762-Q1 NTC pin, thermistors should be connected to LDO_3V3 as shown in Figure 9-41. LDO_3V3 LDO_3V3 RNTC RBIAS NTC NTC ADC ADC RTMP61 RBIAS (b) NTC Connection (a) TI TMP61 Sensor Figure 9-41. Thermistor Connections (a) PTC, (b) NTC See Figure 9-42 and Figure 9-43. Using the application configuration GUI, the user can configure system power policy management responses for up to three VNTC voltages. LDO_3V3 VNTC RNTC 3.3V RNTC VNTC T (°C) VNTC_Ph3_R VNTC_Ph3_F VNTC_Ph2_R VNTC_Ph2_F VNTC_Ph1_R VNTC_Ph1_F RBIAS 0V 25 50 75 100 125 T (°C) Figure 9-42. NTC Response Curve 62 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 LDO_3V3 VNTC 3.3V RBIAS VNTC RTMP61 VNTC_Ph3_R VNTC_Ph3_F VNTC_Ph2_R VNTC_Ph2_F VNTC_Ph1_R VNTC_Ph1_F RTMP61 0V 25 50 75 100 125 T (°C) T (°C) Figure 9-43. TMP61 PTC Response Curve Note For optimum accuracy, use the VLDO_3V3 specifications in Electrical Characteristics tables when performing resistor divider calculations. 9.3.14 Thermal Sensors and Thermal Shutdown There are five internal thermal sensors in the TPS25762-Q1 devices: • TSD_BB. Two diode OR'ed thermal sensors to monitor buck-boost power FETs. Disables buck-boost regulator when asserted. USB-PD engine enters error recovery. • TSD_PA_VCONN. One thermal sensor located in the PA_VCONN path. Opens PA_VCONN FET during overtemperature event. USB-PD engine enters error recovery. • • TSD_PA_VBUS_DISCH. One thermal sensor located in the PA_VBUS discharge path. Opens PA_VBUS discharge FET during over-temperature. Closes PA_VBUS discharge FET when temperature decreases below falling hysteresis. (TSD_HYS) if PA_VBUS is above discharge threshold set by firmware during decreasing VBUS transition. • TSD_LDO5V. One thermal sensor located in the LDO_5V regulator. Operates as master thermal shutdown. Disables device completely during over-temperature events causing M0 to hard reset. Allows device operation when temperature decreases below falling hysteresis (TSD_HYS). 9.4 Device Functional Modes Shutdown Mode The EN/UVLO pin provides electrical ON and OFF control for the TPS25762-Q1. When VEN/UVLO is below 1.15 V (typ), the device is in shutdown mode in which the Cortex M0 is disabled and only minimal analog functions are operating. Refer to VIN UVLO and Enable/UVLO section for the detailed description of the EN/UVLO pin functionality. Active Mode The TPS25762-Q1 enters active mode when VEN/UVLO is above its rising threshold, VEN(OPER), and the supply voltage on the IN pin is above the VIN undervoltage lockout threshold, VIN(UVLO_R). In active mode, the internal analog circuits are fully operational with the M0 enabled and executing firmware from ROM. At the onset of active mode, firmware boot code will attempt to measure the resistance on the TVSP pin and decode a TVSP Index value. Upon successful configuration and firmware patch load, the device is ready to begin operation per configuration settings stored on the external EEPROM. If the configuration and patch data do not load successfully due to communications error the device will continue to operate with only Port A enabled with standard Type-C functionality. Index value 8 is reserved for use when updating device configuration Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 63 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 and firmware patch information through the TPS25762-Q1 GUI and Port A connection. Once device boot is complete, device firmware will control and manage USB connections in accordance with loaded application configuration settings. 64 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 10.1 Application Information The TPS25762-Q1 application GUI provides default settings suitable for most applications. The most common implementations are dual port USB PD charger and dual port USB PD with USB HUB. Consult the TPS2576x, TPS2577x Configuration GUI User's Guide and application GUI for additional configurations. Battery EN LDO5V LDO3V3 LDO1V5 AGND TVSP FW Update PGND PA_CC1 PA_CC2 GPIO7 GPIO8 CSN/BUS CSP OUT SCL2 SDA2 SYNC IRQ SCL1 SDA1 PORT A IN ON OFF TYPE-C CONNECTOR VBAT 3-21V 3V3 LS_GD NTC GPIO0 GPIO1 Figure 10-1. Simplified Single USB PD Charger VBAT 5V EN SYNC LDO_5V BUCK SYNC FW Update TVSP 3V3 3V3 LDO LDO_3V3 LDO_1V5 DP AGND DM MCU/HUB IRQ SCL2 SDA2 PGND PA_CC1 PA_CC2 GPIO7 GPIO8 CSN/BUS CSP OUT FAULT DP DM PORT A Battery OFF TYPE-C CONNECTOR IN ON 3V3 LSGD NTC TMP61 SCL1 SDA1 GPIO0 GPIO1 Figure 10-2. Simplified Single USB PD with MCU/HUB Typical Application describes a detailed step-by-step design procedure for a typical charger application circuit. 10.2 Typical Application Figure 10-3 Shows a typical example of a 65 W output automotive USB Type-C Power Delivery port. The device is internally compensated and optimized for components shown in Table 10-1. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 65 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 CBOOT1 CSNB RSNB RSNB RBOOT2 RBOOT1 RSNB RSNB L CBOOT2 CSNB PGND PGND SW1 BOOT1 LFILT FB CFILT1 CFILT2 7 ~ 18V CFILT3 CFILT4 CIN_BULK CIN TVS SW2 M1 CIN_HF IN BOOT2 M3 M2 M5 CSN/BUS M4 RCSN CFILT RCSP PGND RENT CSP FB PGND 0.1 µF LM74700 PGND RSNS = 10 m
OUT EN/UVLO PGND COUT_HF RENB PGND COUT CBUS PGND AGND PGND 5V AGND LDO_5V C5V C5V_HF 330 pF AGND AGND 330 pF PA_CC1 PGND RFW_UPDATE RTVSP_DAMP TVSP ESD AGND AGND ESD ESD AGND AGND PA_DP PA_DM CTVPS_REG PA_LSGD CTVPS_DAMP FW UPDATE ESD AGND PA_CC2 USB TYPE-C CONNECTOR (Port A) Input Overvoltage Protection, Reverse Polarity Protection and EMI Filter 3V3 3V3 LDO_3V3 RB AGND RP RP C3V3_HF RP C3V3 PGND I2C_SCL1 CBYP I2C_SDA1 TMP61 NTC 1V5 AGND EEPROM IRQ LDO_1V5 C1V5 GPIO0 C1V5_HF AGND GPIO1 I2C_SCL2 AGND I2C_SDA2 Figure 10-3. TPS25762-Q1 Application Schematic Table 10-1. Recommended Inductors, Input and Output Capacitance • 66 fSW CIN + CHF L MIN of COUT + CBUS COUT + CHF CBUS 300 22 µF + 2 × 0.1 µF 4.7 µH 160 µF 30 µF + 2 × 0.1 µF 130 µF + 2 × 0.1 µF 400 22 µF + 2 ×0.1 µF 4.7 µH 120 µF 30 µF + 2 × 0.1 µF 90 µF + 2 × 0.1 µF 400 22 µF + 2 × 0.1 µF 3.3 µH 140 µF 30 µF + 2 × 0.1 µF 110 µF + 2 × 0.1 µF 450 22 µF + 2 × 0.1 µF 3.3 µH 140 µF 30 µF + 2 × 0.1 µF 110 µF + 2 × 0.1 µF 50 V rated capacitors recommended. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 26 27 HF_CAP 28 29 HF_CAP 25 2 24 3 23 5 22 IN SW1 SW2 OUT 4 PGND 1 21 17 15 HF_CAP BOOT1 16 HF_CAP 14 18 13 8 12 19 11 7 BOOT2 10 20 9 6 Inductor Figure 10-4. Input and Output CHF Capacitor Placement To ensure adequate decoupling of VIN and VOUT and robust device operation, use two 0.1 μF, CHF capacitors per node, placed on opposite sides of the IC package, as close to the pins as possible. Typically, the inductor is placed on the same PCB layer (top or bottom) as the IC package. The CHF capacitors on the inductor end of the IC package may be placed on the opposite side of the PCB (bottom or top) using vias to minimize trace length from the inductor side IN and OUT pins to the physical location of these capacitors. Table 10-2. Recommended SWx Snubber and Current Sense Filter Components SW1 (1) SW2 (2) CSP & CSN Filter (3) RSNB (0.25 W) CSNB (50 V) RSNB (0.25 W) CSNB (50 V) RCSP (0.1 W) RCSN (0.1 W) 2.2 Ω || 2.2 Ω 1 nf 2.2 Ω || 2.2 Ω 3.3 nF 10 Ω 0Ω CFLT (50 V) 0.22 μF 1. As needed for EMI mitigation - user optional. (Use of this snubber can also aid in supporting devices with high initial inrush load current that exceeds the power delivery specification.) 2. Required for robust device operation. 3. Required to meet USB-IF current regulation requirements. 10.2.1 Design Requirements For this example, Table 10-3 are used as the target parameters. Table 10-3. Design Inputs DESIGN PARAMETER EXAMPLE VALUE Input Voltage Range 6.8 V to 18 V (transients to 36 V) UVLO Turn on Voltage 6.5 V USB PD Power 65 W USB PD VBUS Voltages 5 V, 9 V, 15 V, 20 V and 3.3 to 21 V (PPS) Output 3.3 - 21 V Load Current PDO: 5 V, 3 A; 9 V, 3 A; 15 V, 3 A, 20 V, 3.25 A APDO: 3.3 - 21 V, 3 A Switching Frequency 400 kHz VCONN 0.1 W Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 67 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 10-3. Design Inputs (continued) DESIGN PARAMETER EXAMPLE VALUE Automotive Module Maximum Current 15 A 10.2.2 Detailed Design Procedure 10.2.2.1 Application GUI Selections Use the application GUI to select the desired operating conditions. Once complete, save the settings to the programming PC, flash the firmware to EEPROM, and power cycle device. Once complete the TPS25762-Q1 will be ready for operation. Table 10-4. Application GUI Selections PARAMETER GUI SELECTION BUCK-BOOST AND USB INPUTS Port A VBUS Power 65 W Port A PDOs and APDOs PDO: 5 V, 3 A; 9 V, 3 A; 15 V, 3 A; 20 V, 3.25 A APDO: 3.3 - 21 V, 3A Port A VCONN Power 0.1 W fSW Switching Frequency 400 kHz L Inductor 4.7 µH Automotive Module Maximum Current 15 A LOW BATTERY INPUTS Engine ON voltage 12.5 V Engine OFF voltage 11 V Run timer after engine off 600 seconds THERMAL MANAGEMENT INPUTS VNTC_PHASE1 1.65 V NTC_PHASE1 Power as Percentage of MAX 50 % VNTC_PHASE2 2.1 V NTC_PHASE2 Power as Percentage of MAX 30 % VNTC_PHASE3 2.4 V NTC_PHASE3 Power as Percentage of MAX 0 % (disable PA_VBUS) 10.2.2.2 EEPROM Selection An EEPROM is required to store user application configuration data as any firmware patch updates released by Texas Instruments during the life of the product. Basic requirements: • 32kB (256kb) • 7 Bit I2C address (0x50) • Organization: 32kb x 8 (totals 256kb) • Active firmware image is stored in one 16kb x 8 partition. The previous firmware image is retained in the other 16kb x 8 partition for reliability. • Page size/buffer should be 64b Table 10-5. Suggested EEPROMs Manufacturer 68 Part Number On Semi CAV24C256 Microchip 24LC256 ST Micro M24256 Rohm BRA24T512=3AM Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 10.2.2.3 EN/UVLO The TPS25762-Q1 has a fixed VIN(UVLO) with rising and falling thresholds between 5 and 5.5 V, refer to Section 7.6 for exact values. The falling threshold, VIN(UVLO_F), disables the device when the battery voltage is too low for continued operation. To establish a turn on voltage higher than VIN(UVLO_R), connect a resistor divider from the IN supply voltage to the EN/UVLO pin. When VEN/UVLO > VEN(OPER), nominally 1.25 V, the device exits low power shutdown and begins to startup. In this example a VIN turn on voltage of approximately 6.5 V is required. Use the equations and examples below to determine the required resistor values. • • Choose standard value RENB = 22 kΩ. Calculate RENT V RENT = V ON − 1 × RENB EN OPER • • (3) 6.5 V RENT = 1.25 V − 1 × 22 kΩ = 92.4 kΩ Select a standard value of 91 kΩ. Using 22 kΩ and 91 kΩ. Rearranging Equation 3 results in R VON = RENT + 1 × VEN OPER ENB • (6) Calculate VOFF VEN HYS × VON (7) 0.1 V VOFF = 1 − 1.25 V × 6.42 V = 5.91 V (8) Lastly, confirm the selected resistors do not trigger the EN/UVLO pin MAX clamp voltage. Assuming 36 V as a maximum VIN transient. VEN/UVLO MAX = • (5) VON = 91 kΩ 22 kΩ + 1 × 1.25 V = 6.42 V VOFF = 1 − V EN OPER • (4) VIN MAX × RENB RENT + RENB (9) 36 V × 22 kΩ VEN/UVLO MAX = 22 kΩ + 91 kΩ = 7 V (10) The result, 7 V, is less than the EN/UVLO pin maximum clamp voltage. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT The TPS25762-Q1 requires a 10-mΩ resistance between the CSP and CSN/BUS pins. For accurate current limit regulation, ±1% precision or better is required. For a DC output current of 3.25 A, the power dissipation in the resistor is I2R, or (3.25 A)² × 0.01 Ω = 0.106 W. A power resistor with 0.33-W rating, ± 1% tolerance and 2010 case is chosen. Check the manufacturers power derating curves when selecting the component. Most derate maximum power above 70°C. An RC filter network is required on the CSP and CSN/BUS pins for proper USB PD PPS current limit accuracy. A filter network with RCSP = 10 Ω, RCSN = 0 Ω, and filter capacitor, CFILT = 0.22 μF is recommended. Suggested RC filter component ratings are shown in Table 10-2. RCSN must be zero ohm to avoid interfering with the VBUS discharge functionality. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 69 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 CSN/BUS RCSN CFILT RCSP CSP RSNS = 10 m
OUT COUT_HF COUT CBUS To Type-C Connetor PGND PGND AGND AGND Figure 10-5. Current Sense Amplifier: RC Filter Components 10.2.2.5 Inductor Currents Table 10-1 lists recommended inductor values based on desired switching frequency, fSW. The following equations were used to derive the values in the Buck Calculation and Boost Calculation results tables below. DBUCK = VOUT VIN(MAX) × DBOOST = 1 - (11) VIN(MIN) × VOUT (12) where • • • • • • VIN(MAX) = maximum input voltage VIN(MIN) = minimum input voltage VOUT = output voltage DBUCK = minimum duty cycle for buck mode DBOOST = maximum duty cycle for boost mode η = estimated efficiency calculated at VIN, VOUT, and IOUT Buck Mode ISW_BUCK(MAX) = 'IL_BUCK(MAX) = 'IL_BUCK(MAX) 2 + IOUT (13) (VIN(MAX) - VOUT(MIN)) × DBUCK fSW × L (14) where • • • • 70 VIN(MAX) = maximum input voltage VOUT(MIN) = minimum output voltage IOUT = maximum DC output current ΔIL-BUCK(MAX) = maximum ripple current through the inductor when in buck operation Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com • • • • SLVSGL9 – DECEMBER 2022 ISW_BUCK(MAX) = maximum switch current when in buck operation DBUCK = minimum duty cycle for buck operation fSW = switching frequency of the converter L = selected inductor value IMAXOUT(BUCK) = IPEAK(BUCK) ± 'IL_BUCK(MAX) 2 (15) where • • • IMAXOUT(BUCK) = maximum deliverable current through inductor by the converter IPEAK(BUCK) = buck switch peak current limit from Electrical Characteristics table ΔIL_BUCK(MAX) = Ripple current through the inductor calculated in Equation 14. Boost Mode 'IL_BOOST(MAX) ISW_BOOST(MAX) = 2 + IOUT 1 ± DBOOST (16) VIN(MIN) × DBOOST 'IL_BOOST(MAX) = fSW × L (17) where • • • • • • • • VIN(MIN) = minimum input voltage VOUT(MAX) = desired output voltage IOUT = desired output current ΔIL_BOOST(MAX) = maximum ripple current through the inductor in boost operation ISW_BOOST(MAX) = maximum switch current in boost operation DBOOST = maximum duty cycle for boost operation fSW= switching frequency of the converter L = selected inductor value ( IMAXOUT(BOOST) = IPEAK(BOOST) ± 'IL_BOOST(MAX) 2 ) × (1 ± DBOOST) (18) where • • • • IMAXOUT(BOOST) = maximum deliverable current through inductor by the converter DBOOST = maximum duty cycle for boost mode IPEAK(BOOST) = boost switch peak current limit from from Electrical Characteristics table ΔIL_MAX(BOOST) = Ripple current through the inductor calculated in Equation 17. Buck Operation Table 10-6 provides the tabulated ΔIL_BUCK(MAX) and ISW_BUCK(MAX) for the conditions below. • • • • η = 0.95 VIN(MAX) = 18 V VOUT(MIN) = 3.3 V DBUCK(MIN) = 0.193 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 71 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 10-6. Buck Calculation Results (L = 4.7 µH), IBUS = 3 A fSW (kHz) IOUT (A) ΔIL_BUCK(MAX) (A) ISW_BUCK(MAX) (A) 300 3.00 2.87 4.44 400 3.00 2.15 4.08 450 3.00 1.91 3.96 300 3.00 2.01 4.01 400 3.00 1.51 3.76 450 3.00 1.34 3.67 Boost Operation Table 10-7 provides the tabulated ΔIL_BOOST(MAX), ISW_BOOST(MAX), suggested GUI IPEAK(BOOST) (MIN) settings for the maximum output power conditions shown below. If ISW_BOOST(MAX) > IPEAK(BOOST) (MIN) → VBUS dropout likely. If ISW_BOOST(MAX) < IPEAK(BOOST) (MIN) → VBUS regulates normally. • • • • η = 0.95 VIN(MIN) = 5.5 V to 9 V VOUT(MAX) = 21 V IOUT = 3 A To be noted, the calculation here uses 21V 3 A instead of 20 V 3.25A because 21 V 3A has bigger inductor peak current. Table 10-7. Boost Calculation Results (L = 4.7 µH), IBUS = 3 A fSW (kHz) 300 400 72 VIN(MIN) (V) DBOOST(MAX) ΔIL_BOOST(MAX) (A) ISW_BOOST(MAX) (A) GUI (1) IPEAK(BOOST) (A) 5.5 0.751 2.93 13.51 12.3 6 0.729 3.10 12.62 12.3 6.5 0.706 3.25 11.83 12.3 7 0.683 3.39 11.16 12.3 7.5 0.661 3.52 10.61 10.8 8 0.638 3.62 10.10 10.8 8.5 0.615 3.71 9.65 10.8 9 0.593 3.79 9.27 9.3 5.5 0.751 2.20 13.15 12.3 6 0.729 2.33 12.24 12.3 6.5 0.706 2.44 11.42 12.3 7 0.683 2.54 10.73 10.8 7.5 0.661 2.64 10.17 10.8 8 0.638 2.71 9.64 10.8 8.5 0.615 2.78 9.18 9.3 9 0.593 2.84 8.79 9.3 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 Table 10-7. Boost Calculation Results (L = 4.7 µH), IBUS = 3 A (continued) fSW (kHz) 450 (1) VIN(MIN) (V) DBOOST(MAX) ΔIL_BOOST(MAX) (A) ISW_BOOST(MAX) (A) GUI (1) IPEAK(BOOST) (A) 5.5 0.751 1.95 13.02 12.3 6 0.729 2.07 12.11 12.3 6.5 0.706 2.17 11.29 12.3 7 0.683 2.26 10.59 10.8 7.5 0.661 2.34 10.02 10.8 8 0.638 2.41 9.49 9.3 8.5 0.615 2.47 9.03 9.3 9 0.593 2.51 8.63 9.3 MIN value of boost peak ILIM shown. See electrical characteristics table for MIN, TYP, MAX values. 10.2.2.6 Output Capacitor In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is given by Equation 19 where the minimum VIN corresponds to the maximum capacitor current. ICOUT(RMS) IOUT u VOUT VIN 1 (19) In this example the maximum output ripple RMS current is ICOUT(RMS) = 3.18 A. A 5-mΩ output capacitor ESR causes an output ripple voltage of 34 mV as given by: 'VRIPPLE(ESR) IOUT u VOUT u ESR VIN(MIN) (20) A 140 µF output capacitor (COUT + CBUS) causes a capacitive ripple voltage of 26 mV as given by: 'VRIPPLE(COUT) VIN(MIN) · § IOUT u ¨ 1 ¸ VOUT ¹ © COUT u Fsw (21) Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current capacity. The complete schematic in Typical Application section provides COUT and CBUS recommendations suitable for most applications. 10.2.2.7 Input Capacitor In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given by: ICIN(RMS) IOUT D u (1 D) (22) The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT/2 = 1.5 A. A combination of ceramic and bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage ripple. Table 10-1 in the Typical Application section is a good starting point for CIN selection. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 73 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 10.2.3 Application Curves VOUT = 5 V 100 Efficiency 80 60 VIN VIN VIN VIN VIN = = = = = 7V 9V 12 V 15 V 18 V 40 0 0.3 0.6 0.9 1.2 1.5 1.8 IBUS (A) 2.1 2.4 2.7 3 L = 4.7 μH L = 4.7 μH Figure 10-6. Efficiency vs Output Current (IOUT), VOUT = 5 V Figure 10-7. Efficiency vs Output Current (IOUT), VOUT = 9 V VOUT = 15 V 100 Efficiency 80 60 VIN VIN VIN VIN VIN = = = = = 7V 9V 12 V 15 V 18 V 40 0 0.3 L = 4.7 μH 0.9 1.2 1.5 1.8 IBUS (A) 2.1 2.4 2.7 3 L = 4.7 μH Figure 10-8. Efficiency vs Output Current (IOUT), VOUT = 12 V Figure 10-9. Efficiency vs Output Current (IOUT), VOUT = 15 V IBUS = 3 A L = 4.7 μH L = 4.7 μH Figure 10-10. Efficiency vs Output Current (IOUT), VOUT = 20 V 74 0.6 Figure 10-11. Efficiency vs Input Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VIN = 13.5 V VBUS = 0 V to 5 V IBUS = 0 A Figure 10-12. Type-C Attach VIN = 13.5 V VBUS = 5 V to 0 V IBUS = 0 A Figure 10-13. Type-C Detach Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 75 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VIN = 7 V VBUS = 20 V IBUS = 0 A Figure 10-14. Boost Mode: Low VIN, No Load VIN = 7 V VBUS = 20 V IBUS = 3 A Figure 10-16. Boost Mode: Low VIN, 3 A Load VIN = 12 V VBUS = 20 V IBUS = 0 A Figure 10-18. Boost Mode: Nominal VIN, No Load VIN = 12 V VBUS = 5 V IBUS = 3 A Figure 10-20. Buck Mode: nominal VIN, 3 A Load 76 VIN = 18 V VBUS = 5 V IBUS = 0 A Figure 10-15. Buck Mode: High VIN, No Load VIN = 18 V VBUS = 5 V IBUS = 3 A Figure 10-17. Buck Mode: High VIN, 3 A load VIN = 12 V VBUS = 5 V IBUS = 0 A Figure 10-19. Buck Mode: Nominal VIN, No Load VIN = 12 V VBUS = 13 V IBUS = 0 A Figure 10-21. Buck-Boost Mode: VIN ≨ VBUS, No Load Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VIN = 12 V VBUS = 12 V IBUS = 0 A Figure 10-22. Buck-Boost Mode: VIN = VBUS, No Load VIN = 12 V VBUS = 12 V IBUS = 3 A Figure 10-24. Buck-Boost Mode: VIN = VBUS, 3 A Load VIN = 12 V VBUS = 15 V IBUS = 3 A Figure 10-26. Buck-Boost Mode: Nominal VIN, 3 A Load VIN = 12 V VBUS = 11 V IBUS = 0 A Figure 10-23. Buck-Boost Mode: VIN ≩ VBUS, No Load VIN = 12 V VBUS = 15 V IBUS = 0 A Figure 10-25. Buck-Boost Mode: Nominal VIN, No Load VIN 12 V ➔ 20 V Figure 10-27. VIN(OVP) Entry Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 77 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VIN 20 V ➔ 12 V VIN 12 V ➔ 20 V Figure 10-28. VIN(OVP) Recovery VIN = 13.5V VBUS = 5 V IBUS = 0 A Figure 10-29. VIN(OVP) Showing VBUS Discharge IBUS 0 A ➔ 3 A Figure 10-30. Load Transient (Buck): VBUS = 5 V VIN = 13.5V VBUS = 9 V IBUS 0 A ➔ 3 A Figure 10-31. Load Transient (Buck): VBUS = 9 V VIN 650 mV/div VIN 650 mV/div VBUS 650 mV/div VBUS 650 mV/div I_IN 1.48 A/div I_IN 1.1 A/d iv IBUS 558 mA/div IBUS 577 mA/div SW1 1.77 V/div SW1 650 mV/div SW2 1.93 V/div SW2 2.45 V/div VIN = 13.5V VBUS = 15 V IBUS 0 A ➔ 3 A Figure 10-32. Load Transient (Buck-Boost): VBUS = 15 V 78 VBUS = 0 V VIN = 13.5V VBUS = 20 V IBUS 0 A ➔ 3 A Figure 10-33. Load Transient (Boost): VBUS = 20 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 VIN 12 V VBUS = 20 V VIN 1.62 V/div VBUS 650 mV/div IBUS 98.3 mA/d iv SW1 2.72 V/div SW2 3.01 V/div ILIMIT = 3.1 A Figure 10-34. Current Limit: Stepped Resistive Load VIN 7 V ➔ 18 V VBUS = 20 V IBUS = 3 A Figure 10-35. Line Transient: VBUS = 20 V VIN VIN 1.61 V/div VBUS 650 mV/div IBUS 86.1 mA/d iv SW1 2.63 V/div SW2 2.32 V/div VIN 7 V ➔ 18 V VBUS = 15 V IBUS = 3 A Figure 10-36. Line Transient: VBUS = 15 V 1.59 V/div VBUS 317 mV/div IBUS 79.6 mA/d iv SW1 2.69 V/div SW2 1.56 V/div VIN 7 V ➔ 18 V VBUS = 9 V IBUS = 3 A Figure 10-37. Line Transient: VBUS = 9 V VIN 1.6 V/d iv VBUS 330 mV/div IBUS 99.6 mA/d iv SW1 2.68 V/div SW2 433 mV/div VIN 7 V ➔ 18 V VBUS = 5 V IBUS = 3 A Figure 10-38. Line Transient: VBUS = 5 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 79 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 11 Power Supply Recommendations The TPS25762-Q1 is a power management device typically operated from an automotive battery, though the power supply for the device can be any dc voltage source within the specified VIN input range. The supply should be capable of supplying sufficient current based on the maximum inductor current in boost mode operation. The input supply should be bypassed with bulk capacitors at the input of the application board to avoid ringing due to parasitic impedance of the connecting cables. A typical choice is an aluminum electrolytic capacitor of 47 to 100 μF. 80 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 12 Layout 12.1 Layout Guidelines The basic PCB board layout requires separation of sensitive signal and power paths. This checklist must be followed to get good performance for a well designed board. • • • • • • • • • • • • • • • Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the IN, OUT, and VBUS capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high di/dt switching currents. Refer to Table 10-1 for suggested CIN values. Place the input bypass capacitors, CIN and CIN_HF, as close to the IN and PGND pins as possible to minimize the loop area for input switching current in buck operation. The CIN_HF capacitors should be as close as possible - see Figure 10-4. The IN and PGND pins transverse the package and it is highly recommended to split CIN and CIN_HF such that capacitors can be placed on either side. Place the output filter capacitors, COUT and COUT_HF, as close to the OUT and PGND pins as possible to minimize the loop area for output switching current in boost operation. Refer to Table 10-1 for suggested COUT and COUT_HF values. Place the current sense resistor and filter components. RSNS, RCSP, RCSN, and CFLT. Place the filter capacitor for the current sense signal as close to the IC CSP and CSN/BUS as possible. Use Kelvin connections between RSNS through the CSP and CSN resistors and to the CSP and CSN/BUS pins to avoid creating offsets in the current sense amplifier. Avoid crossing noisy areas such as SW1 and SW2 nodes. The recommended values in Table 10-2 provide a good starting point but may require some fine adjustment to meet PPS current limit accuracy requirements. When deviating from recommended values, RCSP must not be larger than 10 ohms. RCSN must be 0 ohms. CFLT should not be larger than 0.33 μF. Place CBUS between the RSNS and the USB Type-C connector. See Table 10-1 for suggested CBUS values. . Place the CIN, COUT, and CBUS ground connections as close as possible to the IC with thick ground trace and/or planes on multiple layers. Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes. Place the LDO_5V bypass capacitors, C5V and C5V_HF close to the IC pin, between the LDO_5V and PGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_5V supplies LDO_3V3 and LDO_1V5 as well as the low side buck and boost MOSFETs. Place the LDO_3V3 bypass capacitors, C3V3 and C3V3_HF close to the IC pin, between the LDO_3V3 and AGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_3V3 supplies the analog IO circuits. Place the LDO_1V5 bypass capacitors, C1V5 and C1V5_HF close to the IC pin, between the LDO_1V5 and AGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_3V3 supplies the Cortex M0 and digital circuits. Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins. For EMI mittigation, a series resistor RBOOT1 may be added. Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins. For EMI mittigation, a series resistor RBOOT2 may be added. Bypass the TVSP pin to PGND with a low ESR ceramic capacitor, CTVSP located close to the IC. A 0.1 µF ceramic capacitor is typically used. RTVSP_DAMP and CTVSP_DAMP should be added in parallel close to CTVSP. 10 Ω and 0.47 μF are recommended values. Use care to separate the power and signal paths so that no power or switching current flows through the AGND connections which can either corrupt the USB PD modem or GPIO signals. The PGND and AGND traces can be connected near the AGND pin. USB data lines, DP and DM should be differentially routed between the IC pins and USB connector. Impedance control is based on the PCB stack-up. 90 Ω differential is recommended. Route the DP and DM USB signals using a minimum of vias and corners which will reduce signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 81 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 • • discontinuities. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then the stub should be less than 200 mm. CC lines should be routed with a 10-mil trace to ensure the needed current for supporting powered Type-C cables through VCONN. For more information on VCONN refer to the Type-C specifications. For the 330 pF CC capacitor GND pins use a 16-mil trace if possible. GPIO signals can be fanned out on the top or bottom layer using either a 8-mil or 10-mil trace. 12.2 Layout Example Figure 12-1. TPS25762-Q1 Power Stage Layout 82 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation Please visit TI homepage for latest technical document including application notes, user guides, and reference designs. IC Package Thermal Metrics application report, Semiconductor and IC Package Thermal Metrics. 13.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.4 Trademarks TI E2E™ is a trademark of Texas Instruments. USB Type-C® is a registered trademark of USB Implementers Forum. ARM® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 83 TPS25762-Q1 www.ti.com SLVSGL9 – DECEMBER 2022 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 84 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS25762-Q1 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS25762CQRQLRQ1 ACTIVE VQFN-HR RQL 29 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS25762 C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of