TPS25846-Q1
SLVSFJ5B – JUNE 2020 – REVISED MARCH 2022
TPS25846-Q1 Automotive USB Type-A BC1.2 5-V 3.5-A Output, 36-V Input
Synchronous Step-Down Converter With Cable Compensation
1 Features
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
– HBM ESD classification level H2
– CDM ESD classification level C5
Synchronous buck DC/DC regulator
– Input voltage range: 4.5 V to 36 V
– Output current: 3.5 A
– 5.1-V output voltage with ±1% accuracy
– Current mode control
– Adjustable frequency: 300 kHz to 2.2 MHz
– Frequency synchronization to external clock
– FPWM with spread-spectrum dithering
– Internal compensation for ease of use
Compliant to USB-IF standards
– CDP/SDP mode per USB BC1.2
Optimized for USB power and communication
– User-programmable USB current limit
– Cable droop compensation up to 1.5 V
– High bandwidth data switches on DP and DM
– Client mode for system update
Integrated protection
– VBUS short-to-VBAT protection
– DP_IN and DM_IN short-to-VBAT
– DP_IN and DM_IN short-to-VBUS
•
•
2 Applications
•
•
•
Automotive infotainment
USB media hubs
USB charger ports
3 Description
The TPS25846-Q1 is a USB Type-A BC1.2
charging solution that includes a synchronous DC/DC
converter. With cable droop compensation, the Vbus
voltage remains constant regardless of load current,
ensuring connected portable devices are charged at
optimal current and voltage even under heavy loads.
The TPS25846-Q1 includes high bandwidth analog
switches for DP and DM pass-through. The device
also integrates short to battery protection on VBUS,
DM_IN and DP_IN pins. These pins can withstand
voltage up to 18 V.
Device Information(1)
PART NUMBER
TPS25846-Q1
(1)
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet
100
95
90
Efficiency (%)
•
– DP_IN, DM_IN IEC 61000-4-2 rated
• ±8-kV contact and ±15-kV air discharge
Fault flag reports
32-pin QFN package with wettable flank
85
80
75
70
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
65
60
0.1
1
OUT Current (A)
4
A001
Buck Efficiency vs Output Current fsw = 400 kHz
Simplified Schematic TPS25846-Q1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25846-Q1
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SLVSFJ5B – JUNE 2020 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (Continued)..................................................3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics ............................................8
8.6 Timing Requirements................................................ 11
8.7 Switching Characteristics.......................................... 11
8.8 Typical Characteristics.............................................. 13
9 Parameter Measurement Information.......................... 18
10 Detailed Description....................................................19
10.1 Overview................................................................. 19
10.2 Functional Block Diagram....................................... 20
10.3 Feature Description.................................................20
10.4 Device Functional Modes........................................35
11 Application and Implementation................................ 37
11.1 Application Information............................................37
11.2 Typical Application.................................................. 37
12 Power Supply Recommendations..............................47
13 Layout...........................................................................47
13.1 Layout Guidelines................................................... 47
13.2 Layout Example...................................................... 48
13.3 Ground Plane and Thermal Considerations............48
14 Device and Documentation Support..........................50
14.1 Documentation Support.......................................... 50
14.2 Receiving Notification of Documentation Updates..50
14.3 Support Resources................................................. 50
14.4 Trademarks............................................................. 50
14.5 Electrostatic Discharge Caution..............................50
14.6 Glossary..................................................................50
15 Mechanical, Packaging, and Orderable
Information.................................................................... 50
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2020) to Revision B (March 2022)
Page
• Added RHB0032AA package to the data sheet..................................................................................................4
• Added the thermal information for RHB0032AA package.................................................................................. 8
Changes from Revision * (June 2020) to Revision A (October 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Changed data sheet status from "Advance Information" to "Production Data"...................................................1
2
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5 Description (Continued)
The synchronous buck regulator operates with current mode control and is internally compensated to simplify
design. A resistor on the RT pin sets the switching frequency between 300 kHz and 2.2 MHz. Operating below
400 kHz results in better system efficiency. Operation above 2.1 MHz avoids the AM radio bands and allows for
use of a smaller inductor.
The TPS25846-Q1 integrates electrical signatures necessary for legacy devices which use USB data lines to
determine charging configuration.
A precision current sense amplifier is included for user programmable cable droop compensation and current
limit tuning. Cable compensation aids portable devices in charging at optimum current and voltage under heavy
loads by changing the buck regulator output voltage linearly with load current to counteract the voltage drop
due to wire resistance in automotive cabling. The VBUS voltage measured at a connected portable device
remains approximately constant, regardless of load current, allowing the portable device's battery charger to
work optimally.
The USB specifications require current limiting of USB charging ports, but give system designers reasonable
flexibility to choose overcurrent protection levels based on system requirements. The TPS25846-Q1 uses
a novel two-threshold current limit circuit allowing system designers to either program average current limit
protection of the buck regulator, or optionally, current limit using an external NMOS between the CSN/OUT and
BUS pins. The NFET implementation enables the TPS25846-Q1 buck regulator to supply a 5-V output for other
loads during an overcurrent condition on the USB port.
Protection features include cycle-by-cycle current limit, hiccup short-circuit protection, undervoltage lockout,
VBUS overvoltage and overcurrent, data line (Dx) short to VBUS, and die overtemperature protection.
The TPS25846-Q1 includes high bandwidth analog switches for DP and DM pass-through, and support data line
(Dx) short-to-VBAT protection.
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6 Device Comparison Table
Required Voltage Level
Special Voltage
of External Clock for
Requirements During StartSYNC
up(1)
Part Number
RPU at LS_GD in Average
Current Limit Mode(2)
SDP/CDP
Mode
DP/DM Short to
BATT
TPS25846-Q1
3.3V I/O
No
No
Yes
Yes
TPS25840-Q1
5V I/O
Yes
Yes
Yes
Yes
TPS25842-Q1
5V I/O
Yes
Yes
Yes
No
(1)
(2)
Relate to the voltage at DP, DM and VBUS pin during IC startup: VBUS < 0.8 V, VDP/M_OUT < 2.2 V, VDP/M_IN < 1.5 V.
Relate to the 2.2-KΩ pull-up resistor at LS_GD pin in Average Current Limit mode.
BOOT
SW
SW
SW
SW
PGND
PGND
PGND
31
30
29
28
27
26
25
A1
32
PGND
PGND
PGND
SW
SW
SW
SW
BOOT
7 Pin Configuration and Functions
25
26
27
28
29
30
31
32
A4
IN
1
24
FAULT
IN
1
24
FAULT
IN
2
23
BUCK_ST
IN
2
23
BUCK_ST
IN
3
22
N/C
IN
3
22
N/C
EN
4
21
VCC
EN
4
21
VCC
Thermal Pad
Thermal Pad
DM_OUT
8
17
DM_IN
DM_OUT
8
17
DM_IN
A2
AGND
BUS
CSP
CSN/OUT
ILIM
IMON
LS_GD
A3
RT/SYNC
As of 11/14/2017
16
DP_IN
AGND
18
15
7
BUS
DP_OUT
14
DP_IN
CSP
18
13
7
CSN/OUT
DP_OUT
12
N/C
ILIMIT
19
11
6
IMON
CTRL2
10
N/C
LS_GD
19
9
6
RT/SYNC
CTRL2
16
INT
15
20
14
5
13
CTRL1
12
INT
11
20
10
5
9
CTRL1
NOTES:
1) A1, A2, A3, and A4 are corner anchors for enhanced package stress
performance.
2) A1, A2, A3, and A4 are electrically connected to the thermal pad.
3) A1, A2, A3, and A4 PCB lands should be electrically isolated or
electrically connected to thermal pad and PGND.
Figure 7-2. TPS25846QCWRHBRQ1 Package 32Pin (VQFN) Top View (2)
Figure 7-1. TPS25846QWRHBRQ1 Package 32-Pin
(VQFN) Top View (1)
Table 7-1. Pin Functions
PIN
4
TYPE
I/O(3)
16
G
-
BOOT
32
P
NAME
NO.
AGND
DESCRIPTION
Analog ground terminal. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
Boot-strap capacitor connection for HS FET driver. Connect a high quality 100-nF capacitor
from this pin to the SW pin.
BUS
15
A
I
VBUS discharge input. Connect to VBUS on USB Connector.
CSN/OUT
13
P
I
Negative input of current sense amplifier, also buck output for internal voltage regulation
CSP
14
P
I
Positive input of current sense amplifier.
CTRL1
5
A
I
Logic-level control inputs for device/system configuration (see Table 10-7).
CTRL2
6
A
I
Logic-level control inputs for device/system configuration (see Table 10-7).
DM_IN
17
A
DM data line. Connect to USB connector.
DM_OUT
8
A
DM data line. Connect to USB host controller.
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Table 7-1. Pin Functions (continued)
PIN
NAME
NO.
TYPE
I/O(3)
DESCRIPTION
DP_IN
18
A
DP data line. Connect to USB connector.
DP_OUT
7
A
DP data line. Connect to USB host controller.
EN/UVLO
4
A
Enable pin. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input
allows adjustable UVLO by external resistor divider.
FAULT
24
A
ILIMIT
12
A
External resistor used to set the current-limit threshold (see Table 10-2).
IMON
11
A
External resistor used to set the max cable comp voltage at full load current.
IN
1, 2, 3
P
I
Input Supply to regulator. Connect a high-quality bypass capacitor(s) directly to this pin and
PGND.
BUCK_ST
23
A
O
Active Low open-drain output. After BUCK_ST assert, Buck converter begin to start up. At
the same time, DP and DM data switch will turn on accordingly.
LS_GD
10
A
External NMOS gate driver.
PGND
25, 26,
27
G
Power ground terminal. Connect to system ground and AGND. Connect to bypass
capacitor with short wide traces.
N/C
19, 22
-
Make no electrical connection.
O
Active LOW open-drain output. Asserted during fault conditions (see Table 10-4).
RT/SYNC
9
A
Resistor Timing or External Clock input. An internal amplifier holds this terminal at a fixed
voltage when using an external resistor to ground to set the switching frequency. If the
terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal
becomes a synchronization input. The internal amplifier is disabled and the terminal is a
high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier
is re-enabled and the operating mode returns to resistor frequency programming.
SW
28, 29,
30, 31
P
Switching output of the regulator. Internally connected to source of the HS FET and drain of
the LS FET. Connect to power inductor.
INT
20
A
For internal circuit, must connect a 5.1-K resistor to AGND.
VCC
21
P
Output of internal bias supply. Used as supply to internal control circuits. Connect a high
quality 2.2-µF capacitor from this pin to GND.
(1)
(2)
(3)
For the package drawing, please refer to RHB0032R at the end of the data sheet.
For the package drawing, please refer to RHB0032AA at the end of the data sheet.
A = Analog, P = Power, G = Ground.
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8 Specifications
8.1 Absolute Maximum Ratings
Voltages are with respect to GND (unless otherwise noted)(1)
PARAMETER
Input voltage
Output voltage
Voltage range
Pin positive source current,
IVCC
MIN
MAX
IN to PGND
–0.3
40
OUT to PGND
–0.3
20
EN to AGND
–0.3
VIN + 0.3
CSP to AGND
–0.3
20
CSN to AGND
–0.3
20
BUS to AGND
–0.3
18
RT/SYNC to AGND
–0.3
6
CTRL1 or CTRL2 to AGND
–0.3
6
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND (less than 10 ns transients)
–3.5
40
BOOT to SW
–0.3
6
VCC to AGND
–0.3
6
LS_GD
–0.3
18
INT to AGND
–0.3
18
DP_IN, DM_IN to AGND
–0.3
18
DP_OUT, DM_OUT to AGND
–0.3
6
FAULT to AGND
–0.3
6
ILIMIT or IMON to AGND
–0.3
6
VCC Source Current
UNIT
V
V
V
5
mA
Internally
Limited
Pin positive sink current, ISNK FAULT
I/O current
DP_IN to DP_OUT, or DM_IN to DM_OUT in SDP, CDP, or
Client Mode
TJ
A
–100
100
mA
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
Lifetime
Tj = 150°C, VBUS = 5.1 V, ILOAD = 1 A
63000
hours
Lifetime
Tj = 150°C, VBUS = 5.1 V, ILOAD = 2.4 A
13000
hours
(1)
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
(4)
6
Electrostatic discharge
Human body model (HBM), per AEC
Q100-002(1)
±2000(2)
Charged device model (CDM), per
AEC Q100-011
Corner pins (1, 8, 9, 17, 25 and 32)
±750(3)
Other pins
±750(3)
IEC 61000-4-2 contact discharge
DP_IN, DM_IN pins
±8000(4)
IEC 61000-4-2 air-gap discharge
DP_IN, DM_IN pins
±15000(4)
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The passing level per AEC-Q100 Classification H2.
The passing level per AEC-Q100 Classification C5.
Surges per IEC61000-4-2, 1999 applied between DP_IN, DM_IN and output ground of the TPS25846-Q1 evaluation module.
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8.3 Recommended Operating Conditions
Voltages are with respect to GND (unless otherwise noted)
MIN
IN to PGND
VI
Input voltage
NOM
MAX
4.5
36
EN
0
VIN
VCC when driven from external regulator
0
5.5
DP_IN, DM_IN
0
3.6
DP_OUT, DM_OUT
0
3.6
CTRL1, CTRL2
0
VCC
UNIT
V
RT/SYNC when driven by external clock
0
VCC
VPU
Pull up voltage
BUCK_ST
0
VCC
V
VO
Output voltage
CSN/OUT
0
6.5
V
Buck regulator output current
0
3.5
A
–30
30
IO
Output current
DP_IN to DP_OUT or DM_IN to DM_OUT Continuous
current in SDP, CDP or Client Mode
ISNK
Sink current
FAULT, BUCK_ST
II
Input current
Continuous current into the CSP pin
REXT
External resistnace
RIMON, RILIMIT
TJ
(1)
Operating junction temperature
mA
10
200
µA
0
100
kΩ
–40
125(1)
°C
Operating at junction temperatures greater than 125°C is possible, however lifetime will be degraded.
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8.4 Thermal Information
TPS25846-Q1
THERMAL
METRIC(1)
RHB0032R (VQFN)
RHB0032AA (VQFN)
32 PINS
32 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
28.7
29.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.6
18.6
°C/W
RθJB
Junction-to-board thermal resistance
7.2
9.7
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
7.2
9.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTATE (IN PIN)
VIN
Operating input voltage range
4.5
IQ
Operating quiescent current (non
switching)
VEN/UVLO = VIN, CTRL1 = CTRL2
= VCC, VCSN = 8V, INT pull down
resistance = 5.1kΩ
IQ-SB
Standby quiescent current
VEN/UVLO = VIN, CTRL1 = CTRL2 =
VCC, INT pull down resistance = 5.1kΩ
ISD
Shutdown quiescent current;
measured at IN pin.
EN= 0
700
10
36
V
990
µA
290
µA
16
µA
1.14
V
ENABLE and UVLO (EN/UVLO PIN)
VEN/UVLO_VCC_H
EN/UVLO input level required to turn
on internal LDO
VEN/UVLO rising threshold
VEN/UVLO_VCC_L
EN/UVLO input level required to turn
off internal LDO
VEN/UVLO falling threshold
0.3
VEN/UVLO_H
EN/UVLO input level required to turn
on state machine
VEN/UVLO rising threshold
1.140
VEN/UVLO_HYS
Hysteresis
VEN/UVLO falling threshold
90
mV
ILKG_EN/UVLO
Enable input leakage current
VEN/UVLO = 3.3 V
0.5
uA
2.2
V
V
1.200
1.260
V
INTERNAL LDO
VBOOT_UVLO
Bootstrap voltage UVLO threshold
VCC
Internal LDO output voltage appearing
6 V ≤ VIN ≤ 36 V
on VCC pin
VCC_UVLO_R
Rising UVLO threshold
VCC_UVLO_HYS
Hysteresis
4.75
5
5.25
V
3.4
3.6
3.8
V
600
mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE BUCK AVG CURRENT LIMITING
8
(VCSP – VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
13 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
125°C
43.5
46
48.5
mV
(VCSP – VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
13 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
150°C
42.5
46
49.5
mV
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8.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
(VCSP – VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
26.1 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
125°C
(VCSP – VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
26.1 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
150°C
MIN
TYP
MAX
UNIT
20
22.5
25
mV
19
22.5
26
mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE EXTERNAL NFET CURRENT LIMITING
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
(VCSP – VCSN/OUT) Current limit voltage NFET control loop 6.8 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
125°C
40
43
46
mV
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
(VCSP – VCSN/OUT) Current limit voltage NFET control loop 6.8 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
150°C
38.5
43
47.5
mV
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
(VCSP – VCSN/OUT) Current limit voltage NFET control loop 13.7 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
125°C
18
21
24
mV
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
(VCSP – VCSN/OUT) Current limit voltage NFET control loop 13.7 kΩ, RIMON = 13 kΩ, –40°C ≤ TJ ≤
150°C
17
21
25
mV
4.6
5.4
6.3
A
CURRENT LIMIT - BUCK REGULATOR PEAK CURRENT LIMIT
IL-SC-HS
High-side current limit
IL-SC-LS
Low-side current limit
IL-NEG-LS
Low-side negative current limit
3.5
4
4.5
A
–3.1
–2.1
–1.3
A
0.935
1
1.065
V
CABLE COMPENSATION VOLTAGE
VIMON
Cable compensation voltage
(VCSP – VCSN) = 46 mV, RSET = 300 Ω,
RILIMIT = 13 kΩ, RIMON = 13 kΩ
VIMON
Cable compensation voltage
(VCSP – VCSN) = 23 mV, RSET = 300 Ω,
RILIMIT = 13 kΩ, RIMON = 13 kΩ
0.5
V
VIMON
Cable compensation voltage (internal
clamp)
(VCSP –VCSN) = 46 mV, RSET = 300 Ω,
RILIMIT = 13 kΩ, RIMON = open
1.8
V
BUCK OUTPUT VOLTAGE (CSN/OUT PIN)
VCSN/OUT
Output voltage
INT pull down resistance = 5.1kΩ,
RIMON = 0 Ω, RILIMIT = 0 Ω
5.05
VCSN/OUT
Output voltage accuracy
INT pull down resistance = 5.1kΩ,
RIMON = 0 Ω, RILIMIT = 0 Ω
–1
VCSN/OUT_OV
Overvoltage level on CSN/OUT pin
which buck regulator stops switching
VCSN/OUT rising
7.1
VCSN/OUT_OV_HYS
Hysteresis
VHC
CSN / OUT pin voltage required to
trigger short circuit hiccup mode
VDROP
Dropout voltage ( VIN-VOUT )
5.10
7.5
500
2
VIN = VOUT + VDROP, VOUT = 5.1V,
IOUT = 3A
150
5.15
V
1
%
7.9
V
mV
V
mV
BUCK REGULATOR INTERNAL RESISTANCE
RDS-ON-HS
High-side MOSFET ON-resistance
Load = 3 A, TJ = 25°C
40
45 mOhm
RDS-ON-HS
High-side MOSFET ON-resistance
Load = 3 A, –40°C ≤ TJ ≤ 125°C
40
68 mOhm
RDS-ON-HS
High-side MOSFET ON-resistance
Load = 3 A, –40°C ≤ TJ ≤ 150°C
40
75 mOhm
RDS-ON-LS
Low-side MOSFET ON-resistance
Load = 3 A, TJ = 25C
35
41 mOhm
RDS-ON-LS
Low-side MOSFET ON-resistance
Load = 3 A, –40°C ≤ TJ ≤ 125°C
35
60 mOhm
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8.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
RDS-ON-LS
TEST CONDITIONS
Low-side MOSFET ON-resistance
MIN
Load = 3 A, –40°C ≤ TJ ≤ 150°C
TYP
35
MAX
UNIT
68 mOhm
NFET GATE DRIVE (LS_GD PIN)
VLS_GD
NFET gate drive output voltage
VCSN/OUT = 5.1 V, CG = 1000 pF
ILS_DR_SRC
NFET gate drive output source current VCSN/OUT = 5.1 V, CG = 1000 pF
ILS_DR_SNK
NFET gate drive output sink current
VCSN/OUT = 5.1 V, CG = 1000 pF
VLS_GD_UVLO_R
VCSN/OUT rising threshold for LS_GD
operation
VCSN/OUT rising
VLS_GD_UVLO_HYS
Hysteresis
9.5
11
12.5
V
2
3
4
µA
20
35
50
µA
2.85
3
3.15
V
80
mV
BUS DISCHARGE (BUS PIN)
VBUS_OV
Rising threshold for BUS pin
overvoltage protection
VBUS_OV_HYS
Hysteresis
180
mV
RBUS_DCHG_18V
Discharge resistance for BUS
VBUS = 18V, measure leakage current
29
kOhm
RBUS_DCHG_8V
Discharge resistance for BUS
VBUS = 8V, measure leakage current
35
kOhm
VOL
FAULT Output low voltage
ISNK_PIN = 0.5 mA
IOFF
FAULT Off-state leakage
VPIN = 5.5 V
VBUS rising
6.6
7
7.3
V
FAULT
250
mV
1
µA
2
V
CTRL1, CTRL2 - LOGIC INPUTS
VIH
Rising threshold voltage
VIL
Falling threshold voltage
VHYS
Hysteresis
IIN
Input current
1.48
0.85
1.30
V
180
mV
–1
1
µA
4.15
V
DP_IN AND DM_IN OVERVOLTAGE PROTECTION
VDx_IN_OV
Rising threshold for Dx_IN overvoltage
DP_IN or DM_IN rising
protection
Hysteresis
3.7
3.9
100
mV
RDx_IN_DCHG_18V
Discharge resistance for Dx_IN
VDx_IN = 18V, measure leakage
current
94
kOhm
RDx_IN_DCHG_5V
Discharge resistance for Dx_IN
VDx_IN = 5V, measure leakage
current
416
kOhm
HIGH-BANDWIDTH ANALOG SWITCH
RDS_ON
DP and DM switch on-resistance
VDP_OUT = VDM_OUT = 0 V, IDP_IN =
IDM_IN = 30 mA
3.4
6.3
Ohm
RDS_ON
DP and DM switch on-resistance
VDP_OUT = VDM_OUT = 2.4 V, IDP_IN =
IDM_IN = –15 mA
4.3
7.7
Ohm
|ΔRDS_ON|
Switch resistance mismatch between
DP and DM channels
VDP_OUT = VDM_OUT = 0 V, IDP_IN =
IDM_IN = 30 mA
0.05
0.15
Ohm
|ΔRDS_ON|
Switch resistance mismatch between
DP and DM channels
VDP_OUT = VDM_OUT = 2.4 V, IDP_IN =
IDM_IN = –15 mA
0.05
0.15
Ohm
CIO_OFF
DP/DM switch off-state capacitance
VEN = 0 V, VDP_IN = VDM_IN = 0.3 V,
Vac = 0.03 VPP , f = 1 MHz
6.7
pF
CIO_ON
DP/DM switch on-state capacitance
VDP_IN = VDM_IN = 0.3 V, Vac = 0.03
VPP, f = 1 MHz
10
pF
OIRR
Off-state isolation
VEN = 0 V, f = 250 MHz
9
dB
XTALK
On-state cross-channel isolation
f = 250 MHz
29
dB
10
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8.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
Ilkg(OFF)
Off-state leakage current, DP_OUT
and DM_OUT
VEN = 0 V, VDP_IN = V DM_IN =
3.6 V, VDP_OUT = VDM_OUT = 0 V,
measure IDP_OUT and IDM_OUT
BW
Bandwidth (–3 dB)
RL = 50 Ω
MIN
TYP
MAX
0.1
1.5
800
UNIT
µA
MHz
CHARGING DOWNSTREAM PORT (CDP) DETECT
VDP_IN = 0.6 V, –250 µA < IDM_IN < 0
µA
VDM_SRC
DM_IN CDP output voltage
VDAT_REF
DP_IN rising lower window threshold
for VDM_SRC activation
VDAT_REF
Hysteresis
VLGC_SRC
DP_IN rising upper window threshold
for VDM_SRC deactivation
VLGC_SRC_HYS
Hysteresis
IDP_SINK
DP_IN sink current
0.5
0.6
0.7
V
0.36
0.38
0.4
V
50
0.8
mV
0.84
0.88
100
VDP_IN = 0.6 V
40
V
mV
70
100
µA
RT/SYNC THRESHOLD (RT/SYNC PIN)
VIH_RT/SYNC
RT/SYNC high threshold for external
clock synchronization
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
VIL_RT/SYNC
RT/SYNC low threshold for external
clock synchronization
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
2
V
0.8
V
THERMAL SHUTDOWN
TSD
Thermal shutdown
Shutdown threshold
160
°C
Recovery threshold
140
°C
8.6 Timing Requirements
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
MIN
NOM
MAX UNIT
BUCK CONVERTER
SYNC (RT/SYNC PIN) WITH EXTERNAL CLOCK
fSYNC
Switching frequency using external clock on
RT/SYNC pin
TSYNC_MIN
Minimum SYNC input pulse width
TLOCK_IN
PLL lock time
300
fSYNC = 400 kHz, VRT/SYNC > VIH_RT/SYNC,
VRT/SYNC < VIL_RT/SYNC
2300
kHz
100
ns
100
µs
8.7 Switching Characteristics
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW = 400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT = 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK REGULATOR
SOFT START
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8.7 Switching Characteristics (continued)
Limits apply over the junction temperature (TJ) range of –40°C to +150°C; VIN = 13.5 V, fSW = 400 kHz, CVCC = 2.2 µF, RSNS
= 15 mΩ, RIMON = 13 kΩ, RILIMIT = 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TSS
TEST CONDITIONS
The time of internal reference to
increase from 0 V to 1.0 V
Internal soft-start time
MIN
TYP
MAX
3
5
7
UNIT
ms
HICCUP MODE
NOC
Number of cycles that LS current limit
is tripped to enter Hiccup mode
128
Cycles
TOC
Hiccup retry delay time
118
ms
TON_MIN
Minimum turnon-time
105
ns
TON_MAX
Maximum turnon-time, HS timeout in
dropout
7.5
µs
TOFF_MIN
Minimum turnoff time
80
ns
Dmax
Maximum switch duty cycle
98
%
EN Timing
SW (SW PIN)
TIMING RESISTOR AND INTERNAL CLOCK
fSW_RANGE
fSW
Switching frequency range using RT
mode
300
2300
kHz
Switching frequency
RT = 49.9 kΩ
360
400
440
kHz
Switching frequency
RT = 8.87 kΩ
1953
2100
2247
kHz
FSSS
Frequency span of spread spectrum
operation
tDEGD_CC_DET
Detach asserting deglitch for exiting
UFP state
tDEGA_CC_LONG
tW_CC_DCHG
±6
%
6.98
12.7
19.4
ms
Long deglitch
87
150
217
ms
Discharge wait time
37
66
99
ms
NFET DRIVER
tr
VLS_DR rise time
VOUT = 5.1 V, NFET = CSD87502Q2,
time from LS_GD 10% to 90%
1000
µs
tf
VLS_DR fall time
VOUT = 5.1 V, NFET = CSD87502Q2,
time from LS_GD time 90% to 10%
100
µs
CURRENT LIMIT - EXTERNAL NFET CONNECTED BETWEEN CSN/OUT AND BUS, LS_GD CONNECTED TO FET GATE
tOC_HIC_ON
ON-time during hiccup mode
tOC_HIC_OFF
OFF-time during hiccup mode
2
ms
263
ms
CURRENT LIMIT - BUCK REGULATOR AVERAGE CURRENT LIMIT
FAULT DUE TO VBUS OC, VBUS OV, DP OV, DM OV, CC OV, CC OC
tDEGLA
Asserting deglitch time
5.5
8.2
11.5
ms
tDEGLD
De-asserting deglitch time
5.5
8.2
11.5
ms
Asserting deglitch time
88
150
220
ms
BUCK_ST
tDEGLA
HIGH-BANDWIDTH ANALOG SWITCH
tpd
Analog switch propagation delay
0.14
ns
tSK
Analog switch skew between opposite
transitions of the same port (tPHL –
tPLH)
0.02
ns
tOV_Dn
DP_IN and DM_IN overvoltage
protection response time
2
µs
12
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8.8 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
32
Shutdown Queiscent Current (uA)
Non-switching Quiescent Current (uA)
717
714
711
708
705
702
-40C
25C
150C
699
696
28
24
20
16
12
-40C
25C
125C
150C
8
4
0
4
8
12
VCSN = 8 V
16
20
24
Input Voltage (V)
28
32
36
40
0
INT = 5.1 kΩ
Figure 8-1. Non-Switching Quiescent Current
16
20
24
Input Voltage (V)
28
32
36
40
D003
Figure 8-2. Shutdown Quiescent Current
UP
DN
UP
DN
3.75
VIN UVLO Voltage (V)
EN Threshold Votlage (V)
12
3.9
1.2
1.175
1.15
1.125
1.1
1.075
3.6
3.45
3.3
3.15
3
-25
0
25
50
75
Temperature (C)
100
125
2.85
-60
150
-30
0
D004
Figure 8-3. Precision Enable Threshold
30
60
90
Temperature (C)
120
150
180
D005
Figure 8-4. VIN UVLO Threshold
5.1
5.16
-40C
25C
125C
150C
5.04
Vin = 6V
Vin = 13.5V
Vin = 36V
5.14
VCSN/OUT Voltage (V)
5.07
Vcc Voltage (V)
8
EN = 0 V
1.225
1.05
-50
4
D001
5.01
4.98
4.95
5.12
5.1
5.08
5.06
4.92
4.89
0
4
8
12
16
20
24
Input Voltage (V)
28
32
36
40
5.04
-50
-25
0
D005
Figure 8-5. VCC vs Input Voltage
25
50
75
Temperature (C)
100
125
150
D006
RIMON = 0 Ω
Figure 8-6. VCSN/OUT Voltage vs Junction Temperature
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
80
-40C
25C
150C
6
72
5.8
On Resistance (m?)
High-side MOS Current Limit (A)
6.2
5.6
5.4
5.2
5
0
4
8
12
16
20
24
Input Voltage (V)
28
32
36
40
Vin = 6V
Vin = 13.5V
Vin = 36V
420
55
414
50
45
40
35
Vin = 6V
Vin = 13.5V
Vin = 36V
30
-25
0
25
50
75
Temperature (C)
0
100
125
25
50
75
Temperature (C)
100
125
150
D008
Figure 8-8. High-side MOSFET on Resistance vs Junction
Temperature
60
25
-50
-25
D006
Switching Frequency (kHz)
On Resistance (m?)
48
24
-50
40
Figure 8-7. High-side Current Limit vs Input Voltage
408
402
396
390
384
378
-50
150
-25
0
D009
Figure 8-9. Low-side MOSFET on Resistance vs Junction
Temperature
25
50
75
Temperature (C)
100
125
150
D010
RT = 49.9 kΩ
Figure 8-10. Switching Frequency vs Junction Temperature
2400
4.2
1A
2A
3A
Rlimit = 13k:
Rlimit = 26.1k:
3.6
Buck Avg Current limit (A)
2100
Switching Frequency (kHz)
56
32
4.8
1800
1500
1200
900
600
3
2.4
1.8
1.2
0.6
300
0
5
10
15
20
25
Input voltage (V)
30
35
40
0
-50
-25
0
D011
RT = 8.87 kΩ
RSNS = 15 mΩ
Figure 8-11. Switching Frequency vs VIN Voltage
14
64
25
50
75
Temperature (C)
100
125
150
D012
RSET = 300 Ω
Figure 8-12. Buck Average Current Limit vs Junction
Temperature
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
4.2
4.8
Ext FET Current Limit (A)
3.6
LS_GD Gate Source Current (uA)
Rlimit = 6.8k:
Rlimit = 13.7k:
3
2.4
1.8
1.2
0.6
0
-50
-25
0
25
50
75
Temperature (C)
RSNS = 15 mΩ
100
125
3.6
3.2
2.8
2.4
-25
0
D013
25
50
75
Temperature (C)
100
125
150
D013
Figure 8-14. LS_GD Gate Source Current vs Junction
Temperature
RSET = 300 Ω
1.35
13
Vin = 6V
Vin = 13.5V
Vin = 36V
Load Current = 3 A
Load Current = 1.5 A
1.2
Cable Comp Voltage (V)
12.5
LS_GD Gate Voltage (V)
4
2
-50
150
Figure 8-13. External FET Current Limit vs Junction
Temperature
12
11.5
11
10.5
10
1.05
0.9
0.75
0.6
0.45
9.5
-50
-25
0
25
50
75
Temperature (C)
VCSN/OUT = 5.1 V
100
125
0.3
-50
150
-25
0
D013
RIMON = 0 kΩ
RSNS = 15 mΩ
Figure 8-15. LS_GD Gate Voltage vs Junction Temperature
25
50
75
Temperature (C)
100
125
150
D014
RSET = 300 Ω
RIMON = 13 kΩ
Figure 8-16. Cable Compensation Voltage vs Junction
Temperature
7.5
1
0.9
7.35
0.8
VBUS OVP Threshold (V)
Cable Comp Voltage (V)
Vin = 6V
Vin = 13.5V
Vin = 36V
4.4
0.7
0.6
0.5
0.4
0.3
0.2
7.2
7.05
6.9
6.75
6.6
0.1
0
0
0.3
0.6
0.9
RSNS = 15 mΩ
1.2 1.5 1.8
Load Current (A)
2.1
RSET = 300 Ω
2.4
2.7
3
6.45
-50
-25
D014
RIMON = 13 kΩ
Figure 8-17. Cable Compensation Voltage vs Load Current
0
25
50
75
Temperature (C)
100
125
150
D016
Figure 8-18. VBUS Overvoltage Protection Threshold vs Junction
Temperature
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8.8 Typical Characteristics (continued)
4.3
4.3
4.2
4.2
DM_IN OVP Threshold (V)
DP_IN OVP Threshold (V)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
4.1
4
3.9
3.8
3.7
3.6
-50
4
3.9
3.8
3.7
-25
0
25
50
75
Temperature (C)
100
125
150
3.6
-50
-25
D017
Figure 8-19. DP_IN Overvoltage Protection Threshold vs
Junction Temperature
0
25
50
75
Temperature (C)
100
125
150
D018
Figure 8-20. DM_IN Overvoltage Protection Threshold vs
Junction Temperature
Measured on TPS25846-Q1 EVM with 10-cm cable
Measured Source with 10-cm cable
16
4.1
Figure 8-21. Bypassing the TPS25846-Q1 Data Switch
Figure 8-22. Through the TPS25846-Q1 Data Switch
Figure 8-23. Data Transmission Characteristics vs Frequency
Figure 8-24. Off-State Data-Switch Isolation vs Frequency
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
Figure 8-25. On-State Cross-Channel Isolation vs Frequency
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9 Parameter Measurement Information
IOS
90%
tr
tf
VLS_GD
I(OUT)
10%
t(IO S)
Figure 9-2. NFET Gate Drive Rise and Fall Time
Figure 9-1. Short-Circuit Parameters
0.5m AWG28
10cm AWG18
ICAB LE
0.5m AWG28
0.5m AWG28
Manually Hot-short
PSIL079
18V
27 mF
35V
Voltage
Test Point
TPS2584x-Q1
DC Power Supply
OUT
DP_IN
DM_IN
GND
GND
Figure 9-3. Short-to-Battery System Test Set-up
18
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10 Detailed Description
10.1 Overview
The TPS25846-Q1 devices are full-featured solutions for implementing a compact USB charging port with
support for Type-A BC1.2 standards. Both devices contain an efficient 36-V buck regulator power source
capable of providing up to 3.5 A of output current at 5.10 V (nominal). System designers can optimize efficiency
or solution size through careful selection of switching frequency over the range of 300 to 2200 kHz with sufficient
margin to operate above or below the AM radio frequency band. In all versions the buck regulator operates
in forced PWM mode ensuring fixed switching frequency regardless of load current. Spread-spectrum feature
aid reducing harmonic peaks of the switching frequency potentially simplifying EMI filter design and easing
compliance.
Current sensing through a precision high-side current sense amplifier enables an accurate, user programmable
overcurrent limit setting; and programmable linear cable compensation to overcome IR losses when powering
remote USB ports.
The CTRL1 and CTRL2 pins set the operating mode for the TPS25846-Q1 device. The device can support CDP,
SDP or Client configurations.
The TPS25846-Q1 integrates high band-width (800 MHz) USB switches, includes short-to-VBAT and short-toVBUS protection as well as IEC61000-4-2 electrostatic discharge clamps to protect the host from potentially
damaging overvoltage conditions.
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10.2 Functional Block Diagram
10.3 Feature Description
10.3.1 Buck Regulator
The following operating description of the TPS25846-Q1 will refer to the Functional Block Diagram and the
waveforms in Figure 10-1. TPS25846-Q1 is a step-down synchronous buck regulator with integrated high-side
(HS) and low-side (LS) switches (synchronous rectifier). The TPS25846-Q1 supplies a regulated output voltage
by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time,
the SW pin voltage swings up to approximately VIN, and the inductor current iL increase with linear slope
(VIN – VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after an
anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The
control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch
ON time and TSW is the switching period. The regulator control loop maintains a constant output voltage by
adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output
voltage and inversely proportional to the input voltage: D = VOUT / VIN.
20
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VSW
SW Voltage
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
Inductor Current
iL
TSW
ILPK
IOUT
'iL
t
0
Figure 10-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The TPS25846-Q1 employs fixed frequency peak current mode control. A voltage feedback loop is used to
get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. TPS25846-Q1 operates in FPWM mode for low output voltage ripple, tight output voltage
regulation, and constant switching frequency.
10.3.2 Enable/UVLO
The voltage on the EN/UVLO pin controls the ON or OFF operation of TPS25846-Q1. An EN/UVLO pin voltage
higher than VEN/UVLO-VOUT-H is required to start the internal regulator (Assume 5.1-k pull down resister on INT
pin). The EN/UVLO pin is an input and can not be left open or floating. The simplest way to enable the operation
of the TPS25846-Q1 is to connect the EN to VIN. This connection allows self-start-up of the TPS25846-Q1 when
VIN is within the operation range.
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EN
VEN/UVLO-H
VEN/UVLO-H ± VEN/UVLO-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VCSN/OUT
VCSN/OUT
0
Figure 10-2. Precision Enable Behavior
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 10-3) to
establish a precision system UVLO level for the TPS25846-Q1. System UVLO can be used for sequencing,
ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port
VBUS is within the 5-V operating range as required for USB compliance for the latest USB specifications
and requirements, refer to USB.org), TI suggests that the RENT and RENB resistors be chosen such that the
TPS25846-Q1 enables when VIN is approximately 6 V. Considering the drop out voltage of the buck regulator
and IR loses in the system, 6 V provides adequate margin to maintain VBUS within USB specifications. If system
requirements such as a warm crank (start) automotive scenario require operation with VIN < 6 V, the values
of RENT and RENB can be calculated assuming a lower VIN. An external logic signal can also be used to drive
EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely
for other reasons.
IN
RENT
EN
RENB
Figure 10-3. System UVLO by Enable Divider
UVLO configuration using external resistors is governed by the following equations:
22
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(1)
(2)
Example:
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ (user choice)
RENT = [(VIN(ON) / VEN/UVLO_H) – 1] × RENB= 19.6 kΩ. Choose standard 20 kΩ.
Therefore, VIN(OFF) = 6 V × [1 – (0.09 V / 1.2 V)] = 5.55 V
A typical start-up waveform is shown in Figure 10-4. The rise time of DCDC VBUS voltage is about 5 ms.
EN,
5V/Div
VIN
5V/Div
VBUS,
5V/Div
VCC,
5V/Div
40ms/Div
Figure 10-4. Typical Start-up Behavior, VIN = 13.5 V, RIMON = 12.6 kΩ
10.3.3 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the TPS25846-Q1 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. To determine the RT resistance, for a given switching frequency, use Equation 3.
26660 u ¦SW
1.0483
FREQ Resistance (k:)
RFREQ k:
70
65
60
55
50
45
40
35
30
25
20
15
10
5
200
kHz
(3)
400
600
800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
D024
Figure 10-5. RT Set Resistor vs Switching Frequency
Table 10-1 lists typical RT resistors value.
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Table 10-1. Setting the Switching Frequency with RT
RT (kΩ)
SWITCHING FREQUENCY (kHz)
68.1
300
49.9
400
39.2
500
19.1
1000
12.4
1500
9.31
2000
8.87
2100
8.45
2200
TPS25846-Q1 switching action can be synchronized to an external clock from 300 kHz to 2.3 MHz. The RT/
SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT/SYNC pin. The AC coupled peak-to-peak voltage at the
RT/SYNC pin must exceed the SYNC amplitude threshold of 2.0 V (typical) to trip the internal synchronization
pulse detector, and the minimum SYNC clock ON and OFF time must be longer than 100 ns (typical). When
using a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC
coupling capacitor CCOUP to a termination resistor RTERM (for example: 50 Ω). The two resistors in series provide
the default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be
used for CCOUP. Figure 10-6 show the device synchronized to an external clock.
CCOUP
RT
PLL
Lo-Z
Clock
Source
RTERM
RT/SYNC
PLL
Hi-Z
Clock
Source
RT
RT/SYNC
Figure 10-6. Synchronize to External Clock
In order to avoid AM radio frequency brand and maintain proper regulation when minimum ON-time or minimum
OFF-time is reached, the TPS25846-Q1 implement frequency foldback scheme depends on VIN voltage, refer to
Figure 8-10.
• When 8 V < VIN ≤ 19 V, the switching frequency of TPS25846-Q1 is determined by RT resistor or external
sync clock.
• When VIN ≤ 8 V, the switching frequency of TPS25846-Q1 is set to default 420 kHz, regardless of RT resistor
setting or external sync clock.
• When VIN > 19 V, the switching frequency of TPS25846-Q1 is set to default 420 kHz, regardless of RT
resistor setting or external sync clock.
Figure 10-7, Figure 10-8 and Figure 10-9 show the device switching frequency and behavior under different VIN
voltage and RT = 8.87kΩ.
Figure 10-10, Figure 10-11 and Figure 10-12 show the device switching frequency and behavior under different
VIN voltage and synchronized to an external 2.1-M system clock.
24
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VIN,
10V/Div
VIN,
10V/Div
SW,
10V/Div
SW,
10V/Div
Inductor Current,
5A/Div
VIN = 7.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 10-7. Switching Frequency when RT = 8.87
kΩ
Inductor Current,
5A/Div
VIN = 13.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 10-8. Switching Frequency when RT = 8.87
kΩ
VIN, 5V/Div
VIN,
10V/Div
SW,
10V/Div
Sync, 2V/Div
SW,
5V/Div
Inductor Current,
5A/Div
VIN = 20 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 10-9. Switching Frequency when RT = 8.87
kΩ
Inductor Current,
2A/Div
VIN = 7.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 10-10. Synchronizing to External 2.1-MHz
Clock
VIN, 10V/Div
VIN, 5V/Div
Sync, 2V/Div
Sync, 2V/Div
SW,
10V/Div
SW,
10V/Div
Inductor Current,
2A/Div
VIN = 13.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 10-11. Synchronizing to External 2.1-MHz
Clock
Inductor Current,
2A/Div
VIN = 20 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 10-12. Synchronizing to External 2.1-MHz
Clock
10.3.4 Spread-Spectrum Operation
In order to reduce EMI, the TPS25846-Q1 introduce frequency spread spectrum. The spread spectrum is
used to eliminate peak emissions at specific frequencies by spreading emissions across a wider range of
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frequencies than a part with fixed frequency operation. In most systems, low frequency conducted emissions
from the first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion
is reduction of emissions at higher harmonics which fall in the FM band. These harmonics often couple to the
environment through electric fields around the switch node. The TPS25846-Q1 devices use ±6% spread of
switching frequencies with 1/256 swing frequency.
The spread spectrum function is only available when using the TPS25846-Q1 internal oscillator. If the RT/SYNC
pin is synchronized to an external clock, the spread spectrum function will be turn off.
10.3.5 VCC, VCC_UVLO
The TPS25846-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 5 V. The VCC pin is the output of an LDO and must be properly bypassed. A high
quality ceramic capacitor with a value of 2.2 µF to 4.7 µF, 10 V or higher rated voltage should be placed as close
as possible to VCC and grounded to the PGND ground pin. The VCC output pin should not be loaded with more
than 5 mA, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage
to the TPS25846-Q1.
10.3.6 Minimum ON-time, Minimum OFF-time
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically
105 ns in the TPS25846-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be
off. TOFF_MIN is typically 80 ns in the TPS25846-Q1. In CCM (FPWM) operation, TON_MIN and TOFF_MIN limit the
voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is:
(4)
And the maximum duty cycle allowed is:
(5)
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle.
10.3.7 Internal Compensation
The TPS25846-Q1 is internally compensated as shown in Figure 10-13. The internal compensation is designed
such that the loop response is stable over the specified operating frequency and output voltage range. The
TPS25846-Q1 is optimized for transient response over the range 300 kHz ≤ fsw ≤ 2300 kHz.
10.3.8 Bootstrap Voltage (BOOT)
The TPS25846-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor
is 0.47 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance overtemperature and voltage.
10.3.9 RSNS, RSET, RILIMIT and RIMON
The programmable current limit threshold and full-scale cable compensation voltage are determined by the
values of the RSNS, RSET, RILIMIT and RIMON resistors. Refer to Figure 10-13.
•
26
RSNS is the current sense resistor. The recommended voltage across RSNS under current limit should be
approximately 50 mV as a compromise between accuracy and power dissipation. For example, if current
limiting is desired for IOUT(MAX) ≥ 3.3 A, then RSNS = 0.05 V / 3.3 A = 0.01515 Ω. Choose a standard value of
15 mΩ.
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•
•
•
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RSET determines the input current to the transconductance amplifier and current mirror. The amplifier
balances the voltage to be equal to that across RSNS. Choose a RSET value to produce an ISET current
between 75 - 180 µA at the desired IOUT(MAX). Considering 50 mV across RSET, a value of 300 Ω will provide
approximately 166 µA of ISET current to the amplifier and mirror circuit. Care should be taken to limit the ISET
current below 200 µA to avoid saturating the internal amplifier circuit.
RILIMIT inconjuction with the 0.5 × ISET current produces a voltage on the ILIMIT pin which is proportional
to the load current flowing in RSNS. For details on setting the current limit, see Current Limit Setting using
RILIMIT.
RIMON inconjuction with the 0.5 × ISET current produces a voltage on the IMON pin which is proportional to the
load current flowing in RSNS. For details on setting the current limit., see Cable Compensation.
(1): VSNS = ILOAD x RSNS
(2): VSNS ~= VSET
(by op amp)
(3): ISET = VSET / RSET = VSNS / RSET
ILOAD
RSNS
+ 50mV -
RSET
CSP
CSN/OUT
RT
Low Offset
Amp
RM
RB
+
IMON
±
IIMON = 0.5 x ISET
ISET
+
RIMON
±
RS = RT
ILIMIT
IILIMIT = 0.5 x ISET
RILIMIT
±
+
1V
Soft
Start
+
+
±
VCOMP
1V
VILIMIT = 1V (current limit by Buck)
VILIMIT = 0.49V (current limit by NFET)
LS_GD
±
+
0.49V
BUS
Figure 10-13. Current Limit and Cable Compensation Circuit
10.3.10 Overcurrent and Short Circuit Protection
For maximum versatility, TPS25846-Q1 includes both a precision, programmable current limit as well cycle-bycycle current limit to protect the USB port from extreme overload conditions. In most applications the RILIMIT
resistor in conjunction with the selection of RSNS and RSET will determine the overload threshold. The cycle-bycycle current limit will serve as a backup means of protection in the event RILMIT is shorted to ground disabling
the programmable current limit function.
10.3.10.1 Current Limit Setting using RILIMIT
Refer to Figure 10-13. The TPS25846-Q1 can establish current limit by two methods.
• Using external a single or back-to-back N-Channel MOFETs between CSN/OUT and BUS: A voltage of 0.49
V on the ILIMIT pin initiates current limiting using the external MOSFET by decreasing the LS_GD voltage
causing the FET to operate in the saturation region. To protect the MOSFETs from damage a hiccup timer
limits the duty cycle to prevent thermal runaway. Refer to the Specifications for MOSFET hiccup timing.
• Buck average current limit: No MOSFET, CSN/OUT connected to BUS. In this configuration a voltage of 1 V
across RILIMIT on the ILIMIT pin initiates average current limiting of the buck regulator.
The two level current limit is described below:
• With external MOSFET Figure 10-14:
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– Isolating a fault on the USB port from other loads connected to the CSP output of the TPS25846-Q1. In
some applications, it may be useful to power additional circuitry (for example: USB HUB) from the output
of the TPS25846-Q1 and maintain operation of these circuits in the event of a short circuit downstream
of the BUS pin. To prevent triggering the MOSFET current limit below the programmed ILIMIT threshold,
external circuits should be supplied after the inductor and before the current sense resistor, RSNS.
– After RSNS and RSET are determined and the full load ISET current is known, the resistor value RILIMIT can
be determined by:
(6)
– In most cases, the recommended voltage across RSNS under current limit should be approximately 50 mV
as a compromise between accuracy and power dissipation. While in some application, RILIMIT is the only
resistor that can be changed to achieve different current limit. Typical RILIMIT resistors value are listed in
Table 10-2 given the condition RSNS = 15 mΩ and RSET = 300 Ω.
Table 10-2. Setting the Current Limit with RILIMIT
Current-Limit Threshold (mA)
•
RILIMIT (kΩ)
With External MOSFET
Without External MOSFET
700
26.1
53.6
1500
12.7
26.1
1700
11.3
22.6
2700
7.15
14.7
3000
6.49
13
3400
5.62
11.5
3800
5.11
10.5
Buck Average Current Limit Figure 10-15:
1. CSN/OUT connected directly to BUS, the TPS25846-Q1 can operate as a stand-alone USB charging
port. In this configuration, the internal buck regulator operates with average current limiting as
programmed by the ILIMIT pin, potentially producing less heat compared to N-channel MOSFET current
limiting.
2. After RSNS and RSET are determined and the full load ISET current is known, the resistor value RILIMIT can
be determined by:
(7)
3. Typical RILIMIT resistors value are listed in Table 10-2 given the condition RSNS = 15 mΩ and RSET = 300
Ω.
28
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Figure 10-14. Current Limit with External MOSFET
Figure 10-15. Buck Average Current Limit
10.3.10.2 Buck Average Current Limit Design Example
To start the procedure, the ILOAD(MAX), RSNS and RSET, must be known.
1. Determine ILIMIT, usually chose ILIMIT= ILOAD(MAX) / (1 – 10%).
2. Determine RSNS to achieve 50 mV at current limit. For 3-A load current, choose ILIMIT = 3.3A. RSNS = (0.05
V / 3.3 A) = 15 mΩ.
3. Choose RSET = 300 Ω.
4. According to Equation 7, RLIMIT = 300 / (0.5 × ( 3.3 × 0.015 + 0.0007)) = 11.95 kΩ.
5. Choose standard 11.8 kΩ.
10.3.10.3 External MOSFET Gate Drivers
The TPS25846-Q1 has integrated NFET gate drivers, and can support current limit with external NFET. Refer to
Figure 10-14.
The LS_GD pin of TPS25846-Q1 can source 3-uA (typical) current to enhance the external MOSFET. A 6.2-V
clamp between LS_GD and CSN/OUT pin limits the gate-to-source voltage. During DCDC start up, the LS_GD
gate drivers begin to source current after VCSN/OUT reach 3 V. If the VCSN/OUT > 7.5 V or VBUS > 7 V under
overvoltage condition, the LS_GD will turn off immediately with 35-uA (typical) sink current.
If load current above NFET current limit threshold, LS_GD will also turn off the NFET after 2 ms (typical) and
enter hiccup mode to protect NFET from thermal issue. Refer to Figure 11-24 for application waveform.
In real application, if VBUS short to VBAT function is needed, 20 V back-to-back NFET is suggested in circuit
design.
10.3.10.4 Cycle-by-Cycle Buck Current Limit
The buck regulator cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode
will be activated if a fault condition persists to prevent over-heating.
High-side MOSFET overcurrent protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Refer to
the Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum
peak current threshold IHS_LIMIT which is constant. So the peak current limit of the high-side switch is not affected
by the slope compensation and remains constant over the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch will be kept ON so that inductor current keeps ramping down,
until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch will be turned OFF and
the HS switch will be turned on after a dead time. This is somewhat different than the more typical peak current
limit, and results in Equation 8 for the maximum load current.
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(8)
If VCSN/OUT < 2-V typical due to a short circuit for 128 consecutive cycles, hiccup current protection mode will be
activated. In hiccup mode, the regulator will be shut down and kept off for 118 ms typically, then TPS25846-Q1
go through a normal re-start with soft start again. If the short-circuit condition remains, hiccup will repeat until
the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents over-heating and potential damage to the device and serves as a backup to the programmable current
limit see Current Limit Setting using RILIMIT. Once the output short is removed, the hiccup delay is passed, the
output voltage recovers normally as shown in Figure 11-21.
10.3.11 Overvoltage, IEC and Short-to-Battery Protection
The TPS25846-Q1 integrates OVP and short to battery protection on VBUS, DM_IN and DP_IN pins. These pins
can withstand voltage up to 18 V, and can protect upstream processor or Hub data line when overvoltage or
short to battery condition occurs. Refer to Figure 9-3 for the short-to-battery test setup.
The TPS25846-Q1 also integrates IEC ESD cell on DP_IN and DM_IN pins.
10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
The TPS25846-Q1 integrates overvoltage protection on both BUS and CSN/OUT pin, to meet different
application requirement.
BUS pin can withstand up to 18 V, and the OVP threshold is 7-V typical. Once overvoltage is detected on
BUS pin, the LS_GD will turn off immediately, also FAULT asserts after 8-ms deglitch time. Once the excessive
voltage is removed, the LS_GD will turn on again and FAULT deasserts.
CSN/OUT pin can withstand up to 20 V, and the OVP threshold is 7.5-V typical. Once overvoltage is detected on
CSN/OUT pin, the buck converter will stop regulation, also LS_GD will turn off immediately. Once the excessive
voltage is removed, the buck converter will resume and the LS_GD will turn on again.
Figure 10-16. Current Limit with External MOSFET
Figure 10-17. Buck Average Current Limit
As shown in Figure 10-16, TPS25846-Q1 is configured in external FET current limit mode. When short to
battery occurs on BUS_Connector, the external MOSFET will be turn off immediately after BUS pin detect over
voltage. The FAULT signal will assert after 8-ms deglitch time, see Figure11-28. With Back-to-back FET, the
TPS25846-Q1 can withstand short to battery event even when Vin is off. A 10-Ω 0805 resistor is recommended
between BUS pin and BUS_Connector.
As shown in Figure 10-17, TPS25846-Q1 is configured in buck average current limit mode. When short to
battery occurs on BUS_Connector, the buck regulator will stop switching after CSN/OUT pin detect overvoltage.
The FAULT signal will also assert after 8-ms deglitch time. A 100-Ω 0805 resistor is recommended between BUS
pin and BUS_Connector in buck average current limit mode.
30
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10.3.11.2 DP_IN and DM_IN Protection
DP_IN and DM_IN protection consists of IEC ESD and overvoltage protection.
The DP_IN and DM_IN pins integrate an IEC ESD cell to provide ESD protection up to ±15-kV air discharge
and ±8-kV contact discharge per IEC 61000-4-2 (See the ESD Ratings section for test conditions). The IEC
ESD performance of the TPS25846-Q1 device depends on the capacitance connected from BUS pin to GND. A
0.22-µF capacitor placed close to the BUS pin is recommended.
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors like the parasitic resistance and
inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and
humidity of the environment can cause some difference, so the IEC performance should always be verified in the
end-application circuit.
Overvoltage protection (OVP) is provided for short-to-VBUS or short-to-battery conditions in the vehicle harness,
preventing damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9
V (typical), the TPS25846-Q1 device immediately turn off DP/DM switch, and responds to block the high-voltage
reverse connection to DP_OUT and DM_OUT. FAULT signal will assert after 8-ms deglitch time. See Figure
11-30.
For DP_IN and DM_IN, when OVP is triggered, the device turns on an internal discharge path with 416-kΩ
resistance to ground. On removal of the overvoltage condition, the pin automatically turns off this discharge path
and returns to normal operation by turning on the previously affected analog switch.
10.3.12 Cable Compensation
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered
to the load. Cable droop compensation linearly increases the voltage at the CSN/OUT pin of TPS25846-Q1 as
load current increases with the objective of maintaining VBUS_CON (the bus voltage at the USB connector) at 5 V,
regardless of load conditions. Most portable devices charge at maximum current when 5 V is present at the USB
connector. Figure 10-18 provides an example of resistor drops encountered when designing an automotive USB
system with a remote USB connector location.
Figure 10-18. Automotive USB Resistances
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Output Voltage (V)
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5.x
V(DROP)
VOUT with compensation
VBUS with compensation
VBUS without compensation
1
2
3
Output Current (A)
Figure 10-19. Voltage Drop
The TPS25846-Q1 detects the load current and increases the voltage at the CSN/OUT pin to compensate the IR
drop in the charging path according to the gain set by the RSNS, RSET, and RIMON resistors as described in RSNS,
RSET, RILIMIT, and RIMON.
The amount of cable droop compensation required can be estimated by the following equation ΔVOUT = (RSNS
+ RDSON_NFET + RWIRE) × IBUS . RIMON is then chosen by RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS), Where
ΔVOUT is the desired cable droop compensation voltage at full load.
In most cases, the recommended voltage across RSNS should be 50 mV, see the RSNS, RSET, RILIMIT, and RIMON
section. In type-C application, typical RIMON resistors value are listed in Table 10-3 given the condition full load
current = 3 A, RSNS = 15 mΩ and RSET = 300 Ω.
Table 10-3. Setting the Cable Compensation Voltage with RIMON
Cable Compensation Voltage at 3-A Full Load (V)
RIMON (kΩ)
0.3
4.02
0.6
8.06
0.9
12.1
1.2
16.2
1.5
20
Note
The maximum cable compensation voltage in TPS25846-Q1 is 1.5 V.
10.3.12.1 Cable Compensation Design Example
To start the procedure, the RSNS, RDSON_NFET and wire resistance RWIRE, must be known.
1. Determine RSNS to achieve 50 mV at full current. For 3.3 A (3-A load current plus at approximately 10% for
overcurrent threshold). RSNS = (0.05 V / 3.3 A) = 15 mΩ.
2. RDSON_NFET = 50 mΩ
3. RWIRE = 200 mΩ
4. ΔVOUT = (RSNS + RDSON_NFET + RWIRE) × IBUS = (0.015 + 0.05 + 0.2) × 3 = 0.795 V
5. Choose RSET = 300 Ω
6. RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS) = (0.795 × 300 × 2) / (3 × 0.015) = 10.6 kΩ
32
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10.3.13 USB Port Control
The TPS25846-Q1 include DP_IN, DM_IN pins for automatic or host facilitated USB port power management
of a Type-A downstream facing connector. For details on configuring the TPS25846-Q1, see Device Functional
Modes.
10.3.14 FAULT Response
The device features an active-low, open-drain fault output. Connect a 100-kΩ pullup resistor from FAULT to VCC
or other suitable I/O voltage. FAULT can be left open or tied to GND when not used.
Table 10-4 summarizes the conditions that generate a fault and actions taken by the device.
Table 10-4. Fault and Warning Conditions
EVENT
Overcurrent on OUT
Overvoltage on BUS
CONDITION
ACTION
The device regulates current at ISNS either by external NFET
or by the buck regulator control loop.
When current limiting by external NFET, there is NO fault
indicator assertion under minor overload conditions.
NFET or Buck average current limit
When current limiting by buck average current, there is NO
implemented, see Current Limit Setting using fault indicator assertion under minor overload conditions.
RILIMIT.
Heavy overload conditions or hard shorts during average
ICSN/OUT > programmed ISNS.
buck current limiting may trigger buck hiccup operation. The
FAULT indicator asserts immediately after NOC cycles in and
persists for TOC as specified in Cycle-by-Cycle Buck Current
Limit.
The device turns on the BUS discharge path in the event
of an overvoltage conditions, and turn off the LS_GD and
Data Switch immediately. The FAULT indicator asserts and
de-asserts with a 8-ms deglitch.
VBUS > VBUS_OV
Overvoltage on the data lines DP_IN or DM_IN > VDx_IN_OV
The device immediately shuts off the USB data switches.
The FAULT indicator asserts and de-asserts with a 8-ms
deglitch.
10.3.15 USB Specification Overview
Universal Serial Bus specifications provide critical physical and electrical requirements to electronics
manufacturers of USB capable equipment. Adherence to these specifications during product development
coupled with standardized compliance testing assures very high degrees of interoperability amongst USB
products in the market. Since its inception in the mid 1990s, USB has undergone a number of revisions
to enhance utility and extend functionality. For the most up to date standards, please consult the USB
Implementers Forum (USB-IF).
All USB ports are capable of providing a 5-V output making them a convenient power source for operating
and charging portable devices. USB specification documents outline specific power requirements to ensure
interoperability. In general, a USB 2.0 port host port is required to provide up to 500 mA; a USB 3.0 or USB 3.1
port is required to provide up to 900 mA; ports adhering to the USB Battery Charging 1.2 Specification provide
up to 1500 mA; and newer Type-C ports can provide up to 3000 mA. Though USB standards governing power
requirements exist, some manufacturers of popular portable devices created their own proprietary mechanisms
to extend allowed available current beyond the 1500-mA maximum per BC 1.2. While not officially part of
the standards maintained by the USB-IF, these proprietary mechanisms are recognized and implemented by
manufacturers of USB charging ports.
The TPS25846-Q1 device supports the most-common USB-charging schemes BC1.2 in popular hand-held
media and cellular devices.
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP, supported)
• Charging downstream port (CDP, supported)
• Dedicated charging port (DCP, NOT supported)
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BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable
equipment. Under this definition, CDP and DCP are defined as charging ports.
Table 10-5 lists the difference between these port types.
Table 10-5. Operating Modes Table
PORT TYPE
SUPPORTS USB2.0 COMMUNICATION
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
SDP (USB 2.0)
YES
0.5
SDP (USB 3.0 and 3.1)
YES
0.9
CDP
YES
1.5
DCP
NO
1.5
10.3.16 TPS25846-Q1 Control mode
The TPS25846-Q1 supports three mode below controlled by the CTRL1 and CTRL2 pins.
Table 10-6. TPS25846-Q1 Control Mode
DEVICE
TPS25846-Q1
CTRL1
CTRL2
MODE
SUPPORT USB 2.0
COMMUNICATION
0
0
Client Mode
Stub Connection Only
0
1
Client Mode
Stub Connection Only
1
0
SDP
Stub Connection Only
1
1
CDP
Stub Connection Only
CURRENT LIMIT (typ)
Buck disable
BY RSNS, RSET, RILIMIT
10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
The IN pins are the input power path to the TPS25846-Q1 devices. The internal LDO and buck regulator high
side switch are supplied from the IN pins. The CSN/OUT pin connects to the negative terminal of the current
sense amplifier and the internal voltage feedback network. This pin must be connected to the output LC filter
for proper operation. PGND is the power ground return. For optimum performance, ensure the IN pin is properly
bypassed to PGND with adequate bulk and high-frequency bypass capacitance located as close to these pins as
possible.
10.3.18 Thermal Shutdown
The device has an internal overtemperature shutdown threshold, TSD to protect the device from damage and
overall safety of the system. When device temperature exceeds TSD, the LD_GD pin is pulled low, and the buck
regulator stops switching. The device attempts to power-up when die temperature decreases by approximately
20°C.
34
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10.4 Device Functional Modes
10.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS25846-Q1. When VEN is below 1.2 V (typical), the
device is in shutdown mode. The TPS25846-Q1 also employs VIN and VCC undervoltage lock out protection. If
VIN or VCC voltage is below their respective UVLO level, the regulator will be turned off.
10.4.2 Active Mode
The TPS25846-Q1 is in Active Mode when VEN is above the precision enable threshold, VIN and VCC are above
their respective UVLO levels. The simplest way to enable the TPS25846-Q1 is to connect the EN pin to VIN pin.
This allows self startup when the input voltage is in the operating range: 3.8 V to 36 V and a UFP detection is
made. Refer to VCC, VCC_UVLO and Enable/UVLO for details on setting these operating levels.
In Active Mode, the TPS25846-Q1 buck regulator operates with forced pulse width modulation (FPWM), also
referred to as forced continuous conduction mode (FCCM). This ensures the buck regulator switching frequency
remains constant under all load conditions. FPWM operation provides low output voltage ripple, tight output
voltage regulation, and constant switching frequency. Built-in spread-spectrum modulation aids in distributing
spectral energy across a narrow band around the switching frequency programmed by the RT/SYNC pin. Under
light load conditions the inductor current is allowed to go negative. A negative current limit of IL_NEG is imposed
to prevent damage to the regulator's low side FET. During operation the TPS25846-Q1 will synchronize to any
valid clock signal on the RT/SYNC input.
10.4.3 Device Truth Table (TT)
The device truth table (Table 10-7) lists all valid combinations for the two control pins (CTRL1 and CTRL2). The
TPS25846-Q1 devices monitor the CTRL inputs and transitions to whichever charging mode it is commanded.
Table 10-7. Truth Table
DEVICE(S)
TPS25846-Q1
(1)
CTRL1
CTRL2
CURRENT LIMIT
SETTING
0
0
Buck Disable
Client Mode(1)
OFF
Mode(1)
OFF
0
1
Buck Disable
1
0
1
1
See Current Limit
Setting using RILIMIT
USB MODES
BUCK REGULATOR
LS_GD
OFF
Client
OFF
SDP Mode
ON
CDP Mode
ON
TPS25846-Q1: USB data switches ON during client mode.
10.4.4 USB Port Operating Modes
10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
An SDP is a traditional USB port that follows USB 2.0, USB 3.0 or USB 3.1 protocol. A USB 2.0 SDP supplies
a minimum of 500 mA per port and supports USB 2.0 communications. A USB 3.x SDP supplies a minimum of
900 mA per port and supports USB 3.0 or USB 3.1 communications. For both types, the host controller must be
active to allow charging.
10.4.4.2 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. A CDP provides
power and meets the USB 2.0 requirements for device enumeration. USB-2.0 communication is supported, and
the host controller must be active to allow charging. The difference between CDP and SDP is the host-charge
handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and
allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During step one, the portable equipment outputs a nominal
0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the
connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device
detects the connection to a CDP if the D– voltage is greater than the nominal data detect voltage of 0.3 V and
optionally less than 0.8 V.
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The second step is necessary for portable equipment to determine whether the equipment is connected to a
CDP or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input
on the D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read
remains less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a
DCP if the data line being read is greater than the nominal data detect voltage of 0.3 V.
10.4.4.3 Client Mode and Firmware Update
The TPS25846-Q1 device integrates client mode as shown in Figure 10-20. During Client Mode, only the data
analog switch is ON, the Buck regulator will be disabled, so the external MOSFET can be saved. LS_GD is LOW
in this mode, so if there has the external MOSFET, this MOSFET power switch will be OFF. Client mode can be
used by automotive USB system manufacturers and OEMs for factory-only software programming via the USB
port.
When set the CTRL1/2 pin to "0 0" or "0 1", the TPS25846-Q1 will enter the Client Mode after about 150-ms
(tDEGLA) deglitch time.
Note: when update the firmware update or program software via the USB port, it must configure the device in
Client Mode. Using CDP or SDP mode to program software is strictly prohibited, since that will cause some
system level application issues.
Figure 10-20. Client-Mode Equivalent Circuit
10.4.5 High-Bandwidth Data-Line Switches
The TPS25846-Q1 device passes the D+ and D– data lines through the device to enable monitoring and
handshaking while supporting the charging operation. A wide-bandwidth signal switch allows data to pass
through the device without corrupting signal integrity. The data-line switches are turned on in any of the CDP,
SDP, or client operating modes. The EN input must be at logic high for the data line switches to be enabled.
•
•
•
•
36
Note
While in CDP mode, the data switches are ON, even during CDP handshaking.
The data line switches are OFF if EN/UVLO is low.
The data line switches are ON during Average current limit or External FET current limit conditions.
The data switches are only for a USB-2.0 differential pair. In the case of a USB-3.0 host, the superspeed differential pairs must be routed directly to the USB connector without passing through the
TPS2584x device.
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11 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
11.1 Application Information
The TPS25846-Q1 is a step down DC-to-DC regulator and USB charge port controller. The device is typically
used in automotive systems to convert a DC voltage from the vehicle battery to 5-V DC with a maximum output
current of 3 A. The following design procedure can be used to select components for the TPS25846-Q1.
11.2 Typical Application
The TPS25846-Q1 only requires a few external components to convert from a wide voltage range supply to a
5-V output for powering USB devices. Figure 11-1 shows a basic schematic.
Figure 11-1. Application Circuit
The integrated buck regulator of TPS25846-Q1 is internally compensated and optimized for a reasonable
selection of external inductance and capacitance. The external components have to fulfill the needs of the
application, but also the stability criteria of the device's control loop. Table 11-2 can be used to simplify the output
filter component selection.
11.2.1 Design Requirements
To begin the design process, a few parameters must be known:
•
Cable compensation: Total resistance including cable resistance, contact resistance of connectors,
TPS25846-Q1 current sense resistor and external NFET rDS(on) (if used). Refer to Figure 10-18 for examples
of resistance in an automotive application.
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•
The maximum continuous output current for the charging port. The minimum current-limit setting of
TPS25846-Q1 device must be higher than this current.
For this example, use the parameters listed in Table 11-1 as the input parameters.
Table 11-1. Design Example Parameters
PARAMETER
VALUE
Input Voltage, VIN
13.5-V typical, range from 6 V to 18 V
Output Voltage, VOUT
5.1 V
Maximum Output Current IOUT(MAX)
3.0 A
Transient Response 0.3 A to 3 A
5%
Output Voltage Ripple
50 mV
Input Voltage Ripple
400 mV
Switching Frequency fSW
400 kHz
Cable Resistance for Cable Compensation
300 mΩ
Current Limit by Buck Average
3.3 A
Table 11-2. L, and COUT Typical Values
fSW
VOUT without
Cable
Compensation
CIN + CHF
L
Current Limit
CCSP
CCSN/OUT
CBUS
400 kHz
5.10 V
1 × 10 µF + 1 × 100 nF
8.2 µH
Buck Avg
5 × 22 µF
100 nF
1 to 4.7 µF
400 kHz
5.10 V
1 × 10 µF + 1 × 100 nF
8.2 µH
Ext. NFET
5 × 22 µF
100 nF
1 to 4.7 µF
2100 kHz
5.10 V
1 × 10 µF + 1 × 100 nF
2.2 µH
Buck Avg
2 × 22 µF
100 nF
1 to 4.7 µF
1. Inductance value is calculated based on VIN = 18 V.
2. All the COUT values are after derating.
11.2.2 Detailed Design Procedure
11.2.2.1 Output Voltage
The output voltage of TPS25846-Q1 is internally fixed at 5.10 V. Cable compensation can be used to increase
the voltage on the CSN/OUT pin linearly with increasing load current. Refer to Cable Compensation for more
details on output voltage variation versus load current. If cable compensation is not desired, use a 0-Ω RIMON
resistor.
11.2.2.2 Switching Frequency
The recommended switching frequency of the TPS25846-Q1 is in the range of 300-400 kHz for best efficiency.
Choose RRT = 49.9 kΩ for 400-kHz operation. To choose a different switching frequency, refer to Table 10-1.
11.2.2.3 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 10 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND should be 20% to 40%. During an instantaneous short or over current operation event, the RMS and peak
inductor current can be high. The inductor current rating should be higher than the current limit of the device.
'iL
LMIN
38
VOUT u VIN _ MAX
VOUT
VIN _ MAX u L u fSW
VIN _ MAX
VOUT
IOUT u KIND
u
(9)
VOUT
VIN _ MAX u fSW
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In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too
low of an inductance can generate too large of an inductor current ripple such that over current protection at
the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger
inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current
mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple
improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.3, the minimum inductor value is calculated to be 8.7 µH. Choose the
nearest standard 8.2 μH ferrite inductor with a capability of 4 A RMS current and 6-A saturation current.
11.2.2.4 Output Capacitor Selection
The value of the output capacitor, and its ESR, determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements, rather than the
output voltage ripple. Equation 11 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
COUT t
ESR d
D
fSW
'IOUT
˜ 'VOUT ˜ K
º
K2
˜ 2 D»
12
¼»
ª
˜«1 D ˜ 1 K
¬«
2 K ˜ 'VOUT
ª
K2 §
1 ·º
¸»
˜ ¨¨1
2 ˜ 'IOUT «1 K
12 © (1 D) ¸¹¼»
¬«
VOUT
VIN
(11)
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = Ripple factor from Inductor Selection
Once the output capacitor and ESR have been calculated, Equation 12 can be used to check the peak-to-peak
output voltage ripple; Vr.
Vr # 'IL ˜ ESR 2
1
8 ˜ fSW ˜ COUT
2
(12)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example we require a ΔVOUT of ≤ 250 mV for an output current step of ΔIOUT = 2.7 A. Equation 11 gives
a minimum value of 86 µF and a maximum ESR of 0.08 Ω. Assuming a 20% tolerance and a 10% bias de-rating,
we arrive at a minimum capacitance of 110 µF. This can be achieved with a bank of 5 × 22-µF, 10-V, ceramic
capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.
Ceramic capacitors can easily meet the minimum ESR requirements. In some cases an aluminum electrolytic
capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance.
In practice the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and should always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help to reduce high frequency noise. Small case size ceramic capacitors in the range
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of 1 nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance should be limited to about 10 times the design value, or 1000
µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of
start-up at full load and loop stability must be performed.
11.2.2.5 Input Capacitor Selection
The TPS25846-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage ratings
are recommended. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum
input voltage is recommended. The bulk capacitance selection depends upon a number of factors: long leads
from the automotive battery to the IN pin of TPS25846-Q1, cold or warm engine crank requirements and so forth.
The bulk capacitor is used to dampen voltage spike due to the lead inductance of the cable or the trace. For this
design, one 10 μF, 50 V, X7R ceramic capacitors are used. A 0.1 μF for high-frequency filtering and place it as
close as possible to the device pins. Consider adding additional bulk capacitance for operation through low VIN
warm-crank profiles is required by the vehicle OEM.
11.2.2.6 Bootstrap Capacitor Selection
Every TPS25846-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 10 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
11.2.2.7 VCC Capacitor Selection
The VCC pin is the output of an internal LDO for TPS2584x. The LDO supplies gate charge to the LS buck
switch and is the supply to the digital state-machine and analog USB circuitry. To insure stability of the device,
place a minimum of 2.2 μF, 10 V, X7R capacitor from this pin to ground. In addition a 0.1 μF high frequency
decoupling capacitor is highly recommended.
11.2.2.8 Enable and Under Voltage Lockout Set-Point
The system enable and undervoltage lockout (UVLO) is adjusted using the external voltage divider network of
RENT and RENB. The EN/UVLO has two thresholds, one for power up when the input voltage is rising and
one for power down or brown outs when the input voltage is falling. The following equations can be used to
determine the VIN(ON) and VIN(OFF) levels.
(13)
(14)
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ (user choice)
RENT = [(VIN(ON) / (VEN/UVLO_H) – 1] × RENB
RENB = [(6 V / 1.2 V) – 1] × 5 kΩ = 20 kΩ. Choose standard 20 kΩ.
Therefore VIN(OFF) = 6 V × [1 – (0.09 V / 1.2 V)] = 5.55 V
11.2.2.9 Current Limit Set-Point
The TPS25846-Q1 provides an accurate current limit to protect the USB port from overload based upon the
values of RSNS, RSET and RILIMIT. The design process is the same regardless of whether buck average current
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limiting or external NFET current limiting is chosen. The only difference is the current limit threshold voltage on
the ILIMIT pin.
•
•
•
RSNS is the current sense resistor. The recommended voltage across RSNS under current limit should be
approximately 50 mV as a compromise between accuracy and power dissipation. For example, if current
limiting is desired for IOUT(MAX) ≥ 3.3 A, then RSNS = 0.05 V / 3.3 A = 0.01515 Ω. Choose a standard value of
15 mΩ.
RSET determines the input current to the transconductance amplifier and current mirror. The amplifier
balances the voltage to be equal to that across RSNS. Choose a RSET value to produce an ISET current
between 75 - 180 µA at the desired IOUT(MAX). Considering 50 mV across RSET, a value of 300 Ω will provide
approximately 166 µA of ISET current to the amplifier and mirror circuit. Care should be taken to limit the ISET
current below 200 µA to avoid saturating the internal amplifier circuit.
Buck average current limiting occurs when VILIMIT = 1 V. RILIMIT is calculated as 1 V × 300 Ω / [ 0.5 × (3.3 A ×
15 mΩ + 0.7 mV) ] = 11.95 kΩ. A standard 11.8-kΩ value is chosen.
11.2.2.10 Cable Compensation Set-Point
From Table 11-1 the total cable resistance to be accounted for is 300 mΩ.
1.
2.
3.
4.
From Current Limit Set-Point RSNS and RSET have been determined as 15 mΩ and 300 Ω, respectively.
RWIRE = 300 mΩ.
ΔVOUT = (RSNS + RWIRE) × IBUS = (0.015 + 0.3) × 3 = 1.0395 V.
RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS) = (1.0395 × 300 × 2) / (3.3 × 0.015) = 12.6 kΩ. A standard value
of 12.7 kΩ is selected.
11.2.2.11 FAULT Resistor Selection
The FAULT pins are open-drain output flags. They can be connected to the TPS25846-Q1 VCC pin with 100 kΩ
resistors, or connected to another suitable I/O voltage supply if actively monitored by a USB HUB or MCU. They
can be left floating if unused.
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11.2.3 Application Curves
100
100
95
90
90
80
Efficiency (%)
Efficiency (%)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
85
80
75
70
60
0.1
1
OUT Current (A)
VOUT = 5.1 V
60
50
40
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
65
70
20
0.1
4
fSW = 400 kHz
VOUT = 5.1 V
95
90
90
80
Efficiency (%)
Efficiency (%)
100
85
80
75
60
0.1
1
OUT Current (A)
VOUT = 5.1 V
fSW = 400 kHz
70
60
50
VIN = 8.5V
VIN = 13.5V
VIN = 18V
30
20
0.1
4
1
OUT Current (A)
A003
RSENS = 15 mΩ
VOUT = 5.1 V
Figure 11-4. Efficiency With Sense Resistor
4
A004
fSW = 2100 kHz
RSENS = 15 mΩ
Figure 11-5. Efficiency With Sense Resistor
0.4
0.1
VIN = 6V
VIN = 13.5V
VIN = 18V
Load = 1A
Load = 2A
Load = 3A
0.08
Line Regulation (%)
0.3
Load Regulation (%)
A002
fSW = 2100 kHz
40
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
65
4
Figure 11-3. Buck Only Efficiency
100
70
1
OUT Current (A)
A001
Figure 11-2. Buck Only Efficiency
0.2
0.1
0
-0.1
0.06
0.04
0.02
0
-0.02
-0.2
-0.04
0
0.5
VOUT = 5.1 V
1
1.5
2
OUT Current (A)
2.5
3
6
9
12
A005
fSW = 400 kHz
VOUT = 5.1 V
Figure 11-6. Load Regulation
42
VIN = 8.5V
VIN = 13.5V
VIN = 18V
30
15
18
21
24
VIN Voltage (V)
27
30
33
36
A006
fSW = 400 kHz
Figure 11-7. Line Regulation
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VBUS,
200mV/Div
VBUS,
200mV/Div
Load Current,
2A/Div
Load Current,
2A/Div
200us/Div
VOUT = 5.1 V ILOAD = 0 A to 3.5 A
200us/Div
RIMON = 0 Ω
Figure 11-8. Load Transient Without Cable
Compensation
VOUT = 5.1 V
ILOAD = 0.75 A to
2.25 A
RIMON = 0 Ω
Figure 11-9. Load Transient Without Cable
Compensation
VBUS,
500mV/Div
VBUS,
500mV/Div
Load Current,
2A/Div
Load Current,
2A/Div
2ms/Div
2ms/Div
ILOAD = 0 A to 3.5 A
RIMON = 13 kΩ
Figure 11-10. Load Transient With Cable
Compensation
ILOAD = 0.75 A to
2.25A
RIMON = 13 kΩ
Figure 11-11. Load Transient With Cable
Compensation
6
SW,
5V/Div
VBUS Voltage (V)
5.5
5
4.5
4
VBUS,
10mV/Div (AC coupled)
Load = 0A
Load = 1A
Load = 2A
Load = 3A
Load = 3.5A
3.5
3
4
4.5
5
5.5
6
Input Voltage (V)
6.5
7
7.5
A007
Figure 11-12. Dropout Characteristic
2us/Div
RIMON = 13 kΩ
Figure 11-13. 3.5-A Output Ripple
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SW,
5V/Div
SW,
5V/Div
VBUS,
10mV/Div (AC coupled)
VBUS,
10mV/Div (AC coupled)
2us/Div
2us/Div
RIMON = 13 kΩ
RIMON = 13 kΩ
Figure 11-14. 100-mA Output Ripple
EN,
5V/Div
Figure 11-15. No Load Output Ripple
EN,
5V/Div
VIN
5V/Div
VIN
5V/Div
VBUS,
5V/Div
VBUS,
5V/Div
VCC,
5V/Div
VCC,
5V/Div
10ms/Div
40ms/Div
VIN = 0 V to 13.5 V
INT = 5.1 kΩ
ILOAD = 3 A
Figure 11-16. Startup Relate to VIN
VIN = 13.5 V to 0 V
INT = 5.1 kΩ
ILOAD = 3 A
Figure 11-17. Shutdown Relate to VIN
EN, 5V/Div
EN,
5V/Div
VIN
5V/Div
VIN, 5V/Div
VBUS, 2V/Div
VBUS,
2V/Div
VCC, 2V/Div
VCC,
5V/Div
40ms/Div
EN = 0 V to 5 V
INT = 5.1 kΩ
ILOAD = 3 A
Figure 11-18. Startup Relate to EN
44
40ms/Div
EN = 5 V to 0 V
INT = 5.1 kΩ
ILOAD = 3 A
Figure 11-19. Shutdown Relate to EN
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EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
Short removed
FAULT, 2V/Div
VBUS, 2V/Div
VBUS, 2V/Div
Load Current,
5A/Div
100ms/Div
EN to High
VBUS = GND
Load Current, 5A/Div
40ms/Div
RLIMIT = 13 kΩ
Figure 11-20. Enable into Short Without External
FET
RLIMIT = 13 kΩ
Figure 11-21. Short Circuit Recovery Without
External FET
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 1V/Div
1Ÿ load removed
Load Current, 2A/Div
VBUS, 1V/Div
Load Current, 2A/Div
EN to High
VBUS = GND
100ms/Div
100ms/Div
RLIMIT = 13 kΩ
RLIMIT = 13 kΩ
Figure 11-22. Enable Into 1-Ω Load Without
External FET
Figure 11-23. 1-Ω Load Recovery Without External
FET
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
Short removed
FAULT, 2V/Div
VBUS, 2V/Div
VBUS, 2V/Div
Load Current, 2A/Div
Load Current, 2A/Div
100ms/Div
100ms/Div
RLIMIT = 6.8 kΩ
RLIMIT = 6.8 kΩ
Figure 11-24. Enable Into Short With External FET
Figure 11-25. Short Circuit Recovery With External
FET
EN to High
VBUS = GND
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EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 2V/Div
VBUS hot short to
GND
VBUS, 2V/Div
VBUS hot short to
GND
Load Current, 2A/Div
Load Current, 5A/Div
1ms/Div
2ms/Div
RLIMIT = 13 kΩ
RLIMIT = 6.8 kΩ
Figure 11-26. VBUS Hot Short to GND Without
External FET
Figure 11-27. VBUS Hot Short to GND With
External FET
FAULT, 2V/Div
FAULT, 2V/Div
VBUS short to 18V BAT
VBUS, 5V/Div
VBUS, 5V/Div
20ms/Div
2ms/Div
INT = 5.1 kΩ
NO LOAD
INT = 5.1 kΩ
Figure 11-28. VBUS Short to BAT With External
FET
FAULT, 2V/Div
NO LOAD
Figure 11-29. VBUS Short to BAT Recovery With
External FET
FAULT, 2V/Div
VBUS, 5V/Div
DP, 5V/Div
DP short to 18V BAT
DP, 5V/Div
20ms/Div
2ms/Div
INT = 5.1 kΩ
NO LOAD
INT = 5.1 kΩ
Figure 11-30. DP Short to BAT
46
NO LOAD
Figure 11-31. DP Short to BAT Recovery
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12 Power Supply Recommendations
The TPS25846-Q1 is designed to operate from an input voltage supply range between 6 V and 36 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail should be low enough that an input current transient does not cause a high enough drop
at the TPS25846-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input
supply is located more than a few inches from the TPS25846-Q1, additional bulk capacitance may be required
in addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
13 Layout
13.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
For more detailed EMC design consideration and test report, please refer to the PCB Layout and Parameters
Recommendation for TPS2583X EMC Performance application report.
1. Input capacitor: The input bypass capacitor CIN must be placed as close as possible to the IN and PGND
pins. Grounding for both the input and output capacitors should consist of localized top side planes that
connect to the PGND pin and PAD. A combination of different values and packages of capacitors can help
improve the EMC performance (for example: 10 μF + 0.1 μF + 2.2 nF). Besides, the distance between the
input filter section and the output power section must be at least 15mm to prevent the output high-frequency
signal from coupling into the input filter. A 10-uF cap cross VIN and PGND pin on top of SW is suggested for
TPS25846-Q1.
2. VCC bypass capacitor: Place bypass capacitors for VCC close to the VCC pin and ground the bypass
capacitor to device ground.
3. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
4. Connect the thermal pad to the ground plane. The QFN package has a thermal pad (PAD) connection that
must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of
this solder connection has a direct bearing on the total effective RθJA of the application.
5. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
6. Provide enough PCB area for proper heat sinking. As stated in the section, enough copper area must
be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature.
Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce. Use an array of
heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB
design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer
heat-spreading ground planes.
7. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the
load current without excessive heating. Short, thick traces or copper pours (shapes) will bring a high current
conduction capacity to minimize parasitic resistance, but it will also cause a larger parasitic capacitance.
Thus a balance should be found between smaller parasitic resistance and larger parasitic capacitance. And
the current path should be kept straight forward to the inductor, otherwise the L-shaped or T-shaped path
will make a sudden change of the impedance which causes signal reflection and impacts the performance of
EMC. The output capacitors should be placed close to the VOUT end of the inductor and closely grounded to
PGND pin and exposed PAD. Besides, do not punch vias on SW lines. Using shielded inductors or molded
inductors to reduce high-frequency radiation.
8. Sense and Set Resistors: The RSNS and RSET resistors connect to the current sense amplifier inputs at the
CSP and CSN/OUT pins. For best current limit and cable compensation accuracy; short, parallel traces give
the best performance. If it is not possible to place RSNS and RSET near the CSP and CSN/OUT pins, it is
recommended that the traces from sense resistor be routed in parallel and of similar lengths. A small filter
capacitor in parallel with RSNS and a small filter capacitor from CSN/OUT to AGND help decouple noise.
9. RILIMIT and RIMON resistors should be placed as close as possible to the ILIMIT and IMON pins and
connected to AGND. If needed, these components can be placed on the bottom side of the PCB with signals
routed through small vias.
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10. Trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal
differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference
GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
11. Keep the CC lines close to the same length. Do not create stubs or test points on the CC lines.
12. BUCK_STand FAULT are open-drain outputs. They can be connected to the VCC pin via pull-up resistors.
Suggested resistor value is 100 kΩ.
13. The area enclosed by current loop of input side and output side should be as small as possible; the area
enclosed by the BOOT circuit should be as small as possible.
14. Power ground PGND and the signal ground AGND should be separated in the actual PCB layout.
13.2 Layout Example
Figure 13-1. Layout Example
13.3 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The PGND pins
should be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is connected
to the source of the internal LS switch. The PGND net contains noise at switching frequency and may bounce
due to load variations. PGND trace, as well as VIN and SW traces, should be constrained to one side of the
ground plane. The other side of the ground plane contains much less noise and should be used for sensitive
routes. AGND and PGND should be connected under the QFN package PAD.
48
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It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 2 row, 2 column "+" array of 12 mil thermal vias to connect the PAD to the system ground
plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for
system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the
copper thickness for the four layers, starting from the top of 2 oz, 1 oz, 1 oz, 2 oz. Four layer boards with enough
copper thickness provide low current conduction impedance, proper shielding and lower thermal resistance.
The thermal characteristics of the TPS25846-Q1 are specified using the parameter θJA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD × θJA + TA
(15)
where
TJ = Junction temperature in °C
PD = VIN × IIN × (1 - Efficiency) – 1.1 × IOUT 2 × DCR in Watt
DCR = Inductor DC parasitic resistance in Ω
θJA = Junction to ambient thermal resistance of the device in °C/W
TA = Ambient temperature in °C
θJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow.
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14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
Texas Instruments, PCB Layout and Parameters Recommendation for TPS2583X EMC Performance application
report
14.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
14.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
50
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS25846QCWRHBRQ1
ACTIVE
VQFN
RHB
32
5000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T25846
TPS25846QWRHBRQ1
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
T25846
TPS25846QWRHBTQ1
PREVIEW
VQFN
RHB
32
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
T25846
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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