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TPS259250, TPS259251, TPS259260, TPS259261
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
TPS25925x, TPS25926x Simple 5-V/12-V eFuse Protection Switches
1 Features
3 Description
•
•
•
•
The TPS25925x/6x family of eFuses is a highly
integrated circuit protection and power management
solution in a tiny package. The devices use few
external components and provide multiple protection
modes. They are a robust defense against overloads,
shorts circuits, voltage surges, excessive inrush
current. Current limit level can be set with a single
external resistor and current limit set has a typical
accuracy of ±15%. Over voltage events are limited by
internal clamping circuits to a safe fixed maximum,
with no external components required. TPS25926x
devices provide over voltage protection (OVP) for 12V systems and TPS25925x devices for 5-V systems.
In cases with particular voltage ramp requirements, a
dV/dT pin is provided that can be programmed with a
single capacitor to ensure proper output ramp rates.
12-V eFuse – TPS25926x
5-V eFuse – TPS25925x
Integrated 30-mΩ Pass MOSFET
Fixed Over-Voltage Clamp:
– 6.1-V Clamp - TPS25925x
– 15-V Clamp - TPS25926x
2-A to 5-A Adjustable ILIMIT (±15% Accuracy)
Programmable VOUT Slew Rate, UVLO
Built-in Thermal Shutdown
UL 2367 Recognized – File No. E339631*
– *RILIM ≤ 130 kΩ (5 A maximum)
Safe During Single Point Failure Test (UL60950)
Small Foot Print – 10L (3 mm x 3 mm) VSON
1
•
•
•
•
•
•
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
HDD and SSD Drives
Set Top Boxes
Servers and AUX Supplies
PCI and PCIe Cards
Adapter Powered Devices
TPS259250,
TPS259251
TPS259260,
TPS259261
R1
3.00 mm × 3.00 mm
Transient: Output Short Circuit
OUT
VIN
VSON (10)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Schematic
VIN
PACKAGE
OUT
30 m:
COUT
EN/UVLO
R2
dV/dT
CdVdT
GND
ILIM
RLIM
TPS25925x/6x
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS259250, TPS259251, TPS259260, TPS259261
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions......................
Thermal Information .................................................
Electrical Characteristics..........................................
Timing Requirements ...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 23
10.1 Transient Protection .............................................. 23
10.2 Output Short-Circuit Measurements ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision A (August 2015) to Revision B
•
Page
Updated Features, Description, Feature Description and Device Functional Modes section ................................................ 1
Changes from Original (August 2015) to Revision A
•
2
Page
Changed from Product Preview to Production Data............................................................................................................... 1
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Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
TPS259250, TPS259251, TPS259260, TPS259261
www.ti.com
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
5 Device Comparison Table
PART NUMBER
UV
OV CLAMP
FAULT RESPONSE
STATUS
TPS259250
4.3 V
6.1 V
Latched
Active
TPS259251
4.3 V
6.1 V
Auto Retry
Active
TPS259260
4.3 V
15 V
Latched
Active
TPS259261
4.3 V
15 V
Auto Retry
Active
6 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
dV/dT 1
EN/UVLO
VIN
VIN
GND
VIN 5
10 ILIM
NC
OUT
OUT
6 OUT
Pin Functions
PIN
No.
1
NAME
dV/dT
TYPE
O
DESCRIPTION
Connect a capacitor from this pin to GND to control the ramp rate of OUT
voltage at device turnon
EN/UVLO
I
This is a dual function control pin. When used as an ENABLE pin and pulled
down, it shuts off the internal pass MOSFET. When pulled high, it enables the
device
As an UVLO pin, it can be used to program different UVLO trip point via
external resistor divider
VIN
I
Input supply voltage
OUT
O
Output of the device
9
NC
NC
10
ILIM
O
Thermal Pad
GND
Ground
2
3
4
5
6
7
8
Copyright © 2015–2016, Texas Instruments Incorporated
Not Connected Internally. Can be left floating or grounded
A resistor from this pin to GND sets the overload and short circuit limit
GND
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3
TPS259250, TPS259251, TPS259260, TPS259261
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
www.ti.com
7 Specifications
7.1
Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
Supply voltage (2)
Output voltage
Voltage
(1) (2)
VIN
MIN
MAX
–0.3
20
VIN (transient < 1 ms)
UNIT
V
22
OUT
–0.3
VIN + 0.3
OUT (transient < 1 µs)
V
–1.2
ILIM
–0.3
Continuous output current
7
V
6.25 (3)
A
7
V
Voltage
EN/UVLO
–0.3
Voltage
dV/dT
–0.3
7
V
Storage temperature
Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Device supports high peak current during short circuit conditions until current is internally limited.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
7.3
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
TYP
MAX
VIN (TPS25926x)
4.5
12
13.8
VIN (TPS25925x)
4.5
5
5.5
dV/dT, EN/UVLO
0
6
UNIT
V
ILIM
0
3
Continuous output current
IOUT
0
5
A
Resistance
ILIM
10
100
162
kΩ
OUT
0.1
1
1000
µF
1
1000
nF
External capacitance
dV/dT
Operating junction temperature
TJ
–40
25
125
°C
Operating ambient temperature
TA
–40
25
85
°C
4
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Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
TPS259250, TPS259251, TPS259260, TPS259261
www.ti.com
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
7.4 Thermal Information (1)
over operating free-air temperature range (unless otherwise noted)
TPS25925x/6x
THERMAL METRIC
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
RθJCtop
Junction-to-case (top) thermal resistance
45.9
°C/W
53
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
21.2
°C/W
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
21.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
5.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5
Electrical Characteristics
–40°C ≤ TJ ≤ +125°C, VIN = 12 V for TPS25926x, VIN = 5 V for TPS25925x, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN.
All voltages referenced to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.3
4.45
V
VIN (INPUT SUPPLY)
VUVR
UVLO threshold, rising
VUVhyst
UVLO hysteresis (1)
IQON
Supply current
IQOFF
4.15
5%
Enabled: EN/UVLO = 2 V, TPS25926x
0.3
0.47
0.55
mA
Enabled: EN/UVLO = 2 V, TPS25925x
0.35
0.42
0.6
mA
0.13
0.225
mA
EN/UVLO = 0 V
VIN > 16.5 V, IOUT = 10 mA, TPS25926x
VOVC
Over-voltage clamp
13.8
15
16.5
VIN > 6.75 V, IOUT = 10 mA,
–40℃ ≤ TJ ≤ +85℃, TPS25925x
5.5
6.1
6.75
VIN > 6.75 V, IOUT = 10 mA,
–40℃ ≤ TJ ≤ +125℃, TPS25925x
5.25
6.1
6.75
V
EN/UVLO (ENABLE/UVLO INPUT)
VENR
EN threshold voltage, rising
1.37
1.4
1.44
VENF
EN threshold voltage, falling
1.32
1.35
1.39
V
IEN
EN input leakage current
–100
0
100
nA
0 V ≤ VEN ≤ 5 V
V
dV/dT (OUTPUT RAMP CONTROL)
IdVdT
dV/dT charging current (1)
VdVdT = 0 V
RdVdT_disch
dV/dT discharging resistance
EN/UVLO = 0 V, IdVdT = 10 mA sinking
VdVdTmax
dV/dT maximum capacitor voltage (1)
GAINdVdT
dV/dT to OUT gain (1)
220
50
ΔVdVdT
73
nA
100
Ω
5.5
V
4.85
V/V
ILIM (CURRENT LIMIT PROGRAMMING)
ILIM bias current (1)
IILIM
IOL
Overload current limit (2)
10
µA
RILIM = 45.3 kΩ, VVIN-OUT = 1 V
1.75
2.1
2.45
RILIM = 100 kΩ, VVIN-OUT = 1 V
3.4
3.75
4.05
RILIM = 150 kΩ, VVIN-OUT = 1 V
4.5
5.1
5.7
A
IOL-R-Short
RILIM = 0 Ω, shorted resistor current limit (single point failure
test: UL60950) (1)
0.84
A
IOL-R-Open
RILIM = OPEN, open resistor current limit (single point failure
test: UL60950) (1)
0.73
A
(1)
(2)
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.
Copyright © 2015–2016, Texas Instruments Incorporated
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SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
www.ti.com
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +125°C, VIN = 12 V for TPS25926x, VIN = 5 V for TPS25925x, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN.
All voltages referenced to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Short-circuit current limit (2)
ISCL
MIN
TYP
MAX
RILIM = 45.3 kΩ, VVIN-OUT = 5 V, TPS25925x
1.72
2.05
2.42
RILIM = 45.3 kΩ, VVIN-OUT = 12 V, TPS25926x
2.37
1.62
1.98
RILIM = 100 kΩ, VVIN-OUT = 5 V, TPS25925x
3.1
3.56
4
RILIM = 100 kΩ, VVIN-OUT = 12 V, TPS25926x
2.9
3.32
3.85
RILIM = 150 kΩ, VVIN-OUT = 5 V, TPS25925x
4.22
4.95
5.69
RILIM = 150 kΩ, VVIN-OUT = 12 V, TPS25926x
3.7
4.5
5.5
RATIOFASTRIP
Fast-trip comparator level w.r.t.
overload current limit (1)
IFASTRIP : IOL
VOpenILIM
ILIM open resistor detect
threshold (1)
VILIM Rising, RILIM = OPEN
UNIT
A
160%
3.1
V
OUT (PASS FET OUTPUT)
Turnon delay (1)
TON
RDS(on)
EN/UVLO → H to IVIN = 100 mA, 1-A resistive load at OUT
FET ON resistance
IOUT-OFF-LKG
IOUT-OFF-SINK
OUT bias current in off state
TJ = 25°C
220
21
TJ = 125°C
µs
30
39
40
50
VEN/UVLO = 0 V, VOUT = 0 V (sourcing)
–5
0
1.2
VEN/UVLO = 0V, VOUT = 300 mV (sinking)
10
15
20
mΩ
µA
THERMAL SHUT DOWN (TSD)
TSHDN
TSD threshold, rising (1)
TSHDNhyst
TSD hysteresis (1)
Thermal fault: latched or autoretry
150
°C
10
°C
TPS259250, TPS259260
Latched
TPS259251, TPS259261
Auto-retry
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
Turnoff delay (1)
tOFFdly
MIN
EN↓
TYP
MAX
0.4
UNIT
µs
dV/dT (OUTPUT RAMP CONTROL)
tdVdT
Output ramp time
TPS25926x, EN/UVLO → H to OUT = 11.7 V, CdVdT =
0
0.7
1
1.3
TPS25925x, EN/UVLO → H to OUT = 4.9 V, CdVdT = 0
0.28
0.4
0.52
TPS25926x, EN/UVLO → H to OUT = 11.7 V,
CdVdT = 1 nF (1)
12
TPS25925x, EN/UVLO → H to OUT = 4.9 V,
CdVdT = 1 nF (1)
5
ms
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly
Fast-trip comparator delay (1)
IOUT > IFASTRIP to IOUT= 0 (Switch off)
300
At VIN = 5 V, TPS259251 and TPS259261
110
At VIN = 12 V, TPS259251 and TPS259261
145
ns
THERMAL SHUTDOWN (TSD)
tTSDdly
(1)
6
Retry delay after TSD recovery,
TJ < [TSHDN – 10oC] (1)
ms
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
TPS259250, TPS259251, TPS259260, TPS259261
www.ti.com
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
7.7 Typical Characteristics
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
4.35
0.25
0.2
IQ-OFF (mA)
Input UVLO (Rising, Falling) (V)
4.3
4.25
4.2
4.15
0.15
0.1
4.1
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
0.05
4.05
4
0
-50
0
50
100
150
Temperature (ƒC)
0
5
Figure 1. Input UVLO vs Temperature
15
20
C002
Figure 2. IQ-OFF vs VIN
0.6
1
0.5
0.8
0.4
IVIN-ON (mA)
IVIN-ON (mA)
10
VIN (V)
C001
0.3
0.6
0.4
0.2
125 °C
85 °C
25 °C
-40 °C
0.1
0
0
5
10
15
VIN (V)
125 °C
85 °C
25 °C
-40 °C
0.2
0
20
0
5
TPS25926x
15
20
C004
TPS25925x
Figure 3. IVIN-ON vs VIN
16
10
VIN (V)
C003
Figure 4. IVIN-ON vs VIN
6.6
10 mA
100 mA
500 mA
6.4
6.2
VOVC (V)
VOVC (v)
15.5
6
5.8
15
5.6
14.5
-50
0
50
100
Temperature (ƒC)
150
5.4
-50
C005
10 mA
0
50
Temperature (oC)
100
150
TPS25925x
TPS25926x
Figure 5. VOVC vs Temperature Across IOUT
Copyright © 2015–2016, Texas Instruments Incorporated
Figure 6. VOVC vs Temperature
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SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
www.ti.com
Typical Characteristics (continued)
35
160
30
140
25
RILIM Resistor (k:)
Accuracy (Process, Voltage, Temperature) (%)
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
20
15
10
120
100
80
60
40
5
20
0
0
1
1.5
2
2.5
3
3.5
4
Overload Current Limit (A)
4.5
5
2.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
Overload Current Limit (A)
D001
Figure 7. Accuracy vs Overload Current Limit
C005
Figure 8. RILM Resistor vs Overload Current Limit
150
60
50
100
TdVdT (ms)
TdVdT (ms)
40
50
30
20
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
0
0
2
4
6
8
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
10
0
10
CdVdT (nF)
0
2
4
TPS25926x
6
8
CdVdT (nF)
C013
10
C014
TPS25925x
Figure 9. TdVdT vs CdVdT
Figure 10. TdVdT vs CdVdT
1.41
45
40
1.39
RDSON (m:)
VEN-VIH VEN-VIL (V)
1.4
Rising
1.38
Falling
1.37
30
1.36
25
1.35
1.34
20
-50
0
50
100
Temperature (oC)
Figure 11. VEN-VIH, VEN-VIL vs Temperature
8
35
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150
±50
0
50
100
150
Temperature (oC)
Figure 12. RDSON vs Temperature
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
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SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
0.95
0.8
IOL-R-OPEN (A)
IOL-R-SHORT (A)
0.9
0.85
0.75
0.7
0.8
0.75
-50
0
50
Temperature (oC)
100
150
0.65
-50
RILIM = 0Ω
50
Temperature (oC)
100
150
D001
RILIM = OPEN
Figure 13. IOL-R-Short vs Temperature
Figure 14. IOL-R-Open vs Temperature
160
4
140
3.5
120
3
IVOUT (A)
tTSDdly (ms)
0
D001
100
80
2.5
2
60
o
125 C
o
85 C
o
25 C
o
-40 C
1.5
40
1
20
4.5
0
6
7.5
9
10.5 12
VVIN (V)
13.5
15
16.5
0.5
18
1
1.5
2
VVIN-OUT (V)
D001
RILIM = 100 kΩ
Figure 16. IVOUT vs VVIN-OUT
Figure 15. Retry Delay vs VVIN
6
2.2
2
5
IVOUT (A)
IVOUT (A)
1.8
4
3
1.6
1.4
o
o
125 C
85oC
o
25 C
o
-40 C
2
1
0
0.5
1
1.5
125 C
o
85 C
o
25 C
o
-40 C
1.2
1
2
0
VVIN-OUT (V)
RILIM = 150 kΩ
0.5
1
1.5
2
VVIN-OUT (V)
RILIM = 45.3 kΩ
Figure 17. IVOUT vs VVIN-OUT
Copyright © 2015–2016, Texas Instruments Incorporated
Figure 18. IVOUT vs VVIN-OUT
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
2
2
0
IOL, ISC (% Normalized)
IOL, ISC (% Normalized)
0
-2
-4
-6
IOL-150K
ISC-150K-925x
ISC-150K-926x
-8
-10
-12
-2
-4
IOL-100K
ISC-100K-925x
ISC-100K-926x
-6
-8
-10
-14
-12
-16
-50
0
50
100
-50
150
0
RILIM = 150 kΩ
100
150
RILIM = 100 kΩ
Figure 19. IOL, ISC vs Temperature
Figure 20. IOL, ISC vs Temperature
10000
1
Thermal Shutdown Time (ms)
0
IOL, ISC (% Normalized)
50
Temperature (oC)
Temperature (oC)
-1
-2
IOL-45.3k
ISC-45.3K-925x
ISC-45.3K-926x
-3
-4
-5
-6
-50
0
50
Temperature
100
1000
100
10
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
1
0.1
0.1
150
1
10
Power Dissipation (W)
(oC)
100
D001
RILIM = 45.3 kΩ
Figure 21. IOL, ISC vs Temperature
Figure 22. Thermal Shutdown Time vs Power Dissipation
EN
C1
C2
EN
VIN
C2
C2
C2
C3
VOUT
C3
I_IN
C4
C4
TPS25926x, CdVdT = OPEN, COUT = 4.7 µF
Figure 23. Transient: Output Ramp
10
VIN
C1
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VOUT
I_IN
TPS25925x, CdVdT = OPEN, COUT= 4.7 µF
Figure 24. Transient: Output Ramp
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
VIN
VIN
VOUT
VOUT
C2
C2
C2
C3
C3
TPS25925x
TPS25926x
Figure 25. Transient: Over-Voltage Clamp
TPS259251/61, VVIN = 5 V
Figure 26. Transient: Over-Voltage Clamp
TPS259250/60 , VVIN = 5 V
Figure 27. Transient: Thermal Fault Auto-Retry
TPS25925x/6x, VVIN = 5 V, RILIM = 150 kΩ
Figure 29. Transient: Output Short Circuit
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Figure 28. Transient: Thermal Fault Latched
TPS25925x/6x, VVIN = 5 V, RILIM = 150 kΩ
Figure 30. Short Circuit (Zoom): Fast-Trip Comparator
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
TPS259251/61 , VVIN = 5 V
TPS259251/61 , VVIN = 5 V, CdVdT = 1nF
Figure 31. Transient: Wake Up to Short Circuit
TPS25926x , VVIN = 12 V, RILIM = 150 kΩ
Figure 33. Transient: Output Short Circuit
TPS25926x, VVIN = 12 V
TPS25926x, VVIN = 12 V, RILIM = 150 kΩ
Figure 34. Short Circuit (Zoom): Fast-Trip Comparator
TPS25926x, VVIN = 12 V, CdVdT = 1 nF
Figure 35. Transient: Wake Up to Short Circuit
12
Figure 32. Transient: Recovery from Short Circuit
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Figure 36. Transient: Recovery from Short Circuit
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V for TPS25926x, VVIN = 5 V for TPS25925x, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF,
CdVdT = OPEN (unless stated otherwise)
TPS25926x, VVIN = 12 V
ILOAD stepped From 65% to 125%, back to 65%
Figure 37. Transient: Thermal Fault Auto-Retry
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Figure 38. Transient: Overload Current Limit
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8 Detailed Description
8.1 Overview
The TPS25925x/6x is an e-fuse with integrated power switch that is used to manage current, voltage and start-up
voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds
the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables
the internal MOSFET. As VIN rises, the internal MOSFET of the device starts conducting and allow current to
flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has
the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current and input voltage,
ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN,
typically 150°C, the thermal shutdown circuitry shuts down the internal MOSFET thereby disconnecting the load
from the supply. In TPS259250/60, the output remains disconnected (MOSFET open) until power to device is
recycled or EN/UVLO is toggled (pulled low and then high). The TPS259251/61 device remains off and
commences an auto-retry cycle of 145 ms after device temperature falls below TSHDN – 10°C. This auto-retry
cycle continues until the fault is cleared.
8.2 Functional Block Diagram
VIN
OUT
3,
4,
5
+
4.3V
4.08V
EN/
UVLO
Current
Sense
UVLO
6,
7,
8
30m:
Charge
Pump
+
2
9
EN
1.4V
1.35V
Over
Voltage
Thermal
ShutDown
6V
SWEN
GATE
CONTROL
TSD
6V
VIN
220nA
10uA
+
ILIMIT
dV/dT
4.8x
1
10
+
SWEN
EP
ILIM
+
70pF
GND
N/C
80:
Fast Trip
Comp
1.6*ILIMIT
8.3 Feature Description
8.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.
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Feature Description (continued)
8.3.2 VIN
Input voltage to the TPS25925x/6x. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V – 13.8 V for
TPS25926x and 4.5 V – 5.5 V for TPS25925x. The device can continuously sustain a voltage of 20 V on VIN pin.
However, above the recommended maximum bus voltage, the device is in over-voltage protection (OVP) mode,
limiting the output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN – VOVC) × IOUT, which
can potentially heat up the device and cause thermal shutdown.
8.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Governing slew rate at startup is shown in Equation 1.
dVOUT IdVdT ´ GAINdVdT
=
dt
CdVdT + CINT
(1)
Where:
IdVdT = 220 nA (TYPICAL)
CINT = 70 pF (TYPICAL)
GAINdVdT = 4.85
dVOUT
= Desired output slew rate
dT
The total ramp time (TdVdT) for 0 to VIN can be calculated using Equation 2.
TdVdT = 106 ´ VIN ´ (CdVdT + 70 pF )
(2)
For details on how to select an appropriate charging time/rate, see the applications section Setting Output
Voltage Ramp Time (TdVdT).
8.3.4 EN/UVLO
As an input pin, it controls both the ON and OFF state of the internal MOSFET. In its high state, the internal
MOSFET is enabled and allows current to flow from VIN to OUT. A low on this pin turns off the internal
MOSFET. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS259250/60 by toggling this pin (H→L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 µs typical) for quick detection of
power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is
particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.
8.3.5 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After
start-up event and during normal operation, current limit is set to IOL (over-load current limit). See Equation 3.
(
IOL = 0.7 + 3 ´ 10-5 ´ RILIM
)
(3)
When power dissipation in the internal MOSFET [PD = (VVIN – VOUT) × IOUT] exceeds 10 W, there is a 2% to 12%
thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature. See Figure 39.
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Feature Description (continued)
0
Foldback (ISC - IOL)/IOL (%)
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
Power (W)
40
50
60
Figure 39. Thermal Foldback in Current Limit
During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond to this event because of its limited bandwidth. Therefore, the TPS25925/6 incorporates
a fast-trip comparator, which shuts down the pass device when IOUT > IFASTRIP, and terminates the rapid shortcircuit peak current. The trip threshold is set to 60% higher than the programmed over-load current limit (IFASTRIP
= 1.6 x IOL). After the transient short-circuit peak current has been terminated by the fast-trip comparator, the
current limit amplifier smoothly regulates the output current to IOL. See Figure 40 and Figure 41.
Figure 40. Fast-Trip Current
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Figure 41. Fast-Trip and Current Limit Amplifier Response
for Short Circuit
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8.4 Device Functional Modes
The TPS25925x/6x is a hot-swap controller with integrated power switch that is used to manage current, voltage
and start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When
VVIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on
this pin enables the internal MOSFET. As VIN rises, the internal MOSFET of the device starts conducting and
allows current to flow from VIN to OUT. When EN/UVLO is held low (that is, below VENF), the internal MOSFET is
turned off; thereby, blocking the flow of current from VIN to OUT. The user can modify the output voltage ramp
time by connecting a capacitor between dV/dT pin and GND.
Having successfully completed its start-up sequence, the device now actively monitors the load current and input
voltage, ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. If the device temperature (TJ) exceeds TSHDN, typically
150°C, the thermal shutdown circuitry shuts down the internal MOSFET; thereby, disconnecting the load from the
supply. In the TPS259250/60, the output remains disconnected (MOSFET open) until power to device is recycled
or EN/UVLO is toggled (pulled low and then high). The TPS259251/61 device remains off and commences an
auto-retry cycle of 145 ms after device temperature falls below TSHDN – 10°C. This auto-retry cycle continues until
the fault is cleared.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPA25925x/6x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs, HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web
folder.
9.2 Typical Application
V(IN)
4.5 to 18 V
R1
1MO
V(OUT)
IN
C*IN
0.1µF
COUT
1µF
30mO
EN/UVLO
**
R2
dVdT
GND
ILIM
TPS25926x
RILIM
100kO
**Optional & only needed for external UVLO
*Optional & only for noise suppression
* CIN is optional and 0.1 µF is recommended to suppress transients due to the inductance of PCB routing or from
input wiring.
Figure 42. Typical Application Schematic: Simple e-Fuse for Set Top Boxes
9.2.1 Design Requirements
Table 1 lists the TPA25925x/6x design requirements.
Table 1. Design Parameters
18
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage , VIN
12 V
Undervoltage lockout set point, V(UV)
Default: VUVR = 4.3 V
Overvoltage protection set point , V(OV)
Default: VOVC = 15 V
Load at start-up, RL(SU)
4Ω
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Typical Application (continued)
Table 1. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Current limit, IOL
3.7 A
Load capacitance, COUT
1 µF
Maximum ambient temperatures, TA
85°C
9.2.2 Detailed Design Procedure
To
•
•
•
•
•
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Normal input operation voltage
Maximum output capacitance
Maximum current Limit
Load during start-up
Maximum ambient temperature of operation
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
9.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
I
- 0.7
RILIM = ILIM
3 x 10-5
(4)
For ILIM = 3.7 A, from Equation 4, RILIM is 100 kΩ, choose closest standard value resistor with 1% tolerance.
9.2.2.2 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5.
R + R2
V(UV) = 1
´ VENR
R2
(5)
Where VENR is enable voltage rising threshold (1.4 V). Because R1 and R2 leak the current from input supply
(Vin), these resistors must be selected based on the acceptable leakage current from input power supply (Vin).
The current drawn by R1 and R2 from the power supply {I(R12) = V(IN)/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, I(R12) must be chosen to be 20x greater than the leakage
current expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Because EN/UVLO pin is rated only to 7
V, it cannot be connected directly to VIN = 12 V. It has to be connected through R1 = 1 MΩ only, so that the pullup current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, VUVR. This is calculated using Equation 6.
V(PFAIL) = 0.96 x VUVR
(6)
Where VUVR is 4.3 V, Power fail threshold set is : 4.1 V.
9.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
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The ramp-up capacitor CdVdT needed is calculated considering the two possible cases.
9.2.2.3.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 8.
For TPS25926x device, the inrush current is determined as shown in Equation 7.
I(INRUSH) = C(OUT) x
V(IN)
TdVdT
(7)
Power dissipation during start-up is:
PD(INRUSH) = 0.5 x V(IN) x I(INRUSH)
(8)
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
9.2.2.3.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
When load draws current during the turn-on sequence, there is additional power dissipated. Considering a
resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during
TdVdT time. Equation 9 to Equation 12 show the average power dissipation in the internal FET during charging
time due to resistive load.
V 2(IN)
æ 1ö
PD(LOAD) = çç ÷÷÷ x
çè 6 ø R
L(SU)
(9)
Total power dissipated in the device during startup is:
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(10)
Total current during startup is given by:
I(STARTUP) = I(INRUSH) + IL (t)
(11)
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by:
é
æ
öù
ç
ê
÷÷÷ú
çç I
ê
ú
÷
ç
ê IOL
(INRUSH) ÷÷ú
÷ú
- 1 + LNççç
TdVdT(Current-Limited) = COUT x RL(SU) x ê
÷
÷
V
ç
êI
(IN) ÷÷ú
ç
ê (INRUSH)
÷÷ú
çççIOL - R
ê
÷øú
L(SU)
è
ë
û
(12)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in Figure 43.
Thermal Shutdown Time (ms)
10000
1000
100
10
1
0.1
0.1
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
1
10
Power Dissipation (W)
100
D001
Figure 43. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2.
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TdVdT = 106 x 12 x (0 + 70 pF ) = 840 ms
(13)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 14.
I(INRUSH) = 1 mF x
12
= 15 mA
840 ms
(14)
The inrush power dissipation is calculated using Equation 15.
PD(INRUSH) = 0.5 x 12 x 15 m = 90 mW
(15)
For 90 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time TdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 43 at TA =
85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any
load on output.
Considering the start-up with load 4 Ω, the additional power dissipation, when load is present during start up is
calculated using Equation 9.
PD(LOAD) =
12 x 12
=6W
6 ´ 4
(16)
The total device power dissipation during start up is given in Equation 17.
PD(STARTUP) = 6 + 90 m = 6.09 W
(17)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 6.09 W is more than 10 ms. So it
is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 4 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of
CdVdT capacitor.
9.2.2.4 Support Component Selection—CVIN
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.
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9.2.3 Application Curves
TPS25926x
TPS25926x
Figure 44. Hot-Plug Start-Up: Output Ramp without Load
on Output
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Figure 45. Hot-Plug Start-Up: Output Ramp with 24-Ω Load
at Start Up
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10 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
10.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 18.
L(IN)
VSPIKE(Absolute) = V(IN) + I(LOAD) x
C(IN)
(18)
Where:
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 46.
IN
4.5 to 18 V
IN
OUT
OUT
(Note 1)
CIN
30mO
EN/UVLO
(Note 1)
(Note 1)
dV/dT
GND
(1)
ILIM
TPS25925x/6x
Optional components needed for suppression of transients
Figure 46. Circuit Implementation with Optional Protection Components
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www.ti.com
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
24
For all applications, a 0.01-µF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 47 for a PCB layout example.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
Locate all TPS25925x/6x support components: RILIM, CdVdT and resistors for ENUV, close to their connection
pin. Connect the other end of the component to the GND pin of the device with shortest trace length. The
trace routing for the RILIM and CdVdT components to the device must be as short as possible to reduce
parasitic effects on the current limit and soft start timing. These traces must not have any coupling to
switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
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Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
TPS259250, TPS259251, TPS259260, TPS259261
www.ti.com
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
11.2 Layout Example
Top layer
Bottom layer signal ground plane
Via to signal ground plane
dV/dT
1
10 ILIM
EN/UVLO
2
9
N/C
VIN
3
8
OUT
VIN
4
7
OUT
5
6
VIN
OUT
Ground Bottom
layer
VIN
VOUT
*
*
VIN
High Frequency
Bypass Capacitor
Power Ground
* Optional: Needed only to suppress the transients caused by inductive load switching
Figure 47. Layout Example
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
25
TPS259250, TPS259251, TPS259260, TPS259261
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• TPS2592xx Design Calculator, SLUC570
• TPS259250-61EVM: Evaluation Module for TPS259250/61, SLUUB64
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS259250
Click here
Click here
Click here
Click here
Click here
TPS259251
Click here
Click here
Click here
Click here
Click here
TPS259260
Click here
Click here
Click here
Click here
Click here
TPS259261
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
26
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
TPS259250, TPS259251, TPS259260, TPS259261
www.ti.com
SLVSCQ3B – AUGUST 2015 – REVISED JUNE 2016
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS259250 TPS259251 TPS259260 TPS259261
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS259250DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259250
TPS259250DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259250
TPS259251DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259251
TPS259251DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259251
TPS259260DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259260
TPS259260DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259260
TPS259261DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259261
TPS259261DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
259261
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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