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TPS2592ZA, TPS2592ZL
SLVSCU3 – DECEMBER 2014
TPS2592Zx 4.5-V to 18-V eFuse with Blocking FET Control
Not Recommended for New Designs
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TPS2592xx family of eFuses is a highly
integrated circuit protection and power management
solution in a tiny package. The devices use few
external components and provide multiple protection
modes. They are a robust defense against overloads,
shorts circuits, voltage surges, excessive inrush
current, and reverse current.
1
4.5-V to 18-V Protection
Integrated 28-mΩ Pass MOSFET
Absolute Maximum Voltage of 20 V
1-A to 2.1-A Adjustable ILIMIT
Reverse Current Blocking Support
Programmable OUT Slew Rate, UVLO
Built-in Thermal Shutdown
Safe during Single Point Failure Test (UL60950)
Small Foot Print – 10L (3 mm x 3 mm) VSON
Many systems, such as SSDs, must not allow holdup
capacitance energy to dump back through the FET
body diode onto a drooping or shorted input bus. The
BFET pin is for such systems. An external NFET can
be connected “Back to Back (B2B)” with the TPS2592
output and the gate driven by BFET to prevent
current flow from load to source.
2 Applications
•
•
•
•
•
•
Current limit level can be set with a single external
resistor. Applications with particular voltage ramp
requirements can set dV/dT pin with a single
capacitor to ensure proper output ramp rates.
HDD and SSD Drives
Set Top Boxes
Servers / AUX Supplies
Fan Control
PCI/PCIe Cards
Adapter Powered Devices
Device Information(1)
PART NUMBER
TPS2592ZA
TPS2592ZL
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Transient: Output Short Circuit
4 Application Schematic
OUT
VIN
VIN
OUT
VIN
28m:
R1
VOUT
COUT
EN/UVLO
BFET
dV/dT
ILIM
C2
R2
CdVdT
GND
RLIM
C3
TPS2592xx
C1
I_OUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Not Recommended for New Designs
TPS2592ZA, TPS2592ZL
SLVSCU3 – DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Application Schematic ..........................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
4
8.1
8.2
8.3
8.4
8.5
8.6
8.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Typical Characteristics ..............................................
9.4 Device Functional Modes........................................ 14
10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
10.2 Typical Applications ............................................. 15
10.3 Maximum Device Power Dissipation
Considerations ......................................................... 19
11 Power Supply Recommendations ..................... 20
11.1 Transient Protection .............................................. 20
11.2 Output Short-Circuit Measurements ..................... 20
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
13.5
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 11
Device Support ....................................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
5 Revision History
2
DATE
REVISION
NOTES
December 2014
*
Initial release
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Product Folder Links: TPS2592ZA TPS2592ZL
Not Recommended for New Designs
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SLVSCU3 – DECEMBER 2014
6 Device Comparison Table
PART NUMBER
UV
OV CLAMP
FAULT RESPONSE
TPS2592ZA
4.3 V
—
Auto-retry
STATUS
Active
TPS2592ZL
4.3 V
—
Latched
Preview
7 Pin Configuration and Functions
10-Pin VSON
DRC Package
(Top View)
dV/dT 1
EN/UVLO
VIN
VIN
10 ILIM
BFET
OUT
OUT
6 OUT
GND
VIN 5
Pin Functions
PIN
NAME
DESCRIPTION
NUMBER
BFET
9
Connect this pin to the gate of a blocking NFET. See the Feature Description.
dV/dT
1
Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.
EN/UVLO
2
This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal
pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.
GND
PowerPAD™
ILIM
10
GND
A resistor from this pin to GND will set the overload and short circuit limit.
OUT
6-8
Output of the device
VIN
3-5
Input supply voltage
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3
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SLVSCU3 – DECEMBER 2014
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8 Specifications
8.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
(1) (2)
VIN
Supply voltage range (1)
20
UNIT
V
22
OUT
–0.3
VIN + 0.3
V
-1.2
V
OUT (Transient < 1 µs)
Voltage
ILIM
–0.3
7
EN/UVLO
–0.3
7
dV/dT
–0.3
7
BFET
–0.3
30
Continuous power dissipation
V
See the Thermal Information
Maximum power dissipation (3),
PD = (VVIN-VOUT)*ILIMIT
TA = –40°C to +85°C
40
TA = 0°C to +85°C
50
Storage temperature range, Tstg
(2)
(3)
MAX
VIN (10 ms Transient)
Output voltage
(1)
MIN
–0.3
-65
W
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Refer detailed explanation in the application section Maximum Device Power Dissipation Considerations .
8.2 ESD Ratings
MAX
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage range
TYP
MAX
4.5
18 (1)
BFET
0
VIN+6
dV/dT, EN/UVLO
0
6
3.3
VIN
UNIT
V
ILIM
0
Continuous output current
IOUT
0
1.7
A
Resistance
ILIM
10
45.3
kΩ
OUT
0.1
1
1000
µF
1
1000
nF
External capacitance
dV/dT
Operating junction temperature range, TJ
–40
25
125
°C
Operating Ambient temperature range, TA
–40
25
85
°C
(1)
4
Maximum voltage (including input transients) at VIN pin should not exceed absolute maximum rating as specified in Absolute Maximum
Ratings.
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SLVSCU3 – DECEMBER 2014
8.4 Thermal Information (1)
over operating free-air temperature range (unless otherwise noted)
TPS2592Zx
THERMAL METRIC
RθJA
Junction-to-ambient thermal resistance
RθJCtop
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
21.2
ψJT
Junction-to-top characterization parameter
1.2
ψJB
Junction-to-board characterization parameter
21.4
RθJCbot
Junction-to-case (bottom) thermal resistance
5.9
(1)
UNIT
DRC (10) PINS
45.9
53
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 45.3 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.3
4.45
V
0.42
0.65
mA
0.1
0.25
mA
V
VIN (INPUT SUPPLY)
VUVR
UVLO threshold, rising
VUVhyst
UVLO hysteresis (1)
IQON
IQOFF
4.15
5.4%
Enabled: EN/UVLO = 2 V
Supply current
0.2
EN/UVLO = 0 V
EN/UVLO (ENABLE/UVLO INPUT)
VENR
EN Threshold voltage, rising
1.37
1.4
1.44
VENF
EN Threshold voltage, falling
1.32
1.35
1.39
V
IEN
EN Input leakage current
–100
0
100
nA
0 V ≤ VEN ≤ 5V
dV/dT (OUTPUT RAMP CONTROL)
IdVdT
dV/dT Charging current (1)
VdVdT = 0 V
RdVdT_disch
dV/dT Discharging resistance
EN/UVLO = 0 V, IdVdT = 10 mA sinking
VdVdTmax
dV/dT Max capacitor voltage (1)
GAINdVdT
dV/dT to OUT gain (1)
220
50
ΔVdVdT
73
nA
100
Ω
5.5
V
4.85
V/V
ILIM (CURRENT LIMIT PROGRAMMING)
ILIM Bias current (1)
IILIM
10
IOL
RILIM = 45.3 kΩ, VVIN-OUT = 1 V
IOL-R-Short
Overload current limit (2)
IOL-R-Open
(2)
1.79
2.10
µA
2.42
A
RILIM = 0 Ω, Shorted Resistor Current Limit (Single Point
Failure Test: UL60950) (1)
0.7
A
RILIM = OPEN, Open Resistor Current Limit (Single Point
Failure Test: UL60950) (1)
0.55
A
ISCL
Short-circuit current limit
RATIOFASTRIP
Fast-Trip comparator level w.r.t.
overload current limit (1)
RILIM = 45.3 kΩ, VVIN-OUT = 12 V
IFASTRIP : IOL
VOpenILIM
ILIM Open resistor detect
threshold (1)
VILIM Rising, RILIM = OPEN
1.66
1.98
2.29
A
160%
3.1
V
OUT (PASS FET OUTPUT)
RDS(on)
IOUT-OFF-LKG
IOUT-OFF-SINK
(1)
(2)
FET ON resistance
OUT Bias current in off state
TJ = 25°C
21
TJ = 125°C
28
33
39
46
VEN/UVLO = 0 V, VOUT = 0 V (Sourcing)
–5
0
1
VEN/UVLO = 0V, VOUT = 300 mV (Sinking)
10
15
20
mΩ
µA
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 45.3 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BFET (BLOCKING FET GATE DRIVER)
BFET Charging current (1)
IBFET
VBFET = VOUT
(1)
VBFETmax
BFET Clamp voltage
RBFETdisch
BFET Discharging resistance to
GND
VEN/UVLO = 0 V, IBFET = 100 mA
15
2
µA
VVIN +
6.4
V
26
36
Ω
TSD (THERMAL SHUT DOWN)
TSHDN
TSD Threshold, rising (1)
TSHDNhyst
TSD Hysteresis (1)
Thermal fault: latched or autoretry
160
°C
10
°C
TPS2592ZL
LATCHED
TPS2592ZA
AUTO-RETRY
8.6 Timing Requirements
PARAMETER
Turn-on delay (1)
TON
tOFFdly
Turn Off delay
(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN/UVLO → H to IVIN = 100 mA, 1-A resistive load at
OUT
220
µs
EN↓ to BFET↓, CBFET = 0
0.4
µs
dV/dT (OUTPUT RAMP CONTROL)
EN/UVLO → H to OUT = 11.7 V, CdVdT = 0
tdVdT
Output ramp time
0.7
EN/UVLO → H to OUT = 11.7 V,
CdVdT = 1 nF (2)
1
12
1.3
ms
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly
Fast-Trip comparator delay (2)
IOUT > IFASTRIP to IOUT= 0 (Switch Off)
3
µs
BFET (BLOCKING FET GATE DRIVER)
tBFET-ON
BFET Turn-On duration (2)
tBFET-OFF
BFET Turn-off duration (2)
(1)
(2)
6
EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF
4.2
EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF
42
EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF
0.4
EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF
1.4
ms
µs
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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8.7 Typical Characteristics
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 45.3 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
4.35
0.25
0.2
4.25
IQ-OFF (mA)
Input UVLO (Rising, Falling) (V)
4.3
4.2
4.15
0.15
0.1
4.1
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
0.05
4.05
4
0
-50
0
50
100
150
Temperature (ƒC)
0
5
10
15
20
VIN (V)
C001
Figure 1. Input UVLO vs Temperature
C002
Figure 2. IQOFF vs VIN
250
0.6
0.5
TON (Ps)
IVIN-ON (mA)
230
0.4
0.3
0.2
125 °C
85 °C
25 °C
-40 °C
0.1
0
0
5
10
15
VIN (V)
210
190
170
20
150
C003
-50
TPS2592Zx
0
50
100
150
Temperature (oC)
Figure 4. TON vs Temperature
Figure 3. IVIN-ON vs VIN
230
150
225
TdVdT (ms)
IdVdT (nA)
100
220
215
50
125 ƒC
85 ƒC
25 ƒC
-40 ƒC
210
205
0
-50
0
50
100
Temperature (ƒC)
150
0
2
4
6
8
CdVdT (nF)
C010
10
C013
TPS2592Zx
Figure 5. IdVdT vs Temperature
Figure 6. TdVdT vs CdVdT
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 45.3 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
1.41
100
1.39
10
Rising
IEN (nA)
VEN-VIH VEN-VIL (V)
1.4
1.38
Falling
1.37
125ƒC
85ƒC
25ƒC
-40ƒC
1
1.36
1.35
1.34
0.1
-50
0
50
100
150
0
1
2
Temperature (oC)
EN
4
5
Figure 8. IEN (Leakage Current) vs VEN
Figure 7. VEN_VIH, VEN_VIL vs Temperature
C1
C2
3
VEN (V)
VIN
EN
C1
C2
VOUT
C2
C2
C3
VOUT
C3
I_OUT
I_IN
C4
C4
TPS2592Zx, CdVdT = OPEN, COUT = 4.7 µF
EN ↓
Figure 9. Transient: Output Ramp:
Figure 10. Transient: Turn Off Delay
VIN
EN
C1
C2
VOUT
VOUT
C1
C2
BFET
BFET
C3
C3
C2
C2
EN↓
VIN↓
Figure 11. Turn Off Delay to BFET
8
Figure 12. Turn Off Delay to BFET
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SLVSCU3 – DECEMBER 2014
Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 45.3 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
2.2
45
2
1.8
IVOUT (A)
RDSON (m:)
40
35
30
RILIM = 45.3 kW
1.6
1.4
o
25
125 C
o
85 C
o
25 C
o
-40 C
1.2
1
20
-50
0
50
100
0
150
0.5
Temperature (oC)
1
1.5
2
VVIN-OUT (V)
45.3 kΩ
Figure 14. IOUT vs VVIN-OUT
1
0.9
0
0.85
-1
-2
IOL-R-SHORT (A)
IOL, ISC (% Normalized)
Figure 13. RDSON vs Temperature
IOL-45.3k
ISC-45.3K-92B_
ISC-45.3K-92A_
-3
-4
-5
0.8
0.75
0.7
0.65
0.6
0.55
-6
0.5
-50
0
50
100
150
-50
0
Temperature (oC)
45.3 kΩ
100
150
RILIM = 0
Figure 15. IOL, ISC vs Temperature
Figure 16. IOL-R-Short vs Temperature
3.1
0.58
ILIM Open Detect Threshold (V)
0.57
0.56
IOL-R-OPEN (A)
50
Temperature (oC)
0.55
0.54
0.53
0.52
0.51
0.5
3.09
3.08
3.07
3.06
3.05
-50
0
50
100
150
-50
0
Temperature (oC)
50
100
150
Temperature (oC)
RILIM = OPEN
Figure 17. IOL-R-Open vs Temperature
Figure 18. VOpenILIM vs Temperature
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 45.3 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
VIN
VIN
VOUT
VOUT
C2
C2
C3
C3
C1
C2
I_OJT
C1
C2
Figure 19. Transient: Output Short Circuit
I_OUT
Figure 20. Short Circuit (Zoom): Fast-trip Comparator
EN
C1
C2
VIN
VIN
VOUT
VOUT
C2
C2
C3
I_IN
C3
I_OUT
C4
C1
C2
ILOAD Stepped From 50% to 120%, back to 50%
TPS2592ZA
Figure 21. Transient: Overload Current Limit
Figure 22. Transient: Thermal Fault Auto-Retry
EN
C1
C2
VIN
C2
C2
C3
VOUT
I_IN
C4
TPS2592ZL
TPS2592Zx, CdVdT = OPEN, COUT = 10 µF
Figure 23. Transient: Thermal Fault Latched
10
Figure 24. Transient: Output Ramp
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9 Detailed Description
9.1 Overview
The TPS2592xx is an e-fuse with integrated power switch that is used to manage current/voltage/start-up voltage
ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds the
undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables the
internal MOSFET. As VIN rises, the internal MOSFET of the device will start conducting and allow current to flow
from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has the
ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current, ensuring that the
adjustable overload current limit IOL is not exceeded. The device also has built-in thermal sensor. In the event
device temperature (TJ) exceeds TSHDN, typically 160°C, the thermal shutdown circuitry will shut down the
internal MOSFET thereby disconnecting the load from the supply. In TPS2592xL, the output will remain
disconnected (MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then
high). The TPS2592xA device will remain off during a cooling period until device temperature falls below TSHDN –
10°C, after which it will attempt to restart. This ON and OFF cycle will continue until fault is cleared.
9.2 Functional Block Diagram
VIN
OUT
3,
4,
5
+
4.3V
4.08V
EN/
UVLO
Current
Sense
UVLO
6,
7,
8
28mW
Charge
Pump
+
2
2mA
EN
1.4V
1.35V
BFET
Over
Voltage
9
SWEN
SWEN
Thermal
Shutdown
6V
GATE
CONTROL
22W
TSD
6V
VIN
220nA
10mA
+
ILIMIT
dV/dT
4.8x
1
EP
10
+
70pF
GND
ILIM
+
80W
SWEN
Fast Trip
Comp
1.6*ILIMIT
9.3 Feature Description
9.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.
9.3.2 VIN
Input voltage to the TPS2592Zx. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 18 V for
TPS2592Zx. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the
recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the
output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN - VOVC) x IOUT, which can
potentially heat up the device and cause thermal shutdown.
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Feature Description (continued)
9.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governing slew rate
at start-up is shown below:
dVOUT IdVdT ´ GAINdVdT
=
dt
CdVdT + CINT
(1)
Where:
IdVdT = 220 nA (TYP)
CINT = 70 pF (TYP)
GAINdVdT = 4.85
dVOUT
= Desired output slew rate
dT
The total ramp time (TdVdT) for 0 to VIN can be calculated using the following equation:
TdVdT = 106 ´ VIN ´ (CdVdT + 70 pF )
(2)
For details on how to select an appropriate charging time/rate, refer to the applications section: Setting Output
Voltage Ramp Time (TdVdT)
9.3.4 BFET
Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the
event of power failure at VIN. The BFET pin is controlled by either UVLO event or EN/UVLO (see Table 1). BFET
can source charging current of 2 µA (TYP) and sink (discharge) current from the gate of the external FET via a
26-Ω internal discharge resistor to initiate fast turn-off, typically 10 MΩ impedance when probing the BFET node.
Table 1.
EN/UVLO > VENR
VIN>VUVR
BFET MODE
H
H
Charge
X
L
Discharge
L
X
Discharge
9.3.5 EN/UVLO
As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the external blocking FET.
In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low on this
pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge
resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS2592xL by toggling this pin (H→L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of
power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on
EN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current. For applications
where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO to GND.
9.3.6 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After
start-up event and during normal operation, current limit is set to IOL (over-load current limit).
(
)
(3)
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IOL = 0.7 + 3 ´ 10-5 ´ RILIM
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When power dissipation in the internal MOSFET [PD = (VVIN -VOUT) × IOUT] exceeds 10 W, there is a 2% – 12%
thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature.
0
Foldback (ISC - IOL)/IOL (%)
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
Power (W)
40
50
60
Figure 25. Thermal Foldback in Current Limit
During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592
incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, and
terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed overload current limit (IFASTRIP = 1.6 x IOL). After the transient short-circuit peak current has been terminated by the
fast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see figure below).
VIN
VOUT
C2
C3
C1
C2
Figure 26. Fast-Trip Current
I_OUT
Figure 27. Fast-Trip and Current Limit Amplifier Response
for Short Circuit
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9.4 Device Functional Modes
The TPS2592xx is a hot-swap controller with integrated power switch that is used to manage
current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN
bus. When VVIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high
level on this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if
connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected)
will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below VENF),
the internal MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to
OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT
pin and GND.
Having successfully completed its start-up sequence, the device now actively monitors its load current and input
voltage, ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN ,
typically 160°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the
load from the supply. In the TPS2592xL, the output will remain disconnected (MOSFET open) until power to
device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS2592xA device will remain off
during a cooling period until device temperature falls below TSHDN – 10°C, after which it will attempt to restart.
This ON and OFF cycle will continue until fault is cleared.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA2592xx is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the
WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design.
Additionally, a spreadsheet design tool TPS2592 Design Calculator (SLUC571) is available on web folder. This
section presents a simplified discussion of the design process.
10.2 Typical Applications
10.2.1 Simple 2.1-A eFuse Protection for Set Top Boxes
VIN = 4.5 to 18 V
IN
*
CVIN
0.1µF
R1
1MO
VOUT, IOUT < 1.7A
OUT
COUT
1µF
28mO
EN/UVLO
**
BFET
R2
dVdT
GND
ILIM
TPS2592x
RILIM
45.3kO
**Optional & only needed for external UVLO
*Optional & only for noise suppression
Figure 28. Typical Application Schematic: Simple e-Fuse for STBs
10.2.1.1 Design Requirements
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range, VIN
12 V
Undervoltage lockout set point, V(UV)
Default: VUVR = 4.3 V
Load at Start-Up , RL(SU)
4Ω
Current limit, IOL = IILIM
2.1 A
Load capacitance , COUT
1 µF
Maximum ambient temperatures , TA
85°C
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10.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS2592xx.
10.2.1.2.1 Step by Step Design Procedure
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
10.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
I
- 0.7
RILIM = ILIM
3 x 10-5
(4)
For IOL = IILIM = 2.1 A, from equation 4, RILIM = 45.3 kΩ, choose closest standard value resistor with 1%
tolerance.
10.2.1.2.3 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5.
R + R2
V(UV) = 1
´ VENR
R2
(5)
Where VENR = 1.4 V is enable voltage rising threshold.
Since R1 and R2 will leak the current from input supply (VIN), these resistors should be selected based on the
acceptable leakage current from input power supply (VIN). The current drawnby R1 and R2 from the power
supply {IR12 = VIN/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current
expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it
cannot be connected directly to VIN = 12 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up
current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, VUVR. This is calculated using Equation 6.
V(PFAIL) = 0.96 x VUVR
(6)
Where VUVR is 4.3V, Power fail threshold set is : 4.1 V
10.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:
10.2.1.2.4.1 Case 1: Start-up without Load: Only Output Capacitance COUT Draws Current During Start-up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 8.
For TPS2592xx, the inrush current is determined as,
I(INRUSH) = C(OUT) x
16
V(IN)
TdVdT
(7)
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Power dissipation during start-up is:
PD(INRUSH) = 0.5 x V(IN) x I(INRUSH)
(8)
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
10.2.1.2.4.2 Case 2: Start-up with Load: Output Capacitance COUT and Load Draws Current During Start-up
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a
resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during
TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given
by:
V 2(IN)
æ 1ö
PD(LOAD) = çç ÷÷÷ x
çè 6 ø R
L(SU)
(9)
Total power dissipated in the device during startup is:
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(10)
Total current during startup is given by:
I(STARTUP) = I(INRUSH) + IL (t)
(11)
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by:
é
ù
æ
÷ö
ê
ççç
÷÷úú
ê
÷
ç
I
ê IOL
(INRUSH) ÷÷ú
÷ú
- 1 + LNççç
TdVdT(Current-Limited) = COUT x RL(SU) x ê
V(IN) ÷÷÷ú
ç
ê I(INRUSH)
ç
ççIOL ê
÷÷÷ú
ê
RL(SU) ÷øú
çè
ë
û
(12)
The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as
shown in Figure 29.
Thermal Shutdown Time (ms)
10000
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
1000
100
10
1
0.1
1
10
Power Dissipation (W)
100
D001
Figure 29. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2.
TdVdT = 106 x 12 x (0 + 70 pF ) = 840 ms
(13)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7.
I(INRUSH) = 1 mF x
12
= 15 mA
840 ms
(14)
The inrush Power dissipation is calculated, using Equation 8.
PD(INRUSH) = 0.5 x 12 x 15 m = 90 mW
(15)
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For 90 mW of power loss, the thermal shut down time of the device should not be less than the ramp-up time
TdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 29 at
TA = 85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without
any load on output.
Considering the start-up with load 4 Ω, the additional power dissipation, when load is present during start up is
calculated, using Equation 9.
PD(LOAD) =
12 x 12
=6W
6 ´ 4
(16)
The total device power dissipation during start up is:
PD(STARTUP) = 6 + 90 m = 6.09 W
(17)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 6.09 W is more than 100 ms. So
it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 4 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of
CdVdT capacitor.
10.2.1.3 Support Component Selection - CVIN
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.
10.2.1.4 Application Curves
Figure 30. Output Ramp without Load on Output
18
Figure 31. Output Ramp with 4-Ω Load at Start Up
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10.3 Maximum Device Power Dissipation Considerations
To prevent damage to the TPS2592x, it is necessary to keep internal power dissipation (PD) below the levels
specified in below Table. The power dissipation is defined as (PD = (VIN – VOUT) x IOUT).
MIN
Maximum Power Dissipation
MAX
–40°C ≤ TA ≤ +85°C
40
0°C ≤ TA ≤ +85°C
50
UNIT
W
During normal operation PD is low ( typically < ½ Watt) because the FET is fully on with low (VIN – VOUT).
However, during short circuit and surge protection the FET may be only partially on and (VIN – VOUT) can be high.
Example 1: Short Circuit on Output → VIN = 15 V, ILIMIT = 2.1 A. TJ = –40°C
• PD = 15 V x 2.1 A = 31.5 W
• OK → (PD = 31.5 W) < (PD_MAX = 40 W)
Example 2: Short Circuit on Output → VIN = 18 V, ILIMIT = 2.1 A
• PD = 18 V x 2.1 A = 37.8 W
• OK at TJ = 0°C → (PD = 37.8 W) < (PD_MAX at 0°C = 50 W)
• OK at TJ = –40°C → (PD = 37.8 W) > (PD_MAX at –40°C = 40 W)
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11 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 18.
VSPIKE(Absolute) = V(IN) + I(LOAD) x
L(IN)
C(IN)
(18)
Where:
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current,
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 32.
VIN
IN
*
CVIN
0.1µF
R1
VOUT
OUT
28mO
COUT
EN/UVLO
*
R2
dVdT
BFET
*
CdVdT
GND
*Optional components for
transient suppression
ILIM
TPS2592x
RILIM
Figure 32. Circuit Implementation with Optional Protection Components
11.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 33 for a PCB layout example.
High current carrying power path connections should be as short as possible and should be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be
a copper plane or island on the board.
Locate all support components: RILIM, CdVdT and resistors for EN/UVLO, close to their connection pin. Connect
the other end of the component to the GND pin of the device with shortest trace length. The trace routing for
the RILIM and CdVdT components to the device should be as short as possible to reduce parasitic effects on
the current limit and soft start timing. These traces should not have any coupling to switching signals on the
board.
Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it should be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
12.2 Layout Example
Top layer
Bottom layer signal ground plane
Via to signal ground plane
dV/dT
1
10 ILIM
EN/UVLO
2
9
BFET
VIN
3
8
OUT
VIN
4
7
OUT
5
6
VIN
OUT
Ground Bottom
layer
VIN
VOUT
*
VIN
High Frequency
Bypass Capacitor
*
* Optional: Needed only to suppress the transients caused by inductive load switching
Figure 33. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS2592ZA
Click here
Click here
Click here
Click here
Click here
TPS2592ZL
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
PowerPAD is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS2592ZADRCR
NRND
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2592ZA
TPS2592ZADRCT
NRND
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2592ZA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS2592ZADRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS2592ZADRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2592ZADRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS2592ZADRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
www.ti.com
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