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TPS25940A, TPS25940L
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
TPS25940x 2.7 – 18V eFuse with True Reverse Blocking and DevSleep Support for SSDs
1 Features
3 Description
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The TPS25940 eFuse Power Switch is a compact,
feature rich power management device with a full
suite of protection functions, including a low power
DevSleep™ mode that supports compliance with the
SATA™ Device Sleep standard. The wide operating
range allows control of many popular DC bus
voltages. Integrated back to back FETs provide
bidirectional current control making the device well
suited for systems with load side holdup energy that
must not drain back to a failed supply bus.
1
•
2.7 V – 18 V Operating Voltage, 20 V (Max)
42 mΩ RON (Typical)
0.6 A to 5.3 A Adjustable Current Limit (±8%)
IMON Current Indicator Output (±8%)
200 μA Operating IQ (Typical)
95 μA DevSleep Mode IQ (Typical)
15 μA Disabled IQ (Typical)
±2% Overvoltage, Undervoltage Threshold
Reverse Current Blocking
1 μs Reverse Voltage Shutoff
Programmable dVo/dt Control
Power Good and Fault Outputs
-40°C to 125°C Junction Temperature Range
UL 2367 Recognized
– File No. 169910
– RILIM ≥ 20 kΩ (4.81 A max)
UL60950 - Safe during Single Point Failure Test
– Open/Short ILIM detection
2 Applications
•
•
•
•
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PCIe/SATA/SAS HDD and SSD Drives
Enterprise and Micro Servers
Smart Load Switch
Set-Top-Box (STB), DTVs and Game Consoles
RAID Cards - Holdup Power Management
Telecom Switches and Routers
Adapter Powered Devices
Load, source and device protection are provided with
many programmable features including overcurrent,
dVo/dt
ramp
and
overvoltage,
undervoltage
thresholds. For system status monitoring and
downstream load control, the device provides
PGOOD, FLT and precise current monitor output.
Precise programmable undervoltage, overvoltage
thresholds and the low IQ DevSleep mode simplify
SSD power management design.
The TPS25940 monitors V(IN) and V(OUT) to provide
true reverse current blocking when V(IN) < (V(OUT) - 10
mV). This function supports swift changeover to a
boosted voltage energy storage element in systems
where backup voltage is greater than bus voltage.
Device Information(1)
(2)
PART NUMBER
TPS25940A
TPS25940L
PACKAGE
BODY SIZE (NOM)
WQFN (20)
3.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) TPS25940L = Latched, TPS25940A = Auto Retry
4 Simplified Schematic
2.7 to 18 V
V(IN)
Power Fail Detection and Blocking
IN
OUT
EN/UVLO
RTOTAL =
42 m:
To Load
FLT
PGOOD
OVP
DEVSLP
PGTH
dVdT
IMON
ILIM
GND
TPS25940x
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25940A, TPS25940L
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Characteristics ............................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parametric Measurement Information ............... 15
Detailed Description ............................................ 16
9.1 Overview ................................................................. 16
9.2 Functional Block Diagram ....................................... 17
9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 22
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
10.3 System Examples ................................................. 32
11 Power Supply Recommendations ..................... 35
11.1 Transient Protection .............................................. 35
11.2 Output Short-Circuit Measurements ..................... 36
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Example .................................................... 38
13 Device and Documentation Support ................. 39
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
5 Revision History
Changes from Original (June 2014) to Revision A
Page
•
Changed Features From: UL2367 Recognition Pending To: UL 2367 Recognized, RILIM ≥ 20 kΩ (4.81 A max), File
No. 169910 ............................................................................................................................................................................. 1
•
Moved the Storage Temperature From the Handling Ratings table To Absolute Maximum Ratings table .......................... 4
•
Changed the Handling Ratings table To: ESD Ratings table ................................................................................................ 4
•
Added Test Condition to I(LIM): "R(ILIM) = 20 kΩ" in the Electrical Characteristics .................................................................. 5
•
Changed Figure 24............................................................................................................................................................... 10
•
Added condition R(ILIM) = 17.8 kΩ to Figure 40 and Figure 41 ............................................................................................ 13
•
Changed Figure 43 .............................................................................................................................................................. 17
•
Changed Equation 6 to include I(IMON_OS).............................................................................................................................. 21
•
Added the NOTE to Application and Implementation .......................................................................................................... 24
•
Added Note to Figure 57 ..................................................................................................................................................... 28
•
Changed Equation 35 From: V(IN) x I(LOAD) To: V(IN) + I(LOAD) ................................................................................................. 35
2
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Product Folder Links: TPS25940A TPS25940L
TPS25940A, TPS25940L
www.ti.com
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
6 Pin Configuration and Functions
TPS25940
RVC PACKAGE
(TOP VIEW)
FLT
IMON
dVdT
ILIM
20
19
18
17
DEVSLP
1
16
GND
PGOOD
2
15
OVP
PGTH
3
14
EN
OUT
4
13
IN
12
IN
11
IN
OUT
5
OUT
6
Thermal
Pad
8
9
OUT
OUT
IN
10 IN
7
Pin Functions
NAME
NO.
I/O
DEVSLP
1
I
Active High. DevSleep Mode control. A high at this pin will activate the DevSleep mode(Low Power Mode).
PGOOD
2
O
Active High. A high indicates PGTH has crossed the threshold value. It is an open drain output.
PGTH
3
I
Positive input of PGOOD comparator.
OUT
4-8
O
Power Output of the device.
IN
9 - 13
I
Power Input and supply voltage of the device.
EN/UVLO
14
I
Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and assert
FLT to indicate power-failure. When pulled to GND, resets the fault latch in TPS25940L.
OVP
15
I
Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and
assert FLT to indicate overvoltage.
GND
16
—
Ground.
ILIM
17
I/O
A resistor from this pin to GND sets the overload and short-circuit current limit.
dVdT
18
I/O
A capacitor from this pin to GND sets the ramp rate of output voltage.
IMON
19
O
This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current
to proportional voltage, used as analog current monitor.
FLT
20
O
Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, Reverse voltage and Thermal
shutdown event. It is an open drain output.
PowerPADTM
DESCRIPTION
The GND terminal must be connected to the exposed PowerPAD. This PowerPAD must be connected to a PCB ground
plane using multiple vias for good thermal performance.
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25940A TPS25940L
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TPS25940A, TPS25940L
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
(1)
VALUE
MIN
MAX
–0.3
20
dVdT, ILIM
–0.3
3.6
IMON
–0.3
IN, OUT, PGTH, PGOOD, EN/UVLO, OVP, DEVSLP, FLT
IN (10 ms Transient)
Input voltage range
Sink current
PGOOD, FLT, dVdT
Source current
dVdT, ILIM, IMON
UNIT
22
V
7
10
mA
Internally Limited
Maximum junction, TJ
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
See the Thermal Characteristics (2)
Continuous power dissipation
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.2 ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
IN
Input voltage range
EN/UVLO, OVP, DEVSLP, OUT, PGTH, PGOOD, FLT
0
18
dVdT, ILIM
0
3
IMON
0
6
16.9
150
IMON
External capacitance
MAX
18
ILIM
Resistance
NOM
2.7
1
OUT
0.1
V
kΩ
µF
dVdT
Operating junction temperature range, TJ
UNIT
–40
25
470
nF
125
°C
7.4 Thermal Characteristics (1)
TPS25940
THERMAL METRIC
RVC (20) PINS
RθJA
Junction-to-ambient thermal resistance
38.1
RθJCtop
Junction-to-case (top) thermal resistance
40.5
RθJB
Junction-to-board thermal resistance
13.6
ψJT
Junction-to-top characterization parameter
0.6
ψJB
Junction-to-board characterization parameter
13.7
RθJCbot
Junction-to-case (bottom) thermal resistance
3.4
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: TPS25940A TPS25940L
TPS25940A, TPS25940L
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SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
7.5 Electrical Characteristics
Conditions are –40°C ≤ TJ=TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150
kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN)
Operating Input Voltage
2.7
V(UVR)
Internal UVLO threshold, rising
2.2
2.3
2.4
V
V(UVRhys)
Internal UVLO hysteresis
105
116
125
mV
V(EN/UVLO) = 2 V, V(IN) = 3 V
140
210
300
IQ(ON)
Supply current, Enabled
V(EN/UVLO) = 2 V, V(IN) = 12 V
140
199
260
V(EN/UVLO) = 2 V, V(IN) = 18 V
140
202
270
V(EN/UVLO) = 0 V, V(IN) = 3 V
4
8.6
15
V(EN/UVLO) = 0 V, V(IN) = 12 V
6
15
20
V(EN/UVLO) = 0 V, V(IN) = 18 V
8
18.5
25
70
95
130
µA
IQ(OFF)
IQ(DEVSLP)
Supply current, Disabled
Supply current, DevSleep Mode
V(DEVSLP) = 0 V, V(IN) = 2.7V to 18V
18
V
µA
µA
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(ENR)
EN/UVLO threshold voltage, rising
0.97
0.99
1.01
V
V(ENF)
EN/UVLO threshold voltage, falling
0.9
0.92
0.94
V
V(SHUTF)
EN threshold voltage for Low IQ
shutdown, falling
0.3
0.47
0.63
V
V(SHUTFhys)
EN hysteresis for low IQ shutdown,
hysteresis (1)
IEN
EN Input leakage current
66
0 V ≤ V(EN/UVLO) ≤ 18 V
mV
–100
0
100
nA
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR)
Overvoltage Threshold Voltage,
Rising,
0.97
0.99
1.01
V
V(OVPF)
Overvoltage Threshold Voltage,
Falling
0.9
0.92
0.94
V
I(OVP)
OVP Input Leakage Current
-100
0
100
nA
V
0 V ≤ V(OVP) ≤ 5 V
DEVSLP MODE INPUT (DEVSLP): ACTIVE HIGH
V(DEVSLPR)
DEVSLP threshold voltage, rising
1.6
1.85
2
V(DEVSLPF)
DEVSLP threshold voltage, falling
0.8
0.96
1.1
V
I(DEVSLP)
DEVSLP input leakage current
0.6
1
1.25
µA
0.2 V ≤ V(DEVSLP) ≤ 18 V
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
V(dVdT) = 0 V
R(dVdT)
dVdT discharging resistance
EN/UVLO = 0 V, I(dVdT) = 10 mA sinking
V(dVdTmax)
dVdT maximum capacitor voltage
GAIN(dVdT)
dVdT to OUT gain
ΔV(OUT)/ΔV(dVdT)
0.85
1
1.15
µA
16
24
Ω
2.6
2.88
3.1
11.65
11.9
12.05
V
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
ILIM bias voltage
0.87
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 1 V
I(LIM)
Current limit
I(DEVSLP(LIM))
(1)
(2)
(2)
V
0.53
0.58
0.63
R(ILIM) = 88.7 kΩ, (V(IN) - V(OUT)) = 1 V
0.9
0.99
1.07
R(ILIM) = 42.2 kΩ, (V(IN) - V(OUT)) = 1 V
1.92
2.08
2.25
R(ILIM) = 24.9 kΩ, (V(IN) - V(OUT)) = 1 V
3.25
3.53
3.81
R(ILIM) = 20 kΩ, (V(IN) - V(OUT)) = 1 V
4.09
4.45
4.81
R(ILIM) = 16.9 kΩ, (V(IN) - V(OUT)) = 1 V
4.78
5.2
5.62
R(ILIM) = OPEN, Open resistor current limit (Single Point
Failure Test: UL60950)
0.35
0.45
0.55
R(ILIM) = SHORT, Shorted resistor current limit (Single
Point Failure Test: UL60950)
0.55
0.67
0.8
0.55
0.67
0.8
DevSleep Mode Current Limit
A
A
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25940A TPS25940L
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Electrical Characteristics (continued)
Conditions are –40°C ≤ TJ=TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150
kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to
GND (unless otherwise noted)
PARAMETER
IOS
Short-circuit current limit
TEST CONDITIONS
(2)
MIN
TYP
MAX
R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V
1.91
2.07
2.24
R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V
3.21
3.49
3.77
4.7
5.11
5.52
R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT))= 5 V, -40°C ≤
TJ ≤ 85°C
1.5 x I(LIM) +
0.375
Fast-Trip comparator threshold (1) (2)
I(FASTRIP)
UNIT
A
A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON)
Gain Factor I(IMON):I(OUT)
1 A ≤ I(OUT) ≤ 5 A
47.78
52.3
57.23
1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C
34
42
49
1 A ≤ I(OUT) ≤ 5 A, -40°C ≤ TJ ≤ 85°C
26
42
58
1 A ≤ I(OUT) ≤ 5 A, -40°C ≤ TJ ≤ 125°C
26
42
64
V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (Sourcing)
–2
0
2
V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (Sinking)
6
13
20
µA/A
MOSFET – POWER SWITCH
RON
IN to OUT - ON Resistance
mΩ
PASS FET OUTPUT (OUT)
Ilkg(OUT)
OUT leakage current in off state
µA
V(REVTH)
V(IN) -V(OUT) threshold for reverse
protection comparator, falling
–15
-9.3
–3
mV
V(FWDTH)
V(IN) -V(OUT) threshold for reverse
protection comparator, rising
86
100
114
mV
FAULT FLAG (FLT): ACTIVE LOW
R(FLT)
FLT internal pull-down resistance
V(OVP) = 2 V, I(FLT) = 5 mA sinking
10
18
30
Ω
I(FLT)
FLT input leakage current
0 V ≤ V(FLT) ≤ 18 V
–1
0
1
µA
V
POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH)
V(PGTHR)
PGTH threshold voltage, rising
0.97
0.99
1.01
V(PGTHF)
PGTH threshold voltage, falling
0.9
0.92
0.94
V
I(PGTH)
PGTH input leakage current
–100
0
100
nA
0 V ≤ V(PGTH) ≤ 18 V
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
R(PGOOD)
PGOOD internal pull-down
resistance
V(PGTH) = 0V, I(PGOOD) = 5 mA sinking
10
20
35
Ω
I(PGOOD)
PGOOD input leakage current
0 V ≤ V(PGOOD) ≤ 18 V
–1
0
1
µA
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD Threshold (1)
160
°C
T(TSDhys)
TSD Hysteresis (1)
12
°C
Thermal Fault: (Latched or AutoRetry)
6
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TPS25940L
LATCHED
TPS25940A
AUTORETRY
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SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
7.6 Timing Requirements
Conditions are –40°C ≤ TJ=TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150
kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to
GND (unless otherwise noted). Refer to Figure 42 for the timing diagrams.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE and UVLO INPUT
tON(dly)
tOFF(dly)
EN turn on delay
EN turn off delay
EN/UVLO ↑ (100mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) < 0.8 nF
220
µs
EN/UVLO ↑ (100mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) ≥ 0.8 nF, [C(dVdT) in nF]
100 + 150 x
C(dVdT)
µs
EN/UVLO ↓ (100mV below V(ENF)) to FLT↓
2
µs
OVP↑ (100mV above V(OVPR)) to FLT↓
2
µs
OVERVOLTAGE PROTECTION INPUT (OVP)
tOVP(dly)
OVP disable delay
OUTPUT RAMP CONTROL (dV/dT )
EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open
tdVdT
0.12
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open
Output ramp time
0.25
0.37
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF
0.97
I(OUT) > I(FASTRIP)
200
0.5
ms
CURRENT LIMIT
tFASTRIP(dly)
Fast-Trip comparator delay
ns
REVERSE PROTECTION COMPARATOR
tREV(dly)
(V(IN) - V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓
Reverse protection comparator
delay
tFWD(dly)
10
(V(IN) - V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓
1
(V(IN) - V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑
3.1
µs
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
tPGOODR
tPGOODF
PGOOD delay (de-glitch) time
Rising edge
0.42
0.54
0.66
ms
Falling edge
0.42
0.54
0.66
ms
THERMAL SHUT DOWN (TSD)
Retry delay in TSD
TPS25940A Only
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7.7 Typical Characteristics
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
300
Supply Current, IQ(ON) (µA)
Internal UVLO Threshold Voltage (V)
2.35
2.30
2.25
R
VUVLO
(UVR)
VUVLO
(UVF) F
2.20
2.15
±50
10
±20
40
70
100
100
TA
TA = -40 o0C
C
TA
TA = 25 o0C
C
50
TA = 85 o0C
C
TA
TA = 125 o0C
C
TA
0
5
10
15
20
Input Voltage (V)
C014
Figure 1. UVLO Threshold Voltage vs Temperature
C014
Figure 2. Input Supply Current vs Supply Voltage During
Normal Operation
150
Supply Current, IQ(DEVSLP) (µA)
25
Supply Current, IQ(OFF) (µA)
150
130
Temperature (oC)
20
15
10
TA
TA = -40 o0C
C
TA
TA = 25 o0C
C
5
TA = 85 o0C
C
TA
TA = 125 o0C
C
TA
0
0
5
10
15
125
100
75
50
TA
TA = -40 o0C
C
TA
TA = 25 o0C
C
25
TA = 85 o0C
C
TA
TA = 125 o0C
C
TA
0
20
Input Voltage (V)
0
5
10
15
20
Input Voltage (V)
C014
Figure 3. Input Supply Current vs Supply Voltage at
Shutdown
C014
Figure 4. Input Supply Current vs Supply Voltage in
DevSleep Mode
1.00
OVP Threshold Voltage (V)
1.00
EN/UVLO Threshold Voltage (V)
200
0
2.10
0.98
0.96
EN Ris
V(ENR)
V(ENF)
EN Fall
0.94
0.92
0.90
0.98
0.96
OVP
Rising
V(OVPR)
V(OVPF)
OVP
Falling
0.94
0.92
0.90
±50
±20
10
40
70
100
Temperature (oC)
Figure 5. EN Threshold Voltage vs Temperature
8
250
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130
±50
±20
10
40
Temperature (oC)
C014
70
100
130
C014
Figure 6. OVP Threshold Voltage vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
0.98
0.96
PGTH
Rising
V
(PGTHR)
V
PGTH
(PGHTF)Falling
0.94
0.92
0.90
±50
±20
10
40
70
100
130
Temperature (oC)
EN Threshold Voltage for Low IQ Mode (V)
PGTH Threshold Voltage (V)
1.00
0.60
EN
Rising
V(SHUTR)
V(SHUTF)
EN
Falling
0.55
0.50
0.45
0.40
10
40
70
100
130
C014
Figure 8. EN Threshold Voltage for Low IQ mode vs
Temperature
3.0
Enalbe Turn OFF Delay tOFF(dly) (µs)
300
Enalbe Turn ON delay tON(dly) (µs)
±20
Temperature (oC)
Figure 7. PGTH Threshold Voltage vs Temperature
250
200
150
100
2.6
2.2
1.8
1.4
1.0
50
±50
±20
10
40
70
100
130
Temperature (oC)
±50
±20
10
40
70
100
Temperature (oC)
C014
Figure 9. Enable Turn ON Delay vs Temperature
130
C014
Figure 10. Enable Turn OFF Delay vs Temperature
3.0
2.1
DEVSLP Threshold Voltage (V)
OVP Disable Delay, tOVP(dly) (Ps)
±50
C014
2.6
2.2
1.8
1.4
1.0
1.9
1.7
1.5
R
VDEVSLP
(DEVSLPR)
VDEVLSLP
F
(DEVSLPF)
1.3
1.1
0.9
±50
±20
10
40
70
100
Temperature (oC)
Figure 11. OVP Disable Delay vs Temperature
130
±50
±20
10
40
70
100
Temperature (oC)
C014
130
C014
Figure 12. DEVSLP Threshold Voltage vs Temperature
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Typical Characteristics (continued)
11.90
1.2
11.89
11.88
1.1
Gain(dVdT)
DEVSLP Pull down Current, I(DEVSLP) (µA)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
1.0
11.87
11.86
11.85
11.84
11.83
11.82
0.9
±50
±20
10
40
70
100
Temperature (oC)
130
±50
Figure 13. DEVSLP Pull Down Current vs Temperature
Output Ramp Time, t(dVdT) (ms)
70
100
130
C014
Figure 14. GAIN(dVdT) vs Temperature
10
Current Limit, I(LIM) (A)
100
10
1
1
0
0
1
10
100
10
1000
C(dVdT) (nF)
100
R(ILIM) Resistor (k:)
C014
Figure 15. Output Ramp Time vs C(dVdT)
C014
Figure 16. Current Limit vs Current Limit Resistor
6
9.5
16.9 k:
5
9.0
Current Limit, I(LIM) (A)
Accuracy (%)
(Process, Voltage, Temperature)
40
Temperature (oC)
1000
8.5
8.0
4
24.9 k:
3
42.4 k:
2
88.6 k:
1
150 k:
0
7.5
0
1
2
3
Current Limit(A)
4
5
6
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0
±50
50
Temperature (oC)
C014
Figure 17. Current Limit Accuracy vs Current Limit
10
10
±20
C014
100
150
C014
Figure 18. Current Limit vs Temperature Across R(ILIM)
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
2.0%
1.0%
0.5%
II(OV)
1.0
1.0A
A
(LIM) = =
2.1A
II(OV)
2.1
A
(LIM) = =
=
3.6A
II(OV)
=
3.6
A
(LIM)
5.3A
II(OV)
5.3
A
(LIM) = =
0.0%
I(LIM) Normalized (%)
1.5%
I(LIM) (% Normalized)
0.5%
150 k
88.6 k
42.4 k
24.9 k
16.9 k
0.0%
-0.5%
-1.0%
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-1.5%
-3.0%
-2.0%
-50
0
50
100
0
150
Temperature (oC)
2
4
6
8
10
V(IN) - V(OUT) (V)
C014
12
C014
Thermal shutdown occurs when I(LIM) = 5.3 A
and [V(IN) - V(OUT)] > 8 V
0.70
Current Limit, I(LIM) (A)
0.65
0.60
R(ILIM)
Short
R(ILIM) ==Short
R(ILIM) ==Open
R(ILIM)
Open
0.55
0.50
0.45
0.40
0
±50
50
100
150
Temperature (oC)
Figure 20. Current Limit Normalized (%) vs V(IN) - V(OUT)
Current Limit in DevSleep Mode, I(DEVSLP(LIM)) (A)
Figure 19. Current Limit (% Normalized) vs R(LIMIT) Resistor
0.69
0.68
0.67
0.66
0.65
±50
±20
10
40
70
100
Temperature (oC)
C014
Figure 21. Current Limit for R(ILIM) = Open and Short vs
Temperature
130
C014
Figure 22. Current Limit in DevSleep Mode vs Temperature
1.2
9
8
1.1
7
IMON Offset (PA)
Fast Trip Current, I(FASTTRIP) (A)
0.70
6
5
4
3
1.0
0.9
0.8
2
0.7
1
0
0
1
2
3
4
5
Current Limit I(LIM) (A)
Figure 23. Fast Trip Threshold vs Current Limit
6
0.6
-50
-20
C014
10
40
70
Temperature (qC)
100
130
Figure 24. IMON Offset vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
500
Current Monitor Output I(MON) (µA)
54.0
GAIN, I(MON) (µA/A)
53.5
53.0
52.5
52.0
51.5
±50
10
±20
40
70
100
o
TATA
= 85
= 85C 0C
o
TATA
= 125
= 125C 0C
0.1
130
Temperature (oC)
1.0
10.0
Output Current , IOUT (A)
C014
C014
Figure 26. Current Monitor Output vs Output Current
Figure 25. GAIN(IMON) vs Temperature
60
OUT Pin Leakage Current, Ilkg(out) (µA)
16
55
50
RON (m:
o 0C
= -40
TATA
= -40
C
o
TATA
= 25
= 25C 0C
5
51.0
45
40
35
1A
2A
3A
4A
5A
30
25
±50
0
50
100
Temperature (oC)
14
12
10
vout==00V
V(OUT)
V
8
V(OUT)
18V= 18 V
6
4
2
0
±2
150
0
±50
50
100
Temperature (oC)
C014
Figure 27. RON vs Temperature Across Load Current
150
C014
Figure 28. OUT Leakage Current in Off State vs Temperature
±9.0
102.0
±9.1
101.5
±9.2
101.0
±9.3
V(FWDTH) (mV)
V(REVTH) (mV)
50
±9.4
±9.5
±9.6
±9.7
100.5
100.0
99.5
99.0
±9.8
98.5
±9.9
98.0
±10.0
±50
0
50
100
Temperature (oC)
Figure 29. V(REVTH) vs Temperature
12
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150
0
±50
50
100
Temperature (oC)
C014
150
C014
Figure 30. V(FWDTH) vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
Thermal Shutdown Time (ms)
100000
TA -40C
= -40oC
TA 25C
= 25oC
10000
TA 85C
= 85oC
TA 125C
= 125oC
1000
100
10
1
0.1
1
10
100
Power Dissipation (W)
C014
Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane
area: 14 cm2 (Top) and 20 cm2 (bottom)
V(IN) = 4.5 V
Figure 31. Thermal Shutdown Time vs Power Dissipation
Figure 32. Turn ON with Enable
V(IN) = 11 V
R(FLT)=100 kΩ
Figure 33. Turn ON and OFF with Enable
R(FLT)=100 kΩ
Figure 35. EN Turn OFF Delay : EN ↓ to Fault ↓
Figure 34. EN Turn ON Delay : EN ↑ to Output Ramp ↑
V(IN) = 12 V
RL = 12 Ω
R(FLT)=100 kΩ
Figure 36. OVP Turn OFF delay: OVP ↑ to Fault ↓
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
V(IN) = 12 V
RL = 12 Ω
R(FLT)=100 kΩ
Figure 37. OVP Turn ON delay: OVP ↓ to Output Ramp ↑
V(IN) = 12 V
RL = 12 Ω
R(FLT)= 100 kΩ
R(PGOOD)= 100 kΩ
Figure 39. Power Good Delay (Falling)
R(FLT)= 100 kΩ
RL = 12 Ω
V(IN) = 12 V
R(FLT)= 100 kΩ
R(PGOOD)= 100 kΩ
Figure 38. Power Good Delay (Rising)
R(FLT) = 100 kΩ
R(IMON) = 16.9 kΩ
R(ILIM) = 17.8 kΩ
Figure 40. Hot-Short: Fast Trip Response and Current
Regulation
R(IMON) = 16.9 kΩ
R(ILIM) = 17.8 kΩ
Figure 41. Hot-Short: Fast Trip Response (Zoomed)
14
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8 Parametric Measurement Information
V(OUT)
VEN
V(ENF)-0.1V
0.1V
VEN
FLT
V(ENR)+0.1V
0
10%
time
tON(dly)
time
0
tOFF(dly)
-20mV
V(IN)-V(OUT)
110mV
V(IN)-V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
I(FASTRIP)
0
tFWD(dly)
time
V(OVPR) + 0.1V
V(OVP)
I(LIM)
I(OUT)
FLT
10%
0
time
tFASTRIP(dly)
0
tOVP(dly)
time
Figure 42. Timing Diagrams
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9 Detailed Description
9.1 Overview
TPS25940 is a smart eFuse with integrated back-to-back FETs and enhanced built-in protection circuitry. It
provides robust protection for all systems and applications powered from 2.7 V to 18 V.
For hot-plug-in boards, the device provides hot-swap power management with in-rush current control and
programmable output ramp-rate. The device integrates overcurrent and short circuit protection. The precision
overcurrent limit helps to minimize over design of the input power supply, while the fast response short circuit
protection immediately isolates the load from input when a short circuit is detected. The device allows the user to
program the overcurrent limit threshold between 0.6 A and 5.3 A via an external resistor.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
for downstream system. Its overall threshold accuracy of 2% ensures tight supervision of bus, eliminating the
need for a separate supply voltage supervisor chip.
The device is designed to protect systems such as enterprise SSD drives against sudden power loss events. The
device monitors V(IN) and V(OUT) to provide true reverse blocking from output when reverse condition or input
power fail condition is detected. Also, the device signals the downstream controller to initiate transfer of power to
the hold-up capacitor for data hardening.
The additional features include:
•
•
•
•
•
16
Precise current monitor output for health monitoring of the system
Additional power good comparator with precision internal reference for output or any other rail voltage
monitoring
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for brown-out and overvoltage faults
A choice of latched or automatic restart mode
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9.2 Functional Block Diagram
IN
OUT
9-13
4-8
42m:
+
-10mV
+100mV
UVLOb
2.30V
2.18V
EN/UVLO
+
+
14
+
SWEN
OVP
0.99V
Thermal
Shutdown
0.92V
DEVSLP
IMON
Gate Control Logic
19
TSD
Current Limit Amp
+
1
x52P
REVERSE
0.92V
15
Current
Sense
CP
EN
0.99V
OVP
Charge
Pump
Fast-Trip Comp
Low current
Mode
1.85V
(Threshold=1.5xIOL)
0.96V
0.87V
Shutdown
1PA
ILIM
EN/UVLO
17
Short Detect
FLT
Ramp Control
12x
20
1µA
S
dVdT
18
SET
Q
UVLOb
16:
UVLO
EN
TSD
GND
16
16:
SWEN
R
CLR
Q
PGOOD
Fault Latch
2
+
Hatched Blocks will
be Turned-Off
during DEVSLP
dVdT
over
0.99V
0.5ms
0.5ms
16:
0.92V
TPS25940A/L
3
PGTH
Figure 43. TPS25940A/L Block Diagram
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9.3 Feature Description
9.3.1 Enable and Adjusting Undervoltage Lockout
The EN/UVLO pin controls the ON/OFF state of the internal FET. A voltage V(EN/UVLO) < V(ENF) on this pin will turn
off the internal FET, thus disconnecting IN from OUT, while voltage below V(SHUTF) will take the device into
shutdown mode, with IQ less than 15 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high
resets the TPS25940L that has latched off due to a fault condition.
The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For
applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO terminal to GND.
The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to
EN/UVLO terminal to GND as shown in Figure 44. When an undervoltage or input power fail event is detected,
the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed,
the EN/UVLO terminal should be connected to the IN terminal. EN/UVLO terminal should not be left floating.
The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device
disables when the IN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO threshold
has a hysteresis of 115mV.
V(IN)
IN
TPS25940x
R1
EN/UVLO
+
0.99V
EN
R2
0.92V
OVP
+
OVP
0.99V
R3
GND
0.92V
Figure 44. UVLO and OVP Thresholds Set By R1, R2 and R3
9.3.2 Overvoltage Protection (OVP)
The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from
the supply to OVP terminal to GND (as shown in Figure 44) programs the overvoltage threshold. A voltage more
than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin should be tied to
GND when not used.
9.3.3 Hot Plug-in and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of
the system power. A slew rate controlled startup (dVdT) also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output
voltage at power-on (as shown in Figure 45). Equation governing slew rate at start-up is shown in Equation 1 :
18
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Feature Description (continued)
TPS25940x
1uA
dVdT
16:
C(dVdT)
SWEN
GND
Figure 45. Output Ramp Up Time tdVdT is Set by C(dVdT)
æ
C(dVdT) ö æ dV(OUT) ö
÷ x ç
÷÷
ç GAIN(dVdT) ÷ ç
dt
ø
è
ø è
I(dVdT) = ç
(1)
Where:
• I(dVdT) = 1 µA (typical)
space
dV(OUT)
•
•
= Desired output slew rate
GAIN(dVdT) = dVdT to OUT gain = 12
dt
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2:
tdVdT = 8.3 x 104 x V(IN) x C(dVdT)
(2)
The inrush current, I(INRUSH) can be calculated as
I(INRUSH) = C(OUT) x V(IN) / tdVdT.
(3)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When terminal is left
floating, the device sets an internal ramp rate of 12V/ms for output (V(OUT)) ramp.
Figure 58 and Figure 59 illustrate the inrush current control behavior of the device. For systems where load is
present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the application.
For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage
Ramp time (tdVdT) section.
9.3.4 Overload and Short Circuit Protection :
At all times load current is monitored by sensing voltage across an internal sense resistor. During overload
events, current is limited to the current limit (I(LIM)) programmed by R(ILIM) resistor
I(LIM) =
•
•
89
R(ILIM)
(4)
I(LIM) is overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
The device incorporates two distinct levels: a current limit (I(LIM)) and a fast-trip threshold (I(FASTRIP)). Fast trip and
current limit operation are shown in Figure 46.
Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node
must be kept away from any noisy (switching) signals.
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Feature Description (continued)
9.3.4.1 Overload Protection
For overload conditions, the internal current-limit amplifier regulates the output current to I(LIM). The output
voltage droops during the current regulation, resulting in increased power dissipation in the device. If the device
junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. Once in
thermal shutdown, The TPS25940L version stays latched off, whereas TPS25940A commences an auto-retry
cycle 128 ms after TJ < [T(TSD) - 12°C]. During thermal shutdown, the fault pin FLT pulls low to signal a fault
condition. Figure 62 and Figure 63 illustrate overload behavior.
9.3.4.2 Short Circuit Protection
During a transient short circuit event, the current through the device increases very rapidly. As current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). This comparator shuts down the pass device within 1µs, when the current
through internal FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-circuit peak current. The
trip threshold is set to more than 50% of the programmed overload current limit ( I(FASTRIP) = 1.5 x I(LIM)+ 0.375 ).
The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on
slowly, allowing the current-limit loop to regulate the output current to I(LIM). Then, device behaves similar to
overload condition. Figure 64 through Figure 66 illustrate the behavior of the system when the current exceeds
the fast-trip threshold.
9.3.4.3 Start-Up with Short on Output
During start-up into a short circuit current is limited to I(LIM). Figure 67 and Figure 68 illustrate start-up with a short
on the output. This feature helps in quick fault isolation and hence ensures stability of the DC bus.
9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
When power dissipation in the internal FET [PD = (V(IN) - V(OUT)) × I(OUT)] > 10 W, there is a ~0 to 5 % thermal fold
back in the current limit value so that I(LIM) drops to IOS. Eventually, the device shuts down due to over
temperature.
Current Limit
I(FASTRIP)
I(FASTRIP) = 1.5 x I(LIM) + 0.375
Thermal Foldback
0-5%
I(LIM)
IOS
Figure 46. Fast-Trip Current
9.3.5 FAULT Response
The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage/current and
thermal shutdown conditions. The FLT signal remains asserted until the fault condition is removed and the device
resumes normal operation. The device is designed to eliminate false fault reporting by using an internal "deglitch" circuit for undervoltage and overvoltage (2.2-µs typical) conditions without the need for external circuitry.
This ensures that fault is not accidentally asserted during transients on input bus.
Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when
not used. V(IN) falling below V(UVF) = 2.1 V resets FLT.
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Feature Description (continued)
9.3.6 Current Monitoring:
The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This
current can be converted to a voltage using a resistor R(IMON) from IMON terminal to GND terminal. This voltage,
computed using Equation 6, can be used as a means of monitoring current flow through the system.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(IN)- 2.2 V], 6.0 V) to
ensure linear output. This puts limitation on maximum value of R(IMON) resistor and is determined by Equation 5.
R(IMONmax) =
minimum (V(IN) - 2.2, 6)
1.6 x I(LIM) x GAIN(IMON)
(5)
The output voltage at IMON terminal is calculated from Equation 6.
V(IMON) = éëI(OUT) x GAIN(IMON) + I(IMON_OS) ùû x R(IMON)
(6)
Where
• GAIN(IMON) = Gain factor I(IMON):I(OUT) = 52 µA/A
• I(OUT) = Load current
• I(IMON_OS) = 0.8 µA (typ)
This pin should not have a bypass capacitor to avoid delay in the current monitoring information.
The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current
monitor information over an I2C bus.
9.3.7 Power Good Comparator
The device incorporates a Power Good comparator for co-ordination of status to downstream DC-DC converters
or system monitoring circuits. The comparator has an internal reference of V(PGTHR) = 0.99 V at negative terminal
and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator
output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units.
PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal
reference V(PGTHR).
The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy
load is applied by downstream converters. Rising de-glitch delay is determined by Equation 7.
tPGOOD(degl) = Maximum{(3.5 x 106 x C(dVdT)), tPGOODR}
(7)
Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied
to ground when not used.
9.3.8 IN, OUT and GND Pins
The device has multiple pins for input (IN) and output (OUT).
All IN pins should be connected together and to the power source. A ceramic bypass capacitor close to the
device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is
2.7 V – 18 V.
Similarly all OUT pins should be connected together and to the load. V(OUT) in the ON condition, is calculated
using the Equation 8
V(OUT) = V(IN) - (RON × I(OUT) )
(8)
where, RON is the total ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference
unless otherwise specified.
9.3.9 Thermal Shutdown:
Internal over temperature shutdown disables turns off the FET when TJ > 160°C (typical). The TPS25940L
version latches off the internal FET, whereas TPS25940A commences an auto-retry cycle128 ms after TJ drops
below [T(TSD) - 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition.
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9.4 Device Functional Modes
9.4.1 DevSleep Mode for SATA® Interface Devices
DevSleep is a new state introduced in the SATA® specification, which requires SATA-based storage solutions to
reach a level of low power operation. This is appended to meet the aggressive power/battery life requirements of
SATA-based mobile devices. DevSleep enables hosts and devices to completely hibernate the SATA interface.
This saves more power versus the existing Partial and Slumber interface power states, which require that the
PHY be left powered. In this mode, power consumption is limited to 5 mW or less for SSDs.
Detailed information on DevSleep is available in document 'SATA-DevSleep' and on www.sata-io.org
TPS25940 provides a dedicated DevSleep interface terminal (DEVSLP) to drive the device in low power mode.
The DEVSLP terminal is compatible with standard hardware signals asserted from the host controller. When
pulled high, it puts the device in low power DevSleep mode. In this mode, the quiescent current consumption of
the device is limited to less than 130 µA (95 µA typical). During this mode, the output voltage remains active, the
overload current limit is set to I(DEVSLP(LIM)) and functionality of reverse comparator and current monitoring is
disabled. All other protections are kept active ensuring the safety of the system even in DevSleep mode.
User must ensure that load currents on the bus are limited to less than I(DEVSLP(LIM)), when the device is driven to
DevSleep mode. Also, while coming out of DevSleep, it is important to sequence the TPS25940 earlier than the
load. Otherwise, the load can exceed I(DEVSLP(LIM)) and cause TPS25940 to enter the overload mode.
Figure 47 through Figure 50 illustrate the behavior of the system in DevSleep mode.
V(IN) = 12 V
C(OUT) = 1 µF
l(LIM) = 5.3A
RL = 22Ω
Figure 47. IN and OUT of DevSleep Mode with 550 mA
Load
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V(IN) = 12 V
C(OUT) = 1 µF
l(LIM) = 5.3A
RL = 15Ω
Figure 48. IN and OUT of DevSleep Mode with 800 mA
Load. In DevSleep, Load Current gets Limited to
I(DEVSLP(LIM))
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Device Functional Modes (continued)
RL = 22Ω
l(LIM) = 5.3A
C(OUT) = 1 µF
l(LIM–) = 5.3A
Figure 49. IMON Disabled in DevSleep Mode
C(OUT) = 1 µF
Figure 50. Hot Short and Retry in DevSleep Mode
9.4.2 Shutdown Control
The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V
threshold with an open collector or open drain device as shown in Figure 51. The device quiescent current is
reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle.
V(IN)
IN
TPS25940x
R1
EN/UVLO
+
0.99V
from µC
EN
R2
0.92V
GND
Figure 51. Shutdown Control
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS25940 is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 2.7 V to 18 V with programmable current limit, overvoltage and undervoltage protection. The
device aids in controlling the in-rush current and provides fast turn-off during reverse voltage conditions for
systems such as Enterprise SSDs, HDDs, Servers, Power Back-up Storage units and RAID cards. The device
also provides robust protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS25940 Design Calculator is available on web folder.
This section presents a simplified discussion of the design process.
10.2 Typical Application
10.2.1 eFuse for Enterprise SSDs
IN
2.7 to 18 V
R1
475kO
R2
16.7kO
IN
CIN
0.1µF
(See Note A)
from µC
42mO
R6
EN/UVLO
OVP
DEVSLP
dVdT
R3
31.2kO
A.
CdVdT
1.5nF
OUT
OUT
GND
FLT
PGOOD
PGTH
IMON
R4
R7
475kO
COUT
100µF
Health
Monitor
Load Monitor
ILIM
RILIM
TPS25940x 17.8kO
R5
47kO
RIMON
19.1kO
CIN: Optional and only for noise suppression.
Figure 52. Typical Application Schematics: eFuse for Enterprise SSDs
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Typical Application (continued)
10.2.1.1 Design Requirements
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range, V(IN)
12 V
Undervoltage lockout set point, V(UV)
10.8 V
Overvoltage protection set point , V(LIM)
16.5 V
Load at Start-Up , RL(SU)
4.8 Ω
Current limit, I(LIM)
5A
Load capacitance , C(OUT)
100 µF
Maximum ambient temperatures , TA
85°C
10.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25940A and TPS25940L.
10.2.1.2.1 Step by Step Design Procedure
To
•
•
•
•
•
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Normal input operation voltage
Maximum output capacitance
Maximum current Limit
Load during start-up
Maximum ambient temperature of operation
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
10.2.1.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
R(ILIM) =
89
= 17.8kW
5
(9)
Choose closest standard value: 17.8k, 1% standard value resistor.
10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider
network of R1, R2 and R3 as connected between IN, EN, OVP and GND pins of the device. The values required
for setting the undervoltage and overvoltage are calculated solving Equation 10 and Equation 11.
V(OVPR) =
R3
x V(OV)
R1 + R2 + R3
(10)
R 2 + R3
V(ENR) =
x V(UV)
R1 + R2 + R3
(11)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1 + R2 + R3)}, it is recommended to
use higher values of resistance for R1, R2 and R3.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current expected.
From the device electrical specifications, V(OVPR) = 0.99 V and V(ENR) = 0.99 V. For design requirements, V(OV) is
16.5 V and V(UV) is 10.8 V. To solve the equation, first choose the value of R3 = 31.2 kΩ and use Equation 10 to
solve for (R1 + R2) = 488.8 kΩ. Use Equation 11 and value of (R1 + R2) to solve for R2 = 16.47 kΩ and finally R1=
472.33 kΩ.
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Using the closest standard 1% resistor values gives R1 = 475 kΩ, R2 = 16.7 kΩ, and R3 = 31.2 kΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 7% lower than the
rising threshold, V(UV). This is calculated using Equation 12.
V(PFAIL) = 0.93 x V(UV)
(12)
10.2.1.2.4 Programming Current Monitoring Resistor - RIMON
Voltage at IMON pin V(IMON) represents the voltage proportional to load current. This can be connected to an
ADC of the downstream system for health monitoring of the system. The R(IMON) need to be configured based on
the maximum input voltage range of the ADC used. R(IMON) is set using Equation 13.
R(IMON) =
V(IMONmax)
I(LIM) x 52 x 10-6
kW
(13)
For I(LIM) = 5 A, and considering the operating range of ADC from 0 V to 5 V, V(IMONmax) is 5 V and R(IMON) is
determined by:
R(IMON) =
5
5 x 52 x 10-6
= 19.23 kW
(14)
Selecting R(IMON) value less than determined by Equation 14 ensures that ADC limits are not exceeded for
maximum value of load current.
If the IMON pin voltage is not being digitized with an ADC, R(IMON) can be selected to produce a 1V/1A voltage at
the IMON pin, using Equation 13.
Choose closest 1 % standard value: 19.1 kΩ.
If current monitoring up to I(FASTRIP) is desired, R(IMON) can be reduced by a factor of 1.6, as in Equation 5.
10.2.1.2.5 Setting Output Voltage Ramp time (tdVdT)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(dVdT) needed is calculated considering the two possible cases:
10.2.1.2.5.1 Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up
16
Input Current (A)
Power Dissioation (W)
Output Voltage (V)
14
16
14
12
12
10
10
8
8
6
6
4
4
2
2
0
0
0
20
40
60
80
100
Start-Up Time, tdVdt (%)
V(IN) = 12 V
C(dVdT) = 1 nF
C(OUT)=100 µF
Figure 53. Start-up Without Load
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Output Voltage (V)
Input Current (A), Power Dissipation (W)
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipated decreases as well. Typical ramp-up of output voltage V(OUT) with inrush current limit of 1.2A
and power dissipated in the device during start-up is shown in Figure 53. The average power dissipated in the
device during start-up is equal to area of triangular plot (red curve in Figure 54) averaged over tdVdT.
V(IN) = 12 V
C(dVdT) = 1 nF
C013
C(OUT)=100 µF
Figure 54. PD(INRUSH) Due to Inrush Current
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For TPS25940 device, the inrush current is determined as,
I=C x
V(IN)
dV
=> I(INRUSH) = C(OUT) x
dT
t dVdT
(15)
Power dissipation during start-up is:
PD(INRUSH) = 0.5 x V(IN) x I(INRUSH)
(16)
Equation 16 assumes that load does not draw any current until the output voltage has reached its final value.
10.2.1.2.5.2 Case 2: Start-up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-up
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a
resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during
tdVdT time. Typical ramp-up of output voltage, Load current and power dissipation in the device is shown in
Figure 55 and power dissipation with respect to time is plotted in Figure 56. The additional power dissipation
during start-up phase is calculated as follows.
æ
t ö÷÷
(VI - VO )(t) = V(IN) x ççç1÷
çè
t dVdT ø÷
(17)
æ V
ö
t
ç (IN) ÷÷
IL (t) = çç
÷x
ççè RL(SU) ÷÷ø t dVdT
(18)
Where RL(SU) is the load resistance present during start-up. Average energy loss in the internal FET during
charging time due to resistive load is given by:
(19)
Load Current (A), Power Dissipation (W)
ò0
æ
t ÷÷ö ççæ V(IN)
t ÷÷ö
V(IN) x ççç1 xç
x
÷ dt
÷
t dVdT ø÷ çèç RL(SU)
t dVdT ø÷÷
èç
14
14
Output Voltage (V)
Power Dissipoation (W)
12
12
Load Current (A)
10
10
8
8
6
6
4
4
2
2
Output Voltage (V)
tdVdT
Wt =
0
0
0
20
40
60
80
100
Start-Up Time, tdVdT (%)
V(IN) = 12 V
RL(SU) = 4.8 Ω
C(dVdT) = 1 nF
Figure 55. Start-up With Load
V(IN) = 12 V
C(dVdT) = 1 nF
C013
RL(SU) = 4.8 Ω
Figure 56. PD(LOAD) in Load During Start-up
On solving Equation 19 the average power loss in the internal FET due to load is:
V 2(IN)
æ 1ö
PD(LOAD) = çç ÷÷÷ x
çè 6 ø R
L(SU)
(20)
Total power dissipated in the device during startup is:
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(21)
Total current during startup is given by:
I(STARTUP) = I(INRUSH) + IL (t)
(22)
If I(STARTUP) > I(LIM), the device limits the current to I(LIM) and the current limited charging time is determined by:
t dVdT(current limited) = C(OUT) x
V(IN)
I(LIM)
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The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as
shown in Figure 57.
Thermal Shutdown Time (ms)
100000
TA -40C
= -40oC
TA 25C
= 25oC
10000
TA 85C
= 85oC
TA 125C
= 125oC
1000
100
10
1
0.1
1
10
100
Power Dissipation (W)
C014
Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (bottom)
Figure 57. Thermal Shutdown Limit Plot
For the design example under discussion,
Select ramp-up capacitor C(dVdT) = 1nF, using Equation 2.
t dvdt = 8.3 x 104 x 12 x 1 x 10-9 = 0.996ms = : 1ms
(24)
The inrush current drawn by the load capacitance (C(OUT)) during ramp-up using Equation 3.
I(INRUSH) = 100 x 10-6
(
æ
) x çççèç1 x1210-3
÷÷ö = 1.2 A
÷÷
ø
(25)
The inrush Power dissipation is calculated, using Equation 16.
PD(INRUSH) = 0.5 x 12 x 1.2 = 7.2 W
(26)
For 7.2 W of power loss, the thermal shut down time of the device should not be less than the ramp-up time tdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 57 at TA =
85°C, for 7.2 W of power the shutdown time is ~60 ms. So it is safe to use 1 ms as start-up time without any load
on output.
Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start up is
calculated, using Equation 20.
æ 1 ö 12 x 12
PD(LOAD) = çç ÷÷÷ x
=5W
çè 6 ø
4.8
(27)
The total device power dissipation during start up is:
PD(STARTUP) = (7.2 + 5) = 12.2 W
(28)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.
If there is a need to decrease the power loss during start-up, it can be done with increase of C(dVdT) capacitor.
To illustrate, choose C(dVdT) = 1.5 nF as an option and recalculate:
t dvdt = 1.5ms
I(INRUSH) =
28
(29)
æ
100 x 10-6 x ççç
ç
(
)
÷÷ö = 0.8 A
÷
è1.5 x 10-3 ÷ø
12
(30)
PD(INRUSH) = 0.5 x 12x 0.8 = 4.8 W
(31)
æ 1 ö æ12 x 12 ÷ö
= 5W
PD(LOAD) = çç ÷÷÷ x çç
çè 6 ø èç 4.8 ÷÷ø
(32)
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PD(STARTUP) = 4.8 + 5 = 9.8 W
(33)
From thermal shutdown limit graph at TA = 85°C, the shutdown time for 10 W power dissipation is ~17 ms, which
increases the margins further for shutdown time and ensures successful operation during start up and steady
state conditions.
The spreadsheet tool available on the web can be used for iterative calculations.
10.2.1.2.6 Programing the Power Good Set Point
As shown in Figure 52, R4 and R5 sets the required limit for PGOOD signal as needed for the downstream
converters. Considering a power good threshold of 11 V for this design, the values of R4 and R5 are calculated
using Equation 34.
æ
R ö
V(PGTH) = 0.99 x ççç1 + 4 ÷÷÷
çè
R5 ÷ø
(34)
It is recommended to have high values for these resistors to limit the current drawn from the output node.
Choosing a value of R4 = 475 kΩ, R5 = 47 kΩ provides V(PGTH) = 11 V.
10.2.1.2.7 Support Component Selections - R6, R7 and CIN
Reference to application schematics, R6 and R7 are required only if PGOOD and FLT are used; these resistors
serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins should not exceed 10
mA (refer to the Absolute Maximum Ratings table). CIN is a bypass capacitor to help control transient voltages,
unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is
recommended for C(IN).
10.2.1.3 Application Curves
Figure 58. Hot-Plug Start-Up: Output Ramp Without Load
on output
Figure 59. Hot-Plug Start-Up: Output Ramp With Start-up
load of 4.8Ω
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Figure 60. Overvoltage Shutdown
IMON
30
Figure 61. Overvoltage Recovery
IMON
Figure 62. Over Load: Step Change in Load from 12Ω to
2Ω and Back
Figure 63. Overload Condition: Auto Retry and Recovery TPS25940A
Figure 64. Hot Short: Fast Trip and Current Regulation
Figure 65. Hot Short: Latched - TPS25940L
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Figure 66. Hot Short: Auto-Retry and Recovery from Short
Circuit - TPS25940A
Figure 67. Hot Plug-in with Short on Output: Latched TPS25940L
Figure 68. Hot Plug-in with Short on Output: Auto-Retry TPS25940A
Figure 69. Power Good Response During Turn-ON
Figure 70. Power Good Response During Turn-OFF
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10.3 System Examples
10.3.1 Power Failure Protection and Data Retention in SSDs
For enterprise and Industrial SSDs, it is necessary to have hold-up circuit and capacitor bank to ensure that
critical user data is never lost during power-failure to the drive. The power-failure event could be due to
momentary loss of power regulation (transient brown-out condition) or due to loss of power when drive is hotplugged out.
The TPS25940 continuously monitors the supply voltage at EN/UVLO pin and swiftly disconnects the input bus
from output when the voltage drops below a predefined threshold (power fail detection). The TPS25940 also
monitors the reverse voltage from IN to OUT and when it exceeds -10 mV, it stops the flow of reverse current. In
addition, it provides an instant warning signal (FLT) to the SSD controller to initiate the data hardening process.
Its swift true reverse blocking feature reacts in 1 µs (typical) ensuring that the capacitor bank charge is retained.
This helps the drive to have power for longer time to harden data and reduces the capacitance required in the
hold-up bank, saving system cost.
The typical application diagram and application schematic of TPS25940 usage for enterprise SSD are shown in
Figure 71 and Figure 72
TPS25940
3V3 or 5V
or 12V
Inrush Current
Control
/ Soft start
SSD Controllers
Power FET Isolation
during Power Failure
Hold Up
Capacitor Bank
NAND Flash
FLT (PFAIL)
Power Failure
Detection
EN
Voltage
Regulators
To SSD
Controller
PGOOD
(Voltage monitor & Reset Circuit)
Figure 71. Power Circuit Block Diagram of Enterprise and Industrial SSDs
2.7 to 18 V
R1
IN
IN
R6
EN/UVLO
OVP
DEVSLP
dVdT
R3
COUT
42mO
CIN
(See Note A)
R2
CdVdT
OUT
OUT
R4
FLT
PGOOD
PGTH
IMON
Hold Up
Capacitor Bank
R7
Power Good
System Load
Load Monitor
ILIM
GND
RILIM
R5
RIMON
TPS25940x
A.
CIN: Optional and only for noise suppression.
Figure 72. Enterprise SSD – Holdup Capacitor Implementation using TPS25940
The oscilloscope plots demonstrating the true reverse blocking, fast turn-off and FLT signal delay are shown in
Figure 73 through Figure 75.
32
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System Examples (continued)
V(IN) = 12V
C(OUT) = 1500 µF
RL = 5.6 Ω
V(IN) = 12V
Figure 73. Hot-Plug Out Condition
V(IN) = 12V
C(OUT) = 1500 µF
RL = 5.6 Ω
Figure 74. Hot-Plug Out Condition: FLT Delay
C(OUT) = 1500 µF
RL = 5.6 Ω
Figure 75. Standard Power Shutdown or Brownout Conditions
10.3.2 Boost Power Rail Configuration for Data Retention in Enterprise SSDs
In certain enterprise SSD architectures, the hold-up capacitor voltage is boosted to value higher than the input
bus voltage to optimize the storage capacitor bank. A typical boosted hold-up voltage ranges from 12 V to 18 V.
A typical power circuit block diagram is shown in Figure 76. For these applications, TPS25940 provides quick
and smooth changeover of the power from main input bus to boosted backup voltage.
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System Examples (continued)
TPS25940
3V3 or 5V
or 12V
Inrush Current
Control
/ Soft start
SSD Controllers
Power FET Isolation
during Power Failure
Voltage
Regulators
switchover
signal
PGOOD
(Voltage monitor and Reset Circuit)
EN
To SSD
Controller
NAND Flash
Power FET
Isolation
Power Failure
Detection
EN
OVP
FLT
FLT (PFAIL)
Boost
Converter
TPS25940
Hold Up
Capacitor Bank
VBOOST G 18V
Figure 76. Power Circuit Block Diagram with Boosted Backup Power for Enterprise SSD
A typical application schematic for implementation of boosted backup power configuration is shown in Figure 77.
During startup TPS25940 provides the inrush current control to charge up the C(BUS) as well as C(HOLDUP) close to
V(IN). Once V(BUS) reaches the programmed PGOOD threshold, the boost converter is enabled to charge
C(HOLDUP) to V(BOOST). When V(IN) fails, TPS25940 detects power failure and asserts the fault signal (FLT), which
in turn disables the boost converter and shorts V(BOOST) to V(BUS), through M1. The FLT signal can be interfaced
to SSD controller to initiate the data hardening process. If current limit protection is desired during data hardening
process (when holdup capacitor is supplying system bus), M1 can be replaced by another TPS25940.
The oscilloscope plot demonstrating change over from Main (12 V) to Boosted backup power (14.5 V) is shown
in Figure 78.
EN
2.7 to 18 V
IN
IN
R6
(See Note A)
EN/UVLO
OVP
R2
DEVSLP
dVdT
R3
CdVdT
VBOOST
M1
CBUS
42mO
CIN
R1
VBUS
OUT
OUT
Boost
Converter
R4
FLT
PGOOD
PGTH
IMON
R9
R7
R8
CHOLDUP
Load Monitor
ILIM
GND
RILIM
R5
VBOOST 18V
DC/DC :
System Load
RIMON
TPS25940x
A.
CIN: Optional and only for noise suppression.
Figure 77. Enterprise SSDs: Boosted Backup Power Multiplexing Circuit Implementation
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SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
System Examples (continued)
V(IN) = 12 V
V(BOOST) = 14.5 V
C(BUS) = 150 µF
P(LOAD) = 12.5 W
V(IN-UVLO-low) = 10.2 V
C(dVdT) = 1 nF
Figure 78. Brownout (Power Fail) Condition: Switch over to Boosted Backup Power
11 Power Supply Recommendations
The TPS25940 device is designed for supply voltage range of 2.7 V ≤ VIN ≤ 18 V. If the input supply is located
more than a few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended.
Power supply should be rated higher than the current limit set to avoid voltage droops during over current and
short-circuit conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 35.
VSPIKE(Absolute) = V(IN) + I(LOAD) x
L(IN)
C(IN)
(35)
Where:
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current,
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
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Transient Protection (continued)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 79.
IN
2.7 to 18 V
R1
IN
R2
R6
DEVSLP
dVdT
R3
COUT
42mO
CIN
(See Note A)
EN/UVLO
OVP
(See Note A)
CdVdT
R4
R7
FLT
PGOOD
PGTH
IMON
ILIM
(See Note A)
GND
TPS25940x
A.
OUT
OUT
RILIM
R5
RIMON
Optional components needed for suppression of transients
Figure 79. Circuit Implementation With Optional Protection Components
11.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
For all applications, a 0.1-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 80 for a PCB layout example.
High current carrying power path connections should be as short as possible and should be sized to carry at
least twice the full-load current.
Low current signal ground (SGND), which is the reference ground for the device should be a copper plane or
island.
Locate all TPS25940 support components: R(ILIM), CdVdT, R(IMON), and resistors for UVLO and OVP, close to
their connection pin. Connect the other end of the component to the SGND with shortest trace length.
The trace routing for the RILIM and R(IMON) components to the device should be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces should not have any
coupling to switching signals on the board.
The SGND plane must be connected to high current ground (main power ground) at a single point, that is at
the negative terminal of input capacitor
Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it should be physically close to the OUT pins.
Thermal Considerations: When properly mounted the PowerPAD™ package provides significantly greater
cooling ability than an ordinary package. To operate at rated power, the PowerPAD must be soldered directly
to the board GND plane directly under the device. The PowerPAD is at GND potential and can be connected
using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used
to increase heat sinking in higher current applications. Refer to Technical Briefs: PowerPad™ Thermally
Enhanced Package (TI literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number
SLMA004) or more information on using this PowerPAD™ package
The thermal via land pattern specific to TPS25940 can be downloaded from device webpage
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
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12.2 Layout Example
Top layer
Top layer signal ground plane
Bottom layer signal ground plane
Via to signal ground plane
Power Ground
OUT
OUT
IN
(See Note A)
Output
7
8
9
VI
IN 10
Input
High
Frequency
Bypass
Capacitor
11
6
OUT
IN 12
5
OUT
IN
13
4
OUT
EN 14
3
PGTH
OVP 15
2
PGOOD
GND 16
1
DEVSLP
IN
20
FLT
19 IMON
18 dVdT
17 ILIM
Signal
Ground
Bottom
layer
Signal Ground
Top Layer
A.
VO
Optional: Needed only to suppress the transients caused by inductive load switching
Figure 80. Board Layout
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SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS25940A
Click here
Click here
Click here
Click here
Click here
TPS25940L
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
DevSleep, SATA are trademarks of The Serial ATA International Organization (SATA-IO).
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25940A TPS25940L
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PACKAGE OUTLINE
RVC0020A
WQFN - 0.8 mm max height
WQFN
1
6
0,20 Nominal
2,50
0,50
1,50
16
11
Exposed Thermal Pad
4219150/A 07/2014
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RVC0020A
WQFN - 0.8 mm max height
WQFN
11
16
4219150/A 07/2014
NOTES: (continued)
4.
This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application
note in literature No. SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
EXAMPLE STENCIL DESIGN
RVC0020A
WQFN - 0.8 mm max height
WQFN
11
16
4219150/A 07/2014
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS25940ARVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
25940A
TPS25940ARVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
25940A
TPS25940LRVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
(25940A, 25940L)
TPS25940LRVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
25940L
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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