TPS25974LRPWR

TPS2597 SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 TPS2597xx 2.7 V–23 V, 7-A, 9.8-mΩ eFuse With Accurate Current Monitor and Transient Overcurrent Blanking 1 Features 3 Description • The TPS2597xx family of eFuses is a highly integrated circuit protection and power management solution in a small package. The devices provide multiple protection modes using very few external components and are a robust defense against overloads, short-circuits, voltage surges and excessive inrush current. • • • • • • • • • • • Wide operating input voltage range: 2.7 V to 23 V – 28-V absolute maximum Integrated FET with low on-resistance: RON = 9.8 mΩ (typ.) Fast overvoltage protection – Overvoltage clamp (OVC) with pin-selectable threshold (3.89 V, 5.76 V, 13.88 V) and 5-μs (typical) response time or – Adjustable overvoltage lockout (OVLO) with 1.2-μs (typical) response time Overcurrent protection with load current monitor output (ILM) – Active current limit or circuit-breaker options – Adjustable threshold (ILIM) 0.87 A – 7.7 A • ±10% accuracy for ILIM > 1.74 A – Adjustable transient blanking timer (ITIMER) to allow peak currents up to 2 × ILIM – Output load current monitor accuracy: ±8% (max) Fast-trip response for short-circuit protection – 550-ns (typical) response time – Adjustable (2 × ILIM) and fixed thresholds Active high enable input with adjustable undervoltage lockout threshold (UVLO) Adjustable output slew rate control (dVdt) Overtemperature protection Digital outputs – Fault indication (FLT) or – Power-Good indication (PG) with adjustable threshold (PGTH) UL 2367 recognition – File No. E339631 – RILM ≥ 750 Ω IEC 62368-1 CB certified Small footprint: QFN 2 mm × 2 mm, 0.45-mm pitch Output slew rate and inrush current can be adjusted using a single external capacitor. Loads are protected from input overvoltage conditions either by clamping the output to a safe fixed maximum voltage (pin selectable), or by cutting off the output if the input exceeds an adjustable overvoltage threshold. The devices respond to output overload by actively limiting the current or breaking the circuit. The output current limit threshold as well as the transient overcurrent blanking timer are user adjustable. The current limit control pin also functions as an analog load current monitor. The devices are available in a 2-mm × 2-mm, 10pin HotRod™ QFN package for improved thermal performance and reduced system footprint. The devices are characterized for operation over a junction temperature range of –40°C to +125°C. Package Information (1) PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPS2597xxRPW RPW (QFN, 10) 2.00 mm × 2.00 mm For all available packages, see the orderable addendum at the end of the data sheet. VIN = 2.7 to 23 V IN VOUT OUT VLOGIC COUT EN/UV LO 2 Applications • • • • • • Server, PC motherboard, and add-in cards Enterprise storage – RAID/HBA/SAN/eSSD Patient monitors Appliances and power tools Retail point-of-sale terminals Smartphones and tablets TPS25 970x OVL O FLT ITIMER CITIMER dVd t GND CDVD T ILM RILM Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................7 7.6 Timing Requirements.................................................. 8 7.7 Switching Characteristics............................................9 7.8 Typical Characteristics.............................................. 10 8 Detailed Description......................................................18 8.1 Overview................................................................... 18 8.2 Functional Block Diagram......................................... 19 8.3 Feature Description...................................................22 8.4 Device Functional Modes..........................................33 9 Application and Implementation.................................. 34 9.1 Application Information............................................. 34 9.2 Typical Application.................................................... 35 9.3 Parallel Operation..................................................... 38 9.4 Power Supply Recommendations.............................40 9.5 Layout....................................................................... 42 10 Device and Documentation Support..........................44 10.1 Device Support....................................................... 44 10.2 Documentation Support.......................................... 44 10.3 Receiving Notification of Documentation Updates..44 10.4 Support Resources................................................. 44 10.5 Trademarks............................................................. 44 10.6 Electrostatic Discharge Caution..............................44 10.7 Glossary..................................................................44 11 Mechanical, Packaging, and Orderable Information.................................................................... 45 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2022) to Revision C (April 2023) Page • Updated the UL/IEC certification status..............................................................................................................1 Changes from Revision A (December 2021) to Revision B (January 2022) Page • Added Thermal Information table to the document.............................................................................................5 Changes from Revision * (November 2021) to Revision A (December 2021) Page • Changed status from "Advance Information" to "Production Data".................................................................... 1 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 5 Device Comparison Table PART NUMBER TPS25970ARPW TPS25970LRPW TPS25972ARPW TPS25972LRPW TPS25974ARPW TPS25974LRPW OVERVOLTAGE RESPONSE OVERCURRENT RESPONSE Adjustable OVLO PG and PGTH FLT N Y Active Current Limit Y Circuit Breaker Auto-Retry Latch-Off Auto-Retry Pin Selectable OVC (3.89 V/5.76 V/13.88 V) Adjustable OVLO RESPONSE TO FAULT N Latch-Off Auto-Retry Latch-Off Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 3 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 6 Pin Configuration and Functions IN OUT EN/UV LO 1 10 OVL O/ OVCSE L 2 9 ILM 5 ITIMER 6 PG/ DNC 3 8 GND PGTH/ FLT 4 7 DVDT Figure 6-1. TPS2597xx RPW Package 10-Pin QFN (Top View) Table 6-1. Pin Functions PIN NAME NO. EN/UVLO 1 TYPE Analog Input Active high enable for the device. A resistor divider on this pin from input supply to GND can be used to adjust the undervoltage lockout threshold. Do not leave floating. Refer to Undervoltage Lockout (UVLO and UVP) for details. Analog Input TPS25970x and TPS25974x: A resistor divider on this pin from supply to GND can be used to adjust the overvoltage lockout threshold. This pin can also be used as an active low enable for the device. Do not leave floating. Refer to Overvoltage Lockout (OVLO) for details. OVCSEL Analog Input TPS25972x: Overvoltage clamp threshold select pin. Refer to Overvoltage Clamp (OVC) for details. PG Digital Output TPS25972x and TPS25974x: Power-good indication. This is an open-drain signal, which is asserted high when the internal powerpath is fully turned ON and the PGTH input exceeds a certain threshold. Refer to Power Good Indication (PG) for more details. DNC Digital Output TPS25970x: Can be left floating FLT Digital Output TPS25970x: Active low fault event indicator. This pin is an open-drain signal that is pulled low when a fault is detected. Refer to Fault Response and Indication (FLT) for more details. Analog Input TPS25972x and TPS25974x: Power-good threshold. Refer to Power Good Indication (PG) for more details. OVLO 2 3 4 PGTH 4 DESCRIPTION IN 5 Power Power input OUT 6 Power Power output DVDT 7 Analog Output GND 8 Ground ILM 9 Analog Output This pin is a dual function pin used to limit and monitor the output current. An external resistor from this pin to GND sets the output current limit threshold during start-up as well as steady state. The pin voltage can also be used as analog output load current monitor signal. Do not leave floating. Refer to Circuit-Breaker or Active Current Limiting for more details. ITIMER 10 Analog Output A capacitor from this pin to GND sets the overcurrent blanking interval during which the output current can temporarily exceed set current limit (but lower than fast-trip threshold) before the device overcurrent response takes action. Leave this pin open for the fastest response to overcurrent events. Refer to Circuit-Breaker or Active Current Limiting for more details. A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest turn on slew rate. Refer to Slew Rate (dVdt) and Inrush Current Control for details. This pin is the ground reference for all internal circuits and must be connected to system GND. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Parameter Pin MIN MAX UNIT VIN Maximum input voltage range, –40 ℃ ≤ TJ ≤ 125 ℃ IN –0.3 28 VOUT Maximum output voltage range, –40 ℃ ≤ TJ ≤ 125 ℃ OUT –0.3 VIN + 0.3 VOUT,PLS Minimum output voltage pulse (< 1 µs) OUT –0.8 VEN/UVLO Maximum Enable pin voltage range EN/UVLO –0.3 6.5 V VOV Maximum OVCSEL/OVLO pin voltage range OVCSEL/OVLO –0.3 6.5 V VdVdT Maximum dVdT pin voltage range dVdt Internally limited VITIMER Maximum ITIMER pin voltage range ITIMER Internally limited VPGTH Maximum PGTH pin voltage range PGTH –0.3 6.5 V VPG Maximum PG pin voltage range PG –0.3 6.5 V VFLTB Maximum FLT pin voltage range FLT –0.3 6.5 V VILM Maximum ILM pin voltage range ILM Internally limited V IMAX Maximum continuous switch current IN to OUT Internally limited A TJ Junction temperature TLEAD Maximum lead temperature Tstg Storage temperature (1) V V Internally limited –65 V °C 300 °C 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001((1)) ±2000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002((2)) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Parameter Pin MIN MAX UNIT 2.7 23(1) V OUT VIN V EN/UVLO pin voltage range EN/UVLO 5(2) V VOV OVLO pin voltage range (TPS25970x and TPS25974x variants only) OVLO 1.5 V VdVdT dVdT pin capacitor voltage rating dVdt VPGTH PGTH pin voltage range PGTH 5 V VFLTB FLT pin voltage range FLT 5 V VPG PG pin voltage range PG 5 V VITIMER ITIMER pin capacitor voltage rating ITIMER RILM ILM pin resistance to GND ILM 715 6650 Ω IMAX Continuous switch current, TJ ≤ 125 ℃ IN to OUT 7 A TJ Junction temperature –40 125 °C VIN Input voltage range IN VOUT Output voltage range VEN/UVLO (1) 0.5 VIN + 5 V V 4 V For TPS25972x OVC variants, the input operating voltage must be limited to the selected Output Voltage Clamp Option as listed in the Electrical Characteristics section. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 5 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 (2) For supply voltages below 5 V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5 V, TI recommends to use a resistor divider with a minimum pullup resistor value of 350 kΩ. 7.4 Thermal Information TPS2597xx THERMAL METRIC (1) RPW (QFN) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance RθJB Junction-to-board thermal resistance ΨJT ΨJB (1) (2) (3) 6 49.7((2)) °C/W 71.8((3)) °C/W 15.7 °C/W Junction-to-top characterization parameter 2.1((2)) °C/W Junction-to-top characterization parameter 1.3((3)) °C/W 23 ((2)) °C/W Junction-to-board characterization parameter 14.5 ((3)) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device. Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.5 Electrical Characteristics (Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V for TPS25970x/4x, OVCSEL = 390 kΩ to GND for TPS25972x, RILM = 715 Ω , dVdT = Open, ITIMER = Open, FLT = Open for TPS25970x, PGTH = Open for TPS25972x/4x, PG = Open for TPS25972x/4x. All voltages referenced to GND. Test Parameter Description MIN TYP MAX UNITS IN supply quiescent current (TPS25970x) 413 650 µA IN supply quiescent current (TPS25972x) 407 650 µA IN supply quiescent current (TPS25974x) 413 650 µA IN supply quiescent current during OVC (TPS25972x) 429 650 µA INPUT SUPPLY (IN) IQ(ON) IQ(OFF) IN supply OFF state current (VSD(F) < VEN < VUVLO(F)) 67 131 µA ISD IN supply shutdown current (VEN < VSD(F)) 2.3 25 µA VUVP(R) IN supply UVP rising threshold 2.44 2.54 2.64 V VUVP(F) IN supply UVP falling threshold 2.35 2.45 2.55 V Overvoltage Clamp threshold, OVCSEL = Shorted to GND 3.65 3.89 4.1 V Overvoltage Clamp threshold, OVCSEL = Open 5.25 5.76 6.2 V Overvoltage Clamp threshold, OVCSEL = 390 kΩ to GND 13.2 13.88 14.5 V Output voltage during clamping, OVCSEL = Shorted to GND, IOUT = 10 mA 3.2 3.82 4.2 V Output voltage during clamping, OVCSEL = Open, IOUT = 10 mA 5 5.68 6.12 V Output voltage during clamping, OVCSEL = 390 kΩ to GND, IOUT = 10 mA 13 13.79 14.6 V 98 105.5 114 µA/A Overcurrent threshold, RILM = 6.65 KΩ 0.745 0.87 0.97 A Overcurrent threshold, RILM = 3.32 KΩ 1.55 1.73 1.905 A Overcurrent threshold, RILM = 1.65 KΩ 3.2 3.48 3.715 A 7.03 7.67 8.15 A 0.1 A 2 3.1 A OUTPUT VOLTAGE CLAMP (OUT) - TPS25972x VOVC VCLAMP OUTPUT LOAD CURRENT MONITOR (ILM) GIMON Analog load current monitor gain (IMON : IOUT), 1 A ≤ IOUT ≤ 7.7 A, IOUT < ILIM OVERCURRENT PROTECTION (OUT) ILIM Overcurrent threshold, RILM = 750 Ω ISPFLT Circuit-Breaker threshold, ILM pin open (Single point failure) ISPFLT Circuit-Breaker threshold, ILM pin shorted to GND (Single point failure) ISCGain Scalable fast-trip threshold (ISC) : ILIM ratio 170 201 240 % VFB VOUT threshold to exit current limit foldback 1.55 1.88 2.23 V 2.7 ≤ VIN ≤ 4 V, IOUT = 3 A, TJ = 25℃ 10 18.3 mΩ 4 < VIN ≤ 23 V, IOUT = 3 A, TJ = 25℃ 9.8 18.3 mΩ 1.2 1.228 V ON RESISTANCE (IN - OUT) RON ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO) VUVLO(R) EN/UVLO rising threshold 1.183 VUVLO(F) EN/UVLO falling threshold 1.076 1.1 1.12 V VSD(F) EN/UVLO falling threshold for lowest shutdown current 0.45 0.75 0.95 V IENLKG EN/UVLO pin leakage current -0.1 0.1 µA OVERVOLTAGE LOCKOUT (OVLO) - TPS25970x/4x VOV(R) OVLO rising threshold 1.183 1.2 1.228 V VOV(F) OVLO falling threshold 1.076 1.1 1.12 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 7 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.5 Electrical Characteristics (continued) (Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V for TPS25970x/4x, OVCSEL = 390 kΩ to GND for TPS25972x, RILM = 715 Ω , dVdT = Open, ITIMER = Open, FLT = Open for TPS25970x, PGTH = Open for TPS25972x/4x, PG = Open for TPS25972x/4x. All voltages referenced to GND. Test Parameter IOVLKG Description MIN OVLO pin leakage current (0.5 V < VOVLO < 1.5 V) TYP MAX -0.1 UNITS 0.1 µA 2.72 µA OVERCURRENT FAULT TIMER (ITIMER) IITIMER ITIMER pin internal discharge current, IOUT > ILIM RITIMER ITIMER pin internal pullup resistance VINT ITIMER pin internal pullup voltage VITIMER(F) ΔVITIMER 1.5 2 13.8 35 kΩ 2.1 2.57 2.74 V ITIMER comparator threshold, IOUT > ILIM 0.609 1.05 1.37 V ITIMER discharge differential voltage threshold, IOUT > ILIM 1.286 1.52 1.741 V PG pin voltage while de-asserted. VIN < VUVP(F), VEN < VSD(F), Weak pull-up (IPG = 26 μA) 663 1000 mV PG pin voltage while de-asserted. VIN < VUVP(F), VEN < VSD(F), Strong pull-up (IPG = 242 μA) 782 1000 mV 0 600 mV 3 µA V POWER GOOD INDICATION (PG) - TPS25972x/4x VPGD PG pin voltage while de-asserted, VIN > VUVP(R) IPGLKG PG pin leakage current, PG asserted POWERGOOD THRESHOLD (PGTH) VPGTH(R) PGTH rising threshold 1.178 1.2 1.23 VPGTH(F) PGTH falling threshold 1.071 1.1 IPGTHLKG PGTH pin leakage current 1.13 V -1 1 µA -1 1 µA FAULT INDICATION (FLTB) - TPS25970x IFLTLKG FLT pin leakage current RFLTB FLT pin internal pull-down resistance 12.4 Ω 154 °C 10 °C OVERTEMPERATURE PROTECTION (OTP) TSD Thermal Shutdown rising threshold, TJ↑ TSDHYS Thermal Shutdown hysteresis, TJ↓ DVDT IdVdt dVdt pin internal charging current 1.4 3.4 5.7 µA 7.6 Timing Requirements 8 PARAMETER TEST CONDITIONS tOVLO Overvoltage lockout response time TPS25970x and TPS25974x, VOVLO > VOV(R) to VOUT↓ MIN tOVC Overvoltage clamp response time tCB TYP MAX UNIT 1.2 µs TPS25972x, VIN > VOVC to VOUT↓ 5 µs Circuit-Breaker response time TPS25974x, IOUT > ILIM + 30% to VOUT↓ 2 µs tLIM Current limit response time TPS25970x and TPS25972x, IOUT > ILIM + 30% to IOUT settling to within 5% of ILIM 465 µs tSC Short-circuit response time IOUT > 3x ILIM to output current cut off 550 ns tFT Fixed fast-trip response time IOUT > IFT to IOUT↓ 550 ns tTSD,RST Thermal Shutdown auto-retry Interval Device enabled and TJ < TSD - TSDHYS 110 ms tPGA PG assertion de-glitch time VPGTH > VPGTH(R) to PG↑ 14 µs tPGD PG de-assertion de-glitch time VPGTH < VPGTH(F) to PG↓ 14 µs Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.7 Switching Characteristics The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply is available in steady state condition and the load voltage is completely discharged before the device is enabled. Typical values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF. PARAMETER SRON tD,ON tR tON tD,OFF Output rising slew rate Turn-on delay Rise time Turn-on time Turn-off delay VIN CdVdt = Open CdVdt = 1800 pF CdVdt = 3300 pF 2.7 V 8.922 1.218 0.72 12 V 21.45 1.562 0.901 23 V 34.16 1.761 1.003 2.7 V 0.138 0.505 0.79 12 V 0.145 0.979 1.659 23 V 0.15 1.478 2.562 2.7 V 0.242 1.771 2.993 12 V 0.446 6.131 10.63 23 V 0.538 10.43 18.31 2.7 V 0.379 2.277 3.783 12 V 0.582 7.11 12.29 23 V 0.668 11.91 20.87 2.7 V 22.1 22.1 22.1 12 V 18.9 18.9 18.9 23 V 16.5 16.5 16.5 UNITS V/ms ms ms ms µs Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 9 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 14.5 14 VIN (V) 2.7 13.5 3.3 13 4 12.5 5 12 12 23 11.5 11 10.5 10 9.5 9 8.5 8 7.5 -40 -20 500 480 460 440 IQ(ON) (A) RON (m) 7.8 Typical Characteristics 420 400 380 360 TA (C) -40 25 85 125 340 320 0 20 40 60 TA (C) 80 100 120 300 2.5 140 Figure 7-1. ON-Resistance vs Supply Voltage 5 7.5 10 12.5 15 VIN (V) 17.5 20 22.5 25 Figure 7-2. IN Quiescent Current vs Temperature (TPS25970x, TPS25974x Variants) 500 100 90 80 IQ(OFF) (A) IQ(ON) (A) 450 400 TA (C) -40 25 85 125 350 60 50 TA (C) -40 25 85 125 40 30 20 300 3 4 5 6 7 8 VIN (V) 9 10 11 2 12 Figure 7-3. IN Quiescent Current vs Temperature (TPS25972x Variant) 4 6 8 10 12 14 VIN (V) 16 18 20 22 24 Figure 7-4. IN OFF State (UVLO) Current vs Temperature 8 2.55 TA (C) -40 25 85 125 2.5 VUVP (V) 6 ISD (A) 70 4 Rising Falling 2.45 2 0 2 4 6 8 10 12 14 VIN (V) 16 18 20 22 Figure 7-5. IN Shutdown Current vs Temperature 10 24 2.4 -40 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-6. IN Undervoltage Threshold vs Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.8 Typical Characteristics (continued) 1.208 1.207 VUVLO(R) (V) 1.2065 1.1005 VIN (V) 2.7 5 12 23 1.0995 1.099 1.206 1.2055 1.205 1.2045 1.0985 1.098 1.0975 1.097 1.0965 1.204 1.096 1.2035 1.0955 1.203 -40 VIN (V) 2.7 5 12 23 1.1 VUVLO(F) (V) 1.2075 -20 0 20 40 60 TA (C) 80 100 120 1.095 -40 140 Figure 7-7. EN/UVLO Rising Threshold vs Temperature -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-8. EN/UVLO Falling Threshold vs Temperature 1.21 1.209 1.208 VOV(R) (V) 1.207 VIN (V) 2.7 5 12 23 1.206 1.205 1.204 1.203 1.202 1.201 1.2 -40 1.1005 1.0995 VIN (V) 2.7 5 12 23 1.0985 ILIM (mA) VOV(F) (V) 1.099 1.098 1.0975 1.097 1.0965 1.096 1.0955 1.095 -40 -20 0 20 40 60 TA (C) 80 100 120 Figure 7-11. OVLO Falling Threshold vs Temperature (TPS25970x, TPS25974x Variants) 0 20 40 60 TA (C) 80 100 120 140 Figure 7-10. OVLO Rising Threshold vs Temperature (TPS25970x, TPS25974x Variants) Figure 7-9. EN/UVLO Shutdown Falling Threshold vs Temperature 1.1 -20 140 8000 7500 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0.5 1 1.5 2 2.5 3 3.5 4 4.5 RILM (k) 5 5.5 6 6.5 7 Figure 7-12. Overcurrent Threshold vs ILM Resistor Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 11 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 0.5 10 Min Max 6 0 -2 -4 -8 1.5 2.5 3.5 4.5 ILIM (A) 5.5 6.5 1 7.5 1.5 2 2.5 3 3.5 4 4.5 5 IOUT (A) 5.5 6 6.5 7 7.5 8 Figure 7-14. Analog Current Monitor Gain Accuracy 14 13 201.85 OVCSEL Shorted to GND OPEN 390 k to GND 12 201.75 11 201.65 10 VOVC (V) ISFT/ILIM Ratio (%) 2 -10 201.95 201.55 201.45 201.35 201.25 -20 0 20 40 60 TA (C) 80 100 9 8 VIN (V) 2.7 5 12 23 7 120 3 -40 6 5 4 140 Figure 7-15. Scalable Fast-Trip Threshold: Current Limit Threshold (ILIM) Ratio vs Temperature -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-16. OVC Threshold vs Temperature (TPS25972x Variant) 5.88 14 5.85 13.95 13.85 13.8 5.82 IOUT (mA) 1 10 100 5.79 VCLAMP (V) IOUT (mA) 1 10 100 13.9 VCLAMP (V) 4 -6 Figure 7-13. Overcurrent Threshold Accuracy (Across Process, Voltage and Temperature) 201.15 -40 Min Max 8 GIMON Error (%) ILIM Error (%) 7.8 Typical Characteristics (continued) 5.76 5.73 5.7 5.67 13.75 5.64 13.7 5.61 5.58 13.65 -40 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-17. OVC Clamping Voltage (OVCSEL = 390 kΩ to GND) vs Load Current (TPS25972x Variant) 12 5.55 -40 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-18. OVC Clamping Voltage (OVCSEL = OPEN) vs Load Current (TPS25972x Variant) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.8 Typical Characteristics (continued) 4.02 1.53 3.99 1.528 IOUT (mA) 1 10 100 VCLAMP (V) 3.93 3.9 3.87 3.84 3.81 1.526 1.524 VITIMER (V) 3.96 1.522 1.52 1.518 1.516 3.78 1.514 3.75 1.512 3.72 3.69 -40 VIN (V) 2.7 5 12 23 -20 0 20 40 60 TA (C) 80 100 120 1.51 -40 140 Figure 7-19. OVC Clamping Voltage (OVCSEL = GND) vs Load Current (TPS25972x Variant) -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-20. ITIMER Discharge Differential Voltage Threshold vs Temperature 18.5 18 17.5 RITIMER (k) 17 VIN (V) 2.7 5 12 23 16.5 16 15.5 15 14.5 14 13.5 13 -40 2.8 4 2.7 3.8 2.6 3.6 2.5 2.4 VIN (V) 2.7 5 12 23 2.3 2.2 -40 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-23. ITIMER internal Pullup Voltage vs Temperature 0 20 40 60 TA (C) 80 100 120 140 Figure 7-22. ITIMER Internal Pullup Resistance vs Temperature IDVDT (A) VINT (V) Figure 7-21. ITIMER Discharge Current vs Temperature -20 VIN (V) 2.7 5 12 23 3.4 3.2 3 2.8 -40 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-24. DVDT Charging Current vs Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 13 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.8 Typical Characteristics (continued) 1.206 1.1005 VIN (V) 2.7 5 12 23 1.2055 1.0995 1.099 1.2045 VPGTH(F) (V) VPGTH(R) (V) 1.205 1.204 1.2035 1.097 1.0955 1.202 -40 -20 0 20 40 60 TA (C) 80 100 120 1.095 -40 140 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-25. PGTH Threshold (Rising) vs Temperature (TPS25972x, TPS25974x Variants) Figure 7-26. PGTH Threshold (Falling) vs Temperature (TPS25972x, TPS25974x Variants) 19 10000 5000 VIN (V) 2.7 12 23 18 17 2000 1000 500 Time to TSD (ms) 16 RFLTB () 1.098 1.0975 1.096 1.2025 15 14 13 12 200 100 50 20 10 5 2 1 0.5 11 10 9 -40 0.2 0.1 -20 0 20 40 60 TA (C) 80 100 120 140 Figure 7-27. FLT Pin Pulldown Resistance vs Temperature 1000 500 Time to TSD (ms) 1.0985 1.0965 1.203 0 20 40 60 80 PD (W) 100 120 140 Figure 7-28. Time to Thermal Shut-Down During Inrush State TA (C) -40 25 85 125 200 100 50 20 10 5 2 1 0.5 0.2 0.1 1 2 3 4 5 6 7 8 10 PD (W) 20 30 40 50 60 Figure 7-29. Time to Thermal Shut-Down During Steady State 14 VIN (V) 2.7 5 12 23 1.1 VIN = 12 V, COUT = 22 μF, CdVdt = Open, VEN/UVLO ramped from 0 V → 1.4 V → 0 V Figure 7-30. Power Up and Down With EN/UVLO Control Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.8 Typical Characteristics (continued) VEN/UVLO = 2 V, COUT = 22 μF, CdVdt = Open, VIN ramped from 0 V → 12 V → 0 V COUT = 22 μF, CdVdt = Open, EN/UVLO connected to IN through resistor ladder, 12 V hot-plugged to IN Figure 7-31. Power Up and Down With Input Supply VIN = 12 V, COUT = 470 μF, CdVdt = Open, VEN/UVLO stepped up to 3.3 V Figure 7-33. Inrush Current Without Slew Rate Control – Capacitive Load VIN = 12 V, COUT = 470 μF, ROUT = 10 Ω, CdVdt = 5100 pF, VEN/UVLO stepped up to 3.3 V Figure 7-35. Inrush Current With Slew Rate Control – Resistive and Capacitive Load Figure 7-32. Input Hot-Plug VIN = 12 V, COUT = 470 μF, CdVdt = 5100 pF, VEN/UVLO stepped up to 3.3 V Figure 7-34. Inrush Current With Slew Rate Control – Capacitive Load OV threshold set to 16.7 V, VIN ramped up from 12 V to 17 V Figure 7-36. Overvoltage Lockout Response – TPS25970x and TPS25974x Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 15 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.8 Typical Characteristics (continued) ROVCSEL = GND, COUT = 220 μF, IOUT = 200 mA, VIN ramped up from 3.3 V to 5.8 V Figure 7-37. Overvoltage Clamp Response – TPS25972x ROVCSEL = 390 kΩ, COUT = 220 μF, IOUT = 200 mA, VIN ramped up from 12 V to 16.5 V Figure 7-38. Overvoltage Clamp Response – TPS25972x VIN = 12 V, CITIMER = 1.3 nF, COUT = 220 μF, RILM = 715 Ω, IOUT stepped from 0 A → 11 A Figure 7-39. Overvoltage Clamp Response – TPS25972x Figure 7-40. Active Current Limit Response – TPS25970x VIN = 12 V, CITIMER = 1.3 nF, COUT = 220 μF, RILM = 715 Ω, IOUT stepped from 0 A → 11 A VIN = 12 V, CITIMER = 120 pF, COUT = 470 μF, RILM = 715 Ω, IOUT ramped from 0 A → 8 A→ 4 A within 100 μs Figure 7-41. Active Current Limit Response Followed by TSD – TPS25970x 16 ROVCSEL = Open, COUT = 220 μF, IOUT = 200 mA, VIN ramped up from 5 V to 7.5 V Figure 7-42. Transient Overcurrent Blanking Timer Response Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 7.8 Typical Characteristics (continued) VIN = 12 V, CITIMER = 1.3 nF, COUT = 470 μF, RILM = 715 Ω, IOUT stepped from 0 A → 11 A Figure 7-43. Circuit-Breaker Response TPS25974x VIN = 12 V, RILM = 715 Ω, OUT stepped from Open → Shortcircuit to GND Figure 7-45. Output Short-Circuit During Steady State (Zoomed In) VIN = 12 V, RILM = 715 Ω, OUT stepped from Open → Shortcircuit to GND Figure 7-44. Output Short-Circuit During Steady State VIN = 12 V, COUT = Open, OUT short-circuit to GND, RILM = 715 Ω, VEN/UVLO stepped from 0 V to 3.3 V Figure 7-46. Power Up into Short-Circuit Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 17 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 8 Detailed Description 8.1 Overview The TPS2597xx is an eFuse with an integrated power path that is used to ensure safe power delivery in a system. The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the undervoltage protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on this pin enables the internal power path (HFET) to start conducting and allow current to flow from IN to OUT. When EN/UVLO is held low (< VUVLO), the internal power path is turned off. After a successful start-up sequence, the device now actively monitors its load current and input voltage, and controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (ILIM) is not exceeded and overvoltage spikes are either safely clamped to the selected threshold voltage (VOVC) or cut-off after they cross the user-adjustable overvoltage lockout threshold (VOVLO). The device also provides fast protection against severe overcurrent during short-circuit events. This feature keeps the system safe from harmful levels of voltage and current. At the same time, a user-adjustable overcurrent blanking timer allows the system to pass moderate transient peaks in the load current profile without tripping the eFuse. This action ensures a robust protection solution against real faults which is also immune to transients, thereby ensuring maximum system uptime. The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device temperature (TJ) exceeds the recommended operating conditions. 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 8.2 Functional Block Diagram FFT TPS25 970x - + 354 mV Temp S ense and Overtemperature protection IN TSD 6 OUT 7 DVDT 9 ILM 10 ITIMER 8 GND 5 INRUSH_DONE HFE T CP 2.8 V + 2.45 V; UVPb GHI - 2.54 V9 - + A FFT A/A GHI - 2 1.2 V9 HFE T Control 1.1 V; 1.2 V9 1x + SD INRUSH_DONE SWEN ITIMER_EXPIRED 1.1 V; + 0.75 V; - OC UVLOb - 1 2x + Curren t Limit Amplifier + EN/UV LO - SC OVL Ob + OVL O Sho rt Detect ILM Pin Sh ort RETRY # TSD 1.05 V; 2.57 V R S /Q Q 110 ms TIMER # 13.8 kŸ SD UVPb RETRY # + ITIMER_EXPIRED FLT - ILM Pin Sh ort OC ITIMER_EXPIRED A 4 3 FLT DNC # Not appl icab le to Latch-off variants (TPS 25970L ) Figure 8-1. TPS25970x Block Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 19 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 FFT TPS25 972x - + 354 mV Temp S ense and Overtemperature protection IN TSD 5 6 OUT 7 DVDT INRUSH_DONE HFE T CP + - 2.45 V; A UVPb GHI + OVC GHI OVC Threshold Sele ct 2 A/A FFT OVCSE L - + 2.54 V9 2.8 V - SC HFE T Control + Curren t Limit Amplifier + 1 1.2 V9 1x + SWEN SD INRUSH_DONE ITIMER_EXPIRED 1.1 V; + 0.75 V; - OC UVLOb 9 ILM 10 ITIMER 8 GND - EN/UV LO 2x Sho rt Detect ILM Pin Sh ort 1.05 V; 2.57 V PG_ int SD UVPb RETRY # R + ITIMER_EXPIRED /Q - PG_ int TSD S Q 13.8 kŸ OVC INRUSH_DONE FLT SD OC PG_ int UVPb ILM Pin Sh ort A R S Q /Q + 110 ms TIMER # - RETRY # 1.2 V9 1.1 V; 3 4 PG PGTH # Not appl icab le to Latch-off variants (TPS 25972L ) Figure 8-2. TPS25972x Block Diagram 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 FFT TPS25 974x - + 354 mV Temp S ense and Overtemperature protection IN TSD 6 OUT 7 DVDT 9 ILM 10 ITIMER 8 GND 5 INRUSH_DONE HFE T CP 2.8 V + 2.45 V; UVPb GHI - 2.54 V9 - + A A/A FFT GHI - OVL O 2 1.2 V9 - SC OVL Ob HFE T Control + + 1.1 V; Curren t Limit Amplifier + 1 1.2 V9 - OC UVLOb 1x + - EN/UV LO 2x 1.1 V; SWEN Sho rt Detect INRUSH_DONE SD - ILM Pin Sh ort + 0.75 V; PG_ int 1.05 V; 2.57 V INRUSH_DONE TSD ILM Pin Sh ort 13.8 kŸ SD UVPb RETRY # + R /Q ITIMER_EXPIRED OVL Ob PG_ int S Q FLT - SD PG_ int UVPb ITIMER_EXPIRED OC A R S Q /Q + 110 ms TIMER # - RETRY # 1.2 V9 1.1 V; 3 4 PGTH # Not appl icab le to Latch-off variants (TPS 25974L ) Figure 8-3. TPS25974x Block Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 21 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 8.3 Feature Description The TPS2597xx eFuse is a compact, feature-rich power management device that provides detection, protection, and indication in the event of system faults. 8.3.1 Undervoltage Lockout (UVLO and UVP) The TPS2597xx implements undervoltage protection on IN in case the applied voltage becomes too low for the system or device to properly operate. The undervoltage protection has a default lockout threshold of VUVP which is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the undervoltage protection threshold to be externally adjusted to a user-defined value. Figure 8-4 and Equation 1 show how a resistor divider can be used to set the UVLO set point for a given voltage supply. Power Supply IN R1 EN/UVLO R2 GND Figure 8-4. Adjustable Undervoltage Protection VIN(UV) = VUVLO × (R1 + R2)   R2 (1) 8.3.2 Overvoltage Lockout (OVLO) The TPS25970x and TPS25974x variants allow the user to implement overvoltage lockout to protect the load from input overvoltage conditions. The OVLO comparator on the OVLO pin allows the overvoltage protection threshold to be adjusted to a user-defined value. After the voltage at the OVLO pin crosses the OVLO rising threshold, VOV(R), the device turns off the power to the output. Thereafter, the devices wait for the voltage at the OVLO pin to fall below the OVLO falling threshold, VOV(F) before the output power is turned ON again. The rising and falling thresholds are slightly different to provide hysteresis. Figure 8-5 and Equation 2 show how a resistor divider can be used to set the OVLO set point for a given voltage supply. Power Supply IN R1 OVLO R2 GND Figure 8-5. Adjustable Overvoltage Protection VIN(OV) = VOV × (R1 + R2)   R2 (2) While recovering from a OVLO event, the TPS25970x variants start up with inrush control (dVdt). 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Input O ver vol tage Even t Input O ver vol tage Removed IN 0 OVLO VOV(R) VOV(F) tOVLO 0 OUT dVd t Limite d S tar t-up 0 VFLT FLT 0 Tim e Figure 8-6. TPS25970x Overvoltage Lockout and Recovery While recovering from an OVLO event, the TPS25974x variants start up with inrush control (dVdt). Input O ver vol tage Even t Input O ver vol tage Removed IN 0 OVLO VOV(R) VOV(F) tOVLO 0 OUT dVd t Limite d S tar t-up 0 tPGA tPGD VPG PG 0 Tim e Figure 8-7. TPS25974x Overvoltage Lockout and Recovery 8.3.3 Overvoltage Clamp (OVC) The TPS25972x variants implement a voltage clamp on the output to protect the system in the event of input overvoltage. When the device detects the input has exceeded the overvoltage clamp threshold (VOVC), it quickly responds within tOVC and stops the output from rising further. the device then regulates the HFET linearly to clamp the output voltage below VCLAMP as long as an overvoltage condition is present on the input. If the part stays in clamping state for an extended period of time, there is higher power dissipation inside the part which can eventually lead to thermal shutdown (TSD). After the part shuts down due to TSD fault, it either Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 23 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 stays latched off (TPS25972L variant) or restart automatically after a fixed delay (TPS25972A variant). See Overtemperature Protection (OTP) for more details on device response to overtemperature. Input O ver vol tage Even t IN Input O ver vol tage Removed VOVC Thermal Shu tdo wn Retry Time r E xpir ed (1) 0 tOVC tRST VCL AMP OUT dVd t Limite d S tar t-up 0 tPGA tPGD VPG PG 0 TSD TSDHYS TJ Tim e (1) App lica ble only for TPS259 72A (Auto-retry varian t) Figure 8-8. TPS25972x Overvoltage Response (Auto-Retry) There are three available overvoltage clamp threshold options, which can be configured using the OVCSEL pin. Table 8-1. TPS25972x Overvoltage Clamp Threshold Selection OVCSEL PIN CONNECTION OVERVOLTAGE CLAMP THRESHOLD Shorted to GND 3.89 V Open 5.76 V Connected to GND through a 390-kΩ resistor 13.88 V 8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection TPS2597xx incorporates four levels of protection against overcurrent: 1. 2. 3. 4. Adjustable slew rate (dVdt) for inrush current control Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short-circuits during steadystate 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors or cause the system power supply to droop leading to unexpected restarts elsewhere in the system or both. The inrush current during turn on is directly proportional to the load capacitance and rising slew rate. Use Equation 3 to find the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT): SR (V/ms) = IINRUSH  mA   COUT  µF (3) A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during turn on. Use Equation 4 to calulate the required CdVdt capacitance to produce a given slew rate. 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 CdVdt  pF = 3300   SR  V/ms (4) The fastest output slew rate is achieved by leaving the dVdt pin open. Note For CdVdt > 10 nF, TI recommends to add a 100-Ω resistor in series with the capacitor on the dVdt pin. 8.3.4.2 Circuit-Breaker The circuit-breaker variants (TPS25974x) respond to output overcurrent conditions by turning off the output after a user-adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the fast-trip threshold (2 × ILIM), the device starts discharging the ITIMER pin capacitor using an internal 2-μA pulldown current. If the load current drops below ILIM before the ITIMER pin capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up to VINT internally and the circuit breaker action is not engaged. This action allows short load transient pulses to pass through the device without tripping the circuit. If the overcurrent condition persists, the CITIMER continues to discharge and after it discharges by ΔVITIMER, the circuit breaker action turns off the HFET immediately. At the same time, the CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent event. This action ensures the full blanking timer interval is provided for every overcurrent event. Use Equation 5 to calculate the RILM value for an overcurrent threshold. RILM  Ω = 5747 ILIM  A (5) Note 1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part breaking the circuit with the slightest amount of loading at the output. 2. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the part shuts down. There is a minimum current (IFLT) which the part allows in this condition before the pin short condition is detected. The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER pin to ground. Use Equation 6 to calculate the CITIMER value needed to set the desired transient overcurrent blanking interval. tITIMER (ms) = ∆ VITIMER (V) × CITIMER (nF)   IITIMER (µA) (6) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 25 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Transient O ve rcu rrent Per sistent Ou tpu t Overload ITIMER expire d 2 x ILIM Circuit-Bre ake r ope rati on IOUT ILIM 0 tITIMER VINT ¨VITIMER ITIMER 0 VIN OUT 0 VPGTH PGTH 0 tPGD VPG PG 0 TSD TSDHYS TJ TJ Tim e Figure 8-9. TPS25974x Overcurrent Response Note 1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay. 2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to ITIMER pin open condition), but increases the device current consumption. This action is not a recommended mode of operation. 3. Increasing the ITIMER cap value extends the overcurrent blanking interval, but it also extends the time needed for the ITIMER cap to recharge up to VINT. If the next overcurrent event occurs before the ITIMER cap is recharged fully, it takes less time to discharge to the ITIMER expiry threshold, thereby providing a shorter blanking interval than intended. After the part shuts down due to a circuit-breaker fault, it either stays latched off (TPS25974L variant) or restart automatically after a fixed delay (TPS25974A variant). 8.3.4.3 Active Current Limiting The active current limit variants (TPS25970x and TPS25972x) respond to output overcurrent conditions by actively limiting the current after a user adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the short-circuit threshold (2 × ILIM), the device starts discharging the ITIMER pin capacitor using an internal 2-μA pulldown current. If the load current drops below the overcurrent threshold before the ITIMER capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up to VINT internally and the current limit action is not 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 engaged. This event allows short load transient pulses to pass through the device without getting current limited. If the overcurrent condition persists, the CITIMER continues to discharge and after it discharges by ΔVITIMER, the current limit starts regulating the HFET to actively limit the current to the set overcurrent threshold (ILIM). At the same time, the CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent event. This event ensures the full blanking timer interval is provided for every overcurrent event. Use Equation 7 to calculate the RILM value for a desired overcurrent threshold. RILM  Ω = 5747 ILIM  A (7) Note 1. Leaving the ILM pin open sets the current limit to nearly zero and results in the part entering current limit with the slightest amount of loading at the output. 2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM). 3. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before the pin short condition is detected. The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER pin to ground. Use Equation 8 to calculate the CITIMER value needed to set the desired transient overcurrent blanking interval. tITIMER (ms) = ∆ VITIMER (V) × CITIMER (nF)   IITIMER (µA) (8) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 27 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Transient O ve rcu rrent Per sistent Ou tpu t Overload ITIMER expire d Overloa d Removed Per sistent Ou tpu t Overload ITIMER expire d Thermal sh utd own 2 x ILIM IOUT tLIM tLIM Curren t limitin g ope rati on Curren t limitin g ope rati on ILIM 0 tITIMER tITIMER VINT ¨VITIMER ITIMER 0 VIN OUT 0 1.2 V PGTH (1) tPGD 0 tPGA tPGD VPG PG (1) 0 VFLT FLT (2) 0 TSD TSDHYS TJ TJ Tim e (1) (2) App lica ble only to TP S2597 2x and TPS2 5974x va riants App lica ble only to TP S2597 0x varian ts Figure 8-10. TPS25970x and TPS25972x Active Current Limit Response Note 1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay. 2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to ITIMER pin open condition), but increases the device current consumption. This action is not a recommended mode of operation. 3. Active current limiting based on RILM is active during start-up for TPS25970x, TPS25972x (active current limit) as well as TPS25974x (circuit-breaker) variants. In case the start-up current exceeds ILIM, the device regulates the current to the set limit. However, during start-up the current limit is engaged without waiting for the ITIMER delay. 4. For the TPS25972x variants, during overvoltage clamp condition, if an overcurrent event occurs, the current limit is engaged without waiting for the ITIMER delay. 5. Increasing the CITIMER value extends the overcurrent blanking interval, but it also extends the time needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before the CITIMER is recharged fully, it takes lesser time to discharge to the ITIMER expiry threshold, thereby providing a shorter blanking interval than intended. During active current limit, the output voltage drops, resulting in increased device power dissipation across the HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned off. After the part shuts down due to TSD fault, it either stays latched off (TPS2597xL variants) or restarts automatically after a fixed delay (TPS2597xA variants). See Overtemperature Protection (OTP) for more details on device response to overtemperature. 28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 8.3.4.4 Short-Circuit Protection During an output short-circuit event, the current through the device increases very rapidly. When a severe overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. The internal fast-trip comparator employs a scalable threshold (ISC) which is equal to 2 × ILIM. This action enables the user to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some low current systems. The device also employs a fixed fast-trip threshold (IFT) to protect fast protection against hard short-circuits during steady state. The fixed fast-trip threshold is higher than the maximum recommended user adjustable scalable fast-trip threshold. After the current exceeds ISC or IFT, the HFET is turned off completely within tFT. Thereafter, the devices tries to turn the HFET back on after a short de-glitch interval (30 μs) in a current limited manner instead of a dVdt limited manner. This action ensures that the HFET has a faster recovery after a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the device stays in current limit causing the junction temperature to rise and eventually enter thermal shutdown. For details on the device response to overtemperature, see Overtemperature Protection (OTP). Transient S evere Overcurrent Per sistent Se vere O vercurr ent Output Ha rd S hort-circuit to g round Thermal Shutdown Thermal Shutdown Overcurren t Remove d Retry Time r E lapsed Sho rt-circuit Removed (3) Retry Time r E lapsed (3) VIN IN 0 IFT tSC tFT tSC 2 x ILIM IOUT ILIM 0 VIN OUT Curren t Limite d Start-up 0 dVd t Limite d Start-up dVd t Limite d Start-up tPGD tPGD tPGD VPG PG tPGA tPGA tPGA (1) 0 VFLT FLT (2) 0 tRST TSD tRST TSDHYS TJ Tim e (1) (2) (3) App lica ble only to TP S2597 2x and TPS2 5974x va riants App lica ble only to TP S2597 0x varian ts App lica ble only to TP S2597 xA varian ts Figure 8-11. TPS2597xx Short-Circuit Response 8.3.5 Analog Load Current Monitor The device allows the system to accurately monitor the output load current by providing an analog current sense output on the ILM pin, which is proportional to the current through the FET. The user can sense the voltage (VILM) across the RILM to get a measure of the output load current. VILM (µV) IOUT (A) = RILM (Ω) × GIMON (µA/A)   (9) The waveform below shows the ILM signal response to a load step at the output. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 29 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 VIN = 12 V, RILM = 715 Ω, IOUT varied dynamically between 0 A and 5.5 A Figure 8-12. Analog Load Current Monitor Response Note The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the parasitic capacitive loading on the ILM pin is < 50 pF for stable operation. 8.3.6 Overtemperature Protection (OTP) The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the temperature exceeds a safe operating level (TSD), thereby protecting the device from damage. The device does not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD – TSDHYS). When the TPS2597xL (latch-off variant) detects thermal overload, it shuts down and remains latched-off until the device is power cycled or re-enabled. When the TPS2597xA (auto-retry variant) detects thermal overload, it remains off until it has cooled down by TSDHYS. Thereafter, the device remains off for an additional delay of tRST after which it automatically retries to turn on if it is still enabled. Table 8-2. Thermal Shutdown DEVICE ENTER TSD TPS2597xL (Latch-Off) TPS2597xA (Auto-Retry) EXIT TSD TJ ≥ TSD TJ < TSD – TSDHYS VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO toggled below VSD(F) TJ ≥ TSD TJ < TSD – TSDHYS VIN cycled to 0 V and then above VUVP(R) or EN/UVLO toggled below VSD(F) or tRST timer expired 8.3.7 Fault Response and Indication (FLT) Table 8-3 summarizes the device response to various fault conditions. Additionally, an active low external fault indication (FLT) pin is available on the TPS25970x variants. Table 8-3. Fault Summary EVENT PROTECTION RESPONSE FAULT LATCHED INTERNALLY FLT PIN STATUS (1) Overtemperature Shutdown Y L Undervoltage (UVP or UVLO) Shutdown N H 30 Submit Document Feedback FLT ASSERTION DELAY(1) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Table 8-3. Fault Summary (continued) PROTECTION RESPONSE FAULT LATCHED INTERNALLY FLT PIN STATUS (1) Shutdown(1) (2) N H Voltage Clamp(2) N N/A N N Y N/A N L EVENT Input Overvoltage Transient Overcurrent (ILIM None < IOUT < 2 × ILIM) Persistent Overcurrent Circuit Breaker(3) Limit(4) FLT ASSERTION DELAY(1) Persistent Overcurrent Current Output Short-Circuit to GND Circuit Breaker followed by Current Limit N H ILM Pin Open (During Steady State) Shutdown N L tITIMER ILM Pin Shorted to GND Shutdown Y L tITIMER (1) (2) (3) (4) tITIMER Applicable to TPS25970x variants only. Applicable to TPS25972x variants only. Applicable to TPS25974x variants only. Applicable to TPS25970x and TPS25972x variants only. Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by pulling the EN/UVLO pin voltage below VSD. This action also releases the FLT pin for the TPS25970x variants and resets the tRST timer for the TPS2597xA (auto-retry) variants. During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This fact is true for both TPS2597xL (latch-off) and TPS2597xA (auto-retry) variants. For TPS2597xA (auto-retry) variants, on expiry of the tRST timer after a fault, the device restarts automatically and the FLT pin is de-asserted (TPS25970A variant). 8.3.8 Power-Good Indication (PG) The TPS25972x and TPS25974x variants provide an active high digital output (PG) which serves as a powergood indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and must be pulled up to an external supply. After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time (tPGA). PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 31 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Overloa d E ve nt Overcurren t blan king timer exp ired Overloa d Removed Device En abled VUVL O(R) EN/UV LO 0 IN Slew rate ( dVdt) con trol led star tup /Inrush cu rrent limiting 0 Acti ve Curren t limiting (1) VIN OUT 0 (2) PGTH VPGTH (R) VPGTH (F) 0 VPG PG (2) tPGD tPGA tPGA 0 VIN dVdt 0 VOUT + 2.8V VHGate 0 tITIMER ILIM IINRU SH IOUT 0 (1) (2) Not app licable to TPS25 974x Not app licable to TPS25 970x Tim e Figure 8-13. TPS25972x, TPS25974x PG Timing Diagram 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Table 8-4. TPS25972x and TPS25974x PG Indication Summary EVENT DEVICE STATUS Undervoltage (UVP or UVLO) PG PIN STATUS PG PIN TOGGLE DELAY OFF L Overvoltage (TPS25972x only) ON (Clamping) H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Overvoltage (TPS25974x only) OFF L tPGD ON H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD ON H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Persistent overload (TPS25972x only) ON (Current Limiting) H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Persistent overload (TPS25974x only) OFF (Circuit-Breaker) L tPGD Output short-circuit to GND H (If PGTH pin voltage > VPGTH(R)) Fast-trip followed by Current Limit L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD ILM pin open OFF L (If PGTH < 1.1 V) tPGD + tITIMER ILM pin shorted to GND OFF L tPGD Overtemperature OFF L tPGD Steady state Transient overcurrent When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition. 8.4 Device Functional Modes The TPS25970x and TPS25974x variants have only one functional mode that applies when operated within the recommended operating conditions. The TPS25972x variants have three different functional modes depending on the OVCSEL pin connection. Table 8-5. TPS25972x Overvoltage Clamp Threshold Selection OVCSEL PIN CONNECTION OVERVOLTAGE CLAMP THRESHOLD Shorted to GND 3.89 V Open 5.76 V Connected to GND through a 390-kΩ resistor 13.88 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 33 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The TPS2597xx is a 2.7-V to 23-V, 7-A eFuse that is typically used for power rail protection applications. The device operates from 2.7 V to 23 V with adjustable overvoltage and undervoltage protection. The device provides ability to control inrush current and protection against overcurrent conditions. The device can be used in a variety of systems such as adapter input protection, server, PC motherboard, add-on cards, enterprise storage – RAID/HBA/SAN/eSSD, retail point-of-sale terminals, smartphones, and tablets. The design procedure explained in the subsequent sections can be used to select the supporting component values based on the application requirement. Additionally, a spreadsheet design tool, TPS2597xx Design Calculator, is available in the web product folder. 9.1.1 Single Device, Self-Controlled VIN = 2.7 to 23 V IN VOUT OUT VIN = 2.7 to 23 V IN VOUT OUT COUT COUT VLOGIC EN/UV LO PGTH EN/UV LO TPS25 972x TPS25 970x OVL O OVCSE L FLT ITIMER dVd t VLOGIC GND PG ITIMER ILM VIN = 2.7 to 23 V IN dVd t GND ILM VOUT OUT COUT PGTH EN/UV LO VLOGIC TPS25 974x OVL O PG ITIMER dVd t GND ILM Figure 9-1. Single Device, Self-Controlled Other variations: In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the device. ILM pin can be connected to the MCU ADC input for current monitoring purpose. 34 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Note TI recommends to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. For the TPS25972x and TPS25974x variants, either VIN or VOUT can be used to drive the PGTH resistor divider depending on which supply must be monitored for Power Good indication. 9.2 Typical Application TPS2597xx can be used for server add-on card input power protection. During overcurrent or short-circuit event at load side, TPS2597xx can quickly respond to this fault event by turning off the device and thus protect the load from damage as well as prevent input supply from drooping. The ITIMER feature allows short duration peak currents to pass through without tripping the eFuse, thereby meeting the transient load current profile of these cards. VIN = 12 V IN VOUT OUT R4 47 k R1 470 k 3.3 V TPS25 974L D1* F PGTH EN/UV LO R5 5.6 k R2 11 k CIN COUT D2* 47 k F OVL O PG ITIMER R3 47 k dVd t GND CITIMER CdVd t 1.3 nF 560 0 p F ILM RILM * Optional circuit components needed for transient protection depending on input and output inductance. Please refer to Transient Protection section for details. Figure 9-2. Server Add-on Card Input Power Protection Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 35 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 9.2.1 Design Requirements Table 9-1. Design Parameters PARAMETER VALUE Input supply voltage (VIN) 12 V Undervoltage threshold (VIN(UV)) 10.8 V Overvoltage threshold (VIN(OV)) 13.2 V Output Power Good threshold (VPG) 11.4 V Maximum continuous current 7A Load transient blanking interval (tITIMER) 1 ms Output capacitance (COUT) 470 μF Output rise time (tR) 20 ms Overcurrent threshold (ILIM) 7.7 A Overcurrent response Circuit breaker Fault response Latch-off 9.2.2 Detailed Design Procedure 9.2.2.1 Device Selection Because the application requires circuit-breaker response to overcurrent with latch-off response after a fault, the TPS25974L variant is selected after referring to the Device Comparison Table. 9.2.2.2 Setting Undervoltage and Overvoltage Thresholds The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2, and R3, whose values can be calculated using Equation 10 and Equation 11: VIN(UV) = VIN(OV) = VUVLO(R) × (R1 + R2 + R3)   R2 + R3 (10) VOV(R) × (R1 + R2 + R3)   R3 (11) Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold. Because R1, R2, and R3 leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current from input power supply VIN. The current drawn by R1, R2, and R3 from the power supply is IR123 = VIN / (R1 + R2 + R3). However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the leakage current expected on the EN/UVLO and OVLO pins. From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA (maximum), VOV(R) = 1.2 V and VUVLO(R) = 1.2 V. From design requirements, VIN(OV) = 13.2 V and VIN(UV) = 10.8 V. To solve the equation, first choose the value of R1 = 470 kΩ and use the above equations to solve for R2 = 10.7 kΩ and R3 = 48 kΩ. Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ. 9.2.2.3 Setting Output Voltage Rise Time (tR) For a successful design, the junction temperature of the device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush current limit required with system capacitance to avoid thermal shutdown during start-up. The slew rate (SR) needed to achieve the desired output rise time can be calculated as: SR (V/ms) = 36 VIN  V 12 V = 20 ms = 0.6 V/ms tR  ms Submit Document Feedback (12) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 The CdVdt needed to achieve this slew rate can be calculated as: CdVdt  pF = 3300 = 3300 0.6 = 5500 pF SR  V/ms (13) Choose the nearest standard capacitor value as 5600 pF. For this slew rate, the inrush current can be calculated as: IINRUSH  mA = SR (V/ms) × COUT  µF = 0.6 × 470 = 282 mA  (14) The average power dissipation inside the part during inrush can be calculated as: PDINRUSH  W = IINRUSH  A  × VIN  V = 0.282 × 12 = 1.69 W 2 2 (15) For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time tR to avoid start-up failure. Figure 9-3 shows the thermal shutdown limit. For 1.69 W of power, the shutdown time is more than 10 s, which is very large as compared to tR = 20 ms. Therefore, it is safe to use 20 ms as the start-up time for this application. 10000 5000 Time to TSD (ms) 2000 1000 500 200 100 50 20 10 5 2 1 0.5 0.2 0.1 0 20 40 60 80 PD (W) 100 120 140 Figure 9-3. Thermal Shut-Down Plot During Inrush Note In some systems, there can be active load circuits (for example, DC-DC converters) with low turnon threshold voltages which can start drawing power before the eFuse has completed the inrush sequence. This action can cause additional power dissipation inside the eFuse during start-up and can lead to thermal shutdown. TI recommends to use the Power Good (PG) pin of the eFuse to enable and disable the load circuit. This action ensures that the load is turned on only when the eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal shutdown. 9.2.2.4 Setting Power-Good Assertion Threshold The Power Good assertion threshold can be set using the resistors R4 and R5 connected to the PGTH pin, whose values can be calculated as: VPG = VPGTH(R) × (R4 + R5)   R5 (16) Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize the leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5). However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH leakage current expected. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 37 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 From the device electrical specifications, PGTH leakage current is 1 μA (maximum), VPGTH(R) = 1.2 V and from design requirements, VPG = 11.4 V. To solve the equation, first choose the value of R4 = 47 kΩ and calculate R5 = 5.52 kΩ. Choose the nearest 1% standard resistor value as R5 = 5.6 kΩ. 9.2.2.5 Setting Overcurrent Threshold (ILIM) The overcurrent protection (Circuit Breaker) threshold can be set using the RILM resistor whose value can be calculated as: RILM  Ω = 5747 = 5747 7.7 A = 746.4 Ω ILIM  A (17) Choose nearest 1% standard resistor value as 715 Ω. 9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER) The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as: CITIMER (nF) = tITIMER (ms) ×  IITIMER (µA)  = 1 × 2 1.52   = 1.32 nF ∆ VITIMER (V) (18) Choose nearest standard capacitor value as 1.3 nF. 9.2.3 Application Curves Figure 9-4. Power Up Figure 9-5. Transient Overload Figure 9-6. Circuit Breaker Response 9.3 Parallel Operation Applications that need higher steady current can use two TPS25974x devices connected in parallel as shown in Figure 9-7. In this configuration, the first device turns on initially to provide the inrush current control. The second device is held in an OFF state by driving its EN/UVLO pin low using the PG signal of the first device. After the inrush sequence is complete, the first device asserts its PG pin high and turns on the second device. The second device asserts its PG signal to indicate when it has turned on fully, thereby indicating to the system that the parallel combination is ready to deliver the full steady state current. 38 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 After in steady state, both devices share current nearly equally. There can be a slight skew in the currents depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch. IN OUT VLOGIC EN/UV LO TPS25 974x PGTH PG OVL O ITIMER dVd t VIN = 2.7 to 23 V GND ILM VOUT C OUT IN OUT EN/UV LO TPS25 974x PGTH PG To d ownstrea m ena ble OVL O ITIMER dVd t GND ILM Figure 9-7. Two Devices Connected in Parallel for Higher Steady State Current Capability The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady state. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 39 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 Figure 9-8. Parallel Devices Sequencing During Start-Up Figure 9-9. Parallel Devices Load Current During Steady State and Overload 9.4 Power Supply Recommendations The TPS2597xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 23 V. TI recommends an input ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from the device. The power supply must be rated higher than the set current limit to avoid voltage droops during overcurrent and short-circuit conditions. 9.4.1 Transient Protection In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include: • • • • • Minimize lead length and inductance into and out of the device. Use a large PCB GND plane. Connect a Schottky diode from the OUT pin ground to absorb negative spikes. Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device. Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor voltage rating must be at least twice the input supply voltage to be able to withstand the positive voltage excursion during inductive ringing. Use Equation 19 to estimate the approximate value of input capacitance: 40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 LIN VSPIKE(Absolute)  = VIN + ILOAD ×  CIN (19) where • – VIN is the nominal supply voltage. – ILOAD is the load current. – LIN equals the effective inductance seen looking into the source. – CIN is the capacitance present at the input. Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple to the internal control circuits and cause unexpected behavior. Figure 9-10 shows the circuit implementation with optional protection components. VOUT VIN = 2.7 to 23 V IN OUT R1 D2 COUT CLOAD EN/UV LO TPS25 970x R2 D1 CIN OVL O FLT ITIMER R3 CITIMER dVd t GND ILM CDVD T RILM Figure 9-10. Circuit Implementation With Optional Protection Components 9.4.2 Output Short-Circuit Measurements It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in results: • • • • • • • Source bypassing Input leads Circuit layout Component selection Output shorting method Relative location of the short Instrumentation The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like those in this data sheet because every setup is different. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 41 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 9.5 Layout 9.5.1 Layout Guidelines • • • • • • • • • 42 For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN terminal and GND terminal. The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current. The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection. The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential to achieve the best on-resistance and current sense accuracy. Locate the following support components close to their connection pins: – RILM – CdVdT – CITIMER – Resistors for the EN/UVLO, OVLO/OVCSEL, and PGTH pins Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval and soft start timing. It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have any coupling to switching signals on the board. Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals. Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin, and the GND terminal of the IC. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 9.5.2 Layout Example Inner GND layer Top Power layer 7 OUT 5 IN 4 2 1 IN 6 3 OUT 8 9 10 Bottom Power layer Figure 9-11. Layout Example - Single TPS25974x With PGTH Referred to OUT Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 43 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Device Support 10.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 10.2 Documentation Support 10.2.1 Related Documentation For related documentation see the following: • Texas Instruments, TPS2597EVM eFuse Evaluation Board user's guide • Texas Instruments, TPS2597xx Design Calculator 10.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.5 Trademarks HotRod™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 10.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.7 Glossary TI Glossary 44 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 TPS2597 www.ti.com SLVSGG5C – NOVEMBER 2021 – REVISED APRIL 2023 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS2597 45 PACKAGE OPTION ADDENDUM www.ti.com 15-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS25970ARPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2KNH Samples TPS25970LRPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2KOH Samples TPS25972ARPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2KPH Samples TPS25972LRPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2KQH Samples TPS25974ARPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2KRH Samples TPS25974LRPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2KSH Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of