TPS274160
TPS274160
SLVSF05A – MAY 2020 – REVISED NOVEMBER
2020
SLVSF05A – MAY 2020 – REVISED NOVEMBER 2020
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TPS274160x 160-mΩ Quad-Channel Smart High-Side Switch
1 Features
3 Description
•
•
The TPS274160 device is a smart high-side switch
with four integrated 160-mΩ NMOS power FETs and a
chargepump to drive the gates. The device offers
robust protection and diagnostic features to drive
various loads (inductive, capacitive, and resistive)
such as low wattage bulbs, LEDs, relays, solenoids,
heaters, and sub-modules. The part enables flexible,
multi-channel output configurations through paralleling
channels and is in a very small WQFN package to
enable usage in space constrained applications.
•
•
•
•
•
•
Quad-channel 160-mΩ smart high-side switch
Wide DC operating voltage range: 5 V to 36 V
– 50-V absolute maximum voltage
Accurate adjustable current limiting (250 mA to 4
A)
Intelligent diagnostic features
– TPS274160A: Open-drain fault output
– TPS274160B: Analog current sense
– Open-load or short to supply detection in the
off-state
Robust protection features
– Short-circuit protection
– Inductive load flyback clamp
– Undervoltage lockout (UVLO) protection
– Loss of GND protection
Excellent ESD protection on VS and OUT pins
– ±8/±15 kV IEC 61000-4-2 ESD contact/air
discharge
Available in small and 28-pin leadless QFN
packages
Functional Safety-Capable
– Documentation available to aid functional safety
system design
The device is protected against short circuit events
and over-temperature events, safely shutting off the
output during fault events. The device also
implements an external adjustable current limiting
feature. This feature improves the reliability of the
system by reducing inrush current when driving large
capacitive loads and minimizing overload current
thereby eliminating system supply brown out
condition.
The device also integrates diagnostic features like
output current monitoring (version B) and open load
detection to enable improved intelligence in modules
and to enable predictive maintenance functionality.
Device Information
2 Applications
•
•
•
•
PART NUMBER
TPS274160A
Digital output modules
Standalone remote I/O
Motor drives
Solenoid or valve drive
5-V/24-V
Backplane
Power
Input
Protection
(e-Fuse)
TPS274160B
(1)
TPS274160
VOUT
MON
4 mm x 5 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
Charge
Pump
Overcurrent Is Clamped
at the Set Value of 1 A.
Vds
Clamp
Gate
drive
WQFN (28)
BODY SIZE
Optional 5-V/24-V Field
Power
Input
Protection
(e-Fuse/
V+
RPP)
LDO or
DC/DC
3.3/5V
ISO
DC/DC
Power
PACKAGE(1)
VOUT 1
A0
Bus
ASIC
MCU
Digital
Isolation
4
DeSerializer
4 EN
Enable
and
Fault
VOUT 2
Current Limit &
Thermal
Protection
A1
VOUT 3
A2
VOUT 4
4 Serializer
4 ST
A3
Current
Sense/
FAULT
GND
VIN
VOUT
To Additional
Channels
TPS274160
GND
4
A12
A15
GND
Application Example
Driving a Capacitive Load With Adjustable Current
Limit
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLVSF05A – MAY 2020 – REVISED NOVEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Switching Characteristics ...........................................8
7.7 Typical Characteristics.............................................. 10
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................26
9 Application and Implementation.................................. 27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 28
9.3 Capacitive Load Drive and Application Curves.........28
10 Power Supply Recommendations..............................29
11 Layout........................................................................... 30
11.1 Layout Guidelines................................................... 30
11.2 Layout Examples.....................................................30
12 Device and Documentation Support..........................31
12.1 Receiving Notification of Documentation Updates..31
12.2 Support Resources................................................. 31
12.3 Trademarks............................................................. 31
12.4 Electrostatic Discharge Caution..............................31
12.5 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
Changes from Revision * (May 2020) to Revision A (November 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Changed data sheet status from "Advance Information" to "Production Data"...................................................1
2
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5 Device Comparison Table
PART NO.
FAULT REPORTING MODE
TPS274160A
Open-drain digital output
TPS274160B
Current-sense analog output
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VS
SEL
4
19
VS
VS
FAULT
5
18
VS
VS
CS
6
17
VS
16
NC
CL
7
16
NC
15
OUT3
NC
8
15
OUT3
19
ST3
5
18
ST4
6
17
CL
7
NC
8
GND
OUT4
14
14
13
13
12
12
11
11
10
10
9
9
OUT3
PowerPad
TM
OUT3
4
OUT4
OUT1
OUT2
ST2
NC
OUT4
OUT1
OUT2
SEH
VS
20
OUT4
OUT1
VS
20
3
OUT2
DIAG_EN
GND
OUT1
NC
3
ST1
DIAG_EN
GND
EN4
EN4
THER
EN1
OUT2
21
21
GND
EN2
22
2
22
2
THER
EN1
23
23
24
24
25
25
26
26
27
1
1
PowerPad
27
28
EN3
EN3
TM
28
EN2
6 Pin Configuration and Functions
NC – No internal connection
NC – No internal connection
Figure 6-1. RLH Package 28-Pin WQFN With
Exposed Thermal Pad TPS274160A Top View
Figure 6-2. RLH Package 28-Pin WQFN With
Exposed Thermal Pad TPS274160B Top View
Table 6-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
Version A
Version B
CL
7
7
O
Adjustable current limit. Connect to device GND if external current limit is not
used.
CS
—
6
O
Current-sense output.
DIAG_EN
11
11
I
Enable-disable pin for diagnostics; internal pulldown.
—
5
O
Global fault report with open-drain structure, ORed logic for quad-channel fault
conditions.
GND
9,26
9, 26
—
Ground pin.
EN1
27
27
I
Input control for channel 1 activation; internal pulldown.
EN2
28
28
I
Input control for channel 2 activation; internal pulldown.
EN3
1
1
I
Input control for channel 3 activation; internal pulldown.
Input control for channel 4 activation; internal pulldown.
FAULT
4
TPS274160
EN4
2
2
I
NC
8, 21, 16
8, 21, 16
—
No internal connection.
ST1
3
—
O
Open-drain diagnostic status output for channel 1.
ST2
4
—
O
Open-drain diagnostic status output for channel 2.
ST3
5
—
O
Open-drain diagnostic status output for channel 3.
ST4
6
—
O
Open-drain diagnostic status output for channel 4.
SEH
—
3
I
CS channel-selection high bit; internal pulldown.
SEL
—
4
I
CS channel-selection low bit; internal pulldown.
THER
10
10
I
Thermal shutdown behavior control, latch off or auto-retry; internal pulldown.
OUT1
24, 25
24, 25
O
Output of the channel 1 high side-switch, connect to the load.
OUT2
22, 23
22, 23
O
Output of the channel 2 high side-switch, connect to the load.
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Table 6-1. Pin Functions (continued)
PIN
NAME
OUT3
OUT4
VS
TPS274160
I/O
DESCRIPTION
Version A
Version B
14, 15
14, 15
O
Output of the channel 3 high side-switch, connect to the load.
12, 13
12, 13
O
Output of the channel 4 high side-switch, connect to the load.
I
Power supply.
17, 18, 19, 20 17, 18, 19, 20
Thermal
pad
—
—
—
Connect to device GND or leave floating
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Input Voltage on Supply pin
(3)
Reverse polarity voltage (4)
Current on GND pin
MAX
50
V
250
mA
–36
t < 2 minutes
–100
UNIT
V
Voltage on ENx, DIAG_EN, SEL, SEH, and THER pins
–0.3
7
V
Current on ENx, DIAG_EN, SEL, SEH, and THER pins
–10
—
mA
Voltage on STx or FAULT pins
–0.3
7
V
Current on STx or FAULT pins
–30
10
mA
Voltage on CS pin
–2.7
7
V
Current on CS pin
—
30
mA
Voltage on CL pin
–0.3
7
V
Current on CL pin
—
6
mA
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to GND.
Maximum voltage including long transients < 400 ms.
Reverse polarity condition:time t < 180s, reverse current < IR(2), ENx = 0 V, GND pin 1-kΩ resistor in parallel with diode.
7.2 ESD Ratings
VALUE
UNIT
V(ESD1)
Electrostatic
discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
All pins except VS and
VOUTx
±2000
V
V(ESD2)
Electrostatic
discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
VS and VOUTx with respect
to GND
±5000
V
V(ESD3)
Electrostatic
discharge
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
All pins
±750
V
V(ESD4)
Electrostatic
discharge
Contact/Air discharge, per IEC 61000-4-2 (3)
VS, OUTx
±8/±15
kV
V(surge)
Transient surge
Surge protection with 42 Ω, per IEC 61000-4-5;
1.2/50 μs (3)
VS, OUTx
±1000
V
(1)
(2)
(3)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested with the application circuit and supply voltage of 24 V DC and always ON, EN Inputs High → Output High (ON)
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VVS
MIN
MAX
Continuous DC Supply operating voltage (1)
5
36
V
Voltage on ENx, DIAG EN, SEL, SEH, and THER pins
0
5
V
Voltage on ST and FAULT pins
0
5
V
0
1.35
A
–40
125
°C
Inom
Nominal DC load current per channel (all channels on)
TA
Operating ambient temperature range
(1)
Transients up to the absolute maximum is allowed
UNIT
7.4 Thermal Information
TPS274160
THERMAL
METRIC(1)
RLH(QFN)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
31.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.3
°C/W
RθJB
Junction-to-board thermal resistance
9.6
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
9.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
(5 V ≤ Vs ≤ 36 V; −40°C ≤ TJ ≤ 125°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
VVS(uvr)
Undervoltage turnon
VS voltage rising,VVS > VVS(uvr), device turns on.
VVS(uvf)
Undervoltage shutdown
VS voltage falling, VVS < VVS(uvf) device shuts off.
VVS(uv,hys)
Undervoltage shutdown,
hysteresis
Iqd
Device quiescent current,
diagnostics enabled
Ioff
Standby current
MIN
MAX
UNIT
3.5
3.7
4
V
3
3.2
3.4
V
0.5
V
VVS < 30 V, ENx = 5 V, DIAG_EN = H/L, Ioutx = 0 A,
current limit = 2 A, all channels on
6.2
VVS < 30 V, ENx = DIAG_EN = OUTx = THER = 0 V,
TJ = 25°C
1.4
VVS < 30 V, ENx = DIAG_EN = OUTx = THER = 0 V,
TJ = 125°C
5
5
mA
15
ms
0.5
µA
8
µA
Ioff(diag)
Standby current with diagnostic
enabled
VVS < 30 V, ENx = 0 V, DIAG_EN = 5 V, VVS – VOUTx> V
ol(off), not in open-load mode
toff(deg)
Standby mode deglitch time(1)
EN from high to low, if elapsed time > toff(deg), the
device enters into standby mode.
Iout(leak)
Output leakage current in off-state
12.5
VVS < 30 V, ENx = DIAG_EN = OUTx = 0, TJ = 25°C
VVS < 30 V, ENx = DIAG_EN = OUTx = 0, TJ < 125°C
VVS ≥ 5V, TJ = 25°C
rDS(on)
On-state resistance
ΔrDS(on)
Percentage Difference in On-state
resistance between channels (r
VVS ≥ 5V, TJ = 25°C
(1)
DS(on)CHx - rDS(on)CHy )
Icl(int)
Internal current limit
Icl(TSD)
Current limit during thermal
shutdown
160
VVS ≥ 5 V, TJ = 125°C
260
Internal current limit value, CL pin connected to GND
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8
6.5
External current limit value under thermal shutdown.
The percentage of the external current limit setting
value
mA
µA
10
Internal current limit value under thermal shutdown
6
TYP
mΩ
6
%
14
A
A
70%
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7.5 Electrical Characteristics (continued)
(5 V ≤ Vs ≤ 36 V; −40°C ≤ TJ ≤ 125°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vds(clamp )
Source-to-drain body diode
voltage
VF
Drain−source diode voltage
EN = 0, Iout = −0.15 A.
IR(1)
Continuous reverse current from
source to drain
t < 60 s, VVS = 24 V, ENx = 0 V, TJ = 25°C, single
channel reversed current to supply
2.5
A
IR(2)
Continuous reverse current from
source to drain
t < 60 s, VVS = 24 V, ENx = 0 V, GND pin 1-kΩ resistor
in parallel with diode. TJ = 25°C. Reverse-current
condition, All channels reversed
2.0
A
VIH
Logic high-level voltage
VIL
Logic low-level voltage
R(logic,pd)
Logic-pin pulldown resistor
DIAG_EN VVS = VDIAG_EN=5V
200
R(logic,pd)
Logic-pin pulldown resistor
ENx, SEL, SEH, THER pins, VVS = VENx= VSEL=V
SEH=VTHER=5V
100
Ignd(loss)
Output leakage current under
GND loss condition
VVS = 24 V
Vol(off)
Open load detection threshold
ENx = 0 V, when VVS – VOUTx> Vol(off), duration longer
than tol(off), then open load is detected, off state
1.6
tol(off)
Open-load detection threshold
deglitch time
ENx =0V, when VVS – VOUTx> Vol(off) , duration longer
than tol(off), then open load is detected, off state
300
Iol(off)
Off-state output sink current
50
0.3
0.7
70
V
0.9
V
2
V
0.8
V
275
350
kΩ
175
250
kΩ
20
µA
2.6
V
800
µs
ENx = 0 V, DIAG_EN= 5 V, VVS – VOUTx = 24 V, TJ =
125°C, open load
100
µA
560
VOL(STx)
Status low-output voltage
ISTx = 2 mA, version A only
0.2
V
VOL(FAULT)
Fault low-output voltage
IFAULT = 2 mA, version B only
0.2
V
tcl(deg)
Deglitch time when current limit
occurs(1)
ENx = DIAG_EN = 5 V, the deglitch time from current
limit toggling to FAULT, STx, CS report.
180
µs
TSD
Thermal shutdown threshold
TSD(rst)
Thermal shutdown status reset
threshold
Tsw
80
160
175
°C
155
°C
Thermal swing shutdown
threshold
60
°C
Thys
Hysteresis for resetting the
thermal shutdown or thermal
swing
10
°C
KCS
Current sense ratio (Ver. B only)
300
KCL
Current limit ratio
VCL(th)
Current limit internal threshold
voltage(1) (2)
dKCS / KCS
Current sense accuracy, (ICS × K
CS – IOUT) /IOUT × 100
VVS = 24 V, Ioutx ≥ 5 mA (Version B)
-50
50
%
Current sense accuracy, (ICS × K
– IOUT) /IOUT × 100
VVS = 24 V, Ioutx ≥ 25 mA (Version B)
-10
10
%
Current sense accuracy, (ICS × K
– IOUT) /IOUT × 100
VVS = 24 V, Ioutx ≥ 50 mA (Version B)
-5
5
%
Current sense accuracy, (ICS × K
– IOUT) /IOUT × 100
VVS = 24 V, Ioutx ≥ 100 mA (Version B)
-3
3
%
Current sense accuracy, (ICS × K
– IOUT) /IOUT × 100
VVS = 24 V, Ioutx ≥ 0.5 A (Version B)
-2
2
%
-20
20
%
dKCS / KCS
dKCS / KCS
dKCS / KCS
dKCS / KCS
dKCL / KCL
CS
CS
CS
CS
External current limit accuracy, ( I
OUT – ICL × KCL –) × 100 / ICL × K
2500
0.8
VVS = 24 V, Ilimit ≥ 0.25 A
V
CL
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7.5 Electrical Characteristics (continued)
(5 V ≤ Vs ≤ 36 V; −40°C ≤ TJ ≤ 125°C, unless otherwise specified)
PARAMETER
dKCL / KCL
External current limit accuracy, ( I
OUT – ICL × KCL –) × 100 / ICL × K
TEST CONDITIONS
MIN
VVS = 24 V, 2 A ≤ Ilimit ≤ 7 A
TYP
-15
MAX
15
UNIT
%
CL
VCS(lin)
Current-sense voltage linear
range(1)
IOUTx(lin)
Output-current linear range(1)
VVS ≥ 6.5 V
0
4
5 V ≤ VVS < 6.5 V
0
Vs –
2.5
VVS ≥ 6.5 V, Vcs,lin ≤ 4 V
0
2.2
5 V ≤ VVS < 6.5 V, Vcs,lin ≤ VVS – 2.5 V
0
2.2
4.5
6.5
V
Min(Vs
- 2,
4.5)
6.5
V
VVS ≥ 7 V, fault mode
VCS(H)
Current sense pin output voltage
ICS(H)
Current-sense pin output current
available in fault mode
Vcs = 4.5 V, VVS > 7 V
ICS(leak)
Current-sense leakage current in
disabled mode
DIAG_EN = 0 V, TJ =125ºC
(1)
(2)
5 V ≤ VVS < 7 V, fault mode
15
V
A
mA
0.5
µA
Value specified by design, not subject to production test.
Vcl,th tolerance is included in the dKCL / KCL tolerance.
7.6 Switching Characteristics
PARAMETER
8
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td,on
Turnon delay time
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, IN rising
edge to 10% of Voutx
20
50
90
µs
td,off
Turnoff delay time
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, IN falling
edge to 90% of Voutx
20
50
90
µs
td,rise
Channel turnon time
VS = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A 50% of
EN to 90% of VOUT
90
120
150
µs
td,fall
Channel Turnoff time
VS = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A 50% of
EN to 10% of VOUT
90
120
150
µs
dV/dton
Turnon slew rate
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, Voutx
from 10% to 90%
0.1
0.3
0.55
V/µs
dV/dtoff
Turnoff slew rate
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, Voutx
from 90% to 10%
0.1
0.3
0.55
V/µs
td,match
td,rise – td,fall
Vs = 24 V, Iload= 0.5A. td, rise is the IN rising edge
to Vout = 90%.
td, fall is the IN falling edge to Vout = 10%.
–50
tcs,off1
CS settling time from DIAG_EN
disabled
tcs,on1
50
µs
Vs = 24 V, ENx = 5 V, Ioutx = 0.5 A. current limit =
2 A. DIAG_EN falling edge to 10% of Vcs.
20
µs
CS settling time from DIAG_EN
enabled
Vs = 24 V, ENx = 5 V, Ioutx = 0.5 A. current limit is
2A. DIAG_EN rising edge to 90% of Vcs.
20
µs
tcs,off2
CS settling time from IN falling edge
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A. current
limit = 2 A. EN falling edge to 10% of Vcs
100
µs
tcs,on2
CS settling time from IN rising edge
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A. current
limit = 2 A. EN rising edge to 90% of Vcs
150
µs
tSEx
Multi-sense transition delay from
channel to channel
DIAG_EN = 5 V, current sense output delay when
multi-sense pins SEL and SEH transition from
channel to channel
50
µs
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td,rise
td,fall
V_ENx
90%
V_OUTx
90%
10%
10%
td,on dV/dtoff
td,on dV/dton
Figure 7-1. Output Delay Characteristics
V_ENx
Iout
V_DIAG_EN
V_CS
tcs,on2
tcs,off1
tcs,off2
tcs,on1
Figure 7-2. CS Delay Characteristics
Open Load
V_ENx
Vcs,H
V_CS
V_STx, V_FLT
tol,off
Figure 7-3. Open-Load Blanking-Time Characteristics
SEH
SEL
tSEx
VCS
VCS(CH 2)
VCS(CH 1)
Figure 7-4. Multi-Sense Transition Delay
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1.6
1.7
1.5
1.6
EN1 High
EN1 Low
EN2 High
EN2 Low
1.4
1.3
DIAG_EN Voltage (V)
ENx Voltage (V)
7.7 Typical Characteristics
EN3 High
EN3 Low
EN4 High
EN4 Low
1.2
1.1
DIAG_EN High
DIAG_EN Low
1.5
1.4
1.3
1.2
1.1
1
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
1
-40
140
-20
1.5
140
D002
OUT`1
OUT2
OUT3
OUT4
0.75
Diode Voltage (V)
SEx Voltage (V)
120
0.8
1.4
1.3
SEx High
SEx Low
1.2
1.1
0.7
0.65
0.6
0.55
1
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
0.5
-40
140
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D004
Figure 7-8. Body-Diode Forward Voltage
0.3
0.25
On-Resistance (:)
64
63.5
63
62.5
62
61.5
61
60.5
60
59.5
59
58.5
58
57.5
-40
-20
D003
Figure 7-7. SEx Voltage Threshold
Clamp Voltagge (V)
20
40
60
80
100
Ambient Temperature (qC)
Figure 7-6. DIAG_EN Voltage Threshold
Figure 7-5. ENx Voltage Threshold
Ch 1
Ch 2
Ch 3
Ch 4
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
Figure 7-9. Drain-to-Source Clamp Voltage
10
0
D001
0.2
0.15
0.1
5V
13 V
24 V
0.05
140
0
-40
-20
D005
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D006
Figure 7-10. Channel-1 FET On-Resistance
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0.3
0.3
0.25
0.25
On-Resistance (:)
On-Resistance (:)
7.7 Typical Characteristics (continued)
0.2
0.15
0.1
5V
13 V
24 V
0.05
0
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
0.2
0.15
0.1
5V
13 V
24 V
0.05
0
-40
140
-20
0
D006
D007
Figure 7-11. Channel-2 FET On-Resistance
20
40
60
80
100
Ambient Temperature (qC)
120
D006
D008
Figure 7-12. Channel-3 FET On-Resistanc
0.3
18
Ch 1
Ch 2
Ch 3
Ch 4
16
Current Sense Ratio (%)
On-Resistance (:)
0.25
0.2
0.15
0.1
5V
13 V
24 V
0.05
0
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
14
12
10
8
6
4
2
0
-40
140
-20
0
D006
D009
Figure 7-13. Channel-4 FET On-Resistanc
20
40
60
80
100
Ambient Temperature (ºC)
120
140
D010
Figure 7-14. Current-Sense Ratio at 5 mA
1
2.5
Ch 1
Ch 2
Ch 3
Ch 4
2
Ch 1
Ch 2
0.8
Current Sense Ratio (%)
2.25
Current Sense Ratio (%)
140
1.75
1.5
1.25
1
0.75
0.5
Ch 3
Ch 4
0.6
0.4
0.2
0
-0.2
-0.4
0.25
0
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
Figure 7-15. Current-Sense Ratio at 25 mA
140
-0.6
-40
-20
D011
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D012
Figure 7-16. Current-Sense Ratio at 50 mA
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7.7 Typical Characteristics (continued)
1
1
Ch 1
Ch 2
Ch 3
Ch 4
0.6
Ch 1
Ch 2
Ch 3
Ch 4
0.5
Current Sense Ratio (%)
Current Sense Ratio (%)
0.8
0.4
0.2
0
-0.2
-0.4
-0.6
0
-0.5
-1
-1.5
-0.8
-1
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
-2
-40
-20
0
D013
Figure 7-17. Current-Sense Ratio at 100 mA
20
40
60
80
100
Ambient Temperature (qC)
120
140
D014
Figure 7-18. Current-Sense Ratio at 500 mA
1.5
Current Sense Ratio (%)
1
0.5
Ch 1
Ch 2
Ch 3
Ch 4
0
-0.5
-1
-1.5
-2
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D015
Figure 7-19. Current-Sense Ratio at 1 A
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8 Detailed Description
8.1 Overview
The TPS274160 device is a quad-channel smart high-side switch, with an internal charge pump and NMOS
power FETs. The TPS274160 device integrates fault diagnostics and a high-accuracy current-sense feature that
enable intelligent control of the load. The adjustable current-limit function greatly improves the reliability of whole
system. There are two versions of the device. The TPA274160A contains open drain digital output for diagnostic
reporting. The TPS274160B device implements a high accuracy current sense analog output.
TPS274160A device implements the digital fault report with an open-drain structure. When a fault occurs, the
device pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply
level. The digital status of each channel can report individually, or globally by connecting the STx pins together.
The TPS274160B device integrates a high-accuracy current sense circuit that enables precise load current
sensing without the need for on-board calibration. The integrated current mirror (selectable one-channel at a
time) can source a fraction (1 / K (CS) ) of the load current. The mirrored current flows into the CS-pin resistor to
become a voltage signal. K (CS) is a near-constant value across temperature and supply voltage. A wide linear
region from 0 V to 4 V allows a better real-time load-current monitoring. The CS pin can also report a fault with
pullup voltage of VCS(H).
The external high-accuracy current limit allows setting the current-limit value by applications. When overcurrent
occurs, the device improves system reliability by clamping the inrush current effectively. The device can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage. Besides, the device also implements an internal current limit with a fixed value.
The TPS274160 device integrates active clamp between the drain and the source of the FETs. This clamp
ensures that the device is protected during switch off cycle of inductive loads like relays, solenoids and valves.
During the inductive load turn-off, the energy of the power supply and the load are dissipated on the high-side
switch. The device also optimizes the switching-off slew rate when the clamp is active, which helps the system
design by keeping the effects of transient power dissipation and EMI to a minimum.
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8.2 Functional Block Diagram
Internal LDO
Internal Reference
Auxiliary Charge Pump
Temperature Sensor
Gate Driver
and
Charge Pump
ENx
THER
OUT2
OUT3
CS
SEL
OUT1
Protection
and
Diagnostics
Oscillator
SEH
VS
Output
Clamp
Current-Sense
Mux
Current Sense
OUT4
ESD
Protection
Current Limit
CL
FAULT
Current Limit
Reference
2
DIAG_EN
STx
Diagnosis
4
Temperature
Sensor
GND
OTP
8.3 Feature Description
8.3.1 Pin Current and Voltage Conventions
Note that throughout the data sheet, the current directions on the respective pins are as shown by the arrows in
Figure 8-1. All voltages are measured relative to the ground plane.
14
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Ivs
VENx
VSTx,
VFAULT
VDIAG_EN
VCL
VCS
VTHER
VS
IENx
Vvs
ENx
ISTx,
IFAULT
IDIAG_EN
ICL
STX,
FAULT
IOUTx
DIAG_EN
VOUTx
OUTx
CL
ICS
ITHER
CS
THER
ISEx
SEx
VSEx
GND
IGND
VGND
Ground Plane
Figure 8-1. Voltage and Current Conventions
8.3.2 Accurate Current Sense
High-accuracy current sense is implemented in the TPS274160B device. This feature enables continuous
current monitoring and accurate load diagnostic without extensive calibration.
The integrated current mirror sources 1 / K (CS) of the load current, and the mirrored current flows into the
external current sense resistor to become a voltage signal. The current mirror is shared by the four channels. K
(CS) is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device is calibrated accurately during production, so post-calibration is not required. See
Figure 8-2 for more details.
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VSUP
VS
IOUT/K(CS)
IOUT
VCS(H)
FAULT
4x
CS
OUTx
R(CS)
Figure 8-2. Current-Sense Block Diagram
When a fault occurs, the CS pin also works as a fault report with a pullup voltage, V CS(H). See Figure 8-3 for
more details.
V CS
VCS(H)
VCS(lin)
Fault Report
Current Monitor
I OUTx
Normal Operating
On-State: Current Limit, The rmal Fault
Off-State: Open Load or Short to Batte r y
or Reverse Polarity
Figure 8-3. Current-Sense Output-Voltage Curve
Use Equation 1 to calculate R(CS).
R (CS) =
VCS VCS ´ K (CS)
=
I CS
I OUTx
(1)
Take the following points into consideration when calculating R(CS).
•
Ensure VCS is within the current-sense linear region (VCS, IOUTx(lin)) across the full range of the load current.
Check R(CS) with Equation 2.
R (CS) =
•
(2)
In fault mode, ensure ICS is within the source capacity of the CS pin (ICS(H)). Check R(CS) with Equation 3.
R (CS) =
16
VCS VCS(lin)
£
I CS
I CS
VCS VCS(H,min)
³
I CS
I CS(H,min)
(3)
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8.3.3 Adjustable Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is hit, a closed loop activates immediately. The output current is clamped at the
set value, and a fault is reported out. The device heats up due to the high power dissipation on the power FET. If
thermal shutdown occurs, the current limit is set to I CL(TSD) to reduce the power dissipation on the power FET.
See Figure 8-4 for more details.
The device has two current-limit thresholds.
•
•
Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
External adjustable current limit – An external resistor is used to set the current-limit threshold. Use the
Equation 4 to calculate the R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output
current and the current-limit set value. It is constant across the temperature and supply voltage. The external
adjustable current limit allows the flexibility to set the current limit value by applications.
I CL =
VCL(th)
R(CL)
R(CL) =
=
I OUT
K (CL)
VCL(th) ´ K (CL)
I OUT
(4)
VSUP
VS
IOUT/K(CL)
–
Internal Current Limit
+
–
VCL(th)
+
+
IOUT
4x
OUT
External Current Limit
–
VCL(th)
+
CL
Figure 8-4. Current-Limit Block Diargam
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Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected with device GND.
For better protection from a hard short-to-GND condition (when the ENx pins are enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the related channel before the current-limit
closed loop is set up. The fast-trip response time is less than 1 μs, typically. With this fast response, the device
can achieve better inrush current-suppression performance.
8.3.4 Inductive-Load Turn-Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative.
Excessive negative voltage could cause the power FET to break down. To protect the power FET, an internal
clamp between drain and source is implemented, namely VDS(clamp).
VDS(clamp) = VVS - VOUT
(5)
During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The
inductive load energy is dissipated in the high-side switch. Total energy includes the energy of the power supply
(E (VS)) and the energy of the load (E (load)). If resistance is in series with inductance, some of the load energy is
dissipated on the resistance.
E (HSS) = E (VS) + E (load) = E(VS) + E(L) - E(R)
(6)
When an inductive load switches off, E (HSS) causes a high thermal stress on the device.. The upper limit of the
power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation
condition.
VSUP
VDS(clamp)
EN
L
–
OUT
R
GND
+
Figure 8-5. Drain-to-Source Clamping Structure
18
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IN
VVS
VOUT
VDS(clamp)
E(HSS)
IOUT
t(decay)
Figure 8-6. Inductive Load Switching-Off Diagram, note EN pin waveform referred to as IN
From the perspective of the high-side switch, E (HSS) equals the integration value during the demagnetization
period.
E(HSS) =
ò
t(decay )
VDS(clamp) ´ I OUT (t)dt
0
t(decay) =
æ R ´ I OUT(max) + VOUT
L
´ ln ç
ç
R
VOUT
è
E(HSS) = L ´
VVS + VOUT
R2
ö
÷
÷
ø
é
æ R ´ I OUT(max) + VOUT
´ êR ´ I OUT(max) - VOUT ln ç
ç
VOUT
êë
è
öù
÷ú
÷ú
øû
(7)
When R approximately equals 0, E(HSD) can be given simply as:
E (HSS) =
VVS + VOUT
1
2
´ L ´ I OUT(max
)
2
VOUT
(8)
Figure 8-7 is a waveform of the device driving an inductive load. Channel 1 is the EN signal (blue), channel 2 is
the supply voltage V VS (cyan), channel 3 is the output voltage V OUT (magenta), channel 4 is the output current I
OUT(green), and channel M is the measured power dissipation E(HSS).
On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device optimizes the
switch-off slew rate when the clamp is active. As shown in Figure 8-7, the controlled slew rate is around 0.5
V/µs.
The Figure 8-8 plots the maximum inductive energy (EAS) that can be discharged safely by the device a function
of the inductor load current in a single pulse in a single channel at one time. If the stored energy in the inductor
at the particular load current is higher, then an external clamp will be required.
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500
EAS (mJ)
400
300
200
100
0
0
Figure 8-7. Inductive Load Switching-Off Waveform
1
2
3
4
Load Current (A)
5
6
7
D020
Figure 8-8. Maximum Energy Dissipation (EAS)
Allowed TJ_start = 125°C - Single Pulse, One
Channel
Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry
shown in Figure 8-9 to protect the device from repetitive power stressing. The TVS clamp is used to achieve the
fast decay. See Figure 8-9 for more details.
VS
Output
Clamp
OUTx
GND
D
L
TVS
Figure 8-9. Protection With External Circuitry
8.3.5 Fault Detection and Reporting
8.3.5.1 Diagnostic Enable Function
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the MCU can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and ENx low.
8.3.5.2 Multiplexing of Current Sense
For version B, SEL and SEH are two pins to multiplex the shared current-sense function among the four
channels. See Table 8-1 for more details.
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Table 8-1. Diagnosis Configuration Table
DIAG_EN
L
H
ENx
SEH
SEL
CS ACTIVATED
CHANNEL
CS, FAULT, STx
—
—
—
High impedance
H
L
—
0
0
Channel 1
0
1
Channel 2
1
0
Channel 3
1
1
Channel 4
PROTECTIONS AND DIAGNOSTICS
Diagnostics disabled, full protection
Diagnostics disabled, no protection
See Table 8-2
See Table 8-2
8.3.5.3 Fault Table
Table 8-2 applies when the DIAG_EN pin is enabled.
Table 8-2. Fault Table
CONDITIONS
ENx
OUTx THER
L
Normal
L
CRITERION
—
—
STx
CS
FAULT
(VER. A) (VER. B) (VER. B)
FAULT RECOVERY
H
0
H
—
H
—
H
H
—
—
H
In linear
region
Overlaod, short to ground
H
L
—
Current limit
triggered
L
VCS(H)
L
Auto
Open load(1), short to supply,
reverse polarity
L
H
—
VVS – VOUTx <
V(ol,off)
L
VCS(H)
L
Auto
L
Output auto-retry. Fault
recovers when TJ < T(SD,rst) or
when ENx toggles.
L
Thermal shutdown
H
—
TSD triggered
L
VCS(H)
Output latch off. Fault recovers
when ENx toggles.
H
Thermal swing
(1)
H
—
—
TSW triggered
L
VCS(H)
L
Auto
An external pullup is required for open-load detection.
8.3.5.4 STx and FAULT Reporting
For version A, four individual STx pins report the fault conditions, each pin for its respective channel. When a
fault condition occurs, it pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the supply
level of the microcontroller. The digital status of each channel can be reported individually, or globally by
connecting all the STx pins together.
For version B, a global FAULT pin is used to monitor the global fault condition among all the channels. When a
fault condition occurs on any channel, the FAULT pin is pulled down to GND. A 3.3-V or 5-V external pullup is
required to match the supply level of the microcontroller.
After the FAULT report, the microcontroller can check and identify the channel in fault status by multiplexed
current sensing. The CS pin also works as a fault report with an internal pullup voltage, VCS(H).
8.3.6 Full Diagnostics
8.3.6.1 Short-to-GND and Overload Detection
When a channel is on, a short to GND or overload condition causes overcurrent. If the overcurrent triggers either
the internal or external current-limit threshold, the fault condition is reported out. The microcontroller can handle
the overcurrent by turning off the switch. The device heats up if no actions are taken. If a thermal shutdown
occurs, the current limit is I CL(TSD) to keep the power stressing on the power FET to a minimum. The device
automatically recovers when the fault condition is removed.
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8.3.6.2 Open-Load Detection
8.3.6.2.1 Channel On
When a channel is on and an open-load event occurs, it can be detected as an ultra-low V CS voltage at the CS
pin and handled by the micro-controller. The high-accuracy current sense in the low current range, enables the
open-load detection at very low current thresholds. Note that the detection is not reported on the STx or FAULT
pins. The microcontroller must proactively multiplex the SEL and SEH pins to detect the channel-on open-load
fault.
8.3.6.2.2 Channel Off
When a channel is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUTx< V(ol,off)), and the fault is reported out.
There is always a leakage current I (ol,off) present on the output due to internal logic control path or external
humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 20 kΩ.
VSUP
Open-Load Detection in Off State
V(ol,off)
R(PU)
VDS
Load
Figure 8-10. Open-Load Detection in Off-State
8.3.6.3 Short-to-Supply Detection
Short-to-supply has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state. See Table 8-2 for more details.
In the on-state, reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state.
•
•
If VOUTx – VVS < V(F) (body diode forward voltage), no reverse current occurs.
If VOUTx – VVS > V(F), reverse current occurs. The current must be limited to less than IR(1). Setting an ENx pin
high can minimize the power stress on its channel. Also, for external reverse protection, see Reverse-Current
Protection for more details.
8.3.6.4 Input Reverse Polarity Detection
Reverse polarity detection has the same detection mechanism and behavior as open-load detection both in the
on-state and off-state. See Table 8-2 for more details.
In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state. The reverse current must be limited to less than I R(2).
Set the related ENx pin high to keep the power dissipation to a minimum. For external reverse-blocking circuitry,
see Reverse-Current Protection for more details.
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8.3.6.5 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing). Respective temperature sensors are integrated close to each power FET, so the thermal fault is reported
by each channel. This arrangement can help the device keep the cross-channel effect to a minimum when some
channels are in a thermal fault condition.
8.3.6.5.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature T J > T (SD). When thefrmal shutdown occurs, the
respective output turns off. The THER pin is used to configure the behavior after the thermal shutdown occurs.
•
•
When the THER pin is low, thermal shutdown operates in the auto-retry mode. The output automatically
recovers when TJ < T(SD) – T(hys), but the current is limited to ICL(TSD) to avoid repetitive thermal shutdown.
The thermal shutdown fault signal is cleared when TJ < T(SD,rst) or after toggling the related ENx pin.
When the THER pin is high, thermal shutdown operates in the latch mode. The output latches off when
thermal shutdown occurs. When the THER pin goes from high to low, thermal shutdown changes to autoretry mode. The thermal shutdown fault signal is cleared after toggling the related ENx pin.
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T (FET) – T
(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT = T
(FET) – T (Logic) < T (sw) – T (hys). Thermal swing function improves the device reliability when subjected to repetitive
fast thermal variation. As shown in Figure 8-11, multiple thermal swings are triggered before thermal shutdown
occurs.
Thermal Behavior After Short to GND
V THER
V INx
T(SD)
T(SD,rst)
T(hys)
TJ
T(hys)
T(SW)
ICL
IOUTx
ICL(TSD)
VCS(H)
VCS
VFAULT
or VST
Figure 8-11. Thermal Behavior Diagram
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8.3.7 Full Protections
8.3.7.1 UVLO Protection
The device monitors the supply voltage V VS, to prevent unpredicted behaviors when V VS is too low. When V VS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
8.3.7.2 Loss-of-GND Protection
When loss of GND occurs, output is shut down regardless of whether the ENx pin is high or low. The device can
protect against two ground-loss conditions, loss of device GND and loss of module GND.
8.3.7.3 Protection for Loss of Power Supply
When loss of supply occurs, the output is shut down regardless of whether the ENx pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the I/O pins to maintain the inductance current. To protect the system in this condition, TI recommends
two types of external protections: the GND network or the external free-wheeling diode. In addition, the
recommended components per the application diagram needs to be implemented for protection.
VBAT
VS
I/Os
MCU
High-Side Switch
OUT
L
Figure 8-12. Protection for Loss of Power Supply, Method 1
VBAT
VS
I/Os
MCU
High-Side Switch
OUT
L
Figure 8-13. Protection for Loss of Power Supply, Method 2
8.3.7.4 Reverse-Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
•
•
24
When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin. I
R(2) specifies the limit of the reverse current.
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To protect the device, TI recommends two types of external circuitry.
•
Adding a blocking diode. Both the IC and load are protected when in reverse polarity.
VBAT
VS
´
´
OUT
Load
Copyright © 2016, Texas Instruments Incorporated
•
Figure 8-14. Reverse-Current External Protection, Method 1
Adding a GND network. The reverse current through the device GND is blocked. The reverse current through
the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network.
The recommended selection are 1-kΩ resistor in parallel with an > 100-mA diode. If multiple high-side
switches are used, the resistor and diode can be shared among devices. The reverse current protection
diode in the GND network forward voltage should be less than 0.6 V in any circumstances. In addition a
minimum resistance of 4.7 K is recommended on the I/O pins.
VSUP
VS
OUT
Load
Figure 8-15. Reverse-Current External Protection, Method 2
8.3.7.5 MCU I/O Protection
In some severe conditions, such as the high voltage transients or the loss of supply with inductive loads, a
negative pulse occurs on the GND pin This pulse can cause damage on the connected microcontroller. TI
recommends serial resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V
microcontroller and 10-kΩ for a 5-V microcontroller.
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VSUP
I/Os
VS
MCU
High-Side Switch
OUT
Load
Figure 8-16. MCU I/O External Protection
8.4 Device Functional Modes
8.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics.
Note that IN must be low for t > t (off,deg) to enter the standby mode, where t (off,deg) is the standby mode deglitch
time used to avoid false triggering. Figure 8-17 shows a working-mode diagram.
Standby Mode
(ENx low, DIAG low)
DIAG_EN
high to low
DIAG_EN
low to high
Standby mode
with diagnostic
(ENx low, DIAG high)
ENx low to high
ENx high to low and
DIAG_EN high and
t > toff,deg
DIAG_EN low and
ENx high to low and
t > toff,deg
Normal Mode
(ENx high)
ENx low to high
Figure 8-17. Working Modes
26
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Figure 9-1 shows the schematic of a typical application of the . It includes all standard external components. This
section of the datasheet discusses the considerations in implementing commonly required application
functionality.
Supply
Input
CVS
VS
R(ser)
Load
OUT1
EN1, 2, 3, 4
COUT
R(ser)
DIAG_EN
R(ser)
MCU
Load
OUT2
SEH
Legend
COUT
R(ser)
Module GND
SEL
OUT3
5V
Load
Device GND
COUT
R(pu)
R(ser)
OUT4
Load
FAULT
COUT
CS
OPTIONAL for
reverse polarity
protection
CL
R(CS)
THER
GND
DGND
R(CL)
RGND
With the ground protection network, the device ground will be offset relative to the microcontroller ground.
Figure 9-1. System Diagram
Table 9-1. Recommended External Components
COMPONENT
R(ser)
TYPICAL VALUE
PURPOSE
10 kΩ
Protect microcontroller and device I/O pins
R(CS)
1 kΩ
Translate the sense current into sense voltage
CSNS
100 pF - 10 nF
RGND
1 kΩ
DGND
BAS21 Diode
R(CL)
1-kΩ typical
Low-pass filter for the ADC input
Stabilize GND potential during turn-off of inductive load
Protects device during reverse supply condition
Set current limiting value, short to IC GND to set the current limit to the internal
setting.
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Table 9-1. Recommended External Components (continued)
COMPONENT
TYPICAL VALUE
PURPOSE
10 nF to Device GND and
Filtering of voltage transients (for example, surge)
100 nF to module GND
CVS
ZVS
TVS to module GND
COUT
22 nF
Clamp voltage spikes at the input.
Filtering of voltage transients (for example, ESD)
9.2 Typical Application
The following figure shows example of a typical application based on the TPS274160B device. The loads can be
varied and be different on each channel.
Supply
Input
VS
R(ser)
EN1, 2, 3, 4
OUT1
LED Strings,
Small Power Bulbs
OUT2
Solenoids, Valves, Relays
OUT3
Power-Module:
Cameras, Sensors, Displays
OUT4
General Resistive, Capacitive,
Inductive Loads
R(ser)
DIAG_EN
R(ser)
SEH
MCU
R(ser)
SEL
5V
R(ser)
R(pu)
FAULT
CS
CL
R(CS)
GND
THER
R(CL)
Figure 9-2. Typical Application Diagram.
9.2.1 Design Requirements
•
•
•
•
•
•
VVS = 24-V nominal
Load range is from 0.1 A to 1 A for each channel
Current sense for fault monitoring
Expected current-limit value of 2.5 A
Automatic recovery mode when thermal shutdown occurs
Full diagnostics with 5-V MCU
9.2.2 Detailed Design Procedure
To keep the 1-A nominal current in the 0 to 4-V current-sense range, calculate the R (CS) resistor using Equation
9. To achieve better current-sense accuracy, a 1% tolerance or better resistor is preferred.
R (CS) =
VCS VCS ´ K (CS) 4 ´ 300
=
=
= 1200 W
I CS
I OUT
1
(9)
To set the adjustable current limit value at 2.5-A, calculate R(CL) using Equation 10.
R (CL) =
VCL(th) ´ K (CL)
I OUT
=
0.8 ´ 2500
= 800 W
2.5
(10)
TI recommends R(ser) = 10 kΩ for 5-V MCU, and R(pu) = 10 kΩ as the pullup resistor.
9.3 Capacitive Load Drive and Application Curves
In this application example we show the case of driving a large capacitive load at the input of a sensor hub
supply node. The input capacitance is a 2.3-mF capacitor and is charged to a 12-V supply voltage . The nominal
total load current at the node is 0.4 A and the current limit is set to 1 A and chosen to be well in excess of the
28
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peak load current. Figure 9-3 shows a test example of soft-start when driving the large capacitive load. Figure
9-4 shows an expanded waveform of the output current.
Overcurrent Is Clamped
at the Set Value of 1 A.
VS = 12 V
ENx = ↑
Current limit = 1 A
VVS = 12 V
ENx = ↑
Current limit = 1 A
Load current = 0.4
A
CL = 2.3 mF
CH1 = ENx
Load current = 0.4
A
CL = 2.3 mF
CH1 = ENx
CH2 = FAULT
CH3 = output
voltage
CH4 = output
current
CH2 = FAULT
CH3 = output
voltage
CH4 = output
current
Figure 9-3. Driving a Capacitive Load With
Adjustable Current Limit
Figure 9-4. Driving a Capacitive Load, Expanded
Waveform
10 Power Supply Recommendations
The TPS274160 device is designed to operate with a 12-V or 24-V nominal DC supply input. The DC supply
voltage range should be within the range specified in the Recommended Operating Conditions. The device is
also designed to withstand voltage transients beyond this range at the supply input pin up to the absolute
maximum voltage specifications.
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11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, T J must be less than 150°C. The WQFN package has good thermal impedance.
However, the PCB layout is very important. Good PCB design can optimize heat transfer, which is absolutely
essential for the long-term reliability of the device.
•
•
•
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Examples
11.2.1 Without a GND Network
OUT1
OUT1
OUT2
23
EN1
24
GND
25
26
28
27
EN2
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
EN3
1
22
OUT2
EN4
2
21
NC
ST1
3
20
VS
ST2
4
19
VS
ST3
5
ST4
Thermal
Pad
16
NC
NC
8
15
OUT3
9
10
11
12
13
14
OUT3
7
OUT4
CL
OUT4
VS
DIAG_EN
17
THER
VS
6
GND
18
Figure 11-1. Layout Example Without a GND Network
30
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS274160ARLHR
ACTIVE
WQFN
RLH
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
274160A
TPS274160BRLHR
ACTIVE
WQFN
RLH
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
274160B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
