TPS281C30
SLVSGD3A – DECEMBER 2022 – REVISED JUNE 2023
TPS281C30x, 60-V Tolerant, 30-mΩ, Single-Channel Smart High-Side Switch
1 Features
3 Description
•
•
•
•
TPS281C30x is a single channel smart high-side
switch designed to meet the requirements of industrial
control systems. The low RON (30 mΩ) minimizes
device power dissipation, driving a wide range of
output load current up to 6-A DC and the 64-V DC
tolerance improves system robustness.
•
•
•
•
•
•
•
•
•
•
•
•
Wide operating voltage range: 6 V to 36 V
64-V DC tolerance when disabled
Low RON: 30-mΩ typ, 55-mΩ max
Improve system level reliability through adjustable
current limiting
– Version A: 1 A to 5 A (fixed 0.5 A)
– Version B: 2 A to 10 A (fixed 0.5 A)
Accurate current sensing
– ±4% at 1 A in standard sense mode
– ±12.5% at 6 mA in high accuracy sense mode
Integrated inductive discharge clamp > 65 V
Low standby current of < 0.5 µA
Low quiescent current (Iq) of < 1.5 mA
Functional safety capable
Operating junction temperature: –40 to 125°C
Input control: 1.8-V, 3.3-V, and 5-V logic
compatible
Integrated fault sense voltage scaling for ADC
protection
Open-load detection in off-state
Thermal shutdown and swing detection
14-pin thermally-enhanced TSSOP package
20-pin thermally-enhanced QFN package
The device integrates protection features such as
thermal shut down, output clamp, and current limit.
These features improve system robustness during
fault events such as short circuit. TPS281C30x
implements an adjustable current limiting circuit that
improves the reliability of the system by reducing
inrush current when driving large capacitive loads
and minimizing overload current. In order to drive
high inrush current loads such as lamps or fast
charging capacitive loads, TPS281C30x implements
an inrush current time period with a higher level of
allowed current. The device also provides an accurate
load current sense that allows for improved load
diagnostics such as overload and open-load detection
enabling better predictive maintenance.
TPS281C30x is available in a small 14-pin, 4.4-mm
× 5-mm HTSSOP leaded package with 0.65-mm pin
pitch and 20-pin, 5-mm × 5-mm QFN with 0.65-mm
pin pitch minimizing the PCB footprint.
2 Applications
•
•
•
•
Digital output module
Safe torque off (STO)
Holding brake
General resistive, inductive, and capacitive loads
Package Information
TPS281C30x
(1)
PCB SIZE (NOM)
QFN (20)
5.00 mm × 5.00 mm
HTSSOP (14)
5.00 mm × 6.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VS
+24V Field VS
D1*
PACKAGE(1)
PART NUMBER
Cin
Off-State
Open
Load
Detection
EN
Gate
Driver
VOUT
Cout
FAULT
DIAG_EN
OL_ON
SNS
Current Limit
Thermal
Shutdown
D2*
To Inductive,
Capacitive and
Resistive Load
ILIM
Current Sense
GND
RSNS
RILIM
*TVS for Surge Suppression Only
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS281C30
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SLVSGD3A – DECEMBER 2022 – REVISED JUNE 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Thermal Information....................................................6
7.6 Electrical Characteristics.............................................6
7.7 SNS Timing Characteristics...................................... 10
7.8 Switching Characteristics.......................................... 11
7.9 Typical Characteristics.............................................. 13
8 Parameter Measurement Information.......................... 16
9 Detailed Description......................................................18
9.1 Overview................................................................... 18
9.2 Functional Block Diagram......................................... 19
9.3 Device Functional Modes..........................................20
9.4 Feature Description...................................................21
10 Application and Implementation................................ 40
10.1 Application Information........................................... 40
10.2 Typical Application.................................................. 40
10.3 Power Supply Recommendations...........................42
10.4 Layout..................................................................... 42
11 Device and Documentation Support..........................46
11.1 Receiving Notification of Documentation Updates.. 46
11.2 Support Resources................................................. 46
11.3 Trademarks............................................................. 46
11.4 Electrostatic Discharge Caution.............................. 46
11.5 Glossary.................................................................. 46
12 Mechanical, Packaging, and Orderable
Information.................................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2022) to Revision A (June 2023)
Page
• Updated device status from preview to production data ....................................................................................1
2
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SLVSGD3A – DECEMBER 2022 – REVISED JUNE 2023
5 Device Comparison Table
Table 5-1. Device Options
(1)
CURRENT LIMIT RANGE
INTEGRATED CLAMP FOR
INDUCTIVE LOADS
TPS281C30A(1)
1 A to 5 A
Yes
B
TPS281C30B(1)
2 A to 10 A
Yes
C
TPS281C30C(1)
1 A to 5 A
No
D
TPS281C30D(1)
2 A to 10 A
No
DEVICE VERSION
PART NUMBER
A
Devices available in RGW package now. PWP package in previews. Contact TI for additional information.
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6 Pin Configuration and Functions
3
12
VS
FAULT
4
11
NC
OL_ON
5
10
VOUT
SNS
6
9
VOUT
ILIM
7
8
VOUT
Thermal
Pad
19
ILIM
1
18 17 16
15
EN
NC
2
14
NC
VOUT
3
VOUT
4
VOUT
5
Thermal
Pad
8
VS
12
VS
11
VS
NC
NC
9
10
NC
7
13
VS
6
VOUT
Figure 6-1. PWP Package, 14-Pin HTSSOP (Top
View)
20
FAULT
VS
DIAG_EN
DIAG_EN
VS
13
GND
14
2
SNS
1
EN
OL_ON
GND
Figure 6-2. RGW Package, 20-Pin QFN (Top View)
Table 6-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
PWP
RGW
GND
1
18
Power
EN
2
15
I
Input control for channel activation. Internal pulldown.
DIAG_EN
3
16
I
Enable-disable pin for diagnostics and current sensing.
Internal pulldown.
FAULT
4
17
O
Open drain global fault output. Referred to FLT, or fault pin.
OL_ON
5
19
I
Enable-disable pin for higher resolution current sense(Only
available when IOUT< IKsns2_EN). Internal pulldown.
SNS
6
20
O
Analog current output corresponding to load current.
Connect a resistor to GND to convert to voltage.
Adjustable current limit. Connect a resistor to set the
current limit. Optionally short to ground or leave pin floating
to set the current limit to the default internal current limit.
See the electrical characteristics for more information.
ILIM
7
1
O
NC
11
2, 7, 8, 9, 14
N/A
VOUT
Ground of device. Connect to resistor- diode ground
network to have reverse polarity protection.
No internal connection.
8, 9, 10
3, 4, 5, 6
Power
Output of high side switch, connect to load.
VS
12, 13, 14
10, 11, 12, 13
Power
Power supply input.
Pad
Thermal Pad
Pad
—
Thermal pad, internally shorted to ground.
Recommended Connection for Unused Pins
TPS281C30x is designed to provide an enhanced set of diagnostic and protection features. However, if the
system design only allows for a limited number of I/O connections, some pins may be considered as optional.
Table 6-2. Connections for Optional Pins
PIN NAME
CONNECTION IF NOT USED
SNS
Ground through 10-kΩ resistor
ILIM
Float
If the ILIM pin is left floating, the device will be set to the default internal
current-limit threshold. This is considered a fault state for the device.
FAULT
Float
If the FAULT pin is unused, the system cannot read faults from the
output.
Float or ground through RPROT resistor
With DIAG_EN unused, the analog sense, open-load, and short-tosupply diagnostics are not available.
DIAG_EN
OL_ON
4
Ground through RPROT resistor
IMPACT IF NOT USED
Analog sense is not available.
With OL_ON unused, the high accuracy sense mode is not available.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
Continuous supply voltage, VS with respect to IC GND: Version A, B
-0.7
64
V
Continuous supply voltage, VOUT with respect to IC GND: Version A, B
-60
64
V
Transient (< 100 us) voltage at the supply pin, VS with respect to IC GND: Version A, B
-0.7
81
V
Continuous supply voltage, VS with respect to IC GND: Version C, D
-0.7
81
V
Continuous supply voltage, VOUT with respect to IC GND: Version C, D
-60
81
V
Continuous voltage across the VS and VOUT pins (VS - VOUT ): Version C, D
-0.7
81
V
Enable pin voltage, VEN
–1
6
V
OL_ON pin voltage, VOL_ON
–1
6
V
DIAG_EN pin voltage, VDIAG_EN
–1
6
V
Sense pin voltage, VSNS
–1
6
V
FAULT pin voltage, VFAULT
–1
Reverse ground current, IGND
VS < 0 V
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
6
V
–50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
Electrostatic
discharge
VESD
VALUE
UNIT
All pins except VS and VOUT
±2000
V
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
VS and VOUT with respect to
GND
±4000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
All pins
±750
V
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
V(ESD4)
Electrostatic
discharge
Contact discharge, per IEC 61000-4-2 (3)
VS and VOUT
±8000
V
V(surge)
Electrostatic
discharge
Surge protection with 42 Ω, per IEC 61000-4-5;
1.2/50 μs (3)
VS and VOUT
±1000
V
(1)
(2)
(3)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested with application circuit and supply voltage (VS) of 24-V, ENx pins High (Output Enabled) and and EN pins Low (Outputs
Disabled)
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VS_OP_NOM
Nominal supply voltage(1)
voltage(2)
MIN
MAX
6.0
36
UNIT
V
VS_OP_MAX
Extended operating
6.0
48
V
VEN
Enable voltage
–1
5.5
V
VOL_ON
OL_ON pin voltage, VOL_ON
–1
5.5
V
VDIAG_EN
Diagnostic Enable voltage
–1
5.5
V
VFAULT
FAULT pin voltage
–1
5.5
V
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7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted) (1)
VSNS
Sense voltage
TA
Operating free-air temperature
(1)
(2)
MIN
MAX
–1
5.5
UNIT
V
–40
125
°C
All operating voltage conditions are measured with respect to device GND
Device will function within extended operating range, however some parametric values might not apply
7.4 Thermal Information
TPS1HTC30
PWP (HTSSOP)
THERMAL METRIC
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
31.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.8
°C/W
RθJB
Junction-to-board thermal resistance
7.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
7.5 Thermal Information
TPS281C30x
THERMAL METRIC(1) (2)
RGW (QFN)
PWP (HTSSOP)
UNIT
20 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
28.9
31.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.7
23.8
°C/W
RθJB
Junction-to-board thermal resistance
7.5
7.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.5
7.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
1.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the SPRA953 application report.
The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.
7.6 Electrical Characteristics
VS = 6 V to 36 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS SUPPLY VOLTAGE AND CURRENT
ILNOM
ISTBY, VS
ISTBY,
VS_DIAG
IQ, VS
6
Continuous load current
VEN = HI
TAMB = 85°C
Total device standby
current (including
MOSFET) with
diagnostics disabled
VS ≤ 36 V, VEN =
VDIAG_EN = LO, VOUT = 0
V
TJ = -40°C to 85°C
0.25
0.7
µA
Total device standby
current (including
MOSFET) with
diagnostics disabled
VS ≤ 36 V, VEN =
VDIAG_EN = LO, VOUT = 0
V
TJ = 150°C
0.63
6
µA
VS standby current with
diagnostics enabled
VS ≤ 36 V, VEN = LO, VDIAG_EN = HI, VOUT = 0 V
1.2
1.5
mA
0.98
1.3
mA
VS quiescent current with
VEN = HI, VDIAG_EN = LO
diagnostics disabled
IOUT = 0A
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7.6 Electrical Characteristics (continued)
VS = 6 V to 36 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IQ, VS_DIAG
VS quiescent current with
VENx = HI, VDIAG_EN = HI
diagnostics enabled
tSTBY
Standby mode delay time VEN = VDIAG_EN = 0 V to standby
IOUT(OFF)
Output leakage current
VS ≤ 36 V,
VEN = VDIAG_EN = 0 V,
VOUT = 0 V
MIN
IOUT = 0A
TYP
MAX
1.0
1.5
20
TJ = 85°C
TJ = 125°C
UNIT
mA
ms
0.4
µA
0.5
6
µA
VS UNDERVOLTAGE LOCKOUT (UVLO) INPUT
VS,UVLOR
VS undervoltage lockout
rising
Measured with respect to the GND pin of the device
5.0
5.4
5.75
V
VS,UVLOF
VS undervoltage lockout
falling
Measured with respect to the GND pin of the device
4.1
4.5
4.85
V
VS OVERVOLTAGE LOCKOUT (OVLO) INPUT
VS,OVPR
VS overvoltage protection Measured with respect to the GND pin of the device,
rising
VEN = 5V
51
54
57
V
VS,OVPF
VS overvoltage protection Measured with respect to the GND pin of the device,
recovery falling
VEN = 5V
49
52
56
V
VS,OVPH
VS overvoltage protection Measured with respect to the GND pin of the device,
threshold hysteresis
VEN = 5V
tVS,OVP
VS overvoltage protection
Time from triggering the OVP fault to FET turn-off
deglitch time
1.5
V
80
100
140
µs
65
72.5
80
V
48
53
58
V
VDS CLAMP
VDS,Clamp
VDS clamp voltage
Version A, B FET current VS = 24 V
= 10 mA
VS = 6 V
RON CHARACTERISTICS
RON
VS to VOUT Onresistance
B,D = 0.5A ≤ IOUT ≤ 6A,
A,C = 0.5A ≤ IOUT ≤ 3A
VS = 24V
TJ = 25°C
RON(REV)
On-resistance during
reverse polarity
B,D = 0.5A ≤ IOUT ≤ 6A,
A,C = 0.5A ≤ IOUT ≤ 3A
VS = -24V
TJ = -40°C to 125°C
VS to VOUT OnRON_AUXFE resistance
High Accuracy Sense
T
Mode
VS = 24V, IOUT = 40 mA
OL_ON=DIAG_EN=5V
TJ = -40°C to 125°C
29
TJ = 125°C
mΩ
55
mΩ
30
60
mΩ
5.2
12
Ω
50
60
A * kΩ
CURRENT LIMIT CHARACTERISTICS
KCL
Current Limit Ratio
Device Version A, C
RILIM = 10kΩ to 50kΩ
40
KCL
Current Limit Ratio
Device Version B, D
RILIM = 10kΩ to 50kΩ
80
100
120
A * kΩ
Peak current prior to
Device Version A, C
regulation when switch is
Device Version B, D
enabled
RILIM = 10kΩ to 50kΩ
2x ICL
6.5
A
RILIM = 10kΩ to 50kΩ
2x ICL
14
A
12
ms
ILIM_STARTU
P
ILIM_STARTU
P_DELAY
ICL
Peak current delay time
prior to regulation when
switch is enabled
Current Limit level
Device Version A, C
Short circuit condition
RILIM = 50 kΩ
0.8
1
1.2
A
RILIM = 25 kΩ
1.8
2
2.2
A
RILIM = 16.7 kΩ
2.7
3
3.3
A
RILIM = 12.5 kΩ
3.6
4
4.4
A
RILIM = 10 kΩ
4.5
5
5.5
A
0.5
0.8
A
RILIM = GND, open, or
out of range(100kΩ)
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7.6 Electrical Characteristics (continued)
VS = 6 V to 36 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
ICL
Current Limit level
TEST CONDITIONS
Device Version B, D
Short circuit condition
MIN
TYP
MAX
RILIM = 50 kΩ
1.85
2
2.5
A
RILIM = 25 kΩ
3.7
4
4.6
A
RILIM = 16.7 kΩ
5.6
6
6.6
A
RILIM = 12.5 kΩ
7.2
8
8.8
A
9
10
11
A
0.2
0.5
1
A
1.3x ICL
A
2x ICL
A
RILIM = 10 kΩ
RILIM = GND, open, or
out of range(100kΩ)
ICL_LINPK
Overcurrent Limit
Threshold(1)
IILIM_ENPS
Peak current enabling into permanent short
IILIM_ENPS2
Overload condition
Peak current enabling into permanent short
RILIM = 10 kΩ to 50kΩ
RILIM = 10 kΩ
Rising
ILIM Switchover threshold during overvoltage
IILIM_OVP
ILIM Current Limit
threshold during
overvoltage
Overload condition
tIOS
Short circuit response
time
VS = 24V
ILIM Current Limitation
threshold during
overvoltage
Overload condition when RILIM = X, 48V ≥ VVS ≥
VS > 36V(1)
36V
IILIM_OVERV
OLTAGE
2x
RILIM = 10kΩ,
t VIH,DIAG_EN
ISNSleak
ISNS leakage
VDIAG_EN = 5 V, IL = 0 mA
mA
1.3
µA
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7.6 Electrical Characteristics (continued)
VS = 6 V to 36 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
VS_ISNS
TEST CONDITIONS
VS headroom needed for VDIAG_EN = 3.3V
full current sense and
VDIAG_EN = 5V
fault functionality
MIN
TYP
MAX
UNIT
5.8
V
6.5
V
OPEN LOAD DETECTION CHARACTERISTICS
VOL_OFF
OFF state open-load
(OL) detection voltage
VEN = 0 V, VDIAG_EN = 5 V
1.5
2
2.5
V
ROL_OFF
OFF state open-load
(OL) detection internal
pull-up resistor
VEN = 0 V, VDIAG_EN = 5 V
120
150
180
kΩ
tOL_OFF
OFF state open-load
(OL) detection deglitch
time
VEN = 0 V, VDIAG_EN = 5 V, When Vs – VOUT < VOL,
duration longer than tOL. Open load detected.
480
700
µs
tOL_OFF_1
OL_OFF and STB
indication-time from EN
falling
VEN = 5 V to 0 V, VDIAG_EN = 5 V
IOUT = 0 mA, VOUT = Vs - VOL
310
700
µs
tOL_OFF_2
OL and STB indicationtime from DIA_EN rising
VEN = 0 V, VDIAG_EN = 0 V to 5 V
IOUT = 0 mA, VOUT = VS - VOL
700
µs
0.8
V
OL_ON PIN CHARACTERISTICS
VIL, OL_ON
Input voltage low-level
VIH, OL_ON
Input voltage high-level
VIHYS,
Input voltage hysteresis
OL_ON
1.5
V
282
ROL_ON
Internal pulldown resistor
0.7
IIL_OL_ON
Input current low-level
VOL_ON = -1 V
–25
IIL, OL_ON
Input current low-level
VOL_ON = 0.8 V
IIH, OL_ON
Input current high-level
VOL_ON = 5 V
mV
1
1.3
MΩ
0
µA
0.6
.8
1.2
µA
3
5
7
µA
0.8
V
DIAG_EN PIN CHARACTERISTICS
VIL, DIAG_EN Input voltage low-level
No GND Network
VIH, DIAG_EN Input voltage high-level
No GND Network
VIHYS,
DIAG_EN
1.5
Input voltage hysteresis
RDIAG_EN
Internal pulldown resistor
IIL, DIAG_EN
Input current low-level
IIH, DIAG_EN Input current high-level
V
270
200
350
mV
500
kΩ
VDIAG_EN = 0.8 V, VEN=0V
0.8
µA
VDIAG_EN = 5 V
14
µA
EN PIN CHARACTERISTICS
VIL, EN
Input voltage low-level
No GND Network
VIH, EN
Input voltage high-level
No GND Network
VIHYS, EN
Input voltage hysteresis
REN
Internal pulldown resistor
IIL, EN
Input current low-level
VEN = 0.8 V
2.2
µA
IIH, EN
Input current high-level
VEN = 5 V
14
µA
(1)
0.8
1.5
V
280
200
V
350
mV
500
kΩ
The maximum current output under overload condition before current limit regulation
7.7 SNS Timing Characteristics
VS = 6 V to 36 V, TJ = -40°C to 125°C(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
10
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7.7 SNS Timing Characteristics (continued)
VS = 6 V to 36 V, TJ = -40°C to 125°C(unless otherwise noted)
PARAMETER
tSNSION1
TEST CONDITIONS
MIN
TYP
MAX
VEN= 5 V, VDIAG_EN = 0 V to 5
V, VOL_ON = 0 V ,
Settling time from rising edge of DIAG_EN RSNS = 1 kΩ, IL = 1A
50% of VDIAG_EN to 90% of settled ISNS
VEN = 5 V, VDIAG_EN = 0 V to 5
V, VOL_ON = 0 V ,
RSNS = 1 kΩ, IL = 50 mA
UNIT
15
µs
80
µs
tSNSION2
Settling time from rising edge of EN and
DIAG_EN
50% of VDIAG_EN VEN to 90% of settled
ISNS
VEN = VDIAG_EN = 0 V to 5 V
VS = 24V RSNS = 1 kΩ, IL = 1A
150
µs
tSNSION3
Settling time from rising edge of EN
50% of VEN to 90% of settled ISNS
VEN = 0 V to 5 V, VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 1A
150
µs
tSNSION4
Settling time from rising edge of OL_ON
50% of VOL_ON to 90% of settled ISNS
VOL_ON = 0 to 5V, VEN = VDIAG_EN = 5
V
RSNS = 1 kΩ, IL = 6mA
60
µs
tSNSION5
Settling time from falling edge of IL <
IKSNS2_EN to 90% of settled ISNS
VOL_ON = VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 100 mA to 10mA
60
µs
tSNSION6
Settling time from Rising edge of IL >
IKSNS2_DIS. to 90% of settled ISNS
VOL_ON = VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 10 mA to 100mA
60
µs
tKSNS2_DIS_ Deglitch time for transition of IL >
IKSNS2_DIS.
VOL_ON = VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 10 mA to 100mA
30
µs
tSNSIOFF
Settling time from falling edge of DIAG_EN
VEN = 5 V, VDIAG_EN = 5 V to 0 V
RSNS = 1 kΩ, RL = 48 Ω
20
µs
tSETTLEH
Settling time from rising edge of load step
to 90% of setttled value of current sense
output
VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IOUT = 0.5 A to 3 A
20
µs
tSETTLEL
Settling time from output edge of load step
VEN = VDIAG_EN = 5 V
to 10% of setttled value of current sense
RSNS = 1 kΩ, IOUT = 3 A to 0.5 A
output
20
µs
tTIMEOUT
Time to indicate VSNSFH due to VSVOUT>2V.
VDIAG_EN = VEN = VOL_ON = 0 V to 5 V
From rising edge of EN, DIAG_EN and
RSNS = 1 kΩ, IOUT = 5 mA
OL_ON
C
=50uF
50% of VDIA_EN VEN VOL_ONto 50% of rising OUT
edge of VSNSFH
DGL
245
µs
7.8 Switching Characteristics
VS = 24 V, TJ = -40 °C to +125 °C (unless otherwise noted), COUT = 22 nF
Parameter
Test Conditions
Min
Typ
Max
Unit
tDR
Turnon delay time (from standby)
VS = 24 V, RL = 48 Ω 50% of EN to
20% of VOUT
35
55
µs
tDR
Turnon delay time (from delay or
diagnostic)
VS = 24 V, RL = 48 Ω 50% of EN to
20% of VOUT
25
45
µs
tDF
Turnoff delay time
VS = 24 V, RL = 48 Ω 50% of EN to
80% of VOUT
20
35
50
µs
SRR
VOUT rising slew rate
VS = 24 V, 20% to 80% of VOUT,
RL = 48 Ω
0.4
0.7
0.95
V/µs
SRF
VOUT falling slew rate
VS = 24 V, 80% to 20% of VOUT,
RL = 48 Ω
0.4
0.8
1.2
V/µs
fmax
Maximum PWM frequency
1
kHz
tON
Turnon time
75
µs
VS = 24 V, RL = 48 Ω 50% of EN to
80% of VOUT
55
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7.8 Switching Characteristics (continued)
VS = 24 V, TJ = -40 °C to +125 °C (unless otherwise noted), COUT = 22 nF
Parameter
Test Conditions
Min
Typ
Max
Unit
tOFF
Turnoff time
VS = 24 V, RL = 48 Ω 50% of EN to
20% of VOUT
tON - tOFF
Turnon and off matching
1ms ON time switch enable
pulse Vs = 24 V, RL = 48 Ω
tON_pw
Minimum VOUT ON pulse width
100-µs ON time switch enable
pulse, VOUT @80% of VS, VS = 24
V, RL = 48 Ω, F = fmax
ΔPWM
PWM accuracy - average load
current
200-µs enable pulse, VS = 24 V, RL =
48 Ω
-15
F = fmax
EON
Switching energy losses during
turnon
VS = 24 V, RL = 8 Ω, 1 ms pulse,
VOUT from 20% to 80% of VS
voltage
0.5
mJ
EOFF
Switching energy losses during
turnoff
VS = 24 V, RL = 8 Ω, 1 ms pulse,
VOUT from 20% to 80% of VS
voltage
0.25
mJ
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60
70
µs
–25
45
µs
50
85
µs
15
%
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7.9 Typical Characteristics
45
On-Resistance (m)
40
37.5
35
45
6.5 V
8.5 V
13.5 V
18 V
24 V
27.5 V
36 V
42.5
40
On-Resistance (m)
42.5
32.5
30
27.5
37.5
35
32.5
30
27.5
25
25
22.5
22.5
20
-40
-20
0
20
40
60
80
Temperature (C)
100
120
20
-40
140
IOUT= 0. 2 A
0.55
6.5 V
8.5 V
13.5 V
18 V
24 V
27.5 V
36 V
-20
0
20
40
60
80
Temperature (C)
100
120
VS Standby Current (uA)
Quiescent Current (mA)
20
40
60
80
Temperature (C)
100
120
140
Figure 7-2. On-Resistance (RON) vs Temperature vs Load
Current
0.6
VEN = 5 V
0.4
0.35
0.3
0.25
0.1
-40
VDIAG_EN = 0 V
34.5
34.2
33.9
33.6
33.3
33
40
60
80
Temperature (C)
0
20
100
120
140
40
60
80
Temperature (C)
100
120
140
VDIAG_EN = 0 V
Figure 7-4. Standby Current (ISTBY, VS) From VS Input Supply vs
Temperature vs VS Voltage
Turn-off Delay Time (us)
34.8
20
-20
VEN = 0 V
35.1
0
0.45
0.2
140
6.5 V
18 V
24 V
27.5 V
36 V
-20
0.5
6.5 V
24 V
28 V
36 V
0.15
35.4
Turn-on Deltay Time (us)
0
0.65
Figure 7-3. Quiescent Current (IQ, VS) From VS Input Supply vs
Temperature vs VS Voltage
32.7
-40
-20
VS = 24 V
Figure 7-1. On-Resistance (RON) vs Temperature vs VS Supply
Voltage
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.9
0.89
0.88
0.87
0.86
0.85
-40
0.2 A
0.5 A
6A
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
-40
6.5 V
18 V
24 V
27.5 V
36 V
-20
RL= 48 Ω
0
20
40
60
80
Temperature (C)
100
120
140
RL= 48 Ω
Figure 7-5. Turn-on Delay Time (tDR) vs Temperature vs VS
Voltage
Figure 7-6. Turn-off Delay Time (tDF) vs Temperature vs VS
Voltage
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72
68
64
60
56
52
48
44
40
36
32
28
24
20
-40
70
65
60
6.5 V
18 V
24 V
27.5 V
36 V
-20
0
20
40
60
80
Temperature (C)
100
120
Turn-off Time (us)
Turn-on Time (us)
7.9 Typical Characteristics (continued)
55
50
45
40
35
6.5 V
18 V
24 V
27.5 V
36 V
30
25
20
-40
140
-20
18 V
24 V
27.5 V
36 V
-20
0
20
40
60
80
Temperature (C)
100
120
120
140
0.9
0.8
0.7
0.6
0.5
18 V
24 V
27.5 V
36 V
0.4
0.3
0.2
-40
140
-20
40
60
80
Temperature (C)
100
1440
1420
1400
1380
1360
1340
1320
1300
20
40
60
80
Temperature (C)
100
120
140
25.9
Current Sense Ratio - KSNS2 (A/A)
IOUT
0.1 A
0.2 A
1A
2A
4A
6A
7A
1460
0
20
120
140
Figure 7-10. VOUT Rising Slew Rate (SRF) vs Temperature vs
VS Voltage
1480
-20
0
RL= 48 Ω
Figure 7-9. VOUT Rising Slew Rate (SRR) vs Temperature vs VS
Voltage
Current Sense Ratio - KSNS1 (A/A)
100
1
RL= 48 Ω
IOUT
1 mA
2 mA
30 mA
40 mA
25.7
25.5
25.3
25.1
24.9
24.7
24.5
24.3
-40
-20
0
20
40
60
80
Temperature (C)
100
120
140
VS = 24 V
VS = 24 V
Figure 7-11. Current Sense Ratio (KSNS1) vs Temperature vs
Load Current
14
40
60
80
Temperature (C)
Figure 7-8. Turn-off Time (tOFF) vs Temperature vs VS Voltage
VOUT Falling Slew Rate (V/us)
VOUT Rising Slew Rate (V/us)
Figure 7-7. Turn-on Time (tON) vs Temperature vs VS Voltage
1280
-40
20
RL= 48 Ω
RL= 48 Ω
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
-40
0
Figure 7-12. Current Sense Ratio (KSNS2) vs Temperature vs
Load Current
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7.9 Typical Characteristics (continued)
Current Limit Ratio - Version A/C (A/k)
101.5
RILIM
10 k
25 k
50 k
101
100.5
100
99.5
99
98.5
98
-40
-20
0
20
40
60
80
Temperature (C)
100
120
140
VS = 24 V
Figure 7-13. Current Limit Ratio (KCL) vs Temperature vs RILIM
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8 Parameter Measurement Information
Figure 8-1. Parameter Definitions
IEN
EN
IDIAG_EN
DIAG_EN
IFAULT
VS
VOUT
SNS
IILIM
VOL_ON
IOUT
OL_ON
ISNS
ILIM
GND
IGND
VILIM
VSNS
VFLT
VDIAG_EN
VEN
VOUT
FAULT
IOL_ON
IVS
VS
VEN(1)
50%
50%
90%
90%
tDR
tDF
VOUT
10%
10%
tON
tOFF
Rise and fall time of VEN is 100 ns.
Figure 8-2. Switching Characteristics Definitions
16
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VEN
VDIAG_EN
IOUT
ISNS
tSNSION1
tSNSION2
tSNSION3
tSNSIOFF1
Current (A)
VEN
VDIAG_EN
ICL_ENPS
ICL
IOUT
ISNS
tSETTLEH
tSETTLEL
tIOS
Time (s)
Rise and fall times of control signals are 100 ns. Control signals include: EN, DIA_EN.
Figure 8-3. SNS Timing Characteristics Definitions
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9 Detailed Description
9.1 Overview
The TPS281C30 is a single-channel, fully-protected, high-side power switch with an integrated NMOS power
FET and charge pump rated to 60V DC tolerance. Full diagnostics and high-accuracy current-sense features
enable intelligent control of the load. Low logic high threshold, VIH, of 1.5V on the input pins allow use of MCU's
down to 1.8V. A programmable current-limit function greatly improves the reliability of the whole system. The
device diagnostic reporting has two pins to support both digital status and analog current-sense output, both of
which can be set to the high-impedance state when diagnostics are disabled, for multiplexing the MCU analog or
digital interface among devices.
The digital status report is implemented with an open-drain structure on the fault pin. When a fault condition
occurs, the pin is pulled down to GND. An external pullup is required to match the microcontroller supply level.
High-accuracy current sensing allows a better real-time monitoring effect and more-accurate diagnostics without
further calibration. A current mirror is used to source 1 / KSNS of the load current, which is reflected as voltage
on the SNS pin. KSNS is a constant value across temperature and supply voltage. The SNS pin can also report
a fault by forcing a voltage of VSNSFH that scales with the diagnostic enable voltage so that the max voltage
seen by the system's ADC is within an acceptable value. This removes the need for an external zener diode or
resistor divider on the SNS pin.
The external high-accuracy current limit allows setting the current limit value by application. It highly improves
the reliability of the system by clamping the inrush current effectively under start-up or short-circuit conditions.
Also, it can save system costs by reducing PCB trace, connector size, and the preceding power-stage capacity.
An internal current limit can also be implemented in this device. The lower value of the external or internal
current-limit value is applied.
An active drain to source voltage clamp is built in to address switching off the energy of inductive loads, such as
relays, solenoids, pumps, motors, and so forth. During the inductive switching-off cycle, both the energy of the
power supply (EBAT) and the load (ELOAD) are dissipated on the high-side power switch itself. With the benefits
of process technology and excellent IC layout, the TPS281C30x device can achieve excellent energy dissipation
capacity, which can help save the external free-wheeling circuitry in most cases.
The TPS281C30x device can be used as a high-side power switch for a wide variety of resistive, inductive, and
capacitive loads, including the low-wattage bulbs, LEDs, relays, solenoids, and heaters.
18
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9.2 Functional Block Diagram
TPS281C30x
VS
OL_ON
OFF_OL
DIAG_EN
Voltage
Scaling
IOUT
KSNS1
IOUT
KSNS2
VSNSFH
ISNSFH
Thermal
Shutdown
+
VS_OVP
OFF_PU_EN
Off-State
Open Load
Detection
*
QAUX
14
QMain
30m
TSD ||TREL
OVP
–
OUT
SNS_FLT
+
VS_UVLO
UVLO
–
*
Current Limit Amp
IOUT
KCL
SNS
Charge Pump &
Gate Control
Fast-Trip Comparator
EN
ILIM
ILIM_OPN
ILIM_GND
ILIM_OR
FAULT
GND
OVP
ILIM
OFF_OL
TSD
OL_ON_Invalid
RILIM_INT
ICL = 0.5A
DIAG_EN
DIAG_EN
OL_ON
EN
OFF_PU_EN
IOUT >IKSNS2_EN
OVP
ILIM
TSD
SNS_FLT
*IEC ESD Protection
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9.3 Device Functional Modes
9.3.1 Working Mode
The four working modes in the device are normal mode, normal mode with diagnostics, standby mode, and
standby mode with diagnostics. If an off-state power saving is required in the system, the standby current is less
than 500 nA with EN and DIAG_EN low. If an off-state diagnostic is required in the system, the typical standby
current is around 0.5 mA with DIAG_EN high. Note that to enter standby mode requires IN low and t > tSTBY.
tSTBY is the standby-mode deglitch time, which is used to avoid false triggering or interfere with PWM switching.
DIAG_EN low and
EN high to low
t > toff,deg
Standby Mode
EN low, DIAG_EN low)
Normal Mode
(EN high, DIAG_EN low)
EN low to high
DIAG_EN high to low
DIAG EN low to high
DIAG_EN low to high
Standby Mode
with Diagnostics
(EN low, DIAG_EN high)
EN high to low and
DIAG_EN high and
t > toff,deg
DIAG_EN high to low
Normal Mode
With Diagnostics
(EN high, DIAG_EN high)
EN low to high
Figure 9-1. Work-Mode State Machine
20
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9.4 Feature Description
9.4.1 Accurate Current Sense
The current-sense function is internally implemented, which allows a better real-time monitoring effect and
more-accurate diagnostics without further calibration. A current mirror is used to source 1 / KSNS of the load
current, flowing out to the external resistor between the SNS pin and GND, and reflected as voltage on the SNS
pin.
KSNS is the ratio of the output current and the sense current. The accuracy values of KSNS quoted in the
electrical characteristics do take into consideration temperature and supply voltage. Each device was internally
calibrated while in production, so post-calibration by users is not required in most cases.
The maximum voltage out on the SNS pin is clamped to VSNSFH which is the fault voltage level. In order to
make sure that this voltage is not higher than the system can tolerate, TI has correlated the voltage coming
in on the DIAG_EN pin with the maximum voltage out on the SNS pin. If DIAG_EN is between VIH and 3.3
V, the maximum output on the SNS pin will be ~3.3 V. However, if the voltage at DIAG_EN is above 3.3 V,
then the fault SNS voltage, VSNSFH, will track that voltage up to 5 V. This is done because the GPIO voltage
output that is powering the diagnostics through DIAG_EN, will be close to the maximum acceptable ADC voltage
within the same microcontroller. Therefore, the sense resistor value, RSNS, can be chosen to maximize the range
of currents needed to be measured by the system. The RSNS value should be chosen based on application
need. The maximum usable RSNS value is bounded by the ADC minimum acceptable voltage, VADC,min, for the
smallest load current needed to be measured by the system, ILOAD,min. The minimum acceptable RSNS value has
to ensure the VSNS voltage is below the VSNSFH value so that the system can determine faults. This difference
between the maximum readable current through the SNS pin, ILOAD,max × RSNS, and the VSNSFH is called the
headroom voltage, VHR. The headroom voltage is determined by the system but is important so that there is a
difference between the maximum readable current and a fault condition. Therefore, the minimum RSNS value
has to be the VSNSFH minus the VHR times the sense current ratio, KSNS divided by the maximum load current the
system needs to measure, ILOAD,max. This boundary equation can be seen in Equation 1.
VADC,min × KSNS / ILOAD,min ≤ RSNS ≤ (VSNSFH – VHR) × KSNS / ILOAD,max
(1)
Current Sense
Voltage
ADC Full Scale Range, VADC,max
VSNSFH
Headroom, VHR
Max Measurable Current
Over Current
Max Nominal Current
Normal
1
RSNS
Open Load Current, VADC,min
Sense Current
Figure 9-2. Voltage Indication on the Current-Sense Pin
The maximum current the system wants to read, ILOAD,max, needs to be below the current limit threshold because
once the current limit threshold is tripped the VSNS value will go to VSNSFH. Additionally, currents being measured
should be below 7 A to ensure that the current sense output is not saturated.
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VIN
VS
OL_ON
QMain
QAUX
OL_ON&DIAG_EN
DIAG_EN
Voltage
Scaling
IOUT
KCL
IOUT
KSNS2
IOUT
KSNS1
IOUT
–
VSNSFH
+
SNS
VOUT
Current
Clamp
ILIM
RSNS
RILIM
Figure 9-3. Current-Sense and Current-Limit Block Diagram
Since this scheme adapts based on the voltage coming in from the MCU. There is no need to have a zener
diode on the SNS pin to protect from high voltages.
22
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9.4.1.1 High Accuracy Sense Mode
In some applications, having accurate current sensing at lower load currents can be critical to distinguish
between a real load and a fault scenario such as an open load condition(Wire-Break). To address this challenge,
TPS281C30x implements a high accuracy sense mode that enables customers to achieve ±30% @6mA load.
This mode will be activated when diagnostics are enabled(DIAG_EN=HI), OL_ON = HI and ILoad12LSBs of headroom.
Full Protection and Diagnostics for full device states.
Table 9-1. Current Sensing Operation Modes
Conditions
Normal
Standard Sensing
High Accuracy
Sense
Normal Operation
High Accuracy
Sense
Invalid Range
EN
VOUT
OL_ON KSNS
SNS
FAULT
Behavior
Recovery
L
L
L
1200
0
Hi-Z
Normal
H
H
L
1200
ILoad /
Ksns1
Hi-Z
Normal
H
H
H
24
ILoad /
Ksns2
Hi-Z
Enables x50 sense ratio for high
accuracy sensing and FAULT stays
Hi-Z since valid condition is met
ILoadIKsns2_DIS
H
H
H
1200
ILoad /
Ksns1
Clears when
load falls below
IKSNS2_EN or
OL_ON is reset to
LO.
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ILOAD(I)
ICL
IKSNS2_DIS
IKSNS2_EN
Time (s)
OL_ON(V)
Time (s)
FAULT(V)
Time (s)
SENSE(I)
ISNSFH
SNS = 1/KSNS1
SNS = 1/KSNS2
SNS = 1/KSNS1
SNS = 1/KSNS2
SNS = 1/KSNS1
Time (s)
Standard Sensing
OL_ON=LO
High Accuracy
Sensing
OL_ON=HI
Standard Sensing
with OL_ON=LO
High accuracy
sensing enabled with
OL_ON=HI
Invalid Range due to
OL_ON=HI and
ILOAD>IKSNS2_EN
Figure 9-4. High Accuracy Sensing FAULT Indication
9.4.2 Programmable Current Limit
A high-accuracy current limit allows higher reliability, which protects the power supply during short circuit or
power up. Also, it can save system costs by reducing PCB traces, connector size, and the capacity of the
preceding power stage.
Current limit offers protection from overstressing to the load and integrated power FET. Current limit holds the
current at the set value, and pulls up the SNS pin to VSNSFH and asserts the FAULT pin as diagnostic reports.
The two current-limit thresholds are:
24
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•
•
SLVSGD3A – DECEMBER 2022 – REVISED JUNE 2023
External programmable current limit -- An external resistor, RILIMis used to set the channel current limit. When
the current through the device exceeds ICL (current limit threshold), a closed loop steps in immediately. VGS
voltage regulates accordingly, leading to the VDS voltage regulation. When the closed loop is set up, the
current is clamped at the set value. The external programmable current limit provides the capability to set the
current-limit value by application.
Additionally this value can be dynamically changed by changing the resistance on the ILIM pin. This can be
seen in the Applications Section
Internal current limit: ILIM pin open or pin shorted to ground -- If the external current limit is out of range on the
lower end or the ILIM pin is shorted to ground, the internal current limit is fixed and typically 0.5A. This works
as a safety power limitting mechanicsm during failures with shorts or open connections with PCB
Overstress.
Both the internal current limit (Ilim,nom) and external programmable current limit are always active when VS is
powered and EN is high. The lower value one (of ILIM and the external programmable current limit) is applied as
the actual current limit. The typical deglitch time for the current limit to assert is 2.5µs.
Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the
ILIM pin must be connected with device GND. Calculate RLIM with Equation 2.
RILIM = KCL / ICL
(2)
For better protection from a hard short-to-GND condition (when VS and input are high and a short to GND
happens suddenly), an open-loop fast-response behavior is set to turn off the channel, before the current-limit
closed loop is set up. With this fast response, the device can achieve better inrush-suppression performance.
9.4.2.1 Short-Circuit and Overload Protection
TPS281C30 provides output short-circuit protection to ensure that the device will prevent current flow in the
event of a low impedance path to GND, removing the risk of damage or significant supply droop. The device is
guaranteed to protect against short-circuit events regardless of the state of the ILIM pins and with up to 36-V
supply at 125°C.
On-State Short-Circuit Behavior shows the behavior of TPS281C30x when a short-circuit occurs and the device
is in the on-state and already outputting current. When the internal pass FET is fully enabled, the current
clamping settling time is slower so to ensure overshoot is limited, the device implements a fast trip level at a
level IOVCR. When this fast trip threshold is hit, the device immediately shuts off for a short period of time before
quickly re-enabling and clamping the current to ICL level after a brief transient overshoot to the higher peak
current (ICL_ENPS) level. The device will then keep the current clamped at the regulation current limit until the
thermal shutdown temperature is hit and the device will safely shut-off.
Current (A)
IOVCR
ICL_ENPS
ICL
Thermal Shutdown
INOM
tRETRY
Time (s)
Figure 9-5. On-State Short-Circuit Behavior
Overload Behavior shows the behavior of the TPS281C30x when there is a small change in impedance that
sends the load current above the ICL threshold. The current rises to ICL_LINPK above the regulation level. Then
the current limit regulation loop kicks in and the current drops to the ICL value.
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Current (A)
ICL_ENPS
ICL_LINPK
ICL
INOM
tRETRY
Thermal Shutdown
Time (s)
Figure 9-6. Overload Behavior
In all of these cases, the internal thermal shutdown is safe to hit repetitively. There is no device risk or lifetime
reliability concerns from repeatedly hitting this thermal shutdown level.
9.4.2.2 Capacitive Charging
Capacitive Charging Circuit shows the typical set up for a capacitive load application and the internal blocks that
function when the device is used. Note that all capacitive loads will have an associated "load" in parallel with the
capacitor that is described as a resistive load but in reality it can be inductive or resistive.
Power Supply
VS
QMAIN
EN
Gate Driver
ICL =
KCL
RILIM
RILIM
ILIM
Current
Limit
INOM =
GND
VS
RQMAIN + RLOAD
VOUT
ICL = CLOAD x dVDS/dt
CLOAD
RLOAD
Figure 9-7. Capacitive Charging Circuit
The first thing to check is that the nominal DC current, INOM, is acceptable for the TPS281C30 device. This can
easily be done by taking the RθJA from the Thermal Section and multiplying the RON of the TPS281C30 and the
INOM with it, add the ambient temperature and if that value is below the thermal shutdown value the device can
operate with that load current. For an example of this calculation see the Applications Section.
The second key care about for this application is to make sure that the capacitive load can be charged up
completely without the device hitting thermal shutdown. This is because if the device hits thermal shutdown
during the charging, the resistive nature of the load in parallel with the capacitor will start to discharge the
capacitor over the duration the TPS281C30x is off. Note that there are some application with high enough
load impedance that the TPS281C30 hitting thermal shutdown and trying again is acceptable; however, for the
majority of applications the system should be designed so that the TPS281C30x does not hit thermal shutdown
while charging the capacitor.
With the current clamping feature of the TPS281C30x, capacitors can be charged up at a lower inrush current
than other high current limit switches. This lower inrush current means that the capacitor will take a little longer
to charge all the way up. However, to minimize this longer charge time during startup, TPS281C30 implements
an inrush current handling feature described in On-State Short Circuit Behavior. When the EN pin goes high to
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turn on the high side switch, the device will default its current limit threshold to ILIM_STARTUP for a duration of
ILIM_STARTUP_DELAY. During this delay period, a capacitive load can be charged at a higher rate than what typical
ICL would allow and FAULT will be masked to prevent unwanted Fault triggers. After ILIM_STARTUP_DELAY, the
current limit will default back to ICL and Fault will work normally.
Current (A)
ILIM_STARTUP
ICL
ILIM_STARTUP_DELAY
Voltage (V)
Time (S)
VEN
Time (S)
Voltage (V)
VFAULT
tFAULT_BLANKING
Time (S)
Figure 9-8. Inrush Current Handling
The initial inrush current period when the current limit is higher enables two different system advantages when
driving loads:
•
•
Enables higher load current to be supported for a period of time of the order of milliseconds to drive high
inrush current loads like incandescent bulb loads.
Enables fast capacitive load charging. In some situations, it is ideal to charge capacitive loads at a higher
current than the DC current to ensure quick supply bring up. This architecture allows a module to quickly
charge a capacitive load using the initial higher inrush current limit and then use a lower current limit to
reliably protect the module under overload or short circuit conditions.
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Current (A)
ICL_ENPS2
ILIM_STARTUP
ICL_ENPS
ICL
ILIM_STARTUP_DELAY
Time (S)
Voltage (V)
VEN
Time (S)
Figure 9-9. Auto-retry Behavior After ILIM_STARTUP_DELAY Period Expires
Current (A)
ICL_ENPS2
ILIM_STARTUP
ICL
ILIM_STARTUP_DELAY
Time (S)
Voltage (V)
VEN
Time (S)
Figure 9-10. Auto-retry Behavior Before ILIM_STARTUP_DELAY Period Expires
While in current limiting mode, at any level, the device will have a high power dissipation. If the FET temperature
exceeds the over-temperature shutdown threshold, the device will turn off just the channel that is overloaded.
After cooling down, the device will re-try. If the device is turning off prematurely on start-up, it is recommended to
improve the PCB thermal layout, lower the current limit to lower power dissipation, or decrease the inrush current
(capacitive loading). t limit to lower power dissipation, or decrease the inrush current (capacitive loading).
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For more information about capacitive charging with high side switches see the How to Drive Capacitive Loads
application note. This application note has information about the thermal modeling available along with quick
ways to estimate if a high side switch will be able to charge a capacitor to a given voltage.
9.4.3 Inductive-Load Switching-Off Clamp
When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance
characteristics. The power FET may break down if the voltage is not clamped during the current-decay period.
To protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the
clamp diode between the drain and gate.
VDS,Clamp = VS – VOUT
(3)
During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both
the energy of the power supply (ES) and the load (ELOAD) are dissipated on the high-side power switch itself,
which is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the
resistance.
EHSD = ES + ELOAD = ES + EL – ER
(4)
From the high-side power switch’s view, EHSD equals the integration value during the current-decay period.
TDECAY
EHSD
³0
TDECAY
§ R u IOUT(MAX)
L
u ln ¨
¨
R
VOUT
©
(HSD
/u
VDS,clamp u IOUT (t)dt
VBAT
VOUT
R
2
(5)
VOUT ·
¸
¸
¹
(6)
ª
§ R u IOUT(MAX)
u «5 u ,OUT(MAX) ± 9OUT OQ ¨
¨
VOUT
«¬
©
VOUT · º
¸¸ »
¹ »¼
(7)
When R approximately equals 0, EHSD can be given simply as:
EHSD
VBAT
VOUT
1
2
u L u I OUT(MAX)
2
R2
(8)
Power Supply
VS
VDS
EN
Gate Driver
GND
VOUT
L
R
VOUT
Figure 9-11. Driving Inductive Load
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INPUT
VIN(BAT)
VOUT
VDS, clamp
EHSD
IOUT
tDECAY
Figure 9-12. Inductive-Load Switching-Off Diagram
As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side
power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of
the maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board
dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test
condition: VS = 24 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2× 70-μm copper, 2× 35-μm
copper, thermal pad copper area 600 mm2.
9.4.4 Inductive Load Demagnetization
When switching off an inductive load, the inductor can impose a negative voltage on the output of the switch.
The TPS281C30 includes voltage clamps between VS and VOUT to limit the voltage across the FETs and
demagnetize load inductance if there is any. The negative voltage applied at the OUT pin drives the discharge of
inductor current. Figure 10-14 shows the device discharging a 400-mH load.
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Figure 9-13. TPS281C30 Inductive Discharge (400 mH)
Single Pulse Inductive Discharge Energy (mJ)
The maximum acceptable load inductance is a function of the energy dissipated in the device and therefore the
load current and the inductive load. The maximum energy and the load inductance the device can withstand for
one pulse inductive dissipation at 125°C is shown in Figure 10-15. The device can withstand 50% of this energy
for one million inductive repetitive pulses with a >4-Hz repetitive pulse. If the application parameters exceed this
device limit, use a protection device like a freewheeling diode to dissipate the energy stored in the inductor.
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
VS = 36 V
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 16
Current (A)
Figure 9-14. TPS281C30 Inductive Load Discharge Energy Capability at 125°C
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9.4.5 Full Protections and Diagnostics
Current Sensing is active when DIAG_EN enabled. When DIAG_EN is low, current sense is disabled. The SNS
output is in high-impedance mode.
Table 9-2. DIAG_EN Logic Table
DIAG_EN EN Condition
HIGH
HIGH
LOW
HIGH
LOW
32
LOW
Protections and Diagnostics
See Fault Table
Diagnostics disabled and SNS output
is set to high Impedance. Protection is
normal and FAULT continues to indicate
TSD or ILIM.
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Table 9-3. Status Table (DIAG_EN=HIGH )
Conditions
EN
VOUT
OL_ON
FAULT
SNS
Behavior
Normal
Standard Sensing
L
L
L
Hi-Z
0
Normal
H
H
L
Hi-Z
ILoad /
Ksns1
Normal
High Accuracy
Sense
Invalid Range
H
H
H
L
ILoad /
Ksns1
FAULT is asserted signaling that high
accuracy sensing is not enabled since
ILoad>IKsns2_EN
High Accuracy
Sense
Normal Operation
H
H
H
Hi-Z
ILoad /
Ksns2
Enables x50 sense ratio for high
accuracy sensing and FAULT stays
Hi-Z since valid condition is met
ILoad TREL, the
device shuts down. The faults are continually shown on SNS and FLT and the part waits for the tRETRY
timer to expire. When tRETRY timer expires, since EN is still high, the device will come back on into this IILIM
condition.
2. Absolute thermal shutdown: In this case, the ambient temperature is now much higher than previous.
The device is still enabled in an over current event with DIAG_EN high. However, in this case the junction
temperature rises up and hits an absolute reference temperature, TABS, and then shuts down. The device
will not recover until both TJ < TABS – Thys and the tRETRY timer has expired.
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1
2
DIAG_EN
EN
TABS
TABS
THYS
Junction
Temperature
TREL
Output
Current
VSNS
tRETRY
tRETRY
tRETRY
ILIM
VSNSFH
FLT
Figure 9-16. Thermal Behavior
9.4.5.3 Undervoltage Lockout (UVLO) Protection
The device monitors the supply voltage VS to prevent unpredicted behaviors in the event that the supply voltage
is too low. When the supply voltage falls down to VUVLOF, the output stage is shut down automatically. When the
supply rises up to VUVLOR, the device turns on. If an overcurrent event trips the UVLO threshold, the device will
shut off and come back on into a current limit safely.
9.4.5.4 Overvoltage (OVP) Protection
The device monitors the supply voltage VS to prevent unpredicted behaviors in the event that the supply voltage
is too high. When the supply increases beyond VS,OVPR, the output stage is shut down automatically. When the
supply falls belowVS,OVPF, the device turns on. If an overcurrent event trips the OVP threshold due to inductive
load oscillations, the integrates a deglitcher to avoid immediate output shutoff due to short transients.
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9.4.5.5 Reverse Polarity Protection
Method 1: Blocking diode connected with VBB. Both the device and load are protected when in reverse polarity.
The blocking diode does not allow any of the current to flow during reverse battery condition.
S
VDD
–
+
UT
MCU
d
Figure 9-17. Reverse Protection With Blocking Diode
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Method 2 (GND network protection): Only the high-side device is protected under this connection. The
load reverse loop is limited by the load itself. Note when reverse polarity happens, the continuous reverse
current through the power FET should be less than Irev. Of the three types of ground pin networks, TI strongly
recommends type 3 (the resistor and diode in parallel). No matter what types of connection are between the
device GND and the board GND, if a GND voltage shift happens, ensure the following proper connections for the
normal operation:
•
•
Leave the NC pin floating or connect to the device GND. TI recommends to leave floating.
Connect the current limit programmable resistor to the device GND.
RPROT
s
VD
–
+
UT
MCU
d
RGND
DGND
Figure 9-18. Reverse Protection With GND Network
•
Type 1 (resistor): The higher resistor value contributes to a better current limit effect when the reverse
battery or negative ISO pulses. However, it leads to higher GND shift during normal operation mode. Also,
consider the resistor’s power dissipation.
RGND d
RGND t
VGNDshift
Inom
(9)
±9CC
±,GND
(10)
where
– VGNDshift is the maximum value for the GND shift, determined by the HSS and microcontroller. TI suggests
a value ≤ 0.6 V.
– Inom is the nominal operating current.
– –VCC is the maximum reverse voltage seen on the battery line.
– –IGND is the maximum reverse current the ground pin can withstand, which is available in the Absolute
Maximum Ratings.
•
•
If multiple high-side power switches are used, the resistor can be shared among devices.
Type 2 (diode): A diode is needed to block the reverse voltage, which also brings a ground shift (≈ 600 mV).
However, an inductive load is not acceptable to avoid an abnormal status when switching off.
Type 3 (resistor and diode in parallel (recommended)): A peak negative spike may occur when the
inductive load is switching off, which may damage the HSD or the diode. So, TI recommends a resistor
in parallel with the diode when driving an inductive load. The recommended selection are 1-kΩ resistor in
parallel with an IF > 100-mA diode. If multiple high-side switches are used, the resistor and diode can be
shared among devices.
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9.4.5.6 Protection for MCU I/Os
In many conditions, such as the negative surge pulse, or the loss of battery with an inductive load, a negative
potential on the device GND pin may damage the MCU I/O pins [more likely, the internal circuitry connected to
the pins]. Therefore, the serial resistors between MCU and HSS are required.
Also, for proper protection against loss of GND, TI recommends 10 kΩ resistance for the RPROT resistors.
RPROT
s
VD
–
+
UT
MCU
d
RGND
DGND
Figure 9-19. MCU IO Protections
9.4.5.7 Diagnostic Enable Function
The diagnostic enable pin, DIAG_EN, offers multiplexing of the microcontroller diagnostic input for current sense
or digital status, by sharing the same sense resistor and ADC line or I/O port among multiple devices.
In addition, this pin can be used to manage power dissipation by the device. During the ouput-on period, if no
continious sense output diagnositcs are required, the diagnostic disable feature will lower the operating current.
On the other hand, the output-off period, the diagnostic disable function lowers the current consumption for the
standby condition.
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MCU
GPIO1
DIAG_EN
Switch 1
SNS
GPIO2
DIAG_EN
Switch 2
SNS
GPIO3
DIAG_EN
Switch 3
SNS
GPIO4
DIAG_EN
Switch 4
SNS
RSNS
ADC_IN
Figure 9-20. Resistor sharing
9.4.5.8 Loss of Ground
The ground connection may be lost either on the device level or on the module level. If the ground connection
is lost, the channel output will be disabled irrespective of the EN input level. If the switch was already disabled
when the ground connection was lost, the outputs will remain disabled even when the channels are enabled. The
steady state current from the output to the load that remains connected to the system ground is below the level
specified in the Specifications section of this document. When the ground is reconnected, normal operation will
resume.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
10.2 Typical Application
The Typical Application Circuit shows an example of how to design the external circuitry parameters.
VS
+24V Field VS
D1
CIN
+3.3V/5.0V
RPU
To Inductive,
Capacitive and
Resistive Load
FAULT
RPROT
VOUT
EN
RPROT
COUT
DIAG_EN
D2
RPROT
OL_ON
RPROT
SNS
ILIM
RPROT
CSNS
GND
RSNS
RGND
RILIM
DGND
Figure 10-1. Typical Application Circuit
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10.2.1 Design Requirements
Component
Description
Purpose
D1
SMBJ60CA
Clamp surge voltages at the supply input
D2
SMBJ36CA (Optional)
Clamp surge voltages at the supply output
CIN1
100nF
Stabilize the input supply and filter out low frequency noise.
CIN2
4.7nF
Filtering of voltage transients (for example, ESD, IEC 61000-4-5) and
improved emissions.
RPROT
10kΩ
Protection resistor for microcontroller and device I/O pins - Optional for
reverse polarity protection
RILIM
7.5kΩ – 50kΩ
Set current limit threshold
RSNS
500-2000
Translate the sense current into sense voltage.
CSNS
1nF
Coupled with RPROT on the SNS line creates a low pass filter to filter out
noise going into the ADC of the MCU.
CVOUT
22nF
Improves EMI performance, filtering of voltage transients
RGND
1kΩ
Stabilize GND potential during turn-off of inductive load - Optional for
reverse polarity protection
DGND
BAS21 Diode
Keeps GND close to system ground during normal operation - Optional for
reverse polarity protection
10.2.1.1 IEC 61000-4-5 Surge
The TPS281C30 is designed to survive against IEC 61000-4-5 surge using external TVS clamps. The device
is rated to 64 V ensuring that external TVS diodes can clamp below the rated maximum voltage of the
TPS281C30x. Above 64 V, the device includes VDS clamps to help shunt current and ensure that the device
survives the transient pulses. Depending on the class of the output, TI recommends that the system has a
SMBJ36A or SMCJ36A between VS and module GND.
10.2.2 Detailed Design Procedure
10.2.2.1 Selecting RILIM
In this application, the TPS281C30A must allow for the maximum DC current with margin but minimize the
energy in the switch and the load on the input supply during a fault condition by minimizing the current limit.
The nominal current limit should be set such that the worst case (lowest) current limit will be higher than the
maximum load current (4 A). Since the lower limit is 10% below the typical value, for this application, the best
ILIM set point is approximately 5.5A. The below equation allows you to calculate the RILIM value that is placed
from the ILIMx pins to GND pin of the device. RILIM is calculated in kΩ.
RILIM = KCL / ICL
(11)
The KCL value in the Specifications section is 50A/kΩ. So the calculated value of RILIM is 9.09 kΩ which can be
found as a standard 1% resistor.
10.2.2.2 Selecting RSNS
Table 10-1 shows the requirements for the load current sense in this application. The KSNS value is specified for
the device and can be found in the Specifications section.
Table 10-1. RSNS Calculation Parameters
PARAMETER
EXAMPLE VALUE
Current Sense Ratio (KSNS1)
1300
Current Sense Ratio (KSNS2)
24
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Table 10-1. RSNS Calculation Parameters (continued)
PARAMETER
EXAMPLE VALUE
Largest diagnosable load current
4.8 A
Smallest diagnosable load current
4 mA
Full-scale ADC voltage
5.0 V
ADC resolution
10 bit
The load current measurement up to 4.8 A ensures that even in the event of a overload but below the set current
limit, the MCU can register and react by turning off the FET while the low level of 4 mA allows for accurate
measurement of low load currents and enable the distinction open load faults from supported nominal load
currents. For load currents < 50 mA, the customer can enable high accuracy sensing to change the sense ratio
from KSNS1 to KSNS2. This prevents the requirement of a higher resolution ADC and it also increases sense
accuracy. Go to high accuracy sensing for more information.
The RSNS resistor value should be selected such that the largest diagnosable load current puts the SNS pin
voltage (VSNS) at about 90% of the ADC full-scale. With this design, any ADC value above 80% of full scale (FS)
can be considered a fault. Additionally, the RSNS resistor value should ensure that the smallest diagnosable load
current does not cause VSNS to fall below at a least a few LSB of the ADC.
With the given example values, a 1.0-kΩ sense resistor satisfies both requirements.
Table 10-2. VSNS Calculation
Sense Mode
OL_ON
LOAD (A)
SENSE RATIO
ISNS (mA)
RSNS (Ω)
VSNS (V)
% of 5-V ADC
Standard
Sensing
LO
4.8A
1200
3.69
1000
3.69
73.8%
High Accuracy
Sensing
HI
0.004
24
0.166
1000
0.166
3.3% (~34
LSBs)
10.3 Power Supply Recommendations
The TPS281C30 device is designed to operate in a 24-V industrial system. The allowed supply voltage range
(VS pin) is 6 V to 36 V as measured at the VS pin with respect to the GND pin of the device. In this range
the device meets full parametric specifications as listed in the Electrical Characteristics table. The device is also
designed to withstand voltage transients beyond this range such as SELV supply failures.
It is recommended to place a 0.1uF capacitor at the Vs supply input to stabilize the input supply and filter out
low frequency noise. The power supply must be able to withstand all transient load current steps. In cases
where the power supply is slow to respond to a large transient current or large load current step, additional bulk
capacitance can be required on the input.
VS Input Supply Voltage Range
6 V to 36 V
36 V > VS > VS, OVPR
VS > Vs, OVPR
Description
Nominal supply voltage, all parametric specifications apply. The
device is completely short-circuit protected.
Device is fully functional and protected but timing parametrics can
deviate from specifications.
SELV Supply Voltage. Device disables itself and tolerates up to 64 V
at the input for extended period of time.
10.4 Layout
10.4.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 125°C. If the output current is very high, the power
dissipation may be large. The HTSSOP and QFN packages have good thermal impedance. However, the PCB
layout is very important. Good PCB design can optimize heat transfer, which is absolutely essential for the
long-term reliability of the device.
42
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•
•
•
SLVSGD3A – DECEMBER 2022 – REVISED JUNE 2023
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major
heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is
extremely important when there are not any heat sinks attached to the PCB on the other side of the board
opposite the package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
10.4.1.1 EMC Considerations
10.4.2 Layout Example
10.4.2.1 PWP Layout without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
CVS
RPROT
GND
1
14
VS
EN
2
13
VS
DIAG_EN
3
12
VS
FAULT
4
11
NC
OL_ON
5
10
VOUT
SNS
6
9
7
8
RPROT
RPU
RPROT
RPROT
Thermal
Pad
RPROT
CFILTER
RSNS
ILIM
VOUT
CVOUT
RLIM
Figure 10-2. PWP Layout Without a GND Network
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10.4.2.2 PWP Layout with a GND Network
With a GND network, tie the thermal pad with a single trace through the GND network to the board GND copper.
RGND
DGND
RPROT
CVS_IC
CVS
G
RPROT
RPU
RPROT
DIAG_
FAU
RPROT
OL_
RPROT
S
CFILTER
RSNS
ILIM
CVOUT
RLI
Figure 10-3. PWP Layout With a GND Network
10.4.2.3 RGW Layout with a GND Network
With a GND network, tie the thermal pad with a single trace through the GND network to the board GND copper.
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RPROT
RPROT
RPROT
RPROT
SNS
OL_ON
GND
FAULT
20
19
18
17
DIAG_EN
RSNS
RILIM
ILIM
1
16
15
EN
NC
2
14
NC
VOUT
3
13
VS
VOUT
4
12
VS
VOUT
5
11
VS
NC
RILIM
9
10
NC
8
NC
7
NC
6
DGND
Figure 10-4. RGW Layout With a GND Network
10.4.3 Thermal Considerations
This device possesses thermal shutdown (TABS) circuitry as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the thermal-shutdown trip point. If the junction
temperature exceeds the thermal-shutdown trip point, the output turns off. When the junction temperature falls
below the thermal-shutdown trip point, the output turns on again.
Calculate the power dissipated by the device according to Equation 13.
PT = IOUT 2 x RDSON + VS x INOM
(12)
where
•
PT = Total power dissipation of the device
After determining the power dissipated by the device, calculate the junction temperature from the ambient
temperature and the device thermal impedance.
TJ = TA + RθJA x PT
(13)
For more information please see How to Drive Resistive, Inductive, Capacitive, and Lighting Loads.
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
46
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS281C30ARGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28C30A
Samples
TPS281C30BRGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28C30B
Samples
TPS281C30CRGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28C30C
Samples
TPS281C30DRGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28C30D
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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