TPS3306-33D

TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL FEATURES APPLICATIONS • • • • • • • • • • • • • • • Dual Supervisory Circuits With Power-Fail for DSP and Processor-Based Systems Voltage Monitor for Power-Fail or Low-Battery Warning Watchdog Timer With 0.8 Second Time-Out Power-On Reset Generator With Integrated 100 ms Delay Time Open-Drain Reset and Power-Fail Output Supply Current of 15 µA (Typ.) Supply Voltage Range: 7 V to 6 V Defined RESET Output From VDD≥ 1.1 V MSOP-8 and SO-8 Packages Temperature Range: –40°C to +85°C Multivoltage DSPs and Processors Portable Battery-Powered Equipment Embedded Control Systems Intelligent Instruments Automotive Systems D OR DGK PACKAGE (TOP VIEW) SENSE1 1 SENSE2 2 8 VDD 7 WDI TPS3306 PFI 3 6 PFO GND 4 5 RESET DESCRIPTION The TPS3306 family is a series of supervisory circuits designed for circuit initialization which require two supply voltages, primarily in DSP and processor-based systems. The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of 3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V. TYPICAL OPERATING CIRCUIT 3.3 V 1.5 V AVDD TPS3306–15 R1 1% R4 CVDD SENSE1 VDD DVDD SENSE2 WDI B_XF PFO A_XF PFI R2 1% R3 GND RESET TMS320 VC5441 RESET VSS VSSA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2006, Texas Instruments Incorporated TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS Table 1. SUPPLY VOLTAGE MONITORING DEVICE NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) SENSE1 SENSE2 SENSE1 TPS3306-15 3.3 V 1.5 V 2.93 V SENSE2 1.4 V TPS3306-18 3.3 V 1.8 V 2.93 V 1.68 V TPS3306-20 3.3 V 2V 2.93 V 1.85 V TPS3306-25 3.3 V 2.5 V 2.93 V 2.25 V TPS3306-33 5V 3.3 V 4.55 V 2.93 V For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DESCRIPTION (CONTINUED) The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the Supply Voltage Monitoring table. During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below the threshold voltage VIT. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td(typ) = 100 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage VIT. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT, the output becomes active (low) again. The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply. The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, tt(out) = 0.50 s, RESET becomes active for the time period td. This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. The TPS3306-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages, and are characterized for operation over a temperature range of –40°C to +85°C. 2 Submit Documentation Feedback TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 FUNCTION/TRUTH TABLES SENSE1 > VIT1 SENSE2 > VIT2 RESET 0 0 L 0 1 L 1 0 L 1 1 H FUNCTION/TRUTH TABLES PFI > VIT PFO 0 L 1 H FUNCTIONAL BLOCK DIAGRAM TPS3306 SENSE1 R1 VDD + _ SENSE2 R2 R4 RESET RESET Logic + Timer R3 + _ GND Reference Voltage of 1.25 V Oscillator PFO + _ PFI WDI Transition Detection Watchdog Logic + Timer 40 kW Submit Documentation Feedback 3 TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 TIMING DIAGRAM SENSEn V(nom) VIT 1.1 V t WDI 1 tt(out) 0 t RESET 1 Undefined Behavior Undefined Behavior 0 t td td td RESET Because of Power-Down RESET Because of WDI RESET Because of a Power Drop Below VIT– RESET Because of Power-Up Table 4. Terminal Functions TERMINAL NAME NO. I/O GND 4 I Ground DESCRIPTION PFI 3 I Power-fail comparator input PFO 6 O Power-fail comparator output, open-drain RESET 5 O Active-low reset output, open-drain SENSE1 1 I Sense voltage input 1 SENSE2 2 I Sense voltage input 2 WDI 7 I Watchdog timer input VDD 8 I Supply voltage DETAILED DESCRIPTION Watchdog In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller, or DSP typically has to toggle the watchdog input within 0.8 s to avoid a time-out occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected or tied with a high impedance driver, the watchdog is disabled and will be retriggered internally. 4 Submit Documentation Feedback TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 DETAILED DESCRIPTION (continued) Saving Current While Using the Watchdog The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the time-out period, a current of 5 V/40 kΩ = 125 µA can flow into WDI. VDD VIT t WDI t(tout) t RESET td td t Figure 1. Watchdog Timing Power-Fail Comparator (PFI and PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input (PFI) will be compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold (VPFI) of typ. 1.25 V, the power-fail output (PFO) goes low. If it goes above 1.25 V plus about 10 mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above 1.25 V. The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to assure that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected. V(SENSE) R1 1% VCC PFI R2 1% PFO TPS3306 GND VPFI,trip = 1.25 V × R1 + R2 R2 Submit Documentation Feedback 5 TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) UNIT Supply voltage, VDD (see (2)) 7V PFI pin –0.3 V to VDD + 0.3 V All other pins (see (2)) –0.3 V to 7 V Maximum low output current, IOL 5 mA Maximum high output current, IOH – 5 mA Input clamp current, IIK (VI < 0 or VI > VDD) ±20 mA ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA –40°C to +85°C Storage temperature range, Tstg –65°C to +150°C Soldering temperature (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h continuously. DISSIPATION RATING TABLE PACKAGE TA ≤ +25°C POWER RATING DERATING FACTOR ABOVE TA = +25°C TA = +70°C POWER RATING TA = +85°C POWER RATING DGK 424 mW 3.4 mW/°C 271 mW 220 mW D 725 mW 5.8 mW/°C 464 mW 377 mW RECOMMENDED OPERATING CONDITIONS At specified temperature range. MIN Supply voltage, VDD 2.7 Input voltage at WDI and PFI, VI 0 Input voltage at SENSE1 and SENSE2, VI UNIT 6 V VDD + 0.3 V 0 (VDD + 0.3)VIT/1.25 V High-level input voltage at WDI, VIH 0.7 x VDD Low-level input voltage at WDI, VIL Operating free-air temperature range, TA 6 MAX –40 Submit Documentation Feedback V V 0.3 × VDD V +85 °C TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted). PARAMETER VOL RESET, PFO Low-level output voltage Power-up reset voltage (see TEST CONDITIONS Negative-going input threshold voltage (see (2)) VDD = 3.3 V, IOL= 2 mA 0.4 VDD = 6 V, IOL = 3 mA 0.4 VDD = 2.7 V to 6 V TA = 0°C to +85°C VDD = 2.7 V to 6 V TA = –40°C to +85°C PFI PFI Hysteresis IH(AV) VSENSEn IH High-level input current 1.43 1.64 1.68 1.72 1.81 1.85 1.89 2.20 2.25 2.30 2.86 2.93 3 4.46 4.55 4.64 1.22 1.25 1.28 1.37 1.40 1.44 1.64 1.68 1.73 1.81 1.85 1.90 2.20 2.25 2.32 2.86 2.93 3.02 4.46 4.55 4.67 1.22 1.25 1.29 VIT = 1.25 V 10 VIT = 1.40 V 15 VIT = 1.68 V 15 VIT = 1.86 V 20 VIT = 2.25 V 20 VIT = 2.93 V 30 VIT = 4.55 V 40 WDI = 0 V, VDD = 6 V, Time average (dc = 12%) –15 –20 WDI WDI = VDD = 6 V 120 170 SENSE1 VSENSE1 = VDD = 6 V 5 8 SENSE2 VSENSE2 = VDD = 6 V 6 9 –120 –170 Low-level input current WDI WDI = 0 V, VDD, = 6 V II Input current PFI VDD = 6 V, 0 V ≤ VI ≤ VDD IDD Supply current Ci Input capacitance V V V V µA –25 15 VI = 0 V to VDD UNIT mV 150 IL (1) (2) 1.40 100 WDI Average low-level input current 0.4 1.37 WDI = VDD = 6 V, Time average (dc = 88%) Average high-level input current IL(AV) MAX 0.2 PFI VSENSE1, VSENSE2 Vhys TYP VDD ≥ 1.1 V, IOL = 20 µA (1)) VSENSE1, VSENSE2 VIT MIN VDD = 2.7 V to 6 V, IOL = 20 µA 10 µA µA 25 nA 40 µA pF The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals. Submit Documentation Feedback 7 TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 TIMING REQUIREMENTS at VDD = 2.7 V to 6 V, RL= 1 MΩ, CL= 50 pF, TA= 25°C PARAMETER tw Pulse width TEST CONDITIONS SENSEn VSENSEnL = VIT– 0.2 V, VSENSEnH = VIT + 0.2 V WDI VIH = 0.7 × VDD, VIL= 0.3 × VDD MIN TYP MAX UNIT 6 µs 100 ns SWITCHING CHARACTERISTICS at VDD = 2.7 V to 6 V, RL= 1 MΩ, CL = 50 pF, TA= 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tt(out) Watchdog time-out VI(SENSEn) ≥ VIT + 0.2 V, See Timing Diagram 0.5 0.8 1.2 s td Delay time VI(SENSEn) ≥ VIT + 0.2 V, See Timing Diagram 70 100 140 ms tPHL Propagation (delay) time, high-to-low level output 1 5 µs tPHL Propagation (delay) time, high-to-low level output Propagation (delay) time, low-to-high level output 0.5 1 µs tPLH SENSEn to RESET VIH = VIT + 0.2 V, VIL = VIT– 0.2 V PFI to PFO TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 18 1.005 16 VDD = 6 V 1.004 14 1.003 12 I DD − Supply Current − µ A Normalized Input Threshold Voltage − VIT(TA), VIT(25 °C) NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD 1.002 1.001 1 0.999 0.998 0.997 8 6 4 2 0 −2 −4 SENSEn = VDD TA = 25°C −6 0.996 0.995 −40 −15 10 35 60 85 −8 −10 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 TA − Free-Air Temperature − °C Figure 2. 8 TPS3306−33 10 VDD − Supply Voltage − V Figure 3. Submit Documentation Feedback TPS3306-15 TPS3306-18, TPS3306-20 TPS3306-25, TPS3306-33 www.ti.com SLVS290C – APRIL 2000 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.8 6.5 1.6 85°C 0.8 −40°C 0.4 VOL − Low-Level Output Voltage − V 2 1.2 VDD = 6 V 6 2.4 5.5 5 4.5 4 3.5 3 85°C 2.5 2 1.5 −40°C 1 0.5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 IOL − Low-Level Output Current − mA 0 0 5 10 15 20 25 30 35 40 45 50 55 60 IOL − Low-Level Output Current − mA Figure 4. Figure 5. MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE 10 tw − Minimum Pulse Duration at Vsense − µ s VOL − Low-Level Output Voltage − V VDD = 2.7 V VDD = 6 V 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900 1000 SENSE − Threshold Overdrive − mV Figure 6. Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3306-15D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30615 Samples TPS3306-15DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30615 Samples TPS3306-15DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIC Samples TPS3306-15DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIC Samples TPS3306-15DGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIC Samples TPS3306-15DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30615 Samples TPS3306-18D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30618 Samples TPS3306-18DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30618 Samples TPS3306-18DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AID Samples TPS3306-18DGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AID Samples TPS3306-18DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AID Samples TPS3306-18DGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AID Samples TPS3306-18DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30618 Samples TPS3306-20D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30620 Samples TPS3306-25D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30625 Samples TPS3306-25DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIF Samples TPS3306-25DGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIF Samples TPS3306-25DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIF Samples TPS3306-25DGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIF Samples TPS3306-25DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30625 Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3306-33D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30633 Samples TPS3306-33DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIG Samples TPS3306-33DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIG Samples TPS3306-33DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30633 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of