TPS3307-33DGNR

TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 TRIPLE PROCESSOR SUPERVISORS FEATURES • • • • • • • • D OR DGN PACKAGE (TOP VIEW) Triple Supervisory Circuits for DSP and Processor-Based Systems Power-On Reset Generator With Fixed Delay Time of 200ms, No External Capacitor Needed Temperature-Compensated Voltage Reference Maximum Supply Current of 40µA Supply Voltage Range: 2V to 6V Defined RESET Output From VDD ≥ 1.1V MSOP-8 and SO-8 Packages Temperature Range : – 40°C to +85°C SENSE1 SENSE2 SENSE3 GND 1 8 2 7 3 6 4 5 VDD MR RESET RESET TYPICAL APPLICATIONS Figure 1 lists some of the typical applications for the TPS3307 family, and a schematic diagram for a processor-based system application. This application uses TI part numbers TPS3307-33 and MSP430C325. 2.5V 5V 3.3V • VDD 100nF SENSE 1 MSP430C325 SENSE 2 470kΩ RESET RESET TPS3307−33 GND SENSE 3 620kΩ VDD GND w w w w w w w Applications using DSPs, Microcontrollers or Microprocessors Industrial Equipment Programmable Controls Automotive Systems Portable/Battery Powered Equipment Intelligent Instruments Wireless Communication Systems Notebook/Desktop Computers Figure 1. Applications Using the TPS3307 Family DESCRIPTION The TPS3307 family is a series of micropower supply voltage supervisors designed for circuit initialization primarily in DSP and processor-based systems, which require more than one supply voltage. The product spectrum of the TPS3307-xx is designed for monitoring three independent supply voltages: 3.3V/1.8V/adj, 3.3V/2.5V/adj or 3.3V/5V/adj. The adjustable SENSE input allows the monitoring of any supply voltage >1.25V. The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the following supply voltage monitoring table. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2006, Texas Instruments Incorporated TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1V. Thereafter, the supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain below the threshold voltage VIT+. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td (typ) = 200ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low) again. The TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-high RESET output. The devices are available in either 8-pin MSOP or standard 8-pin SO packages. The TPS3307-xx devices are characterized for operation over a temperature range of –40°C to +85°C. SUPPLY VOLTAGE MONITORING DEVICE (1) NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) SENSE1 SENSE2 SENSE3 SENSE1 SENSE2 SENSE3 TPS3307-18 3.3V 1.8V User defined 2.93V 1.68V 1.25V (1) TPS3307-25 3.3V 2.5V User defined 2.93V 2.25V 1.25V (1) TPS3307-33 5V 3.3V User defined 4.55V 2.93V 1.25V (1) The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements. AVAILABLE OPTIONS (1) PACKAGED DEVICES TA CHIP FORM (Y) TPS3307-18DGN TIAAP TPS3307-18Y TPS3307-25DGN TIAAQ TPS3307-25Y TPS3307-33DGN TIAAR TPS3307-33Y PowerPAD™ µ-SMALL OUTLINE (DGN) TPS3307-18D TPS3307-25D TPS3307-33D –40°C to +85°C (1) MARKING DGN PACKAGE SMALL OUTLINE (D) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Function/Truth Tables (1) 2 MR SENSE1 > VIT1 SENSE2 > VIT2 SENSE3 > VIT3 RESET RESET L X (1) X (1) X L H H 0 0 0 L H H 0 0 1 L H H 0 1 0 L H H 0 1 1 L H H 1 0 0 L H H 1 0 1 L H H 1 1 0 L H H 1 1 1 H L X = Don't care Submit Documentation Feedback TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 Functional Block Diagram VDD TPS3307 14 kΩ MR R1 + _ SENSE 1 R2 RESET R3 SENSE 2 R4 RESET Logic + Timer + _ RESET GND Reference Voltage of 1.25V _ Oscillator + SENSE 3 Timing Diagram SENSEn V(nom) VIT– t MR 1 0 t RESET 1 t 0 td td td RESET Because of SENSE Below VIT RESET Because of MR RESET Because of SENSE Below VIT– RESET Because of SENSE Below VIT– Submit Documentation Feedback 3 TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 TPS3307Y Chip Information These chips, when properly assembled, display characteristics similar to those of the TPS3307. Thermal compression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. (1) (8) (2) TPS3307Y (7) (3) (6) (4) (5) 48 CHIP THICKNESS: 10 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS 56 Table 2. Terminal Functions TERMINAL NAME 4 NO. I/O DESCRIPTION GND 4 MR 7 I Ground Manual reset RESET 5 O Active-low reset output RESET 6 O Active-high reset output SENSE1 1 I Sense voltage input 1 SENSE2 2 I Sense voltage input 2 SENSE3 3 I Sense voltage input 3 VDD 8 Supply voltage Submit Documentation Feedback TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 Absolute Maximum Ratings (1) Over operating free-air temperature range (unless otherwise noted). UNIT Supply voltage, VDD (2) 7V MR pin –0.3V to VDD +0.3V All other pins (2) –0.3V to 7V Maximum low output current, IOL 5mA Maximum high output current, IOH –5mA Input clamp current, IIK (VI < 0 or VI > VDD) ±20mA ±20mA Output clamp current, IOK (VO < 0 or VO > VDD) Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA –40°C to +85°C Storage temperature range, Tstg –65°C to +150°C Soldering temperature (1) (2) +260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. For reliable operation the device must not be operated at 7V for more than t = 1000h continuously. Dissipation Rating Table PACKAGE TA ≤ +25°C POWER RATING DERATING FACTOR ABOVE TA = +25°C TA = +70°C POWER RATING TA = +85°C POWER RATING DGN 2.14W 17.1mW/°C 1.37W 1.11W D 725mW 5.8mW/°C 464mW 377mW Recommended Operating Conditions At specified temperature range. MIN MAX UNIT Supply voltage, VDD 2 6 V Input voltage at MR and SENSE3, VI 0 VDD + 0.3 V 0 (VDD+0.3)VIT/1.25V V Input voltage at SENSE1 and SENSE2, VI High-level input voltage at MR, VIH 0.7 x VDD Low-level input voltage at MR, VIL V 0.3 × VDD Input transition rise and fall rate at MR, ∆t/∆V Operating free-air temperature range, TA –40 Submit Documentation Feedback V 50 ns/V +85 °C 5 TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 Electrical Characteristics Over recommended operating free-air temperature range (unless otherwise noted). PARAMETER VOH VOL TEST CONDITIONS High-level output voltage Low-level output voltage VSENSE3 VDD = 3.3V, IOH = –2mA VDD – 0.4V VDD = 6V, IOH = –3mA VDD – 0.4V VSENSE3 0.2 0.4 VDD = 6V, IOL = 3mA 0.4 VDD = 2V to 6V, TA = 0°C to +85°C VDD = 2V to 6V, TA = –40°C to +85°C Hysteresis at VSENSEn input 0.4 1.22 1.25 1.28 1.64 1.68 1.72 2.20 2.25 2.30 2.86 2.93 3 4.46 4.55 4.64 1.22 1.25 1.29 1.64 1.68 1.73 2.20 2.25 2.32 2.86 2.93 3.02 4.46 4.55 4.67 VIT–= 1.25V 10 VIT–= 1.68V 15 VIT–= 2.25V 20 VIT–= 2.93V 30 VIT–= 4.55V IH IL Low-level input current IDD Supply current Ci Input capacitance (1) (2) 6 High-level input current MR MR = 0.7 × VDD, VDD = 6V SENSE1 VSENSE1 = VDD = 6V SENSE2 VSENSE2 = VDD = 6V SENSE3 VSENSE3 = VDD MR MR = 0V, VDD = 6V SENSEn VSENSE1,2,3 = 0V VI = 0V to VDD UNIT V VDD = 3.3V, IOL = 2mA VSENSE1, VSENSE2 Vhys MAX VDD = 2V to 6V, IOL = 20µA VSENSE1, VSENSE2 Negative-going input threshold voltage (2) TYP VDD – 0.2V VDD ≥ 1.1V, IOL = 20µA Power-up reset voltage (1) VIT– MIN VDD = 2V to 6V, IOH = –20 µA V V V V V mV 40 –130 –180 5 8 6 –25 –430 –25 10 µA 9 25 nA –600 µA 25 nA 40 µA pF The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15µs/V To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1µF) should be placed close to the supply terminals. Submit Documentation Feedback TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 Timing Requirements At VDD = 2V to 6V, RL = 1MΩ, CL = 50pF, TA = +25°C. PARAMETER tw Pulse width TEST CONDITIONS SENSEn VSENSEnL = VIT–– 0.2V, VSENSEnH = VIT+ +0.2V MR VIH = 0.7 × VDD, VIL = 0.3 × VDD MIN TYP MAX UNIT 6 µs 100 ns Switching Characteristics At VDD = 2V to 6V, RL = 1MΩ, CL = 50pF, TA = +25°C. PARAMETER TEST CONDITIONS VI(SENSEn) ≥ VIT+ + 0.2V, MR ≥ 0.7 × VDD. See Timing Diagram. td Delay time tPHL Propagation (delay) time, high-to-low level output MR to RESETMR to RESET tPLH Propagation (delay) time, low-to-high level output MR to RESETMR to RESET tPHL Propagation (delay) time, high-to-low level output SENSEn to RESET SENSEn to RESET tPLH Propagation (delay) time, low-to-high level output SENSEn to RESET SENSEn to RESET VI(SENSEn) ≥ VIT+ + 0.2V, VIH = 0.7 × VDD, VIL = 0.3 × VDD VIH = VIT+ +0.2V, VIL = VIT–– 0.2V, MR ≥ 0.7 × VDD Submit Documentation Feedback MIN 140 TYP MAX UNIT 200 280 ms 200 500 ns 1 5 µs 7 TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 Typical Characteristics SUPPLY CURRENT vs SUPPLY VOLTAGE 18 1.005 16 VDD = 2V MR = Open 1.004 14 12 1.003 I DD − Supply Current − µ A Normalized Input Threshold Voltage − VIT(TA), VIT(25 °C) NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD 1.002 1.001 1 0.999 0.998 0.997 TPS3307−33 10 8 6 4 2 0 −2 −4 SENSEn = VDD MR = Open TA = 25°C −6 −8 −10 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 0.996 0.995 −40 −15 10 35 60 85 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 2. Figure 3. INPUT CURRENT vs INPUT VOLTAGE AT MR MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE 100 tw − Minimum Pulse Duration at Vsense − µ s 0 10 VDD = 6V TA = 25°C I I − Input Current − µ A −100 −200 −300 −400 −500 −600 −700 −800 −900 −1−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VI − Input Voltage at MR − V VDD = 6V MR = Open 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900 1000 SENSE − Threshold Overdrive − mV Figure 4. 8 Figure 5. Submit Documentation Feedback TPS3307-18, TPS3307-25, TPS3307-33 www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006 Typical Characteristics (continued) HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.5 6.5 VDD = 6V MR = Open 6 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V VDD = 2V MR = Open 2 1.5 −40°C 1 85°C 0.5 5.5 5 4.5 4 −40°C 3.5 3 85°C 2.5 2 1.5 1 0.5 0 0 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 −5.5 −6 0 IOH − High-Level Output Current − mA Figure 6. Figure 7. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.5 6.5 VDD = 2V MR = Open 2 1.5 1 VDD = 6V MR = Open 6 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 IOH − High-Level Output Current − mA 85°C 0.5 −40°C 5.5 5 4.5 4 3.5 3 85°C 2.5 2 1.5 −40°C 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 IOL − Low-Level Output Current − mA 6 0 0 Figure 8. 5 10 15 20 25 30 35 40 45 50 55 60 IOL − Low-Level Output Current − mA Figure 9. Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3307-18D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30718 Samples TPS3307-18DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30718 Samples TPS3307-18DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAP Samples TPS3307-18DGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAP Samples TPS3307-18DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAP Samples TPS3307-18DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAP Samples TPS3307-18DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30718 Samples TPS3307-18DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30718 Samples TPS3307-25D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30725 Samples TPS3307-25DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30725 Samples TPS3307-25DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAQ Samples TPS3307-25DGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAQ Samples TPS3307-25DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAQ Samples TPS3307-25DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30725 Samples TPS3307-25DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30725 Samples TPS3307-33D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30733 Samples TPS3307-33DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30733 Samples TPS3307-33DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAR Samples TPS3307-33DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAR Samples TPS3307-33DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAR Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 13-Jul-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3307-33DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30733 Samples TPS3307-33DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30733 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of