TPS3513N

TPS3513 www.ti.com SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 PC POWER SUPPLY SUPERVISOR Check for Samples: TPS3513 FEATURES 1 • Overvoltage Protection and Lockout for 12 V, 5 V, and 3.3 V Overcurrent Protection and Lockout for 12 V, 5 V, and 3.3 V Undervoltage Protection and Lockout for 12 V, and Undervoltage Detect for 5 V and 3.3 V Fault-Protection Output With Open Drain Output Stage Open-Drain, Power Good Output Signal for Power-Good Input, 3.3 V and 5 V 300-ms Power-Good Delay 75-ms Delay for 5-V and 3.3-V Power Supply Short-Circuit Turnon Protection 2.3 ms PSON Control to FPO Turnoff Delay 38 ms PSON Control Debounce Wide Supply Voltage Range From 4.5 V to 15 V • • • • • • • • • D OR N PACKAGE (TOP VIEW) PGI GND FPO PSON IS12 RI NC 1 14 2 13 3 12 4 11 5 10 6 9 7 8 PGO VDD VS5 VS33 VS12 IS33 IS5 NC – No internal connection DESCRIPTION The TPS3513 is designed to optimize PC switching power supply system with minimum external components. It provides undervoltage lockout (UVLO), protection circuits, power good indicator, and on/off control. TYPICAL APPLICATION IO 0.01 Ω 12 V 12 V 0.01 Ω 5V 3.3 V 5 V VSB PG From Transformer 0.01 Ω R1 Ω R2 Ω System Side 560 Ω 470 kΩ 5V 3.3 V 5 V VSB 1 kΩ TPS3513 PGI PGO GND VDD FPO VS5 PSON VS33 IS12 VS12 RI IS33 NC IS5 Power Supply Output Side 820 Ω 56 kΩ Max Output Current † Over Current Protection Trip Point† 12 V 6A 9.2 A 5V 16 A 24.6 A 3.3 v 9A 13.5 A 1.5 kΩ Over current protection trip point can be programmable. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2010, Texas Instruments Incorporated TPS3513 SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) UVLO thresholds are 4.45 V (on) and 3.65 V (off). Overcurrent protection (OCP) and overvoltage protection (OVP) monitor 3.3 V, 5 V, and 12 V. When an OC or OV condition is detected, the power-good output (PGO) is asserted low and the fault protection output (FPO) is latched high. PSON from low-to-high resets the latch. The OCP function will be enabled 75 ms after PSON goes low, and a debounce of typically 38 ms. A built-in 2.3-ms delay with 38-ms debounce from PSON to FPO output is enabled at turnoff. An external resistor is connected between the RI pin and the GND pin. This will introduce an accurate I(ref) for OCP function. The I(ref) range is from 12.5 µA to 62.5 µA. The formula for choosing RI resistor is V(RI)/I(ref). Three OCP comparators and the I(ref) section are supplied by VS12. The current draw from the VS12 pin is less than 1 mA. The power good feature monitors PGI, 3.3 V and 5 V, and issues a power good signal when the output is ready. The TPS3513 is characterized for operation from –40°C to 85°C. Table 1. FUNCTION TABLE (1) (1) 2 PGI PSON UV CONDITION 3.3 V / 5 V OV CONDITIONS UV CONDITION 12 V OC Conditions FPO PGO < 0.9 V L No No No L L < 0.9 V L No No Yes L L < 0.9 V L No Yes No H L < 0.9 V L No Yes Yes H L < 0.9 V L Yes No No L L < 0.9 V L Yes No Yes L L < 0.9 V L Yes Yes No H L < 0.9 V L Yes Yes Yes H L 1.0 V < PGI < 1.1 V L No No No L L 1.0 V < PGI < 1.1 V L No No Yes H L 1.0 V < PGI < 1.1 V L No Yes No H L 1.0 V < PGI < 1.1 V L No Yes Yes H L 1.0 V < PGI < 1.1 V L Yes No No L L 1.0 V < PGI < 1.1 V L Yes No Yes H L 1.0 V < PGI < 1.1 V L Yes Yes No H L 1.0 V < PGI < 1.1 V L Yes Yes Yes H L >1.2 V L No No No L H >1.2 V L No No Yes H L >1.2 V L No Yes No H L >1.2 V L No Yes Yes H L >1.2 V L Yes No No L L >1.2 V L Yes No Yes H L >1.2 V L Yes Yes No H L >1.2 V L Yes Yes Yes H L x H x x x H L x = don't care, FPO = L means: fault is not latched, FPO = H means: fault is latched, PGO = L means: fault, PGO = H means: No fault Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 TPS3513 www.ti.com SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 SCHEMATIC 0.95 V Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 3 TPS3513 SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 www.ti.com TIMING REQUIREMENTS FPO Figure 1. AC Turnon and Overvoltage Protect VDD PSON FPO PGI 3.3 V/5 V 12 V 300 ms 300 ms PGO 38 ms 38 ms 300 ms 3.3-V or 5-V Drop OCP Occurs 300 ms 12-V UVP Occurs Figure 2. Overcurrent and Undervoltage Detect/Protect 4 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 TPS3513 www.ti.com SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 Terminal Functions TERMINAL NAME NO. I/O O DESCRIPTION FPO 3 Inverted fault protection output, open-drain, output stage. A low level indicates that the fault is not latched, while floating indicates that the fault is latched. GND 2 IS12 5 I 12-V overcurrent protection IS5 8 I 5-V overcurrent protection IS33 9 I 3.3-V overcurrent protection NC 7 PGI 1 I Power-good input. A low level indicates that power is not good, while a high (>1.2V) indicates that power is good. PGO 14 O Power-good output, open drain output stage. A low level indicates that power is not good, while floating indicates that power is good. PSON 4 I On/off control. Pull low to enable the PC Power Supply; float to disable it. RI 6 I Current sense setting VDD 13 I Supply voltage VS12 10 I 12-V overvoltage/undervoltage protection VS33 11 I 3.3-V overvoltage protect/undervoltage detect VS5 12 I 5-V overvoltage protect/undervoltage detect Ground No internal connection DETAILED DESCRIPTION Power-Good and Power-Good Delay A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that the 5-VDC and 3.3-VDC outputs are above the undervoltage threshold limit. At this time the converter should be able to provide enough power to assure continuous operation within the specification. Conversely, when either the 5-VDC or the 3.3-VDC output voltages fall below the undervoltage threshold, or when main power has been removed for a sufficiently long time so that power supply operation is no longer assured, PGO should be deasserted to a low state. The power-good (PGO), DC enable (PSON), and the 5-V/3.3-V supply rails are shown in Figure 3. Figure 3. Timing of PSON and PGO Although there is no requirement to meet specific timing parameters, the following signal timings are recommended: 2 ms ≤ t2 ≤ 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 ≤ 10 ms Furthermore, motherboards should be designed to comply with the above recommended timing. If timings other than these are implemented or required, this information should be clearly specified. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 5 TPS3513 SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 www.ti.com The TPS3513 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a 300-ms power-good delay. If the voltage signals at PGI, VS33, and VS5 rise above the undervoltage threshold, the open-drain, power-good output (PGO) will go high after a delay of 300 ms. When the PGI voltage or any of the 3.3-V, 5-V rail drops below the undervoltage threshold, PGO will be disabled immediately. Power-Supply Remote On/Off (PSON) and Fault Protect Output (FPO) Since the latest personal computer generation focuses on easy turnon and power saving functions, the PC power supply will require two characteristics. One is a dc power supply remote on/off function; the other is standby voltage to achieve very low power consumption of the PC system. Thus, the main power needs to be shut down. The power supply remote on/off (PSON) is an active-low signal that turns on all of the main power rails including the 3.3-V, 5-V, -5-V, and -12-V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver current and should be held at 0 V. When the FPO signal is held high due to an occurring fault condition, the fault status will be latched and the outputs of the main power rails should not deliver current and should be held at 0 V. Toggling the power-supply remote on/off (PSON) from low-to-high will reset the fault-protection latch. During this fault condition only the standby power is not affected. When PSON goes from high to low or low-to-high, the 38-ms debounce block will be active to avoid that a glitch on the input will disable/enable the FPO output. During this period, the undervoltage function is disabled to prevent turnon failure. Power should be delivered to the rails only if the PSON signal is held at ground potential, thus, FPO is active low. The FPO pin can be connected to 5 VDC (or up to 15 VDC) through a pullup resistor. Under-Voltage Protection The TPS3513 provides undervoltage protection (UVP) for the 12-V rail and undervoltage detect for the 3.3-V and 5-V rails. When an undervoltage condition appears at the VS12 input pin for more than 150 µs, the FPO output goes high and PGO goes low. Also, this fault condition will be latched until PSON is toggled from low-to-high or VDD is removed. In flyback or forward type off-line switching power supplies, usually designed for small power, the overload protection design is very simple. Most of these type of power supplies are only sensing the input current for an overload condition. The trigger-point needs to be set much higher than the maximum load in order to prevent false turnon. However, this will cause one critical issue. In case that the connected load is larger than the maximum allowable load but smaller than the trigger-point, the system will always become over-heated and cause failure and damage. Overcurrent Protection In bridge or forward type, off-line switching power supplies, usually designed for medium to large power, the overload protection design needs to be very precise. Most of these types of power supplies are sensing the output current for an overload condition. The trigger-point needs to be set higher than the maximum load in order to prevent false turnon. The TPS3513 provides overcurrent protection (OCP) for the 3.3-V, 5-V, and 12-V rails. When an over current condition appears at the OCP comparator input pins for more than 73 µs, the FPO output goes high and PGO goes low. Also, this fault condition will be latched until PSON is toggled from low-to-high or VDD is removed. The resistor connected between the RI pin and the GND pin will introduce an accurate I(ref) for the OCP function. Of course, a more accurate resistor tolerance will be better. The formula for choosing the RI resistor is V(RI)/I(ref). The I(ref) range is from 12.5 µA to 62.5 mA. Three OCP comparators and the I(ref) section are supplied by VS12. Current drawn from the VS12 pin is less than 1 mA. Following is an example on calculating OCP for the 12-V rail: RI = V(RI)/I(ref) = 1.15 V/20 µA = 56 kΩ 6 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 TPS3513 www.ti.com SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 I(ref) x C x R(IS12) = R(sense) x I(OCP_Trip) I(OCP_Trip) = 20 µA x 8 x 560 Ω/0.01 Ω = 9.2 A C = Current ratio (see recommended operating conditions) Overvoltage Protection The overvoltage protection (OVP) of the TPS3513 monitors 3.3 V, 5 V, and 12 V. When an overvoltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 µs, the FPO output goes high and PGO goes low. Also, this fault condition will be latched until PSON is toggled from low-to-high or VDD is removed. During fault conditions, most power supplies have the potential to deliver higher output voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages to be high enough to cause internal or external damage of the system. To protect the system under these abnormal conditions, it is common practice to provide overvoltage protection within the power supply. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD VI VO Supply voltage (2) 16 V Input voltage (2) PSON, IS5, IS33, PGI 8V Input voltage VS33, VS5 16 V Output voltage FPO VDD + 0.3 V or 16 V (whichever is less) PGO VDD + 0.3 V or 8 V (whichever is less) All other pins (2) –0.3 V to 16 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C Tstg Storage temperature range –65°C to 150°C Soldering temperature (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 956 mW 7.65 mW/°C 612 mW 497 mW N 1512 mW 12.1 mW/°C 968 mW 786 mW PACKAGE Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 7 TPS3513 SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS at specified temperature range VDD Supply voltage MIN MAX 4.5 15 PSON, VS5, VS33, IS5, IS33 VI 7 VS12, IS12 Input voltage 15 VDD + 0.3 V (max = 7 V) PGI FPO 15 PGO 7 FPO 20 PGO 10 VO Output voltage IO(Sink) Output sink current tr Supply voltage rising time See IO(RI) Output current RI TA Operating free-air temperature range (1) (1) 1 UNIT V V V V mA ms 12.5 62.5 µA 40 85 °C MIN TYP MAX VDD rising and falling slew rate must be less than 14V/ms. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT OVER-VOLTAGE PROTECTION AND OVER-CURRENT PROTECTION Overvoltage threshold VS33 3.7 3.9 VS5 5.7 6.1 6.5 VS12 13.2 13.8 14.4 7.6 8 8.4 I(ref) Ratio of current sense sink current to current sense setting pin (RI) source current Resistor at RI = 30 kΩ, 0.1% resistor Ilkg Leakage current (FPO) V(FPO) = 5 V VOL Low-level output voltage (FPO) I(sink) = 20 mA, VDD = 5 V Noise deglitch time OVP VDD = 5 V 35 Current source reference voltage VDD = 5 V 1.1 V(RI) 4.1 V 5 µA 0.7 V 73 110 µs 1.15 1.2 V 4.45 V UNDERVOLTAGE LOCKOUT SECTION Start threshold voltage Minimum operation voltage after start-up 3.65 V PGI AND PGO VIT(PGI) Input threshold voltage PGI1 1.10 1.15 1.20 PGI2 0.9 0.95 1 VS33 Undervoltage threshold 2 2.2 2.4 VS5 3.3 3.5 3.7 VS12 8.5 9 9.5 Input offset voltage for OCP comparators Ilkg Leakage current (PGO) VOL Low-level output voltage (PGO) Short-circuit protection delay td(1) Delay time 5 PGO = 5 V I(sink) = 10 mA, VDD = 4.5 V 3.3 V, 5 V PGI to PGO PGI to PGO Noise deglitch time VDD = 5 V PGI to FPO 3.2 VDD = 5 V V V 5 mV 5 µA 0.4 V 49 75 114 ms 200 300 450 4.8 7.2 88 150 PGI to FPO ms 225 µs 12-V UVP to FPO PSON CONTROL II 8 Input pullup current PSON = 0 V Submit Documentation Feedback 120 µA Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 TPS3513 www.ti.com SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.4 UNIT VIH High-level input voltage V VIL Low-level input voltage 1.2 V t(b) Debounce time (PSON) VDD = 5 V 24 38 57 ms td(2) Delay time (PSON to FPO) VDD = 5 V tb +1.1 tb+2.3 tb+4 ms 1 mA TOTAL DEVICE IDD Supply current PSON = 5 V Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 9 TPS3513 SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE INPUT CURRENT (PSON) vs INPUT VOLTAGE (PSON) 20 400 VDD = 4 V TA = −40°C 0 TA = 85°C 200 I I − Input Current − µ A I DD − Supply Current − µ A 300 TA = 25°C 100 TA = 0°C 0 −100 −20 −40 −60 −80 TA = −40°C TA = 0°C TA = 25°C TA = 85°C −100 −200 −120 PGI = 1.4 V PSON = 5 V −300 0 2.5 5 10 7.5 12.5 −140 0 15 1 2 VDD − Supply Voltage − V 5 6 Figure 5. LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) 7 800 VOL − Low-Level Output Voltage − mV VDD = 4 V PSON = GND VOL − Low-Level Output Voltage − V 4 Figure 4. 4 3 TA = 85°C 2 TA = 25°C TA = −40°C 1 TA = 0°C VDD = 4 V PSON = GND Exploded View 700 600 TA = 85°C 500 400 300 TA = −40°C TA = 25°C 200 TA = 0°C 100 0 0 0 100 40 60 80 IOL − Low-Level Output Current − mA 20 120 0 Figure 6. 10 3 VI − Input Voltage − V 5 10 15 20 IOL − Low-Level Output Current − mA 25 Figure 7. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 TPS3513 www.ti.com SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) 4 600 VOL − Low-Level Output Voltage − mV VOL − Low-Level Output Voltage − V VDD = 4 V PSON = GND TA = 85°C 3 2 TA = −40°C TA = 25°C 1 TA = 0°C 0 500 400 TA = 85°C 300 TA = 25°C 200 TA = −40°C 100 TA = 0°C 0 125 50 75 100 IOL − Low-Level Output Current − mA 0 25 150 0 5 10 15 IOL − Low-Level Output Current − mA Figure 8. Figure 9. NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD CURRENT RATIO vs FREE-AIR TEMPERATURE 20 8 1.001 VDD = 4 V PSON = GND 7.99 1 RI = 30 kΩ I(IS5) I(ref) 0.999 Current Ratio Normalized Input Threshold Voltage − VIT(TA)/VIT(25 °C) VDD = 4 V PSON = GND Exploded View 0.998 0.997 0.996 7.98 7.97 7.96 0.995 0.994−40 −15 10 35 60 85 7.95 −40 TA − Free-Air Temperature − °C Figure 10. −20 0 20 40 60 TA − Free-Air Temperature − °C 80 Figure 11. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 11 TPS3513 SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010 www.ti.com REVISION HISTORY Note: Page numbers of current version may differ from previous versions. Changes from Revision A (June 2005) to Revision B Page • Deleted space between OV in the OV Conditions column of Function Table. Also changed 2 H's in FPO column to L's (5th row from bottom and 13th row from bottom) ........................................................................................................... 2 • Changed schematic, Figure 1, and Figure 3 image objects. ................................................................................................ 3 • Added text to descriptions for FPO, PGI, PGO, and PSON pins for clarification. ................................................................ 5 • Changed tb+1.1 in MIN column, delay time row to tb+1.1 ....................................................................................................... 9 12 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): TPS3513 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3513D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS3513D Samples TPS3513DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS3513D Samples TPS3513N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TPS3513N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of