TPS3600D25PW




  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 features typical applications D Supply Current of 40 µA (Max) D Precision Supply Voltage Monitor D D D D D D D D D D D D D D D D D D D D − 2.0 V, 2.5 V, 3.3 V, 5.0 V − Other Versions on Request Watchdog Timer With 800-ms Time-Out Backup-Battery Voltage Can Exceed VDD Power-On Reset Generator With Fixed 100-ms Reset Delay Time Battery OK Output Voltage Monitor for Power-Fail or Low-Battery Monitoring Manual Switchover to Battery-Backup Mode Chip-Enable Gating −3 ns (at VDD = 5 V) Max. Propagation Delay Manual Reset Battery Freshness Seal 14-Pin TSSOP Package Temperature Range . . . −40°C to 85°C Fax Machines Set-Top Boxes Advanced Voice Mail Systems Portable Battery Powered Equipment Computer Equipment Advanced Modems Automotive Systems Portable Long-Time Monitoring Equipment Point of Sale Equipment TSSOP (PW) Package (TOP VIEW) VOUT VDD GND MSWITCH CEIN BATTON PFI 1 2 3 4 5 6 7 VBAT RESET WDI MR CEOUT BATTOK PFO 14 13 12 11 10 9 8 ACTUAL SIZE (5,10mm x 6,60mm) typical operating circuit Address Decoder Power Supply 0.1 µF External Source CEIN Rx VDD VBAT TPS3600 PFI MR uC I/O PFO I/O BATTOK I/O MSWITCH V OUT GND 8 RESET WDI BATTON CE CMOS RAM VCC Address Bus Backup Battery RESET Ry Manual Reset CEOUT CE CMOS RAM VCC RealTime Clock VCC 8 Data Bus 16 I/O Switchover Capacitor 0.1 µF VCC GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright  2000−2007, Texas Instruments Incorporated 
 
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        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 description The TPS3600 family of supervisory circuits monitor and control processor activity. In case of power-fail or brownout conditions, the backup-battery switchover function of TPS3600 allows to run a low-power processor and its peripherals from the installed backup battery without asserting a reset beforehand. During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than Vres. Thereafter, the supply voltage supervisor monitors VOUT and keeps RESET output active as long as VOUT remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. This delay timer starts its time-out, after VOUT has risen above the threshold voltage (VIT). In case of a brownout or power failure of both supply sources, a voltage drop below the threshold voltage (VIT) get detected and the output becomes active (low) again. The product spectrum is designed for supply voltages of 2 V, 2.5 V, 3.3 V, and 5 V. The circuits are available in a 14-pin TSSOP package. They are characterized for operation over a temperature range of −40°C to 85°C. PACKAGE INFORMATION TA DEVICE NAME TPS3600D20 TPS3600D25 −40°C to 85°C TPS3600D33 TPS3600D50 ordering information application specific versions (see Note) TPS360 0 D 20 PW R Reel Package Nominal Supply Voltage Nominal BATTOK Threshold Voltage Functionality Family DEVICE NAME NOMINAL VOLTAGE, VNOM TPS3600x20 PW 2.0 V TPS3600x25 PW 2.5 V TPS3600x33 PW 3.3 V TPS3600x50 PW 5.0 V DEVICE NAME THRESHOLD VOLTAGE, VBOK TPS3600Dxx PW TPS3600Fxx PW{ VIT + 7% VIT + 6% NOMINAL BATTOK TPS3600Hxx PW{ TPS3600Jxx PW{ VIT + 8% VIT + 10% † For the application specific versions, please contact the local TI sales office for availability and lead time. www.ti.com 2 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 FUNCTION TABLES VDD > VSW 0 VOUT > VIT 0 VDD > VBAT 0 MSWITCH MR 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 VBAT > VBOK 0 BATTOK 1 1 VOUT VBAT BATTON RESET CEOUT 1 0 DIS VBAT VBAT 1 0 DIS 1 0 DIS VBAT VDD 1 0 DIS 0 0 DIS VDD VBAT 0 0 DIS 1 0 DIS VBAT VBAT 1 0 DIS 1 0 DIS VBAT VBAT 1 1 EN 1 0 DIS VBAT VDD 1 1 EN 0 0 DIS VDD VBAT 0 1 EN 1 0 DIS VBAT VDD 1 1 EN 0 0 DIS VDD VBAT 0 1 EN 1 0 DIS VBAT VDD 1 1 EN 0 0 DIS VDD VBAT VBAT 0 1 EN 1 0 DIS 1 1 EN 0 CONDITION: VOUT > VDD(min) CEIN CEOUT 0 0 1 1 CONDITION: Enabled PFI > VPFI PFO 0 0 1 1 CONDITION: VOUT > VDD(min) www.ti.com 3 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 functional schematic TPS3600 MR MSWITCH VBAT + _ Switch Control Internal Supply Voltage VDD VOUT BATTON + _ Reference Voltage or 1.15 V BATTOK R1 GND RESET Logic and Timer _ + R2 RESET _ PFO + PFI Oscillator WDI Transition Detector Watchdog Logic and Control VOUT 40 kΩ CEOUT CEIN www.ti.com 4 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 timing diagram VBAT V(BOK) V(SWP) V(SWN) V(IT) VDD t VOUT V(SWN) t RESET t BATTOK 1 0 t BATTON VBAT VDD VBAT VDD VBAT t NOTES: A. MSWITCH = 0, MR = 1 NOTES: B. Timing diagram shown under normal operation, not in freshness seal mode. www.ti.com 5 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BATTOK 9 O Battery status output BATTON 6 O Logic output/external bypass switch driver output CEIN 5 I Chip-enable input CEOUT 10 O Chip-enable output GND 3 I Ground MR 11 I Manual reset input MSWITCH 4 I Manual switch to force device into battery-backup mode (connect to GND if not used) PFI 7 I Power-fail comparator input (connect to GND if not used) PFO 8 O Power-fail comparator output RESET 13 O Active-low reset output VBAT VDD 14 I Backup-battery input 2 I Input supply voltage 1 O Supply output 12 I Watchdog timer input VOUT WDI detailed description battery freshness seal The battery freshness seal of the TPS3600 family disconnects the backup battery from the internal circuitry until it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is put to use. The following steps explain how to enable the freshness seal mode: 1. Connect VBAT (VBAT > VBAT(min)) 2. Ground PFO 3. Connect PFI to VDD or PFI > V(PFI) 4. Connect VDD to power supply (VDD > VIT) 5. Ground MR 6. Power down VDD 7. The freshness seal mode is entered and pins PFO and MR can be disconnected. The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied. BATTOK output This is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks the battery voltage every 200 ms with a voltage divider load of approximately 100 KΩ and a measure cycle on-time of 25 µs. This measurement cycle starts after the reset is released. If the battery voltage VBAT is below the negative-going threshold voltage V(BOK), the indicator BATTOK does a high-to-low transition. Otherwise, its status remains to the VOUT level. Table 1. Typical Values for BATTOK Indication SUPERVISOR TYPE TPS3600D20 VIT TYP 1.78 V VBOK MIN 1.84 V VBOK TYP 1.91 V VBOK MAX 1.97 V TPS3600D25 TPS3600D33 2.22 V 2.3 V 2.38 V 2.46 V 2.93 V 3.04 V 3.14 V TPS3600D50 3.24 V 4.40 V 4.56 V 4.71 V 4.86 V www.ti.com 6 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 detailed description (continued) IBAT 25 µs 200 ms 100 µA t Figure 1. BATTOK Timing chip-enable signal gating The internal gating of chip-enable signals (CE) prevents erroneous data from corrupting CMOS RAM during an under-voltage condition. The TPS3600 use a series transmission gate from CEIN to CEOUT. During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CEIN to CEOUT enables the TPS3600 devices to be used with most processors. The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted. During a power-down sequence when VDD crosses the reset threshold, the CE transmission gate will be disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low during reset is asserted, the CE transmission gate will be disabled same time when CEIN goes high, or 15 µs after reset asserts, whichever occurs first. This will allow the current write cycle to complete during power down. When the CE transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device propagation delay through the CE transmission gate depends on VOUT, the source impedance of the device connected to CEIN and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a low-output-impedance driver be used. During disable mode, the transmission gate is off and an active pullup connects CEOUT to VOUT. This pullup turns off when the transmission gate is enabled. CEIN t CEOUT 15 µs t RESET t Figure 2. Chip-Enable Timing www.ti.com 7 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 detailed description (continued) power-fail comparator (PFI and PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail input (PFI) will be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold, V(PFI), of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above V(PFI) plus about 12-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to ensure that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected. BATTON Most often BATTON is used as a gate drive for an external pass transistor for high-current applications. In addition it can be also used as a logic output to indicate the battery switchover status. BATTON is high when VOUT is connected to VBAT. BATTON can be directly connected to the gate of a PMOS transistor (see Figure 3). No current-limiting resistor is required. When using a PMOS transistor, it must be connected backwards from the traditional method (see Figure 3). This method orients the body diode from VDD to VOUT and prevents the backup battery from discharging through the FET when its gate is high. PMOS FET Body Diode D S G VDD BATTON VOUT TPS3600 GND Figure 3. Driving an External MOSFET Transistor With BATTON backup-battery switchover In the event of a brownout or power failure, it may be necessary to keep a processor running. If a backup battery is installed at VBAT, the devices automatically connect the processor to backup power when VDD fails. In order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, this family of supervisors will not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 2-Ω switch) when VOUT falls below V(SWN) and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until VDD crosses VBAT, or when VDD rises above the threshold V(SWP). (See the timing diagram) VDD > VBAT 1 VDD > V(SW) 1 VOUT VDD 1 0 0 1 VDD VDD 0 0 VBAT www.ti.com 8 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 detailed description (continued) manual switchover (MSWITCH) While operating in the normal mode from VDD, the device can be manually forced to operate in the battery-backup mode by connecting MSWITCH to VDD. The table below shows the different switchover modes. MSWITCH GND VDD mode Battery-backup mode VDD GND VDD STATUS VDD mode Switch to battery-backup mode Battery-backup mode Battery-backup mode If the manual switchover feature is not used, MSWITCH must be connected to ground. watchdog In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important to ensure the correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller, or the DSP have to toggle the watchdog input within typically 0.8 s to avoid a time-out from occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected the watchdog is disabled and will be retriggered internally. saving current while using the watchdog The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead, WDI is externally driven high for the majority of the time-out period, a current of e.g. 5 V/40 kΩ ≈ 125 µA can flow into WDI. VOUT VIT WDI t(tout) RESET td td td Undefined Figure 4. Watchdog Timing www.ti.com 9 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V MR and WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VDD + 0.3 V) All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA All other pins, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000h continuously. DISSIPATION RATING TABLE PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PW 700 mW 5.6 mW/°C 448 mW 364 mW recommended operating conditions at specified temperature range MIN Supply voltage, VDD MAX 1.65 Battery supply voltage, VBAT Input voltage, VI High-level input voltage, VIH UNIT 5.5 V 1.5 5.5 V 0 VOUT + 0.3 V 0.7 x VOUT Low-level input voltage, all other pins, VIL V 0.3 x VOUT V Continuous output current at VOUT, IO 200 Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V 100 ns/V 34 mV/µs 85 °C Slew rate at VDD or VBAT Operating free-air temperature range, TA −40 www.ti.com 10 mA 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL Vres High-level output voltage Low-level output voltage TEST CONDITIONS VOUT = 1.8 V, IOH = −20 µA VOUT = 3.3 V, IOH = −80 µA VOUT = 5.0 V, IOH = −120 µA VOUT − 0.3 V CEOUT Enable mode CEIN = VOUT VOUT = 2.0 V, IOH = −1 mA VOUT = 3.3 V, IOH = −2 mA VOUT = 5.0 V, IOH = −5 mA VOUT − 0.2 V CEOUT Disable mode VOUT = 3.3 V, IOH = −0.5 mA VOUT − 0.4 V RESET, PFO, BATTOK VOUT = 2.0 V, IOL = 400 µA VOUT = 3.3 V, IOL = 2 mA VOUT = 5.0 V, IOL = 3 mA 0.2 0.2 BATTON VOUT = 1.8 V, IOL = 500 µA VOUT = 3.3 V, IOL = 3 mA VOUT = 5.0 V, IOL = 5 mA CEOUT Enable mode CEIN = 0 V VOUT = 2.0 V, IOL = 1 mA VOUT = 3.3 V, IOL = 2 mA VOUT = 5.0 V, IOL = 5 mA 0.2 V(SWN) VBAT > 1.1 V OR VDD > 1.4 V, IOL = 20 µA IO = 5 mA, VDD = 1.8 V IO = 75 mA, VDD = 3.3 V IO = 150 mA, VDD = 5 V IO = 4 mA, VBAT = 1.5 V Battery-backup mode V(PFI) V(BOK) UNIT PFO Power-up reset voltage (see Note 2) VDD to VOUT on-resistance VBAT to VOUT on-resistance Negative-going input threshold voltage (see Notes 3 and 4) MAX RESET, BATTOK, BATTON VOUT VIT TYP VOUT − 0.2 V Normal mode rds(on) MIN VOUT = 2.0 V, IOH = −400 µA VOUT = 3.3 V, IOH = −2 mA VOUT = 5.0 V, IOH = −3 mA IO = 75 mA, VDD = 3.3 V VBAT = 3.3 V VOUT − 0.4 V VOUT − 0.4 V V VOUT − 0.3 V 0.4 0.4 0.3 0.4 VDD − 50 mV VDD − 150 mV VDD − 250 mV VBAT = 3.3 V V 1 2 1 2 1.74 1.78 1.82 TPS3600x25 2.17 2.22 2.27 TPS3600x30 2.57 2.63 2.69 2.87 2.93 2.99 4.31 4.40 4.49 TA = −40 −40°C C to 85 85°C C TPS3600x50 PFI 1.13 TPS3600Dxx Battery switch threshold voltage negative-going VOUT V VBAT − 50 mV VBAT − 150 mV TPS3600x20 TPS3600x33 V 1.15 Ω V 1.17 VIT + 5.8% VIT + 7.1% VIT + 8.3% VIT + 1% VIT + 2% VIT + 3.2% V NOTES: 2. The lowest supply voltage at which RESET becomes active. tr(VDD) ≥ 15 µs/V. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal. 4. Voltage is sensed at VOUT www.ti.com 11 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 electrical characteristics over recommended operating conditions (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS VIT BATTOK Vhys Hysteresis MIN TYP 1.65 V < VIT < 2.5 V 20 2.5 V < VIT < 3.5 V 40 3.5 V < VIT < 5.5 V 50 1.65 V < V(BOK) < 2.5 V 30 2.5 V < V(BOK) < 3.5 V 60 3.5 V < V(BOK) < 5.5 V 100 PFI IIH High-level input current IIL Low-level input current II Input current IOS Short-circuit current VDD = 1.8 V 1.65 V < V(SWN) < 2.5 V 66 V(SWN) 2.5 V < V(SWN) < 3.5 V 100 3.5 V < V(SWN) < 5.5 V 110 WDI (see Note 5) WDI = VDD = 5 V MR MR = 0.7 × VDD, VDD = 5 V WDI (see Note 5) WDI = 0 V, MR MR = 0 V, PFI, MSWITCH VI < VDD PFO = 0 V, VDD = 5 V VDD = 5 V mV 85 150 −33 −76 −150 −110 25 −0.3 PFO = 0 V, VDD = 1.8 V VDD = 3.3 V PFO = 0 V, VDD = 5 V −2.4 VDD supply current VOUT = VDD VOUT = VBAT I(BAT) VBAT supply current VOUT = VDD VOUT = VBAT Ilkg CEIN leakage current Disable mode, VI < VDD −1.1 40 8 −0.1 Ci Input capacitance VI = 0 V to 5.0 V NOTE 5: For details on how to optimize current consumption when using WDI, see the detailed description section. www.ti.com µA −255 −25 IDD 12 UNIT 12 V(BSW) PFO MAX 0.1 40 ±1 5 nA mA A µA µA µA pF 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 timing requirements at RL = 1 MΩ, CL = 50 pF, TA = −40°C to 85°C PARAMETER tw TEST CONDITIONS VDD MR Pulse width WDI VIH = VIT + 0.2 V, VIL = VIT − 0.2 V MIN TYP 5 VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD MAX UNIT µs 1 100 ns switching characteristics at RL= 1 MΩ, CL = 50 pF, TA = −40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td Delay time VDD ≥ VIT + 0.2 V, MR ≥ 0.7 x VDD, See timing diagram 60 100 140 ms t(tout) Watchdog time-out VDD > VIT + 0.2 V, See timing diagram 0.48 0.8 1.12 s tPLH Propagation (delay) time, low-to-high-level output tPHL Propagation (delay) time, high-to-low-level output VOUT = VIT VDD to RESET VIL = VIT − 0.2 V, VIH = VIT + 0.2 V 2 5 µs PFI to PFO VIL = V(PFI) − 0.2 V, VIH = V(PFI) + 0.2 V 3 5 µs 0.1 1 µs 5 15 ns 1.6 5 ns 1 3 ns 3 µs MR to RESET 50% CEIN to 50% CEOUT CL = 50 pF only (see Note 6) Transition time µs 50% RESET to 50% CEOUT VDD ≥ VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD VDD = 1.8 V VDD = 3.3 V VDD = 5 V VIL = VBAT − 0.2 V, VIH = VBAT + 0.2 V, V(BAT) < VIT VDD to BATTON 15 NOTE 6: Ensured by design. TYPICAL CHARACTERISTICS Table of Graphs FIGURE Static Drain-source on-state resistance VDD to VOUT rDS(on) IDD VIT Static Drain-source on-state resistance VBAT to VOUT 5 vs Output current Static Drain-source on-state resistance vs Chip enable input voltage Supply current vs Supply voltage Normalized threshold voltage vs Free-air temperature High-level output voltage at RESET VOH VOL 7 8, 9 10 11, 12 High-level output voltage at PFO vs High-level output current 13, 14 High-level output voltage at CEOUT 15, 16, 17, 18 Low-level output voltage at RESET 19, 20 Low-level output voltage at CEOUT vs Low-level output current Low-level output voltage at BATTON tp(min) 6 21, 22 23, 24 Minimum Pulse Duration at VDD vs Threshold voltage overdrive at VDD 25 Minimum Pulse Duration at PFI vs Threshold voltage overdrive at PFI 26 www.ti.com 13 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS STATIC DRAIN SOURCE ON-STATE RESISTANCE (VBAT TO VOUT) vs OUTPUT CURRENT rDS(on) − Static Drain Source On-State Resistance (V BAT to VOUT) − Ω rDS(on) − Static Drain Source On-State Resistance (V DD to VOUT) − Ω STATIC DRAIN SOURCE ON-STATE RESISTANCE (VDD TO VOUT) vs OUTPUT CURRENT 1.5 TA = 85°C 1.4 1.3 TA = 25°C 1.2 TA = 0°C 1.1 1 TA = −40°C VDD = 3.3 V VBAT = GND MSWITCH = GND 0.9 0.8 50 76 100 125 150 IO − Output Current − mA 175 1.6 VBAT = 3.3 V MSWITCH = VDD 1.5 TA = 85°C 1.4 1.3 TA = 25°C 1.2 TA = 0°C 1.1 TA = −40°C 1 0.9 50 200 75 Figure 5 200 SUPPLY CURRENT vs SUPPLY VOLTAGE 40 7 VBAT Mode VBAT = 5 V MSWITCH = GND 35 6 TA = 25°C 30 I DD − Supply Current − µ A rDS(on) − Static Drain Source On-State Resistance (CEIN to CEOUT) − Ω 175 Figure 6 STATIC DRAIN SOURCE ON-STATE RESISTANCE (CEIN to CEOUT) vs CHIP-ENABLE INPUT VOLTAGE TA = 85°C 25 20 TA = 0°C 15 TA = −40°C 10 5 5 TA = −40°C TA = 0°C 4 TA = 25°C 3 2 TA = 85°C ICEOUT = 5 mA VDD = 5 V MSWITCH = GND 1 0 0 0 1 2 3 4 VCEIN − Chip-Enable Input Voltage − V 5 0 Figure 7 0.5 1 1.5 2 2.5 3 3.5 4 VDD − Supply Voltage − V Figure 8 www.ti.com 14 100 125 150 IO − Output Current − mA 4.5 5 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS NORMALIZED THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 1.001 VBAT Mode VDD = GND or MSWITCH = GND 25 20 VDD Mode VBAT = GND MSWITCH = GND TA = 25°C VIT − Normalized Threshold Voltage − V I DD(BAT)− Supply Current − µ A 30 TA = 0°C TA = 85°C 15 TA = −40°C 10 5 1 2 3 4 VDD − Supply Voltage − V 5 0.999 0.998 0.997 0.996 0.995 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 TA − Free-Air Temperature − °C 0 0 1 6 Figure 9 Figure 10 HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT 5.1 VDD = 5 V VBAT = GND MSWITCH = GND 5 VOH − High-Level Output Voltage at RESET − V VOH− High-Level Output Voltage at RESET − V 6 TA = −40°C TA = 25°C 4 TA = 0°C 3 2 TA = 85°C 1 Expanded View 5 TA = −40°C 4.9 TA = 25°C TA = 0°C 4.8 4.7 TA = 85°C VDD = 5 V VBAT = GND MSWITCH = GND 4.6 4.5 0 0 −5 −10 −15 −20 −25 −30 IOH − High-Level Output Current − mA 0 −35 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 IOH − High-Level Output Current − mA Figure 11 Figure 12 www.ti.com 15 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE AT PFO vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT PFO vs HIGH-LEVEL OUTPUT CURRENT 5.55 5 VOH − High-Level Output Voltage at PFO − V VOH − High-Level Output Voltage at PFO − V 6 TA = −40°C TA = 25°C 4 TA = 0°C 3 TA = 85°C 2 VDD = 5.5 V PFI = 1.4 V VBAT = GND MSWITCH = GND 1 0 0 Expanded View 5.50 TA = −40°C 5.45 5.35 5.30 5.20 5.15 −2.5 VDD = 5.5 V PFI = 1.4 V VBAT = GND MSWITCH = GND 0 −20 −40 −60 −80 −100 −120 −140 −160 −180 −200 IOH − High-Level Output Current − µA Figure 14 HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT 3.35 3.5 V(CEIN)= 3.3 V VDD = 5 V MSWITCH = GND Enable Mode 3 VOH − High-Level Output Voltage at CEOUT − V VOH − High-Level Output Voltage at CEOUT − V TA = 85°C 5.25 Figure 13 TA = −40°C 2.5 TA = 25°C 2 TA = 0°C 1.5 1 TA = 85°C 0.5 0 V(CEIN) = 3.3 V VDD = 5 V MSWITCH = GND Expanded View Enable Mode 3.30 TA = −40°C TA = 25°C TA = 0°C 3.25 3.20 TA = 85°C 3.15 3.10 −10 −30 −50 −70 −90 −110 −130 −150 IOH − High-Level Output Current − mA Figure 15 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 IOH − High-Level Output Current − mA Figure 16 www.ti.com 16 TA = 0°C 5.40 5.10 −0.5 −1 −1.5 −2 IOH − High-Level Output Current − mA TA = 25°C 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT 3.5 3.5 3 VOH − High-Level Output Voltage at CEOUT − V VOH − High-Level Output Voltage at CEOUT − V HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT TA = −40°C 2.5 TA = 25°C TA = 0°C 2 1.5 TA = 85°C 1 Disable Mode V(CEIN) = open VDD = 1.65 V MSWITCH = GND 0.5 0 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 3.3 TA = −40°C 3.2 TA = 25°C TA = 0°C 3.1 TA = 85°C 3 2.9 2.8 2.7 0 −0.1 −0.2 −0.3 −0.4 −0.5 −0.6 −0.7 −0.8 −0.9 −1 −4 −4.5 IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA Figure 17 Figure 18 LOW-LEVEL OUTPUT VOLTAGE AT RESET vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE AT RESET vs LOW-LEVEL OUTPUT CURRENT 500 3.5 VOL − Low-Level Output Voltage at RESET − mV VOL − Low-Level Output Voltage at RESET − V V(CEIN) = open VDD = 1.65 V MSWITCH = GND Expanded View Disable Mode 3.4 VDD = 3.3 V VBAT = GND MSWITCH = GND 3 2.5 TA = 0°C 2 TA = 25°C 1.5 TA = 85°C 1 TA = −40°C 0.5 0 0 5 10 15 20 IOL − Low-Level Output Current − mA 25 Figure 19 Expanded View TA = 85°C VDD = 3.3 V VBAT = GND MSWITCH = GND 400 TA = 25°C 300 TA = 0°C 200 TA = −40°C 100 0 0 1 2 3 4 IOL − Low-Level Output Current − mA 5 Figure 20 www.ti.com 17 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE AT CEOUT vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE AT CEOUT vs LOW-LEVEL OUTPUT CURRENT VOL− Low-Level Output Voltage at CEOUT − mV VOL− Low-Level Output Voltage at CEOUT − V 3.5 Enable Mode V(CEIN) = GND VDD = 5 V MSWITCH = GND 3 2.5 TA = 85°C 2 TA = 25°C TA = 0°C 1.5 TA = −40°C 1 0.5 140 V(CEIN) = GND VDD = 5 V MSWITCH = GND 120 TA = 85°C 100 TA = 25°C 80 TA = 0°C 60 TA = −40°C 40 20 0 0 0 10 20 30 40 50 60 70 80 90 IOL − Low-Level Output Current − mA 0 100 1 VOL − Low-Level Output Voltage at BATTON − mV VOL − Low-Level Output Voltage at BATTON − V Enable Mode VDD = 3.3 V VBAT = GND MSWITCH = GND TA = 85°C TA = 0°C TA = 25°C 1.5 1 TA = −40°C 0.5 0 0 5 10 15 20 25 IOL − Low-Level Output Current − mA 30 5 400 VDD = 3.3 V VBAT = GND MSWITCH = GND 350 Enable Mode Expanded View TA = 85°C 300 TA = 25°C 250 TA = 0°C 200 150 TA = −40°C 100 50 0 0 1 2 3 4 IOL − Low-Level Output Current − mA Figure 23 Figure 24 www.ti.com 18 4 LOW-LEVEL OUTPUT VOLTAGE AT BATTON vs LOW-LEVEL OUTPUT CURRENT 3.5 2 3 Figure 22 LOW-LEVEL OUTPUT VOLTAGE AT BATTON vs LOW-LEVEL OUTPUT CURRENT 2.5 2 IOL − Low-Level Output Current − mA Figure 21 3 Enable Mode Expanded View 5 



  

        SLVS336B − DECEMBER 2000 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS TPS3600D50 MINIMUM PULSE DURATION AT VDD vs THRESHOLD OVERDRIVE AT VDD Minimum Pulse Duration at VCC− µ s 10 9 8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VT(0) − Threshold Overdrive at VDD − V Figure 25 TPS3600D50 MINIMUM PULSE DURATION AT PFI vs THRESHOLD OVERDRIVE AT PFI Minimum Pulse Duration at PFI − µ s 5 4.6 VDD = 1.65 V 4.2 3.8 3.4 3 2.6 2.2 1.8 1.4 1 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Threshold Overdrive at PFI − V 1 Figure 26 www.ti.com 19 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS3600D20PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D20 TPS3600D20PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D20 TPS3600D25PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D25 TPS3600D33PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D33 TPS3600D33PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D33 TPS3600D33PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D33 TPS3600D50PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3600D50 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of