TPS3610U18PWRG4



 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 features typical applications D Supply Current of 40 µA (Max) D Battery Supply Current of 100 nA (Max) D Precision Supply-Voltage Monitor, D D D D D D D D D 1.8 V, 5 V; Other Options on Request D Watchdog Timer With 800-ms Time-Out D Backup-Battery Voltage Can Exceed VDD D Power-On Reset Generator With Fixed D D D D D D D 100-ms Reset Delay Time Battery-OK Output Voltage Monitor for Power-Fail or Low-Battery Monitoring Manual Switchover to Battery-Backup Mode Chip-Enable Gating . . . 3 ns (at VDD = 5 V) Max Propagation Delay Battery-Freshness Seal 14-pin TSSOP Package Temperature Range . . . –40°C to 85°C Fax Machines Set-Top Boxes Advanced Voice Mail Systems Portable Battery-Powered Equipment Computer Equipment Advanced Modems Automotive Systems Portable Long-Time Monitoring Equipment Point of Sale Equipment TPS3610 TSSOP (PW) Package (TOP VIEW) VOUT VDD GND MSWITCH CEIN BATTON PFI typical operating circuit 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VBAT RESET WDI LOWLINE CEOUT BATTOK PFO ACTUAL SIZE (5,10mm x 6,60mm) Address Decoder Power Supply 0.1 µF External Source CEIN Rx Ry CEOUT VDD VBAT TPS3610 PFI Backup Battery uC 8 RESET RESET WDI I/O PFO I/O BATTOK I/O BATTON LOWLINE MSWITCH V OUT GND CE CMOS RAM VCC Address Bus Switchover Capacitor 0.1 µF CE CMOS RAM VCC RealTime Clock VCC 8 Data Bus 16 I/O I/O VCC GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated 
 
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 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 description The TPS3610 family of supervisory circuits monitors and controls processor activity by providing backup-battery switchover for data retention of CMOS RAM. Other features include an additional power-fail comparator, low-line indication, watchdog function, battery-status indicator, manual switchover, and write protection for CMOS RAM. The TPS3610 family allow usage of 3-V or 3.6-V lithium batteries as the backup supply in systems with, e.g., VDD = 1.8 V. During power-on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V. Thereafter, the supply-voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. The product spectrum is designed for supply voltages of 1.8 V and 5 V. The circuits are available in a 14-pin TSSOP package. TPS3610 devices are characterized for operation over a temperature range of –40°C to 85°C. standard and application-specific versions (see Note 1) TPS3610U 18 PW R Tape and Reel TI Package Designator Nominal Supply Voltage Nominal Battok Threshold Voltage APPLICATION-SPECIFIC VERSIONS, NOMINAL SUPPLY AND BATTOK VOLTAGE TA 40°C to 85°C –40°C NOMINAL SUPPLY VOLTAGE, VDD(NOM) (V) 1.8 NOMINAL BATTOK THRESHOLD VOLTAGE, VIT(BOK) (V) 1.6 5 2.4 PACKAGED DEVICES TSSOP (PW)† TPS3610U18PWR TPS3610T50PWR † The PW package is only available taped and reeled (indicated by the R suffix on the device type). NOTE 1: For other NOMINAL and BATTOK voltage versions, contact your local TI sales office for availability and order lead time. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 TRUTH TABLES INPUTS VDD > VLL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VDD > VIT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OUTPUTS VDD > VBAT 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSWITCH 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BATTOK VBAT > VBOK 0 1 Condition: VDD > VIT VOUT VBAT VBAT VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT BATTON LOWLINE RESET CEOUT 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DIS DIS DIS DIS DIS DIS DIS DIS DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN POWER-FAIL CHIP-ENABLE BATTOK PFI > V(PFI) PFO CEIN CEOUT 0 1 0 1 0 1 0 1 0 1 Condition: VDD > VDDmin POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Condition: Enabled 3 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 functional block diagram MSWITCH VBAT + _ Switch Control VOUT Internal Power Supply VDD BATTON + _ Reference Voltage of 1.15 V _ RESET Logic + Timer + GND BATTOK RESET + _ LOWLINE Oscillator _ PFI WDI PFO + Transition Detector Watchdog Logic + Control VOUT 40 kΩ CEOUT CEIN 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 timing diagram VBAT VLL VIT VBOK VDD VOUT t BATTOK 1 t VBAT 0 t RESET td td t BATTON t LOWLINE t † MSWITCH = 0 Timing diagram shown under operation, not in freshness seal mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 Terminal Functions TERMINAL NAME I/O NO. DESCRIPTION BATTOK 9 O Battery status output BATTON 6 O Logic output/external bypass switch driver output CEIN 5 I Chip-enable input CEOUT 10 O Chip-enable output GND 3 I Ground LOWLINE 11 O Early power-fail warning output MSWITCH 4 I Manual switch to force device into battery-backup mode VOUT PFI 1 O Supply output 7 I Power-fail comparator input PFO 8 O Power-fail comparator output RESET 13 O Active-low reset output VBAT VDD 14 I Backup-battery input 2 I Input supply voltage WDI 12 I Watchdog timer input detailed description battery freshness seal The battery freshness seal of the TPS3610 family disconnects the backup battery from internal circuitry until it is needed. This function ensures that the backup battery connected to VBAT is fresh when the final product is put to use. The following steps explain how to enable the freshness seal mode: 1. Connect VBAT (VBAT > VBATmin) 2. Ground PFO 3. Connect PFI to VDD (PFI = VDD) 4. Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied. BATTOK output BATTOK is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks the battery voltage every 200 ms with a voltage divider load of approximately 100 kΩ and a measurement cycle on-time of 25 µs. The measurement cycle starts after the reset is released. If the battery voltage VBAT is below the negative-going threshold voltage VIT(BOK), the indicator BATTOK does a high-to-low transition. Otherwise it retains its status to VDD level. IBAT 25 µs 200 ms 100 µA t Figure 1. BATTOK Timing 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 detailed description (continued) chip-enable signal gating The internal gating of chip-enable signals, CE, prevents erroneous data from corrupting CMOS RAM during an undervoltage condition. The TPS3610 use a series transmission gate from CEIN to CEOUT. During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CEIN to CEOUT enables TPS3610 devices to be used with most processors. The CE transmission gate is disabled and CEIN is high-impedance (disable mode) while reset is asserted. During a power-down sequence, when VDD crosses the reset threshold, the CE transmission gate is disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low while reset is asserted, the CE transmission gate is disabled at the same time CEIN goes high, or 15 µs after RESET asserts, whichever occurs first. This allows the current write cycle to complete during power-down. When the CE transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device propagation delay through the CE transmission gate depends on VOUT, the source impedance of the device connected to CEIN and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a low-output-impedance driver should be used. During disable mode, the transmission gate is off and an active pullup connects CEOUT to VOUT. The pullup turns off when the transmission gate is enabled. CEIN t CEOUT 15 µs t RESET t Figure 2. Chip-Enable Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 detailed description (continued) power-fail comparator (PFI and PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input (PFI) is compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold VIT(PFI) of typical 1.15 V, the power-fail output (PFO) goes low. If VIT(PFI) goes above V(PFI), plus about 12-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to assure that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, PFI should be connected to ground and PFO left unconnected. LOWLINE The lowline comparator monitors VDD with a threshold voltage typically 2% above the reset threshold (VIT). For normal operation (VDD above the reset threshold), LOWLINE is pulled to VDD. LOWLINE can be used to provide a nonmaskable interrupt (NMI) to the processor when power begins to fall. In most battery-operated portable systems, reserve energy in the battery provides enough time to complete the shutdown routine once the low-line warning is encountered and before reset asserts. If the system must also contend with a more rapid VDD fall time, such as when the main battery is disconnected or a high-side switch is opened during normal operation, a capacitor can be used on the VDD line to provide enough time for executing the shutdown routine. First, the worst-case settling time (tsd) required for the system to perform its shutdown routine needs to be defined. Then, using the worst-case load current (IL) that can be drained from the capacitor, and the minimum reset threshold voltage (VITmin), the capacitor value (CH) can be calculated as follows: CH + I L t sd V ITmin 0.012 BATTON Most often BATTON is used as a gate drive for an external pass transistor for high-current applications. In addition, it can be used as a logic output to indicate the battery switchover status. BATTON is high when VOUT is connected to VBAT. BATTON can be connected directly to the gate of a PMOS transistor (see Figure 3). No current-limiting resistor is required. If a PMOS transistor is used, it must be connected in the reverse of the traditional method (see Figure 3), which orients the body diode from VDD to VOUT and prevents the backup battery from discharging through the FET when its gate is high. PMOS FET Body Diode D S G VDD BATTON VOUT TPS3610 GND Figure 3. Driving an External MOSFET Transistor With BATTON 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 detailed description (continued) backup-battery switchover In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup-battery is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In order to allow the backup-battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors do not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until VDD crosses VBAT, or until VDD rises above the reset threshold VIT. VOUT connects to VDD through a 1-Ω (max) PMOS switch when VDD crosses the reset threshold. VDD – Normal Supply Voltage – V FUNCTION TABLE VDD > VBAT 1 VDD > VIT 1 VOUT VDD 1 0 0 1 VDD VDD 0 0 VBAT VDD Mode VIT Hysteresis VBAT Mode VBSW Hysteresis Undefined VBAT – Backup-Battery Supply Voltage – V Figure 4. Normal Supply Voltage vs Backup-Battery Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 detailed description (continued) manual switchover (MSWITCH) While operating in the normal mode from VDD, the device can be forced manually to operate in battery-backup mode by connecting MSWITCH to VDD. Refer to Table 1 for different switchover modes. Table 1. Switchover Modes MSWITCH GND VDD mode VDD GND Batter back p mode Battery-backup VDD STATUS VDD mode Switch to battery-backup mode Battery-backup mode Battery-backup mode If the manual switchover feature is not used, MSWITCH must be connected to ground. watchdog In a microprocessor- or DSP-based system, it is important not only to supervise the supply voltage, but also to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller or DSP has to toggle the watchdog input within typically 0.8 s to avoid the occurence of a time-out. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected, the watchdog is disabled and is retriggered internally. saving current while using the watchdog The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then the input momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), WDI should be left low for the majority of the watchdog time-out period, and pulsed low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the timeout period, a current of, e.g., 5 V/40 kΩ ≈ 125 µA, can flow into WDI. VOUT VIT WDI t(tout) RESET td td Undefined Figure 5. Watchdog Timing 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 td 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Continuous output current at VOUT, IO(VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Continuous output current (all other pins) IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h continuously. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PW 700 mW 5.6 mW/°C 448 mW 364 mW recommended operating conditions Supply voltage, VDD Battery supply voltage, VBAT Input voltage, VI High-level input voltage, VIH MIN MAX 1.65 5.5 V 1.5 5.5 V 0 VDD+0.3 V 0.7xVDD Low-level input voltage, VIL V 0.3×VDD 300 Continuous output current at VOUT, IO Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V Slew rate at VDD or VBAT Operating free-air temperature range, TA –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V mA 100 ns/V 1 V/µs 85 °C 11 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS RESET, BATTOK BATTON VOH High-level output voltage O LOWLINE, PFO CEOUT, CEOUT Enable mode, CEIN = VOUT CEOUT, Disable mode RESET, PFO, RESET PFO BATTOK, LOWLINE VOL Low-level Low level out output ut voltage BATTON CEOUT CEOUT, Enable mode, CEIN = 0 V Power-up reset voltage (see Note 3) Normal mode VOUT Battery backup mode Battery-backup IOH = –400 µA IOH = –2 mA VDD = 5 V, VOUT = 1.8 V, IOH = –3 mA IOH = –400 µA VOUT = 3.3 V, VOUT = 5 V, IOH = –2 mA IOH = –3 mA VDD = 1.8 V, VDD = 3.3 V, IOH = –20 µA IOH = –80 µA, VDD = 5 V, VOUT = 1.8 V, IOH = –120 µA IOH = –1 mA VOUT = 3.3 V, VOUT = 5 V, IOH = –2 mA IOH = –5 mA VOUT–0.3 03V VOUT = 3.3 V, IOH = –0.5 mA VOUT–0.4 V VDD = 1.8 V, VDD = 3.3 V, IOL = 400 µA IOL = 2 mA VDD = 5 V, VOUT = 1.8 V, IOL = 3 mA IOL = 500 µA VOUT = 3.3 V, VOUT = 5 V, IOL = 3 mA IOL = 5 mA VOUT = 1.8 V, VOUT = 3.3 V, IOL = 1 mA IOL = 2 mA VOUT = 5 V, IOL = 5 mA VBAT > 1.1 V, OR VDD > 1.1 V, IOL = 20 µA, IO = 8.5 mA, VBAT = 0 V VDD = 1.8 V, IO = 125 mA, VBAT = 0 V VDD = 3.3 V, IO = 200 mA, VBAT = 0 V VDD = 5 V, IO = 0.5 mA, VBAT = 1.5 V IO = 7.5 mA, VBAT = 3.3 V VDD = 0 V, VDD = 0 V, NOTE 3: The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V 12 MIN VDD = 1.8 V, VDD = 3.3 V, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX UNIT VDD–0.2 V 04V VDD–0.4 VOUT–0.2 V VOUT–0.4 04V VDD–0.3 V V VDD–0.4 04V VOUT–0.2 V 0.2 04 0.4 0.2 04 0.4 V 0.2 03 0.3 0.4 V VDD–50 mV VDD–150 mV VDD–200 mV VBAT–20 mV VBAT–113 mV V 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER VIT V(PFI) Negative-going Negative going input in ut threshold voltage g ((see Note 4)) V(BOK) MIN TYP MAX TPS3610U18 TEST CONDITIONS 1.68 1.71 1.74 TPS3610T50 4.46 4.55 4.64 PFI 1.13 1.15 1.17 2.33 2.4 2.47 TA = –40°C 40 C to 85°C 85 C TPS3610T50 TPS3610U18 V(LL) LOWLINE 1.55 1.6 1.65 VIT+1.2% VIT+2% 20 VIT+2.8% 1.65 V < VIT < 2.5 V VIT LOWLINE Vh s hys Hysteresis BATTOK 2.5 V < VIT < 3.5 V 40 3.5 V < VIT < 5.5 V 60 1.65 V < V(LL) < 2.5 V 20 2.5 V < V(LL) < 3.5 V 40 3.5 V < V(LL) < 5.5 V 60 1.65 V < V(BOK) < 2.5 V 20 2.5 V < V(BOK) < 3.5 V 40 3.5 V < V(BOK)< 5.5 V 60 PFI V V mV 12 VBSW (see Note 5) IIH IIL High-level input current II Input current PFI, MSWITCH IOS Short-circuit output current PFO Low-level input current UNIT WDI (see Note 6) VDD = 1.8 V 55 WDI = VDD = 5 V WDI = 0 V, 150 VDD = 5 V –150 –25 PFO = 0 V 25 VDD = 1.8 V VDD = 3.3 V –0.3 VDD = 5 V –2.4 –1.1 VOUT = VDD 40 VOUT = VBAT 40 IDD Supply current at VDD IBAT Supply current at VBAT Ilkg Leakage current at CEIN Disable mode, rDS(on) DS( ) VDD to VOUT on-resistance VBAT to VOUT on-resistance VDD = 5 V VBAT = 3.3 V VOUT = VDD –0.1 0.1 VOUT = VBAT 0.5 ±1 VI < VDD 0.6 1 8 15 µA nA mA µA µA µA Ω Ci Input capacitance VI = 0 V to 5 V 5 pF NOTES: 4. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals. 5. For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT 6. For details on how to optimize current consumption when using WDI. Refer to detailed description section, watchdog. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 timing requirements at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C PARAMETER tw TEST CONDITIONS At VDD Pulse width VIH = VIT + 0.2 V, VIL = VIT –0.2 V VDD = VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD At WDI MIN TYP MAX UNIT 6 µs 100 ns switching characteristics at RL = 1 MΩ, CL = 50 pF, TA =–40°C to 85°C PARAMETER td t(tout) tPLH TEST CONDITIONS Delay time VDD > VIT +0.2 V (see timing diagram Watchdog timeout Propagation (delay) time, low-tohigh-level output tPHL tt Propagation (delay) time time, high-tolow-level output Transition time VDD to RESET TYP MAX UNIT 60 100 140 ms 0.48 0.8 1.12 s µs 15 50% RESET to 50% CEOUT 50% CEIN to 50% CEOUT,, F only l ((see N CL = 50 pF Note 7)) MIN VDD = 1.8 V VDD = 3.3 V VDD = 5 V VIL = VIT–0.2 V, VIH = VIT+0.2 V PFI to PFO VIL = V(PFI)–0.2 V, VIH = V(PFI)+0.2 V VDD to BATTON VIH = VBAT + 200 mV, VIL = VBAT – 200 mV, VBAT < VIT 5 15 1.6 5 1 3 2 5 3 5 ns µss µs 3 NOTE 7: Specified by design TYPICAL CHARACTERISTICS Table of Graphs FIGURE Static drain-source on-state resistance (VDD to VOUT) rDS(on) IDD VIT Static drain-source on-state resistance (VBAT to VOUT) 6 vs Output current vs Input voltage at CEIN 8 Supply current vs Supply voltage 9 Normalized threshold at RESET vs Free-air temperature High-level output voltage at RESET VOH VOL High-level output voltage at PFO 10 11, 12 vs High-level High level output out ut current 13, 14 High-level output voltage at CEOUT 15, 16, 17, 18 Low-level output voltage at RESET 19, 20 Low-level output voltage at CEOUT vs Low-level Low level output out ut current Low-level output voltage at BATTON 14 7 Static drain-source on-state resistance 21, 22 23, 24 tp(min) Minimum Pulse Duration at VDD vs Threshold overdrive at VDD 25 tp(min) Minimum Pulse Duration at PFI vs Threshold overdrive at PFI 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 1000 VDD = 3.3 V VBAT = GND MSWITCH = GND 900 TA = 85°C 800 TA = 25°C 700 TA = 0°C TA = –40°C 600 500 50 75 100 125 150 175 200 – Static Drain-Source On-State Resistance – Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE (VDD to VOUT) vs OUTPUT CURRENT rDS(on) rDS(on) – Static Drain-Source On-State Resistance – mΩ TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE (VBAT to VOUT) vs OUTPUT CURRENT 20 VBAT = 3.3 V MSWITCH = GND 17.5 15 TA = 85°C 12.5 TA = 25°C TA = 0°C 10 7.5 5 2.5 TA = –40°C 4.5 IO – Output Current – mA 6.5 8.5 10.5 12.5 IO – Output Current – mA Figure 7 Figure 6 STATIC DRAIN-SOURCE ON-STATE RESISTANCE (CEIN to CEOUT) vs INPUT VOLTAGE AT CEIN SUPPLY CURRENT vs SUPPLY VOLTAGE 40 30 35 TA = 85°C 30 25 20 TA = 0°C 15 TA = –40°C 10 ICEOUT = 5 mA VDD = 5 V MSWITCH = GND 5 1 2 3 4 VI(CEIN) – Input Voltage at CEIN – V 20 VDD Mode VBAT = GND MSWITCH = GND TA = 25°C TA = 0°C TA = 85°C 15 TA = –40°C 10 5 0 0 VBAT Mode VBAT = 2.6 V or MSWITCH = GND 25 TA = 25°C I DD– Supply Current – µ A rDS(on) – Static Drain Source On-State Resistance (CEIN to CEOUT) – Ω 14.5 5 0 0 1 Figure 8 2 3 4 VDD – Supply Voltage – V 5 6 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TPS3610T50 VIT – Normalized Threshold Voltage at RESET – V NORMALIZED THRESHOLD AT RESET vs FREE-AIR TEMPERATURE 1.001 1 0.999 0.998 0.997 0.996 0.995 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TA – Free-Air Temperature – °C Figure 10 HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT 5.1 VDD = 5 V VBAT = GND MSWITCH = GND 5 VOH – High-Level Output Voltage at RESET – V VOH– High-Level Output Voltage at RESET – V 6 TA = –40°C TA = 25°C 4 TA = 0°C 3 2 TA = 85°C 1 Expanded View 5 TA = –40°C 4.9 TA = 25°C TA = 0°C 4.8 4.7 TA = 85°C VDD = 5 V VBAT = GND MSWITCH = GND 4.6 4.5 0 0 –5 –10 –15 –20 –25 –30 IOH – High-Level Output Current – mA –35 0 –0.5 –1 –1.5 Figure 11 16 –2 –2.5 –3 –3.5 –4 –4.5 –5 IOH – High-Level Output Current – mA Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE AT PFO vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT PFO vs HIGH-LEVEL OUTPUT CURRENT 5.55 5 VOH – High-Level Output Voltage at PFO – V VOH – High-Level Output Voltage at PFO – V 6 TA = –40°C TA = 25°C 4 TA = 0°C 3 TA = 85°C 2 VDD = 5.5 V PFI = 1.4 V VBAT = GND MSWITCH = GND 1 0 0 Expanded View 5.50 TA = –40°C 5.45 TA = 0°C 5.40 5.35 5.30 TA = 85°C 5.25 5.20 5.15 5.10 –0.5 –1 –1.5 –2 IOH – High-Level Output Current – mA TA = 25°C –2.5 VDD = 5.5 V PFI = 1.4 V VBAT = GND MSWITCH = GND 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 IOH – High-Level Output Current – µA Figure 13 Figure 14 HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT 3.35 V(CEIN)= 3.3 V VDD = 5 V MSWITCH = GND Enable Mode 3 TA = –40°C 2.5 TA = 25°C 2 TA = 0°C 1.5 1 TA = 85°C 0.5 0 VOH – High-Level Output Voltage at CEOUT – V VOH – High-Level Output Voltage at CEOUT – V 3.5 V(CEIN) = 3.3 V VDD = 5 V MSWITCH = GND Expanded View Enable Mode 3.30 TA = –40°C TA = 25°C TA = 0°C 3.25 TA = 85°C 3.20 3.15 3.10 –10 –30 –50 –70 –90 –110 –130 –150 IOH – High-Level Output Current – mA 0 –0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5 –5 IOH – High-Level Output Current – mA Figure 15 Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT 3.5 3.5 3 VOH – High-Level Output Voltage at CEOUT – V VOH – High-Level Output Voltage at CEOUT – V HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT TA = –40°C 2.5 TA = 25°C TA = 0°C 2 1.5 TA = 85°C 1 Disable Mode V(CEIN) = open VDD = 1.65 V MSWITCH = GND 0.5 0 0 –0.5 –1 –1.5 –2 –2.5 –3 –3.5 3.3 TA = –40°C 3.2 TA = 25°C TA = 0°C 3.1 TA = 85°C 3 2.9 2.8 2.7 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1 –4 –4.5 IOH – High-Level Output Current – mA IOH – High-Level Output Current – mA Figure 17 Figure 18 LOW-LEVEL OUTPUT VOLTAGE AT RESET vs LOW-LEVEL OUTPUT CURRENT 500 3.5 VOL – Low-Level Output Voltage at RESET – mV VOL – Low-Level Output Voltage at RESET – V LOW-LEVEL OUTPUT VOLTAGE AT RESET vs LOW-LEVEL OUTPUT CURRENT VDD = 3.3 V VBAT = GND MSWITCH = GND 3 2.5 TA = 0°C 2 TA = 25°C 1.5 TA = 85°C 1 TA = –40°C 0.5 0 0 5 10 15 20 IOL – Low-Level Output Current – mA 25 Expanded View TA = 25°C 300 TA = 0°C 200 TA = –40°C 100 0 0 1 2 3 4 IOL – Low-Level Output Current – mA Figure 20 POST OFFICE BOX 655303 TA = 85°C VDD = 3.3 V VBAT = GND MSWITCH = GND 400 Figure 19 18 V(CEIN) = open VDD = 1.65 V MSWITCH = GND Expanded View Disable Mode 3.4 • DALLAS, TEXAS 75265 5 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE AT CEOUT vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE AT CEOUT vs LOW-LEVEL OUTPUT CURRENT VOL– Low-Level Output Voltage at CEOUT – mV VOL– Low-Level Output Voltage at CEOUT – V 3.5 Enable Mode V(CEIN) = GND VDD = 5 V MSWITCH = GND 3 2.5 TA = 85°C 2 TA = 25°C TA = 0°C 1.5 TA = –40°C 1 0.5 140 V(CEIN) = GND VDD = 5 V MSWITCH = GND 120 TA = 85°C 100 TA = 25°C 80 TA = 0°C 60 TA = –40°C 40 20 0 0 0 10 20 30 40 50 60 70 80 90 IOL – Low-Level Output Current – mA 0 100 1 VOL – Low-Level Output Voltage at BATTON – mV VOL – Low-Level Output Voltage at BATTON – V Enable Mode VDD = 3.3 V VBAT = GND MSWITCH = GND TA = 85°C TA = 0°C TA = 25°C 1.5 1 TA = –40°C 0.5 0 0 5 4 5 LOW-LEVEL OUTPUT VOLTAGE AT BATTON vs LOW-LEVEL OUTPUT CURRENT 3.5 2 3 Figure 22 LOW-LEVEL OUTPUT VOLTAGE AT BATTON vs LOW-LEVEL OUTPUT CURRENT 2.5 2 IOL – Low-Level Output Current – mA Figure 21 3 Enable Mode Expanded View 10 15 20 25 IOL – Low-Level Output Current – mA 30 400 VDD = 3.3 V VBAT = GND MSWITCH = GND 350 Enable Mode Expanded View TA = 85°C 300 TA = 25°C 250 TA = 0°C 200 150 TA = –40°C 100 50 0 0 1 2 3 4 5 IOL – Low-Level Output Current – mA Figure 23 Figure 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 


 

     

 SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TPS3610T50 MINIMUM PULSE DURATION AT VDD vs THRESHOLD OVERDRIVE AT VDD Minimum Pulse Duration at VDD – µ s 10 9 8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Threshold Overdrive at VDD – V Figure 25 TPS3610T50 MINIMUM PULSE DURATION AT PFI vs THRESHOLD OVERDRIVE AT PFI Minimum Pulse Duration at PFI – µ s 5 4.6 VDD = 1.65 V 4.2 3.8 3.4 3 2.6 2.2 1.8 1.4 1 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Threshold Overdrive at PFI – V Figure 26 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS3610T50PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610T50PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610T50PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610T50PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610U18PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610U18PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610U18PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3610U18PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS3610T50PWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 7.0 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3610T50PWR TSSOP PW 14 2000 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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