TPS3700-Q1
SLVSCI7C – MARCH 2014 – REVISED MARCH 2021
TPS3700-Q1 Automotive High Voltage (18V) Window Voltage Detector With Internal
Reference for Over and Undervoltage Monitoring
1 Features
3 Description
•
•
The TPS3700-Q1 wide-supply window voltage
detector operates over a 1.8 V to 18 V range. The
device has two high-accuracy comparators with an
internal 400-mV reference and two open-drain outputs
rated to 18 V for overvoltage and undervoltage
detection. The TPS3700-Q1 device can be used as
a window voltage detector or as two independent
voltage monitors; the monitored voltage can be set
with the use of external resistors. For even wider input
voltage capability up to 65 V, see the TPS37A-Q1 or
the TPS38A-Q1 devices.
•
•
•
•
•
•
•
The OUTA terminal is driven low when the voltage at
the INA+ terminal drops below (VIT+ – V hys), and goes
high when the voltage returns above the respective
threshold (VIT+). The OUTB terminal is driven low
when the voltage at the INB– terminal rises above
VIT+, and goes high when the voltage drops below the
respective threshold (VIT+ – Vhys). Both comparators
in the TPS3700-Q1 device include built-in hysteresis
for filtering to reject brief glitches, thereby ensuring
stable output operation without false triggering.
2 Applications
The TPS3700-Q1 device is available in a Thin SOT-6
and a 1.5-mm x 1.5-mm WSON-6 package and is
specified over the junction temperature range of –
40°C to 125°C.
Advanced Driver Assistance System (ADAS)
ADAS Domain Controller
Digital cockpit
Automotive Infotainment & Cluster
HEV/EV OBC and wireless charger
Industrial Robot
Device Information
ORDER NUMBER
TPS3700-Q1
(1)
VMON
PACKAGE (1)
BODY SIZE
SOT23 (6)
2.90 mm × 1.60 mm
WSON (6)
1.50 mm x 1.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1.8 V to 18 V
0.1 µF
VDD
R1
OUTA
•
•
•
•
•
•
RP1
OUTA
INA+
RP2
R2
Device
INA+
VIT+
INB±
VIT+
Output vs Input Thresholds and Hysteresis
OUTB
INB–
R3
To a reset
or enable
input of
the system.
OUTB
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Wide Supply Voltage Range: 1.8 V to 18 V
Adjustable Threshold: Down to 400 mV
Open-Drain Outputs for Overvoltage and
Undervoltage Detection
Low Quiescent Current: 5.5 µA (typ)
High Threshold Accuracy:
– 1% Over Temperature
– 0.25% (typ)
Internal Hysteresis: 5.5 mV (typ)
Available in ThinSOT23-6 and WSON Packages
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3700-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Timing Diagram ..........................................................6
6.8 Switching Characteristics............................................6
6.9 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................11
8 Application and Implementation.................................. 12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................16
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 17
11 Device and Documentation Support..........................18
11.1 Documentation Support.......................................... 18
11.3 Electrostatic Discharge Caution.............................. 18
11.4 Glossary.................................................................. 18
12 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2017) to Revision C (March 2021)
Page
• Added bullet for Functional Safety-Capable device............................................................................................1
• Added links to TI.com applications pages.......................................................................................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document, corrected
part# to GPN in device information.....................................................................................................................1
• Moved Storage temperature range here in the Absolute Maximum Ratings from the section previously called
handling ratings (which also included ESD ratings) when the ESD ratings section was updated per the latest
format..................................................................................................................................................................4
• Corrected table formatting, descriptions and the notes in ESD Ratings section per the latest standards..........4
• Corrected Input Voltage Max on INA+, INB- from 6 V to 6.5 V to match the device capability...........................4
• Added missing Thermal Information for the DSE package.................................................................................4
• Added the missing max start-up delay spec and corrected corresponding note 2............................................. 5
Changes from Revision A (April 2014) to Revision B (July 2017)
Page
• Added WSON Package to Device Information Table..........................................................................................1
• Added WSON Package to Pin Configuration and Function table ...................................................................... 3
Changes from Revision * (March 2014) to Revision A (April 2014)
Page
• Changed device status from Product Preview to Production Data. ................................................................... 1
2
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5 Pin Configuration and Functions
OUTA
1
6
OUTB
GND
2
5
VDD
INA+
3
4
INB-
Figure 5-1. DDC Package
SOT-6
Top View
OUTB
1
6
OUTA
VDD
2
5
GND
INB-
3
4
INA+
Figure 5-2. DSE Package
WSON-6
Top View
Table 5-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
DDC
DSE
GND
2
5
—
INA+
3
4
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal drops below the threshold voltage (VIT+ –
VHYS), OUTA is driven low.
INB–
4
3
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal exceeds the threshold voltage (VIT+), OUTB is
driven low.
OUTA
1
6
O
INA+ comparator open-drain output. OUTA is driven low when the voltage at this
comparator is below (VIT+ – VHYS). The output goes high when the sense voltage returns
above the respective threshold (VIT+).
OUTB
6
1
O
INB– comparator open-drain output. OUTB is driven low when the voltage at this
comparator exceeds VIT+. The output goes high when the sense voltage returns below
the respective threshold (VIT+ – VHYS).
VDD
5
2
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
MIN
MAX
VDD
–0.3
20
V
OUTA, OUTB
–0.3
20
V
INA+, INB–
–0.3
7
V
40
mA
Operating junction temperature, TJ
–40
125
°C
Storage temperature range, Tstg
-65
150
°C
Voltage(2)
Current
Output terminal current
UNIT
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2)
All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Electrosatic discharge
VESD
(1)
Q100-002(1)
±2500
Charge device model (CDM), per AEC Q100-011
±1000
Human body model (HBM), per AEC
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Supply voltage
1.8
18
V
VI
Input voltage
INA+, INB–
0
6.5
V
VO
Output voltage
OUTA, OUTB
0
18
V
6.4 Thermal Information
TPS3700-Q1
THERMAL
DDC (SOT)
DSE (WSON)
6 pins
6 pins
RθJA
Junction-to-ambient thermal resistance
174.0
160.7
RθJC(top)
Junction-to-case (top) thermal resistance
81.5
101.9
RθJB
Junction-to-board thermal resistance
47.2
68.8
ψJT
Junction-to-top characterization parameter
22.0
5.4
ψJB
Junction-to-board characterization parameter
46.9
68.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
(1)
4
METRIC(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
VDD
TEST CONDITIONS
Supply voltage range
V(POR)
VIT+
Power-on reset
voltage(1)
Positive-going input threshold voltage
MIN
TYP
1.8
18
VOLmax = 0.2 V, I(OUTA/B) = 15 µA
VDD = 1.8 V
396
MAX
400
UNIT
V
0.8
V
404
mV
VDD = 18 V
396
400
404
mV
VDD = 1.8 V
387
394.5
400
mV
VDD = 18 V
387
394.5
400
mV
5.5
12
mV
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (hys = VIT+ – VIT–)
I(INA+)
I(INB–)
Input current (at the INA+ or INB–
terminal)
VDD = 1.8 V and 18 V, VI = 6.5 V
–25
1
25
nA
VDD = 1.8 V and 18 V, VI = 0.1 V
–15
1
15
nA
VDD = 1.3 V, IO = 0.4 mA
250
mV
VOL
Low-level output voltage
VDD = 1.8 V, IO = 3 mA
250
mV
VDD = 5 V, IO = 5 mA
250
mV
VDD = 1.8 V and 18 V, VO = VDD
300
nA
Ilkg(OD)
Open-drain output leakage-current
VDD = 1.8 V, VO = 18 V
VDD = 1.8 V, no load
IDD
Supply current
5.5
(1)
Undervoltage
µA
6
13
µA
VDD = 12 V
6
13
µA
7
13
µA
150
450
µs
1.7
V
VDD = 18 V
UVLO
nA
11
VDD = 5 V
Startup delay(2)
lockout(4)
300
VDD falling
1.3
The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2)
During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state.
(3)
High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–).
(4)
When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR).
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6.6 Timing Requirements
Over operating temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
tPHL
High-to-low propagation delay(3)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV
See Figure 6-1
18
µs
tPLH
Low-to-high propagation delay(3)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV
See Figure 6-1
29
µs
6.7 Timing Diagram
VDD
VIT+
Vhys
INA+
OUTA
tPHL
tPLH
tPLH
VIT+
Vhys
INB–
OUTB
tPLH
tPHL
Figure 6-1. Timing Diagram
6.8 Switching Characteristics
Over operating temperature range (unless otherwise noted)
PARAMETER
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Output rise time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
2.2
µs
tf
Output fall time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
0.22
µs
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6.9 Typical Characteristics
At TJ = 25°C and VDD = 5 V, unless otherwise noted.
10
Positive-Going Input Threshold (mV)
401
9
Supply Current (µA)
8
7
6
5
4
3
40qC
0qC
25qC
85qC
125qC
2
1
2
4
6
8
10
12
Supply Voltage (V)
14
16
D001
1.8 V
5V
1.2 V
18 V
399.8
399.4
-25
-10
5
20
35
50
65
Temperature (qC)
80
95
110 125
D003
Figure 6-3. Rising Input Threshold Voltage (VIT+) vs
Temperature
9
Low-to-High Propagation Delay (µs)
31
8
Hysteresis Voltage (mV)
=
=
=
=
400.2
18
Figure 6-2. Supply Current (IDD) vs Supply Voltage (VDD)
7
6
5
VDD
VDD
VDD
VDD
4
3
-40
-25
-10
5
20
35
50
65
Temperature (qC)
80
95
=
=
=
=
1.8 V
5V
12 V
18 V
18
26
16
Input Pulse Duration (µs)
20
24
22
20
18
16
VDD = 1.8 V, INB to OUTB
VDD = 18 V, INB to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
10
8
-40
-25
-10
5
20 35 50 65
Temperature (qC)
25
23
21
19
17
15
13
11
-25
80
95
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D005
Figure 6-5. Propagation Delay vs Temperature (High-to-Low
Transition at the Inputs)
28
12
27
D004
30
14
VDD = 1.8 V, INB to OUTB
VDD = 18 V, INB to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
29
9
-40
110 125
Figure 6-4. Hysteresis (Vhys) vs Temperature
Low-to-High Propagation Delay (µs)
400.6
399
-40
0
0
VDD
VDD
VDD
VDD
INA+
INB–
14
12
10
8
6
4
2
110 125
D006
Figure 6-6. Propagation Delay vs Temperature (Low-to-High
Transition at the Inputs)
0
2.5
4
5.5
7
8.5
10
11.5
13
14.5
Positive-Going Input Threshold Overdrive (%)
16
D007
INA+ = negative spike below VIT–
INB– = positive spike above VIT+
Figure 6-7. Minimum Pulse Width vs Threshold Overdrive
Voltage
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6.9 Typical Characteristics (continued)
At TJ = 25°C and VDD = 5 V, unless otherwise noted.
2000
10
1750
Low-Level Output Voltage(mV)
11
Supply Current (µA)
9
8
7
6
5
4
40qC
0qC
25qC
85qC
125qC
3
2
4
8
12
16
20
24
28
Output Sink Current (mA)
32
36
750
500
250
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
D009
Figure 6-9. Output Voltage Low (VOL) vs Output Sink Current
(–40°C)
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
Low-Level Output Voltage (mV)
Low-Level Output Voltage(mV)
1000
D008
2000
1500
1250
1000
750
500
250
0
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
0
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
0
5
10
D010
Figure 6-10. Output Voltage Low (VOL) vs Output Sink Current
(0°C)
15
20
25
30
Output Sink Current (mA)
35
40
D011
Figure 6-11. Output Voltage Low (VOL) vs Output Sink Current
(25°C)
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
Low-level output voltage (mV)
1750
Low-level output voltage (mV)
1250
40
Figure 6-8. Supply Current (IDD) vs Output Sink Current
1500
1250
1000
750
500
250
1500
1250
1000
750
500
250
0
0
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
0
D012
Figure 6-12. Output Voltage Low (VOL) vs Output Sink Current
(85°C)
8
1500
0
1
0
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
5
10
15
20
25
30
Output Sink Current (mA)
35
40
D013
Figure 6-13. Output Voltage Low (VOL) vs Output Sink Current
(125°C)
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7 Detailed Description
7.1 Overview
The TPS3700-Q1 device combines two comparators for overvoltage and undervoltage detection. The TPS3700Q1 device is a wide-supply voltage range (1.8 to 18 V) device with a high-accuracy rising input threshold of 400
mV (1% over temperature) and built-in hysteresis. The outputs are also rated to 18 V and can sink up to 40 mA.
The TPS3700-Q1 device is designed to assert the output signals, as shown in Table 7-1. Each input terminal
can be set to monitor any voltage above 0.4 V using an external resistor divider network. With the use of two
input terminals of different polarities, the TPS3700-Q1 device forms a window voltage detector. Broad voltage
thresholds can be supported that allow the device to be used in a wide array of applications.
Table 7-1. TPS3700-Q1 Truth Table
CONDITION
OUTPUT
INA+ > VIT+
OUTA high
Output A not asserted
STATUS
INA+ < VIT–
OUTA low
Output A asserted
INB– > VIT+
OUTB low
Output B asserted
INB– < VIT–
OUTB high
Output B not asserted
7.2 Functional Block Diagram
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
7.3 Feature Description
7.3.1 Inputs (INA+, INB–)
The TPS3700-Q1 device combines two comparators. Each comparator has one external input (inverting and
noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed
and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling
hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation.
The INA+ and INB- inputs can swing from ground to 6.5 V, regardless of the device supply voltage used.
Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor
at the comparator input for extremely noisy applications in order to reduce sensitivity to transients and layout
parasitics.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops
below (VIT+ – Vhys). When the voltage exceeds VIT+, the output (OUTA) goes to a high-impedance state; see
Figure 6-1.
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB–
exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state;
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see Figure 6-1 . Together, these comparators form a window-detection function as discussed in the Section 7.3.3
section.
7.3.2 Outputs (OUTA, OUTB)
In a typical TPS3700-Q1 application, the outputs are connected to a reset or enable input of the processor
(such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA],
or application-specific integrated circuit [ASIC]) or the outputs are connected to the enable input of a voltage
regulator (such as a DC-DC or low-dropout regulator [LDO]).
The TPS3700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to
hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to
the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels.
The TPS3700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. To ensure proper
voltage levels, some thought should be given while choosing the pullup resistor values. The pullup resistor value
is determined by VOL, sink-current capability, and output-leakage current (Ilkg(OD)). These values are specified in
the Section 6.5 table. By using wired-AND logic, OUTA and OUTB can merge into one logic signal.
Table 7-1 and the Section 7.3.1 section describe how the outputs are asserted or de-asserted. See Figure 6-1 for
a timing diagram that describes the relationship between threshold voltages and the respective output.
7.3.3 Window Voltage Detector
The inverting and noninverting configuration of the comparators forms a window voltage detector circuit using
a resistor divider network, as shown in Figure 7-1 and Figure 7-2. The input terminals can monitor any system
voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor for
undervoltage and overvoltage conditions, respectively.
VMON
(13.2 V to 10.8 V)
1.8 V to 18 V
VDD
RP1
(50 kW)
IN
OUTA
INA+
Voltage
Regulator VO
R2
(13.7 kW)
EN
Device
OUTB
INB–
R3
(69.8 kW)
OUT
R1
(2.21 MW)
UV VMON OV
OUT
GND
Figure 7-1. Window Voltage Detector Block Diagram
10
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Overvoltage
Limit
VMON
Undervoltage
Limit
OUTB
OUTA
Figure 7-2. Window Voltage Detector Timing Diagram
7.3.4 Immunity to Input Terminal Voltage Transients
The TPS3700-Q1 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity
to transients is dependent on both transient duration and amplitude; see the Minimum Pulse Width vs Threshold
Overdrive Voltage curve (Figure 6-7) in the Section 6.9 section.
7.4 Device Functional Modes
The TPS3700-Q1 has a single functional mode, which is on when VDD is greater than 1.8 V.
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8 Application and Implementation
8.1 Application Information
The TPS3700-Q1 device is a wide-supply voltage window voltage detector that operates over a VDD range
of 1.8-V to 18-V. The device has two high-accuracy comparators with an internal 400-mV reference and two
open-drain outputs rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a
window voltage detector or as two independent voltage monitors. The monitored voltages are set with the use of
external resistors.
8.1.1 VPULLUP to a Voltage Other Than VDD
The outputs are often tied to VDD through a resistor. However some applications may require the outputs to
be pulled up to a higher or lower voltage than VDD in order to correctly interface with the reset and enable the
terminal of other devices.
VPULLUP
(Up To 18 V)
1.8 V to 18 V
VDD
OUTA
INA+
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 8-1. Interfacing to Voltages Other Than VDD
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8.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
VDD
OUTA
INA+
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 8-2. Monitoring the Same Voltage as VDD
8.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired thresholds in connected to the rail that is being monitored.
VMON
(26.4 V to 21.7 V)
1.8 V to 18 V
R1
(2.61 MW)
VDD
OUTA
INA+
R2
(8.06 kW)
Device
OUTB
INB–
R3
(40.2 kW)
To a reset or enable input
of the system.
GND
NOTE: The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network.
Figure 8-3. Monitoring a Voltage Other Than VDD
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8.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
Some applications may want to monitor for overvoltage conditions on one rail while also monitoring for
undervoltage conditions on a different rail. In those applications two independent resistor dividers will need
to be used.
1.8 V to 18 V
OUTA
INA+
To a reset or enable
input of the system.
Device
12 V
OUTB
INB–
INA+
VIT+
INB–
VIT+
OUTB
5V
OUTA
VDD
GND
NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is driven low when an
overvoltage condition is detected at the 12-V rail.
Figure 8-4. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail
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8.2 Typical Application
VDD
C1
0.1 µF
VPULLUP
R4
49.9 k
U1
TPS3700DDC
R1
2.21 M
VDD
INA+
INB±
R2
13.7 k
5
1
3
6
4
2
R5
49.9 k
OUTA
OUTB
GND
R3
69.8 k
Figure 8-5. Typical Application Schematic
8.2.1 Design Requirements
8.2.1.1 Input Supply Capacitor
Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance
(ESR) capacitor across the VDD terminal and GND terminal is good analog design practice. A higher-value
capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located
close to the power source.
8.2.1.2 Input Capacitors
Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor
from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor
placement reduces device sensitivity to transients.
8.2.2 Detailed Design Procedure
Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltage.
RT = R1 + R2 + R3
(1)
Select a value for RT such that the current through the divider is approximately 100-times higher than the input
current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as
a result of low-input bias current without adding significant error to the resistive divider. See the application note
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.
Use Equation 2 to calculate the value of R3.
R3 =
RT
VMON(OV)
´ VIT+
(2)
where
•
VMON(OV) is the target voltage at which an overvoltage condition is detected
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Use Equation 3 or Equation 4 to calculate the value of R2.
RT
R2 =
VMON (no UV)
´ VIT+ - R3
(3)
where
•
VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises
RT
R2 =
VMON(UV)
´ (VIT+ - Vhys)
- R3
(4)
where:
VMON(UV) is the target voltage at which an undervoltage condition is detected
•
8.2.3 Application Curves
TJ = 25°C
OUTB
C2
(2 V/div)
C1
(2 V/div)
C2
(2 V/div)
OUTB
OUTA
C3
(2 V/div)
C1
(2 V/div)
C3
(2 V/div)
VDD
Time (100 µs/div)
VDD = 5 V
OUTA
V(INA+) = 390 mV
VDD
Time (100 µs/div)
G013
V(INB–) = 410 mV
Figure 8-6. Startup Delay (Outputs Pulled Up to
VDD)
VDD = 5 V
V(INA+) = 410 mV
G014
V(INB–) = 390 mV
Figure 8-7. Startup Delay (Outputs Pulled Up to
VDD)
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.8 V and 18 V.
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10 Layout
10.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog
design practice. The pullup resistors can be separated if separate logic functions are needed (see Figure 10-1)
or both resistors can be tied to a single pullup resistor if a logical AND function is desired.
VPULLUP
VPULLUP
10.2 Layout Example
Figure 10-1. TPS3700-Q1 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Using the TPS3700 as a Negative Rail Over- and Undervoltage Detector, SLVA600
• Optimizing Resistor Dividers at a Comparator Input, SLVA450
• TPS3700EVM-114 Evaluation Module, SLVU683
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3700QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PD7Q
TPS3700QDSERQ1
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
5O
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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