TPS3707-50DR

TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 TPS370x-xx Processor Supervisory Circuits With Power-Fail 1 Features 3 Description • The TPS370x-xx family of microprocessor supplyvoltage supervisors provide circuit initialization and timing supervision, primarily for DSP and processorbased systems. • • • • • • • Power-on reset generator with fixed delay time of 200 ms (no external capacitor needed) Precision supply voltage monitor: 2.5 V, 3 V, 3.3 V, and 5 V Pin-for-pin compatible with the MAX705 through MAX708 Series Integrated watchdog time (TPS3705-xx Only) Voltage monitor for power-fail or low-battery warning Maximum supply current of 50 µA 8-Pin MSOP and 8-Pin SOIC packages Temperature range: –40°C to 85°C (–40°C to 125°C for TPS3705-33) During power-on, RESET is asserted when the supply voltage V DD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active as long as V DD remains below the threshold voltage VIT+. When the supply voltage drops below the threshold voltage V IT–, the output becomes active (low) again. No external components are required. All the devices of this family have a fixedsense threshold voltage VIT– set by an internal voltage divider. 2 Applications • • • • • • • • The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in either 8-pin MSOP or standard SOIC packages. The TPS370x-xx devices are characterized for operation over a temperature range of −40°C to 85°C. Designs using DSPs, microcontrollers, or microprocessors Industrial equipment Programmable controls Automotive systems Portable or battery powered equipment Intelligent instruments Wireless communication systems Notebook or desktop computers Device Information (1) PART NUMBER TPS3705-xx, TPS3707-xx (1) PACKAGE BODY SIZE (NOM) MSOPPowerPAD™ (8) 3.00 mm × 3.00 mm SOIC (8) 3.90 mm × 4.90 mm For all available packages, see the orderable addendum at the end of the data sheet. 12 V 5V VDD VDD PFO TPS3705−50 MR RESET MSP430P112 100 nF RESET/NMI 910 kΩ WDO I/O WDI I/O PFI 120 kΩ GND GND Copyright © 2016, Texas Instruments Incorporated Typical MSP430 Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 1 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 6.1 Pin Functions.............................................................. 4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................7 7.6 Electrical Characteristics for TPS3705-33 Only..........8 7.7 Timing Requirements.................................................. 8 7.8 Switching Characteristics............................................9 7.9 Dissipation Ratings..................................................... 9 7.10 Timing Diagram.......................................................10 7.11 Typical Characteristics.............................................11 8 Detailed Description......................................................16 8.1 Overview................................................................... 16 8.2 Functional Block Diagram......................................... 16 8.3 Feature Description...................................................16 8.4 Device Functional Modes..........................................17 9 Application and Implementation.................................. 18 9.1 Application Information............................................. 18 9.2 Typical Application.................................................... 18 10 Power Supply Recommendations..............................19 11 Layout........................................................................... 20 11.1 Layout Guidelines................................................... 20 11.2 Layout Example...................................................... 20 12 Device and Documentation Support..........................21 12.1 Receiving Notification of Documentation Updates..21 12.2 Support Resources................................................. 21 12.3 Trademarks............................................................. 21 12.4 Electrostatic Discharge Caution..............................21 12.5 Glossary..................................................................21 13 Mechanical, Packaging, and Orderable Information.................................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (July 2017) to Revision F (October 2020) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated Device Comparison Table by adding -40°C to 125°C for TPS3705-33D............................................. 3 • Updated Absolute Maximum Ratings table to include Operating Temperature of -40°C to 125°C for TPS3705-33D..................................................................................................................................................... 5 • Added TPS3705-33 Electrical Table................................................................................................................... 8 • Added histograms............................................................................................................................................. 11 Changes from Revision D (May 2016) to Revision E (July 2017) Page • Updated package body sizes in the Device Information table............................................................................ 1 Changes from Revision C (December 2005) to Revision D (May 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 5 Device Comparison Table PACKAGED DEVICES TA –40°C to 85°C –40°C to 125°C THRESHOLD VOLTAGE SMALL OUTLINE (D) POWER-PAD µ-SMALL OUTLINE (DGN) 2.63 V TPS3705−30D TPS3705−30DGN TIAAT TPS3705-30Y 4.55 V TPS3705−50D TPS3705−50DGN TIAAV TPS3705−50Y 2.25 V TPS3707−25D TPS3707−25DGN TIAAW TPS3707−25Y 2.63 V TPS3707−30D TPS3707−30DGN TIAAX TPS3707−30Y 2.93 V TPS3707−33D TPS3707−33DGN TIAAY TPS3707−33Y 4.55 V TPS3707−50D TPS3707−50DGN TIAAZ TPS3707−50Y 2.93 V TPS3705−33D TPS3705−33DGN TIAAU TPS3705−33Y Copyright © 2020 Texas Instruments Incorporated MARKING DGN PACKAGE CHIP FORM (Y) Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 3 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 6 Pin Configuration and Functions MR 1 8 WDO MR 1 8 RESET VDD 2 7 RESET VDD 2 7 RESET GND 3 6 WDI GND 3 6 NC PFI 4 5 PFO PFI 4 5 PFO Figure 6-1. TPS3705-xx D Package 8-Pin SOIC Top View Figure 6-2. TPS3707-xx D Package 8-Pin SOIC Top View RESET 1 8 WDI RESET 1 8 NC WDO 2 7 PFO RESET 2 7 PFO MR 3 6 PFI MR 3 6 PFI VDD 4 5 GND VDD 4 5 GND Figure 6-3. TPS3705-xx DGN Package 8-Pin MSOP- Figure 6-4. TPS3707-xx DGN Package 8-Pin MSOPPowerPAD Top View PowerPAD Top View 6.1 Pin Functions PIN NAME 4 TPS3705-xx SOIC TPS3707-xx MSOP-PowerPAD I/O SOIC MSOP-PowerPAD GND 3 5 3 5 — MR 1 3 1 3 I DESCRIPTION Ground Manual reset NC — — 6 8 — PFI 4 6 4 6 I Power-fail comparator input PFO 5 7 5 7 O Power-fail comparator output RESET 7 1 7 1 O Active-low reset output RESET — — 8 2 O Active-high reset output VDD 2 4 2 4 — Supply voltage WDI 6 8 — — I Watchdog timer input WDO 8 2 — — O Watchdog timer output Submit Document Feedback No internal connection Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN Supply voltage, VDD (2) MAX UNIT 7 V PFI voltage range, VPFI –0.3 VDD + 0.3 V All other pins(2) –0.3 7 V Maximum low output current, IOL 5 mA Maximum high output current, IOH –5 mA Input clamp current, IIK (VI < 0 or VI > VDD) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ±20 mA Continuous total power dissipation See Section 7.9 Soldering temperature 260 °C Operating temperature, TA –40 85 °C Operating temperature, TA for TPS3705-33 only –40 125 °C Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000h continuously. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD Supply voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage Δt/ΔV Input transition rise and fall rate at MR or WDI TA Operating free-air temperature TA Operating free-air temperature for TPS3705-33 only Copyright © 2020 Texas Instruments Incorporated NOM MAX UNIT 2 6 V 0 VDD + 0.3 V 0.7 × VDD V 0.3 × VDD V 100 ns/V –40 85 °C –40 125 °C Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 5 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.4 Thermal Information THERMAL TPS3705-xx TPS3707-xx D (SOIC) DGN (MSOP-PowerPAD) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 118.2 66.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 64.4 62.6 °C/W RθJB Junction-to-board thermal resistance 58.5 45.1 °C/W ψJT Junction-to-top characterization parameter 15.8 7.6 °C/W ψJB Junction-to-board characterization parameter 57.9 44.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 18.5 °C/W (1) 6 METRIC(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TPS370x-xx, VDD = 1.1 V, IOH = –4 μA VOH VOL High-level output voltage Low-level output voltage Power-up reset VIT– voltage(1) Negative-going input threshold voltage(2) Negative-going input threshold voltage, PFI(2) Vhys Hysteresis, VDD Hysteresis, PFI MIN TYP MAX 0.8 TPS3707-25, TPS370x-30, TPS370x-33, VDD = VIT+ + 0.2 V, IOH = –500 μA 0.7 × VDD TPS370x-50, VDD = VIT+ + 0.2 V, IOH = –800 μA VDD – 1.5 TPS370x-xx, VDD = 6 V, IOH = –800 μA VDD – 1.5 V TPS3707-25, TPS370x-30, TPS370x-33, VDD = VIT+ + 0.2 V, IOL = 1 mA 0.3 TPS370x-50, VDD = VIT+ + 0.2 V, IOL = 2.5 mA 0.4 TPS370x-xx, VDD = 6 V, IOL = 3 mA 0.4 VDD ≥ 1.1 V, IOL = 50 μA 0.3 TPS3707-25, TA = 0°C to 85°C 2.2 TPS370x-30, TA = 0°C to 85°C 2.57 2.63 2.68 TPS370x-33, TA = 0°C to 85°C 2.87 2.93 2.98 TPS370x-50, TA = 0°C to 85°C 2.25 4.45 4.55 4.63 2.2 2.25 2.32 TPS370x-30, TA = –40°C to 85°C 2.57 2.63 2.7 TPS370x-33, TA = –40°C to 85°C 2.87 2.93 3 TPS370x-50, TA = –40°C to 85°C 4.45 4.55 4.65 1.2 1.25 1.3 TPS3707-25 40 TPS370x-30 50 TPS370x-33 50 TPS370x-50 70 TPS370x-xx 10 V V 2.3 TPS3707-25, TA = –40°C to 85°C TPS370x-xx, VDD ≥ 2 V, TA = –40°C to 85°C UNIT V mV IIH(AV) Average high-level input current, WDI WDI = VDD = 6 V, time average (dc = 88%) 100 150 µA IIL(AV) WDI = 0 V, VDD = 6 V, time average (dc = 12%) –15 –20 µA IIH IIL II IDD Ci (1) (2) Average low-level input current, WDI High-level input current, WDI WDI = VDD = 6 V 120 170 High-level input current, MR MR = 0.7 × VDD, VDD = 6 V –130 –180 Low-level input current, WDI WDI = 0 V, VDD = 6 V –120 –170 Low-level input current, MR MR = 0 V, VDD = 6 V –430 –600 Input current, PFI VDD = 6 V, 0 V ≤ VI ≤ VDD 0 1 TPS3705-xx, VDD = 2 V to 6 V, MR = VDD, MR, WDI and outputs unconnected 30 50 TPS3707-xx, VDD = 2 V to 6 V, MR = VDD, MR, WDI and outputs unconnected 20 50 Supply current Input capacitance –1 µA µA µA µA VI = 0 V to VDD 5 pF The lowest supply voltage at which RESET becomes active, tr,VDD ≥ 15 µs/V To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 7 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.6 Electrical Characteristics for TPS3705-33 Only over operating free-air temperature range -40 to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 1.1 V, IOH = –4 μA VOH VOL VIT– Vhys High-level output voltage MIN TYP MAX 0.8 VDD = VIT+ + 0.2 V, IOH = –500 μA 0.7 × VDD VDD = 6 V, IOH = –800 μA VDD – 1.5 V VDD = VIT+ + 0.2 V, IOL = 1 mA 0.3 VDD = 6 V, IOL = 3 mA 0.4 Power-up reset voltage(1) VDD ≥ 1.1 V, IOL = 50 μA 0.3 Negative-going input threshold voltag TA = 0°C to 125°C 2.87 2.93 3 TA = –40°C to 125°C 2.87 2.93 3.02 Negative-going input threshold voltage, PFI(2) VDD ≥ 2 V 1.2 1.25 1.3 Low-level output voltage UNIT Hysteresis, VDD 50 Hysteresis, PFI 10 V V V mV IIH(AV) Average high-level input current, WDI WDI = VDD = 6 V, time average (dc = 88%) 100 150 µA IIL(AV) Average low-level input current, WDI WDI = 0 V, VDD = 6 V, time average (dc = 12%) –15 –20 µA High-level input current, WDI WDI = VDD = 6 V 120 170 High-level input current, MR MR = 0.7 × VDD, VDD = 6 V –130 –180 Low-level input current, WDI WDI = 0 V, VDD = 6 V –120 –170 Low-level input current, MR MR = 0 V, VDD = 6 V –430 –600 II Input current, PFI VDD = 6 V, 0 V ≤ VI ≤ VDD 0 1 µA IDD Supply current VDD = 2 V to 6 V, MR = VDD, MR, WDI and outputs unconnected 30 50 µA Ci Input capacitance VI = 0 V to VDD IIH IIL –1 5 µA µA pF 7.7 Timing Requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C (unless otherwise noted) PARAMETER tw 8 Pulse width TEST CONDITIONS MIN At VDD, VDD = VIT+ + 0.2 V, VDD = VIT– – 0.2 V 6 µs 100 ns At MR and WDI, VDD ≥ VIT+ + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD Submit Document Feedback NOM MAX UNIT Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.8 Switching Characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tt(out) Watchdog time out VDD ≥ VIT+ + 0.2 V, see Figure 7-1 1.1 1.6 2.3 s td Delay time VDD ≥ VIT+ + 0.2 V, see Figure 7-1 140 200 280 ms tPHL Propagation (delay) time, high-to-low-level output MR to RESET delay, VDD ≥ VIT+ + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 50 250 ns tPLH Propagation (delay) time, low-to-high-level output MR to RESET delay (TPS3707-xx only) VDD ≥ VIT+ + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 50 250 ns tPHL Propagation (delay) time, high-to-low-level output VDD to RESET delay 3 5 µs tPLH Propagation (delay) time, low-to-high-level output VDD to RESET delay (TPS3707-xx only) 3 5 µs tPHL Propagation (delay) time, high-to-low-level output PFI to PFO delay, VDD = 2 V to 6 V 0.5 1 µs tPLH Propagation (delay) time, low-to-high-level output PFI to PFO delay, VDD = 2 V to 6 V 0.5 1 µs 7.9 Dissipation Ratings TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C DGN 2.14 W 17.1 mW/°C 1.37 W 1.11 W D 725 mW 5.8 mW/°C 464 mW 377 mW PACKAGE Copyright © 2020 Texas Instruments Incorporated TA = 70°C POWER RATING TA = 85°C POWER RATING Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 9 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.10 Timing Diagram VDD 5V 4.5 V 1.1 V 0V t MR 5V 4.5 V 1.1 V 0V RESET t td td td 5V 4.5 V 1.1 V 0V t Undefined Behavior Don’t Care 1.1 V Don’t Care 5V 4.5 V Don’t Care WDI 0V WDO t t t(out) 5V 4.5 V 1.1 V 0V t Figure 7-1. Timing Diagrams 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 50 1.002 VDD = 6 V PFI = 1.05 V MR = Open 1.001 1 TPS3707−50 10 −10 −30 0.999 −40 −15 10 35 60 TA − Free-Air Temperature − °C −50 −0.5 85 2.5 4.5 3.5 5.5 6.5 Figure 7-3. Supply Current vs Supply Voltage 100 10 tw − Minimum Pulse Duration at VDD − µ s VDD = 6 V PFI = 1.05 V 0 −100 −200 −300 −40°C −400 85°C −500 PFI = 1.05 V MR = Open 8 6 4 2 0 −1 0 1 2 3 4 5 6 0 VI − Input Voltage at MR − V 200 400 800 600 1000 VDD − Threshold Overdrive − mV Figure 7-4. Input Current vs Input Voltage at MR Figure 7-5. Minimum Pulse Duration at VDD vs VDD Threshold Overdrive 6.5 3.5 VDD = 3.2 V PFI = 1.05 V MR = Open 3 2.5 2 1.5 −40°C 1 85°C 0.5 VDD = 6 V PFI = 1.05 V MR = Open 6 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V 1.5 0.5 VDD − Supply Voltage − V Figure 7-2. Normalized Input Threshold Voltage vs Free-Air Temperature at VDD I I − Input Current − µ A PFI = 1.05 V MR = Open TA = 25°C 30 I DD − Supply Current − µ A Normalized Input Threshold Voltage VIT(TA), VIT (25 °C ) 7.11 Typical Characteristics 5.5 5 4.5 4 3.5 −40°C 3 85°C 2.5 2 1.5 1 0.5 0 0 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 IOH − High-Level Output Current − mA Figure 7-6. High-Level Output Voltage vs High-Level Output Current Copyright © 2020 Texas Instruments Incorporated 0 −5 −10 −15 −20 −25 −30 IOH − High-Level Output Current − mA Figure 7-7. High-Level Output Voltage vs High-Level Output Current Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 11 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.11 Typical Characteristics (continued) VOL − Low-Level Output Voltage − V 3 VDD = 2.67 V PFI = 1.05 V MR = Open 2.5 2 1.5 85°C −40°C 1 0.5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 IOL − Low-Level Output Current − mA 12 Figure 7-8. Low-Level Output Voltage vs Low-Level Output Current Figure 7-9. Watchdog Timeout Histogram for TSP3705-33 Devices at -40°C (Unit Count = 20) Figure 7-10. Watchdog Timeout Histogram for TSP3705-33 Devices at 25°C (Unit Count = 20) Figure 7-11. Watchdog Timeout Histogram for TSP3705-33 Devices at 125°C (Unit Count = 20) Figure 7-12. Reset Delay Histogram for TPS3705-33 Devices at -40°C (Unit Count = 20) Figure 7-13. Reset Delay Histogram for TPS3705-33 Devices at 25°C (Unit Count = 20) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.11 Typical Characteristics (continued) Figure 7-14. Reset Delay Histogram for TPS3705-33 Devices at 125°C (Unit Count = 20) Figure 7-15. MR to RESET (tPHL) Delay Histogram for TPS3705-33 Devices at -40°C (Unit Count = 20) Figure 7-16. MR to RESET (tPHL) Delay Histogram for TPS3705-33 Devices at 25°C (Unit Count = 20) Figure 7-17. MR to RESET (tPHL) Delay Histogram for TPS3705-33 Devices at 125°C (Unit Count = 20) Figure 7-18. VDD to RESET (tPHL) Delay Histogram for TPS3705-33 Devices at -40°C (Unit Count = 20) Figure 7-19. VDD to RESET (tPHL) Delay Histogram for TPS3705-33 Devices at 25°C (Unit Count = 20) Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 13 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.11 Typical Characteristics (continued) 14 Figure 7-20. VDD to RESET (tPHL) Delay Histogram for TPS3705-33 Devices at 125°C (Unit Count = 20) Figure 7-21. PFI to PFO (tPHL) Delay Histogram for TPS3705-33 Devices at -40°C (Unit Count = 20) Figure 7-22. PFI to PFO (tPHL) Delay Histogram for TPS3705-33 Devices at 25°C (Unit Count = 20) Figure 7-23. PFI to PFO (tPHL) Delay Histogram for TPS3705-33 Devices at 125°C (Unit Count = 20) Figure 7-24. PFI to PFO (tPLH) Delay Histogram for TPS3705-33 Devices at -40°C (Unit Count = 20) Figure 7-25. PFI to PFO (tPLH) Delay Histogram for TPS3705-33 Devices at 25°C (Unit Count = 20) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 7.11 Typical Characteristics (continued) Figure 7-26. PFI to PFO (tPLH) Delay Histogram for TPS3705-33 Devices at 125°C (Unit Count = 20) Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 15 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 8 Detailed Description 8.1 Overview The TPS370x-xx family of supervisors feature an integrated reference and comparator for V DD supervision, an additional power-fail supervisor, and a manual reset input. The TPS3705-xx devices feature a watchdog timer, where the TPS3707-xx devices feature a complimentary RESET output. 8.2 Functional Block Diagram TPS3705 TPS3707 VDD 14 kΩ MR Reset Logic + Timer R1 + _ RESET RESET Only TPS3707 R2 GND Oscillator Reference Voltage of 1.25 V _ WDI Only TPS3705 PFO + PFI Transition Detection 40 kΩ Watchdog Logic + Timer WDO Only TPS3705 Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Manual Reset Input The TPS370x-xx devices incorporate a manual reset input, MR. A low level at MR causes RESET to become active. 8.3.2 Power-Fail Comparator The TPS370x-xx family integrates a power-fail comparator which can be used for low-battery detection, powerfail warning, or for monitoring a power supply other than the main supply. 8.3.3 Watchdog Timer The TPS3705-xx devices have a watchdog timer that is periodically triggered by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the timeout interval, t t(out) = 1.6 s, WDO becomes active. This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. The TPS3707-xx devices do not have the watchdog function, but include a high-level output RESET. 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 8.4 Device Functional Modes 8.4.1 VDD < 1.1 V When VDD is less than 1.1 V, the status of the outputs cannot be determined. 8.4.2 1.1 V < VDD ≤ 2 V When V DD is greater than 1.1 V but less than 2 V, the output states are valid. However, the specifications in Section 7.5 do not apply. 8.4.3 2 V < VDD < 6 V When VDD is greater than 2 V but less than 6 V, the device is within the recommended operating conditions (see Section 7.3). See Table 8-1, Table 8-2, and Table 8-3 for corresponding truth tables. Table 8-1. TPS3705 Truth Table MR VDD > VIT RESET TYPICAL DELAY H→L 1 H→L 30 ns L→H 1 L→H 200 ms H 1→0 H→L 3 µs H 0→1 L→H 200 ms Table 8-2. TPS3707 Truth Table MR VDD > VIT RESET RESET TYPICAL DELAY H→L 1 H→L L→H 30 ns L→H 1 L→H H→L 200 ms H 1→0 H→L L→H 3 µs H 0→1 L→H H→L 200 ms Table 8-3. TPS370x Truth Table PFI > VIT PFO TYPICAL DELAY 0→1 L→H 0.5 µs 1→0 H→L 0.5 µs Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 17 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS370x-xx family of devices offers several options for power monitoring. The TPS3705-xx offers a watchdog supervisor, V DD rail monitoring, and a power-fail interrupt monitor. The TPS3707-xx offers V DD rail monitoring with complimentary outputs and a power-fail interrupt monitor. 9.2 Typical Application 12 V 5V VDD VDD PFO TPS3705−50 MR MSP430P112 100 nF RESET RESET/NMI 910 kΩ WDO I/O WDI I/O PFI 120 kΩ GND GND Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Typical MSP430 Application 9.2.1 Design Requirements Table 9-1 lists the required design parameters for Figure 9-1. Table 9-1. Application Parameters DESIGN PARAMETER VALUE Monitored voltage 1 5V Monitored voltage 2 12 V 9.2.2 Detailed Design Procedure To create two voltage monitoring rails, the PFI input can be used along with the MR pin to create a single output. The 5-V monitor is created by selecting a 5-V device option, giving threshold of 4.55 V. The PFI input is configured to any adjustable rail with a voltage divider. Use Equation 1 to select resistors. VTH 18 R1 R2 u VIT R2 910 k 120 k u 1.25 10.73 V 120 k Submit Document Feedback (1) Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 50 1.002 VDD = 6 V PFI = 1.05 V MR = Open 30 I DD − Supply Current − µ A Normalized Input Threshold Voltage VIT(TA), VIT (25 °C ) 9.2.3 Application Curves 1.001 1 PFI = 1.05 V MR = Open TA = 25°C TPS3707−50 10 −10 −30 0.999 −40 −15 10 35 60 TA − Free-Air Temperature − °C 85 Figure 9-2. Normalized Input Threshold Voltage vs Free-Air Temperature at VDD −50 −0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDD − Supply Voltage − V Figure 9-3. Supply Current vs Supply Voltage 10 Power Supply Recommendations These devices are designed to operate from an input supply with a voltage range from 2 V to 6 V. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 19 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 11 Layout 11.1 Layout Guidelines Place a 0.1-µF decoupling capacitor as close to the device as possible. If a resistor divider is used, place the resistors as close to the device as possible to minimize noise coupling. 11.2 Layout Example MR VDD 1 8 WDO 2 7 RESET 3 6 WDI 4 5 PFO Decoupling Cap PFI R1 R2 Monitored Voltage TPS3705 D Package Figure 11-1. TPS3705 Layout 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 TPS3705-30, TPS3705-33, TPS3705-50, TPS3707-30, TPS3707-50 www.ti.com SLVS184F – NOVEMBER 1998 – REVISED OCTOBER 2020 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS3705-30 TPS3705-33 TPS3705-50 TPS3707-30 TPS3707-50 21 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3705-30D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70530 Samples TPS3705-30DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAT Samples TPS3705-30DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70530 Samples TPS3705-33D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 70533 Samples TPS3705-33DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 70533 Samples TPS3705-33DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAU Samples TPS3705-33DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAU Samples TPS3705-33DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 70533 Samples TPS3705-50D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70550 Samples TPS3705-50DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70550 Samples TPS3705-50DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAV Samples TPS3705-50DGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAV Samples TPS3705-50DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAV Samples TPS3705-50DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70550 Samples TPS3705-50DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70550 Samples TPS3707-25D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70725 Samples TPS3707-25DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAW Samples TPS3707-25DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAW Samples TPS3707-25DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70725 Samples TPS3707-30D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70730 Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3707-30DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70730 Samples TPS3707-30DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAX Samples TPS3707-30DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAX Samples TPS3707-30DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70730 Samples TPS3707-33D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70733 Samples TPS3707-33DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70733 Samples TPS3707-33DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAY Samples TPS3707-33DGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAY Samples TPS3707-33DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAY Samples TPS3707-33DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAY Samples TPS3707-33DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70733 Samples TPS3707-50D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70750 Samples TPS3707-50DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAZ Samples TPS3707-50DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAZ Samples TPS3707-50DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 70750 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of