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TPS3710-Q1
SBVS341 – JULY 2017
TPS3710-Q1 Wide VIN Voltage Detector
1 Features
3 Description
•
•
The TPS3710-Q1 wide-supply voltage detector
operates over a 1.8-V to 18-V range. The device has
a high-accuracy comparator with an internal 400-mV
reference and an open-drain output rated to 18 V for
precision voltage detection. The monitored voltage
can be set with the use of external resistors.
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: -40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Wide Supply Voltage Range: 1.8 V to 18 V
Adjustable Threshold: Down to 400 mV
High Threshold Accuracy:
– 1.0% Over Temperature
– 0.25% (Typical)
Low Quiescent Current: 5.5 µA (Typical)
Open-Drain Output
Internal Hysteresis: 5.5 mV (Typical)
Temperature Range: –40°C to +125°C
Packages:
– 1.5-mm × 1.5-mm WSON-6
1
•
•
•
•
•
•
•
•
The TPS3710-Q1 is available in a 1.5-mm × 1.5-mm
6-pin WSON package, and is specified over the
junction temperature range of –40°C to +125°C.
Device Information
PART NUMBER
TPS3710-Q1
PACKAGE
WSON (6)
(1)
BODY SIZE (NOM)
1.50 mm × 1.50 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
2 Applications
•
•
•
The OUT pin is driven low when the voltage at the
SENSE pin drops below (VIT–), and goes high when
the voltage returns above the respective threshold
(VIT+). The comparator in the TPS3710-Q1 includes
built-in hysteresis for filtering to reject brief glitches,
thereby ensuring stable output operation without false
triggering.
Automotive Systems
Embedded Computing Modules
DSP, Microcontroller, or Microprocessor
Applications
Notebook and Desktop Computers
Portable- and Battery-Powered Products
FPGA and ASIC Applications
•
•
•
Rising Input Threshold Voltage (VIT+) vs
Temperature
Simplified Schematic
VMON
401
0.01 F
VPULLUP
Up to 18 V
R1
VDD
RP
SENSE
R2
GND
OUT
To a reset or enable
input of the system.
Positive-Going Input Threshold (mV)
1.8 V to 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
400.6
400.2
399.8
399.4
399
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3710-Q1
SBVS341 – JULY 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 13
8.3 Do's and Don'ts ....................................................... 14
9 Power-Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
2
DATE
REVISION
NOTES
July 2017
*
Initial release
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5 Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
GND
1
6 OUT
VDD
2
5 GND
GND
3
4 SENSE
Pin Functions
PIN
NAME
DSE
I/O
DESCRIPTION
GND
1, 3, 5
—
Connect all three pins to ground.
OUT
6
O
SENSE comparator open-drain output. OUT is driven low when the voltage at this comparator is
below (VIT-). The output goes high when the sense voltage returns above the respective
threshold (VIT+).
SENSE
4
I
This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT-), OUT is driven low.
VDD
2
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good analog
design practice is to place a 0.1-µF ceramic capacitor close to this pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
Voltage (2)
Current
(2)
MAX
–0.3
20
OUT
–0.3
20
SENSE
–0.3
7
OUT (output sink current)
Temperature
(1)
MIN
VDD
UNIT
V
40
Operating junction, TJ
–40
125
Storage, Tstg
–65
150
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground pin.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2500
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Supply voltage
1.8
18
V
VI
Input voltage
SENSE
0
6.5
V
VO
Output voltage
OUT
0
18
V
6.4 Thermal Information
TPS3710-Q1
THERMAL METRIC
(1)
DSE (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
194.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
128.9
°C/W
RθJB
Junction-to-board thermal resistance
153.8
°C/W
ψJT
Junction-to-top characterization parameter
11.9
°C/W
ψJB
Junction-to-board characterization parameter
157.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to +125°C, and 1.8 V < VDD < 18 V (unless otherwise noted).
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
TEST CONDITIONS
(1)
V(POR)
Power-on reset voltage
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (hys = VIT+ – VIT–)
I(SENSE)
Input current (at the SENSE pin)
VOL
Low-level output voltage
Ilkg(OD)
Open-drain output leakage-current
MIN
Supply current
UVLO
Undervoltage lockout
(1)
(2)
UNIT
V
VDD = 1.8 V
396
400
404
VDD = 18 V
396
400
404
VDD = 1.8 V
387
394.5
400
VDD = 18 V
387
394.5
400
5.5
12
mV
VDD = 1.8 V and 18 V, VI = 6.5 V
–25
1
25
nA
VDD = 1.3 V, output sink current = 0.4 mA
250
VDD = 1.8 V, output sink current = 3 mA
250
VDD = 5 V, output sink current = 5 mA
250
VDD = 1.8 V and 18 V, VO = VDD
300
VDD = 1.8 V, VO = 18 V
300
5.5
11
VDD = 5 V
6
13
VDD = 12 V
6
13
VDD = 18 V
(2)
MAX
0.8
VDD = 1.8 V, no load
IDD
TYP
VOLmax = 0.2 V, output sink current = 15 µA
VDD falling
7
1.3
mV
mV
mV
nA
µA
13
1.7
V
The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
When VDD falls below UVLO, OUT is driven low. The output cannot be determined below V(POR).
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6.6 Timing Requirements
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
tpd(HL)
High-to-low propagation delay
(1)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
18
µs
tpd(LH)
Low-to-high propagation delay
(1)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
29
µs
td(start)
Start-up delay
150
µs
(1)
(2)
(2)
High-to-low and low-to-high refers to the transition at the input pin (SENSE).
During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state.
6.7 Switching Characteristics
over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tr
Output rise time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tf
Output fall time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
MIN
TYP
MAX
UNIT
2.2
µs
0.22
µs
VDD
V(POR)
VIT+
SENSE
V HYS
VIT±
OUT
t pd(LH)
t pd(HL)
t pd(LH)
t d(start)
Figure 1. Timing Diagram
6
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6.8 Typical Characteristics
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
401
10
Positive-Going Input Threshold (mV)
9
Supply Current (PA)
8
7
6
5
4
3
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
2
1
400.6
400.2
399.8
399.4
399
-40
0
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
Figure 2. Supply Current (IDD) vs Supply Voltage (VDD)
6
5
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
Low-to-High Propagation Delay (µs)
Hysteresis Voltage (mV)
7
4
23
5
20 35 50 65
Temperature (qC)
80
95
110 125
19
17
15
13
11
9
-40
110 125
28
14
Input Pulse Duration (µs)
16
24
22
20
18
16
VDD = 1.8 V
VDD = 18 V
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
Figure 5. Propagation Delay vs Temperature
(High-to-Low Transition at Sense)
30
26
VDD = 1.8 V
VDD = 18 V
21
Figure 4. Hysteresis (Vhys) vs Temperature
Low-to-High Propagation Delay (µs)
-10
25
8
14
-40
-25
Figure 3. Rising Input Threshold Voltage (VIT+) vs
Temperature
9
3
-40
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
12
10
8
6
4
2
0
2.5
4
5.5
7
8.5
10
11.5
13
Positive-Going Input Threshold Overdrive (%)
14.5
SENSE = negative spike below VIT–
Figure 6. Propagation Delay vs Temperature
(Low-to-High Transition at Sense)
Figure 7. Minimum Pulse Width vs
Threshold Overdrive Voltage
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Typical Characteristics (continued)
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
2000
12
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
Low-Level Output Voltage (mV)
1800
Supply Current (PA)
10
8
6
4
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
2
4
8
12
16
20
24
28
Output Sink Current (mA)
32
36
1400
1200
1000
800
600
400
200
0
0
0
1600
0
40
4
2000
36
40
1600
36
40
36
40
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1800
Low-Level Output Voltage (mV)
Low-Level Output Voltage (mV)
32
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1800
1400
1200
1000
800
600
400
200
1600
1400
1200
1000
800
600
400
200
0
0
0
4
8
12
16
20
24
28
Output Sink Current (mA)
32
36
40
0
Figure 10. Output Voltage Low (VOL) vs
Output Sink Current (0°C)
4
8
12
16
20
24
28
Output Sink Current (mA)
32
Figure 11. Output Voltage Low (VOL) vs
Output Sink Current (25°C)
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1600
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1800
Low-Level Output Voltage (mV)
1800
Low-Level Output Voltage (mV)
12
16
20
24
28
Output Sink Current (mA)
Figure 9. Output Voltage Low (VOL) vs
Output Sink Current (–40°C)
Figure 8. Supply Current (IDD) vs
Output Sink Current
1400
1200
1000
800
600
400
200
1600
1400
1200
1000
800
600
400
200
0
0
0
4
8
12
16
20
24
28
Output Sink Current (mA)
32
Figure 12. Output Voltage Low (VOL) vs
Output Sink Current (85°C)
8
8
36
40
0
4
8
12
16
20
24
28
Output Sink Current (mA)
32
Figure 13. Output Voltage Low (VOL) vs
Output Sink Current (125°C)
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7 Detailed Description
7.1 Overview
The TPS3710-Q1 provides precision voltage detection. The TPS3710-Q1 is a wide-supply voltage range (1.8 V
to 18 V) device with a high-accuracy rising input threshold of 400 mV (1% over temperature) and built-in
hysteresis. The output is also rated to 18 V, and can sink up to 40 mA.
The TPS3710-Q1 asserts the output signal, as shown in Table 1. To monitor any voltage above 0.4 V, set the
input using an external resistor divider network. Broad voltage thresholds are supported that enable the device
for use in a wide array of applications.
Table 1. TPS3710-Q1 Truth Table
CONDITION
OUTPUT
STATUS
SENSE > VIT+
OUT high
Output not asserted
SENSE < VIT–
OUT low
Output asserted
7.2 Functional Block Diagram
VDD
SENSE
OUT
VIT+
GND
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7.3 Feature Description
7.3.1 Input (SENSE)
The TPS3710-Q1 comparator has two inputs: one external input, and one input connected to the internal
reference. The comparator rising threshold is trimmed to be equal to the reference voltage (400 mV). The
comparator also has a built-in falling hysteresis that makes the device less sensitive to supply-rail noise and
provides stable operation.
The comparator input (SENSE) is able to swing from ground to 6.5 V, regardless of the device supply voltage.
Although not required in most cases, in order to reduce sensitivity to transients and layout parasitics for
extremely noisy applications, place a 1-nF to 10-nF bypass capacitor at the comparator input.
OUT is driven to logic low when the input SENSE voltage drops below (VIT-). When the voltage exceeds VIT+, the
output (OUT) goes to a high-impedance state; see Figure 1.
7.3.2 Output (OUT)
In a typical TPS3710-Q1 application, the output is connected to a reset or enable input of the processor (such as
a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]) or the output is connected to the enable input of a voltage regulator
(such as a dc-dc converter or low-dropout regulator [LDO]).
The TPS3710-Q1device provides an open-drain output (OUT). Use a pullup resistor to hold this line high when
the output goes to high impedance (not asserted). To connect the output to another device at the correct
interface-voltage level, connect a pullup resistor to the proper voltage rail. The TPS3710-Q1 output can be pulled
up to 18 V, independent of the device supply voltage.
Table 1 and the Input (SENSE) section describe how the output is asserted or deasserted. See Figure 1 for a
timing diagram that describes the relationship between threshold voltage and the respective output.
7.3.3 Immunity to Input-Pin Voltage Transients
The TPS3710-Q1i s relatively immune to short voltage transient spikes on the sense pin. Sensitivity to transients
depends on both transient duration and amplitude; see Figure 7, Minimum Pulse Width vs Threshold Overdrive
Voltage.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUT signal correspond to the voltage on
SENSE as listed in Table 1.
7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUT signal is asserted regardless of the voltage on SENSE.
7.4.3
Power-On Reset (VDD < V(POR))
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)),
SENSE is in a high-impedance state.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3710-Q1 device is a wide-supply voltage comparator that operates over a VDD range of 1.8 V to
18 V. The device has a high-accuracy comparator with an internal 400-mV reference and an open-drain output
rated to 18 V for precision voltage detection. The device can be used as a voltage monitor. The monitored
voltage are set with the use of external resistors.
8.1.1 VPULLUP to a Voltage Other Than VDD
The output is often tied to VDD through a resistor. However, some applications may require the output to be
pulled up to a higher or lower voltage than VDD to correctly interface with the reset and enable pins of other
devices.
VMON
1.8 V to 18 V
0.01 F
VPULLUP
Up to 18 V
R1
VDD
RP
SENSE
OUT
To a reset or enable
input of the system.
R2
GND
Figure 14. Interfacing to a Voltage Other Than VDD
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Application Information (continued)
8.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
0.01 F
VPULLUP
Up to 18 V
R1
VDD
RP
SENSE
To a reset or enable
input of the system.
OUT
R2
GND
Figure 15. Monitoring the Same Voltage as VDD
8.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired threshold is connected to the rail that is being monitored.
VMON
1.8 V to 18 V
0.01 F
VPULLUP
Up to 18 V
R1
VDD
RP
SENSE
OUT
To a reset or enable
input of the system.
R2
GND
NOTE: The input can monitor a voltage greater than maximum VDD with the use of an external resistor divider
network.
Figure 16. Monitoring a Voltage Other Than VDD
12
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8.2 Typical Application
The TPS3710-Q1 device is a wide-supply voltage comparator that operates over a VDD range of 1.8 to 18 V. The
monitored voltage is set with the use of external resistors, so the device can be used either as a precision
voltage monitor.
VMON
1.8 V to 18 V
0.01 F
VPULLUP
Up to 18 V
R1
2.21 MŸ
VDD
SENSE
OUT
RP
49.9 kŸ
To a reset or enable
input of the system.
R2
83.5 kŸ
GND
Figure 17. Wide VIN Voltage Monitor
8.2.1 Design Requirements
For this design example, use the values summarized in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Monitored voltage
12-V nominal rail with maximum falling
threshold of 10%
VMON(UV)= 10.99 V (8.33%)
8.2.2 Detailed Design Procedure
8.2.2.1 Resistor Divider Selection
The resistor divider values and target threshold voltage can be calculated by using Equation 1 to determine
VMON(UV).
R1 ·
§
VMON(UV) = ¨ 1 +
¸ × VIT
R2
©
¹
(1)
where
•
•
R1 and R2 are the resistor values for the resistor divider on the SENSEx pins
VMON(UV) is the target voltage at which an undervoltage condition is detected
Choose RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the
input current at the SENSE pin. The resistors can have high values to minimize current consumption as a result
of low input bias current without adding significant error to the resistive divider. For details on sizing input
resistors, refer to application report SLVA450, Optimizing Resistor Dividers at a Comparator Input, available for
download from www.ti.com.
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8.2.2.2 Pullup Resistor Selection
To ensure the proper voltage level, the pullup resistor value is selected by ensuring that the pullup voltage
divided by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated
by verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater
than the desired logic-high voltage. These values are specified in the Electrical Characteristics .
Use Equation 2 to calculate the value of the pullup resistor.
VPU
(VHI - VPU)
³ RPU ³
IO
Ilkg(OD)
(2)
8.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF low
equivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source.
8.2.2.4 Sense Capacitor
Although not required in most cases, for extremely noisy applications, place a 1-nF to 10-nF bypass capacitor
from the comparator input (SENSE) to the GND pin for good analog design practice. This capacitor placement
reduces device sensitivity to transients.
8.2.3 Application Curve
Positive-Going Input Threshold (mV)
401
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
400.6
400.2
399.8
399.4
399
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
Figure 18. Rising Input Threshold Voltage (VIT+) vs Temperature
8.3 Do's and Don'ts
Do connect a 0.1-µF decoupling capacitor from VDD to GND for best system performance.
If the monitored rail is noisy, do connect a decoupling capacitor from the comparator input (sense) to GND.
Don't use resistors for the voltage divider that cause the current through them to be less than 100 times the input
current of the comparator without also accounting for the effect to the accuracy.
Don't use a pullup resistor that is too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
14
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TPS3710-Q1
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SBVS341 – JULY 2017
9 Power-Supply Recommendations
This device operates from an input voltage supply range between 1.8 V and 18 V.
10 Layout
10.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD pin to reduce the input impedance to the device is good analog
design practice.
10.2 Layout Example
Pullup
Voltage
RP1
Output
Flag
Monitored
Voltage
R1
1
6
2
5
3
4
CVDD
Input
Supply
R2
Figure 19. Layout Example
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15
TPS3710-Q1
SBVS341 – JULY 2017
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature
PRODUCT
TPS3710yyyz
DESCRIPTION
yyy is package designator
z is package quantity
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Optimizing Resistor Dividers at a Comparator Input
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Product Folder Links: TPS3710-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3710QDSERQ1
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
5P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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