TPS3760E012DYYR

TPS3760 SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 TPS3760 High Voltage Supervisor with Programmable Sense and Reset Delay Function 1 Features 3 Description • The TPS3760 is a family of wide input range and low quiescent current window supervisors for fast detection of overvoltage (OV) or undervoltage (UV) conditions. The TPS3760 can be connected directly to and monitor 12 V / 24 V supply rails in a variety of industrial applications including factory automation, motor drives, building automation and others. Built-in hysteresis on the SENSE pins prevents false reset signals when monitoring a supply voltage rail. • • • • • • 2 Applications • • • • • • Analog input module CPU (PLC controller) Servo drive control module Servo drive power stage module Servo drive functional safety module HVAL valve and actuator control The separate VDD and SENSE pins allow redundancy sought by high-reliability systems. SENSE is decoupled from VDD and can monitor higher and lower voltages than VDD. Optional use of external resistors are supported by the high impedance input of the SENSE pins. CTSx and CTRx pins allow delay adjustability on the rising and falling edges of the RESET signals. Also, CTSx functions as a debouncer by ignoring voltage glitches on the monitored voltage rails; CTRx operates as a manual reset (MR) that can be used to force a system reset. The TPS3760 is available in a 4.1-mm×1.9-mm SOT 14-pin package. TPS3760 operates over –40°C to +125°C TA. Device Information PART NUMBER TPS3760 (1) (1)) PACKAGE ( SOT-23 (14) (DYY) BODY SIZE (NOM) 4.1 mm × 1.9 mm For package details, see the mechanical drawing addendum at the end of the data sheet. 0.95 DC/DC 0.90 MCU VDD VDD RESET SENSE MCU Flag TPS3760 GND GND GPIO Quiescent Current (μA) • • • • Functional Safety-Capable – Documentation available to aid functional safety system design Wide supply voltage range: 2.7 V to 65 V SENSE and RESET pins are 65 V graded Low quiescent current: 1 µA (typical) Flexible and wide voltage threshold options Table 12-1 – 2.7 V to 36 V (1.5% maximum accuracy) – 800 mV option (1% maximum accuracy) Built-in hysteresis (VHYS) – Percentage options: 2% to 13% (1% steps) – Fixed options: VTH < 8 V = 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V Programmable reset time delay – 10 nF = 12.8 ms, 10 μF = 12.8 s Programmable sense time delay – 10 nF = 1.28 ms, 10 μF = 1.28 s Manual Reset (MR) feature Output reset latching feature Output topology: Open-Drain or Push-Pull 0.85 0.80 0.75 0.70 0.65 0.60 -40oC 25oC 125oC 0.55 Backup Vba
Boost Converter Typical Application Circuit 0.50 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) Typical IDD vs VDD An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison......................................................... 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings .............................................................. 6 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................7 7.6 Timing Requirements.................................................. 9 7.7 Timing Diagrams ...................................................... 10 7.8 Typical Characteristics.............................................. 13 8 Detailed Description......................................................17 8.1 Overview................................................................... 17 8.2 Functional Block Diagram......................................... 17 8.3 Feature Description...................................................18 8.4 Device Functional Modes..........................................27 9 Application and Implementation.................................. 28 9.1 Application Information............................................. 28 9.2 Adjustable Voltage Thresholds................................. 28 9.3 Typical Application.................................................... 29 10 Power Supply Recommendations..............................32 10.1 Power Dissipation and Device Operation............... 32 11 Layout........................................................................... 33 11.1 Layout Guidelines................................................... 33 11.2 Layout Example...................................................... 33 11.3 Creepage Distance................................................. 34 12 Device and Documentation Support..........................35 12.1 Device Nomenclature..............................................35 12.2 Receiving Notification of Documentation Updates..36 12.3 Support Resources................................................. 36 12.4 Trademarks............................................................. 36 12.5 Electrostatic Discharge Caution..............................36 12.6 Glossary..................................................................36 13 Mechanical, Packaging, and Orderable Information.................................................................... 36 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (March 2022) to Revision A (September 2023) Page • Added Latch nomenclature.................................................................................................................................3 • Removed DSK pinout description.......................................................................................................................4 • Added CTS and CTR timing plots.....................................................................................................................13 • Added Reset latch mode information................................................................................................................26 • Fixed nomenclature 08 to 01............................................................................................................................ 35 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 5 Device Comparison Voltage Threshold Hysteresis TPS3760 X X XX 1. 2. 3. 4. 5. X DYY R Sense logic: OV = overvoltage; UV = undervoltage Reset topology: PP = Push-Pull; OD = Open-Drain Reset logic: L = Active-Low; H = Active-High A to I hysteresis options are only available for 2.9 V to 8V threshold options Suffix 01 with VIT of 800mV corresponds to the adjustable variant, does not have internal voltage divider Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 3 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 6 Pin Configuration and Functions VDD 1 14 NC NC 2 13 GND SENSE 3 12 NC NC 4 11 NC NC 5 10 CTS RESET 6 9 CTR NC 7 8 GND Figure 6-1. DYY Package, 14-Pin SOT-23, TPS3760 (Top View) Table 6-1. Pin Functions PIN SOT23 (DYY) NAME NO. VDD 1 SENSE RESET/RESET CTS /LATCH 4 3 6 10 I/O DESCRIPTION I Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND. I Sense Voltage: The voltage monitored by this pin is compared to the internal voltage threshold, Vth, that is determined by an internal voltage divider for fixed variants or an external voltage divider for adjustable variants. When the SENSE pin detects a fault, RESET/RESET asserts after the sense time delay, set by CTS. When the voltage on the SENSE pin transitions back past Vth and hysteresis, VHYS, RESET/RESET deasserts after the reset time delay, set by CTR. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance. Sensing Topology: Overvoltage (OV) or Undervoltage (UV) O Output Reset Signal: See Device Comparison for output topology options. RESET/RESET asserts when SENSE crosses the voltage threshold after the sense time delay, set by CTS. RESET/RESET remains asserted for the reset time delay period after SENSE transitions out of a fault condition. For active low open-drain reset output, an external pullup resistor is required. Do not place external pullup resistors on push-pull outputs. Output topology: Open Drain or Push Pull, Active Low or Active High O SENSE Time Delay: Capacitor programmable sense delay: CTS pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to assert. LATCH: CTS functionality is disabled in latch capable devices. When latch mode is activated, RESET/RESET will not de-assert even if the fault is cleared. To activate latch mode, the LATCH pin has to be driven low, to at least 1.4V. It is recommended to have a 10kΩ pull-down to ground. To deactivate latch mode, a 2.1V or greater for 3µs has to be applied to the LATCH pin while SENSE pin is not detecting a fault. RESET/RESET will de-assert with delay tctr starting on the rising edge of the deactivating signal. CTR /MR 9 - RESET Time Delay: User-programmable reset time delay for RESET/RESET. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. Manual Reset: If this pin is driven low, the RESET/RESET output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high. GND 8, 13 - Ground. All GND pins must be electrically connected to the board ground. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 Table 6-1. Pin Functions (continued) PIN SOT23 (DYY) NAME NO. NC 2, 4, 5, 7, 11,12, 14 I/O - DESCRIPTION NC stands for “No Connect.” The pins are to be left floating. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 5 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range, unless otherwise noted (1) MIN MAX UNIT Voltage VDD, VSENSE, VRESET, VRESET –0.3 70 V Voltage VCTS, VCTR –0.3 6 V Current IRESET, IRESET 10 mA Temperature (2) Operating junction temperature, TJ –40 150 °C Operating Ambient temperature, TA –40 150 °C Storage, Tstg –65 150 °C Temperature (2) Temperature (2) (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. As a result of the low dissipated power in this device, it is assumed that TJ = TA. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-002 ±2000 (1) V(ESD) (1) (2) Electrostatic discharge UNIT V Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Voltage VDD Voltage VSENSE, VRESET, VRESET Voltage VCTS, VCTR Current IRESET, IRESET TJ Junction temperature (free air temperature) NOM 2.7 MAX UNIT 65 V 0 65 V 0 5.5 V 0 ±5 mA –40 125 °C 7.4 Thermal Information TPS3760 THERMAL METRIC (1) DYY UNIT 14-PIN RθJA Junction-to-ambient thermal resistance 131.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61.1 °C/W RθJB Junction-to-board thermal resistance 56.6 °C/W ψJT Junction-to-top characterization parameter 3.4 °C/W ψJB Junction-to-board characterization parameter 56.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.5 Electrical Characteristics At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR/MR = CTS = open, output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD VDD Supply Voltage UVLO (1) 2.7 65 V Under Voltage Lockout VDD Falling below VDD (MIN) 2.7 V VPOR Power on Reset Voltage (2) RESET, Active Low (Open-Drain, Push-Pull ) VOL(MAX) = 300 mV IOUT (Sink) = 15 µA 1.4 V VPOR Power on Reset Voltage (2) RESET, Active High (Push-Pull ) VOH(MIN) = 0.8 x VDD IOUT (Source) = 15 µA 1.4 V 1 2.6 µA 1 2 µA IDD Supply current into VDD pin VIT = 800 mV VDD (MIN) ≤ VDD ≤ VDD (MAX) VIT = 2.7 V to 36 V VDD (MIN) ≤ VDD ≤ VDD (MAX) SENSE (Input) ISENSE Input current VIT = 800 mV 100 nA ISENSE Input current VIT < 10 V 0.8 µA ISENSE Input current 10 V < VIT < 26 V 1.2 µA ISENSE Input current VIT > 26 V 2 µA VITN Input Threshold Negative (Undervoltage) VIT = 2.7 V to 36 V 1.5 % VITP Input Threshold Positive (Overvoltage) VIT = 2.7 V to 36 V Hysteresis Accuracy (4) VHYS VIT = 800 mV (3) VIT = 800 mV (3) -1.5 0.792 0.800 -1.5 0.792 0.800 0.808 V 1.5 % 0.808 V VIT = 0.8 V and 2.7 V to 36 V VHYS Range = 2% to 13% (1% step) -1.5 1.5 % VIT = 2.7 V to 8 V VHYS = 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V (VITP - VHYS) ≥ 2.4 V, OV Only -1.5 1.5 % VRESET = 5.5 V VITN < VSENSE < VITP 300 nA VRESET = 65 V VITN < VSENSE < VITP 300 nA 2.7 V ≤ VDD ≤ 65 V IRESET = 5 mA 300 mV 2.7 V ≤ VDD ≤ 65 V IRESET = 500 uA 100 mV RESET (Output) Ilkg(OD) VOL (5) VOH_DO VOH (5) Open-Drain leakage Low level output voltage High level output voltage dropout (VDD - VOH = VOH_DO) (Push-Pull only) High level output voltage (Push-Pull only) 2.7 V ≤ VDD ≤ 65 V IRESET = 5 mA 0.8VDD V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 7 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.5 Electrical Characteristics (continued) At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR/MR = CTS = open, output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 877 1000 1147 Kohms 88 100 122 Kohms Capacitor Timing (CTS, CTR) RCTR Internal resistance (CTR / MR) RCTS Internal resistance (CTS) Manual Reset (MR) VMR_IH CTR / MR pin logic high input VDD = 2.7 V 2200 VMR_IH CTR / MR pin logic high input VDD = 65 V 2500 VMR_IL CTR / MR pin logic low input VDD = 2.7 V 1300 mV VMR_IL CTR / MR pin logic low input VDD = 65 V 1300 mV (1) (2) (3) (4) (5) 8 mV mV When VDD voltage falls below UVLO, reset is asserted for Output. VDD slew rate ≤ 100 mV / µs VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD dv/dt ≤ 100mV/µs For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation section Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis. For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.6 Timing Requirements At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR/MR = CTS = open (1), output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5V, and CLOAD = 10 pF. VDD and SENSE slew rate = 1V / µs. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to either VITN or VITP). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT = 2.7 V to 36 V CCTR = Open 20% Overdrive from Hysteresis 100 µs VIT = 800 mV CCTR = Open 20% Overdrive from Hysteresis 40 µs Common timing parameters tCTR tCTS tSD (1) (2) (3) (4) Reset release time delay (CTR/MR) (2) Sense detect time delay (CTS) (3) Startup Delay (4) VIT = 2.7 V to 36 V CCTS = Open 20% Overdrive from VIT 34 90 µs VIT = 800 mV CCTS = Open 20% Overdrive from VIT 8 17 µs 2 ms CCTR/MR = Open CCTR = Reset delay channel CCTS = Sense delay channel CTR Reset detect time delay: Overvoltage active-LOW output is measure from VITP - HYS to VOH Undervoltage active-LOW output is measure from VITN + HYS to VOH Overvoltage active-HIGH output is measure from VITP - HYS to VOL Undervoltage active-HIGH output is measure from VITN + HYS to VOL CTS Sense detect time delay: Active-low output is measure from VIT to VOL (or VPullup) Active-high output is measured from VIT to VOH VIT refers to either VITN or VITP During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state based on VSENSE. tSD time includes the propagation delay (CCTR = Open). Capaicitor on CCTR will add time to tSD. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 9 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.7 Timing Diagrams Highest Absolute Limit for the Monitored Voltage Rail [1%] VIT+(OV)MAX Accuracy band across (-40ºC to 125ºC) Tolerance[+3% to +11%] VIT+(OV) VIT+(OV)MIN [0.63% * (VIT+(OV)MIN)] [VHYSMAX = 0.9% * (VIT+(OV)MIN )] Hys band for VIT+(OV) Tolerance[-3% to -11%] Power Supply Tolerance Window [VHYSMAX = 0.9% * (VIT-(UV)MIN )] [1%] [0.25% ] [-0.25%] [0.63% * (VIT-(UV)MIN)] Hys band for VIT-(UV) VIT-(UV)MIN VIT-(UV) Accuracy band across (-40ºC to 125ºC) VIT-(UV)MAX Lowest Absolute Limit for the Monitored Voltage Rail Figure 7-1. Voltage Threshold and Hysteresis Accuracy 10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 VDD(MIN) VDD UVLO(MIN) VPOR SENSE VSENSE VITN (UV) + VHYS VITN (UV) *See Note C t < tCTS tSD + tCTR tCTS tCTR tSD + tCTR tCTS tCTR Undefined *See Note C Undefined A. B. C. Undefined RESET_UVxx Undefined RESET_UVxx Hysteresis For open-drain output option, the timing diagram assumes the RESET_UVOD / RESET_UVOD pin is connected via an external pull-up resistor to VDD. Be advised that Figure 7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time. RESET_UVxx / RESET_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached. Figure 7-2. SENSE Undervoltage (UV) Timing Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 11 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 VDD(MIN) VDD UVLO(MIN) VPOR VITP (OV) SENSE VITP (OV) - VHYS Hysteresis VSENSE tSD + tCTR tCTS tCTR tSD + tCTR tCTS tCTR Undefined *See Note C Undefined A. B. C. Undefined RESET_OVxx Undefined RESET_OVxx *See Note C t < tCTS For open-drain output option, the timing diagram assumes the RESET_OVOD / RESET_OVOD pin is connected via an external pull-up resistor to VDD. Be advised that Figure 7-3 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time. RESET_OVxx / RESET_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached. Figure 7-3. SENSE Overvoltage (OV) Timing Diagram 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.8 Typical Characteristics Typical characteristics show the typical performance of the device. Test conditions are TA = 25°C, RPU = 100 kΩ, CLoad = 50 pF, unless otherwise noted. 20000 10000 TCTR(ms) 1000 100 10 1 25oC 0.1 0.0001 0.001 0.01 0.1 CCTR_EXT (F) 1 10 Figure 7-5. TCTS vs CCTS 0.95 0.90 0.90 0.85 0.85 Quiescent Current (μA) Quiescent Current (μA) Figure 7-4. TCTR vs CCTR 0.80 0.75 0.70 0.65 0.60 -40oC 25oC 125oC 0.55 0.80 0.75 0.70 0.65 0.60 -40oC 25oC 125oC 0.55 0.50 0.50 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) 0 5 RESET = High, VIT = 2.7 V RESET = Low, VIT = 2.7 V Figure 7-7. VDD vs IDD (RESET = Low, VIT = 2.7 V) 1.30 1.40 1.25 1.35 1.20 1.30 Quiescent Current (μA) Quiescent Current (μA) Figure 7-6. VDD vs IDD (RESET = High, VIT = 2.7 V) 1.15 1.10 1.05 1.00 0.95 0.90 -40C 25oC 125C 0.85 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) 0.80 1.25 1.20 1.15 1.10 1.05 1.00 -40oC 25oC 125oC 0.95 0.90 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) 0 5 RESET = High, VIT = 0.8 V 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) RESET = Low, VIT = 0.8 V Figure 7-8. VDD vs IDD (RESET = High, VIT = 0.8 V) Figure 7-9. VDD vs IDD (RESET = Low, VIT = 0.8 V) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 13 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.8 Typical Characteristics (continued) 1600 1600 1400 1400 1200 1200 Sense Current (nA) Sense Current (nA) Typical characteristics show the typical performance of the device. Test conditions are TA = 25°C, RPU = 100 kΩ, CLoad = 50 pF, unless otherwise noted. 1000 800 600 400 1000 800 600 400 -40oC 25oC 125oC 200 -40oC 25oC 125oC 200 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Sense Voltage (V) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Sense Voltage (V) VDD = 2.7 V VDD = 65 V Figure 7-10. VSENSE vs ISENSE Figure 7-11. VSENSE vs ISENSE 0.21 0.21 -40oC 25oC 125oC 0.15 0.15 0.12 0.12 0.09 0.09 0.06 0.06 0.03 0.03 0 0.0 0.5 1.0 -40oC 25oC 125oC 0.18 VOL (V) VOL (V) 0.18 1.5 2.0 2.5 3.0 IRESET (mA) 3.5 4.0 4.5 0.00 0.0 5.0 0.5 1.0 1.5 VDD = 2.7 V 4.5 5.0 0.21 -40oC 25oC 125oC 0.18 0.15 0.15 0.12 0.12 0.09 0.09 0.06 0.06 0.03 0.03 0.5 1.0 -40oC 25oC 125oC 0.18 VOL (V) VOL (V) 4.0 Figure 7-13. Open-Drain Active Low VOL vs IRESET 0.21 1.5 2.0 2.5 3.0 IRESET (mA) 3.5 4.0 4.5 5.0 0 0.0 0.5 VDD = 2.7 V 1.0 1.5 2.0 2.5 3.0 IRESET (mA) 3.5 4.0 4.5 5.0 VDD = 65 V Figure 7-14. Open-Drain Active High VOL vs IRESET 14 3.5 VDD = 65 V Figure 7-12. Open-Drain Active Low VOL vs IRESET 0 0.0 2.0 2.5 3.0 IRESET (mA) Figure 7-15. Open-Drain Active High VOL vs IRESET Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.8 Typical Characteristics (continued) Typical characteristics show the typical performance of the device. Test conditions are TA = 25°C, RPU = 100 kΩ, CLoad = 50 pF, unless otherwise noted. 0.21 0.21 -40oC 25oC 125oC 0.18 0.15 0.15 0.12 0.12 VOL (V) VOL (V) 0.18 0.09 0.09 0.06 0.06 0.03 0.03 0 0.0 0.5 1.0 -40oC 25oC 125oC 1.5 2.0 2.5 3.0 IRESET (mA) 3.5 4.0 4.5 0 0.0 5.0 0.5 VDD = 2.7 V 2.0 2.5 3.0 IRESET (mA) 3.5 4.0 4.5 5.0 Figure 7-17. Push-Pull Active High VOL vs IRESET 0.21 0.21 0.18 0.18 0.15 0.15 0.12 0.12 VOL (V) VOL (V) 1.5 VDD = 65 V Figure 7-16. Push-Pull Active High VOL vs IRESET 0.09 0.06 0.09 0.06 -40oC 25oC 125oC 0.03 -40oC 25oC 125oC 0.03 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) 0 Figure 7-18. Open-Drain Active Low VOL vs VDD 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) Figure 7-19. Open-Drain Active High VOL vs VDD 0.21 0.21 0.18 0.18 0.15 0.15 0.12 0.12 VOL (V) VOL (V) 1.0 0.09 0.06 0.09 0.06 o -40 C 25oC 125oC 0.03 0 -40oC 25oC 125oC 0.03 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) Figure 7-20. Push-Pull Active Low VOL vs VDD 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) Figure 7-21. Push-Pull Active High VOL vs VDD Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 15 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 7.8 Typical Characteristics (continued) 70 70 60 60 50 50 40 40 VOH (V) VOH (V) Typical characteristics show the typical performance of the device. Test conditions are TA = 25°C, RPU = 100 kΩ, CLoad = 50 pF, unless otherwise noted. 30 20 30 20 o -40 C 25oC 125oC 10 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) Figure 7-22. Push-Pull Active Low VOH vs VDD 16 -40oC 25oC 125oC 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Supply Voltage (V) Figure 7-23. Push-Pull Active High VOH vs VDD Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8 Detailed Description 8.1 Overview The TPS3760 is a family of high voltage and low quiescent current reset ICs with fixed threshold voltage. A voltage divider is integrated to eliminate the need for external resistors and eliminate leakage current that comes with resistor dividers. However, it can also support an external resistor if required by the application. The lowest threshold 800 mV (bypass internal resistor ladder) is recommenced for external resistors use case to take advantage of faster detection time and lower ISENSE current. VDD, SENSE and RESET pins can support 65 V continuous operation; both VDD and SENSE voltage levels can be independent of each other, meaning VDD pin can be connected at 2.7 V while SENSE pins are connected to a higher voltage. Note, the TPS3760 does not have clamps within the device so external circuits or devices must be added to limit the voltages to the absolute maximum limit. Additional features include programmable sense time delay (CTS) and reset delay time and manual reset (CTR / MR). 8.2 Functional Block Diagram VDD *Device Op
ons Boxes shaded in blue See Device Nomenclature CTS CTR / MR IQ SubReg POR VDD Voltage Divider - VRef Divider + SENSE OV or UV Select Sense Delay Manual Reset Reset Delay Output Logic select (High/Low) RESET REFERENCE GND Figure 8-1. Functional Block Diagram 1 1 Refer to Section 5 for complete list of topologies and output logic combination Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 17 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3 Feature Description 8.3.1 Input Voltage (VDD) VDD operating voltage ranges from 2.7 V to 65 V. An input supply capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a 0.1 µF capacitor between the VDD and GND. VDD needs to be at or above VDD(MIN) for at least the start-up time delay (tSD) for the device to be fully functional. VDD voltage is independent of VSENSE and VRESET, meaning that VDD can be higher or lower than the other pins. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO) When the voltage on VDD is less than the UVLO voltage, but greater than the power-on reset voltage (VPOR), the output pins will be in reset, regardless of the voltage at SENSE pins. 8.3.1.2 Power-On Reset (VDD < VPOR ) When the voltage on VDD is lower than the power on reset voltage (VPOR), the output signal is undefined and is not to be relied upon for proper device function. Note: Figure 8-2 and Figure 8-3 assume an external pull-up resistor is connected to the reset pin via VDD. SENSE VOLTAGE OUTSIDE OF THRESHOLD VITN > VSENSE > VITP VSENSE VDD(MIN) VDD UVLO(MIN) VPOR RESET Active Low Output stays low since VSENSE is outside of threshold VOL RESET Active High VOL Undefined tSD+tCTR Undefined Figure 8-2. Power Cycle (SENSE Outside of Nominal Voltage) 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 SENSE VOLTAGE WITH IN THRESHOLD VITN < VSENSE < VITP VSENSE VDD(MIN) VDD UVLO(MIN) VPOR RESET Active Low VOL RESET Active High VOL Undefined tSD+tCTR Undefined Figure 8-3. Power Cycle (SENSE Within Nominal Voltage) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 19 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3.2 SENSE The TPS3760 high voltage family integrates a voltage comparator, a precision reference voltage and a trimmed resistor divider. This configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and performance specifications. Device also has built-in hysteresis that provides noise immunity and ensures stable operation. Although not required in most cases, for noisy applications good analog design practice is to place a 10 nF to 100 nF bypass capacitor at the SENSE inputs in order to reduce sensitivity to transient voltages on the monitored signal. SENSE can be connected directly to VDD pin. 8.3.2.1 SENSE Hysteresis Built-in hysteresis to avoid erroneous output reset release. The hysteresis is opposite to the threshold voltage; for overvoltage options the hysteresis is subtracted from the positive threshold (VITP), for undervoltage options hysteresis is added to the negative threshold (VITN). VRESET VRESET VSENSE VSENSE VITP - VHYS VITP VITP - VHYS VITP Figure 8-4. Hysteresis (Overvoltage Active-Low) Figure 8-5. Hysteresis (Overvoltage Active-High) VRESET VRESET VSENSE VITN VITN VITN+VHYS Figure 8-6. Hysteresis (Undervoltage Active-High) 20 VSENSE VITN+VHYS Figure 8-7. Hysteresis (Undervoltage Active-Low) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 Table 8-1. Common Hysteresis Lookup Table TARGET DEVICE ACTUAL HYSTERESIS OPTION DETECT THRESHOLD TOPOLOGY RELEASE VOLTAGE (V) 18.0 V Overvoltage 17.5 V -3% 18.0 V Overvoltage 16.0 V -11% 17.0 V Overvoltage 16.5 V -3% 16.0 V Overvoltage 15.0 V -6% 15.0 V Overvoltage 14.0 V -7% 6.0 V Undervoltage 6.5 V 0.5 V 5.5 V Undervoltage 6V 0.5 V 8V Undervoltage 9V 1V 5V Undervoltage 7.5 V 2.5 V Table 8-1 shows a sample of hysteresis and voltage options for the TPS3760. For threshold voltages ranging from 2.7 V to 8 V, one option is to select a fixed hysteresis value ranging from 0.5 V to 2.5 V in increments of 0.5 V. Additionally, a second option can be selected where the hysteresis value is a percentage of the threshold voltage. The percentage of voltage hysteresis ranges from 2% to 13%. Knowing the amount of hysteresis voltage, the release voltage for the undervoltage (UV) channel is (VITN (UV) + VHYS) and for the overvoltage (OV) channel is (VITP (OV) - VHYS). The accuracy of the release voltage, or stated in the Electrical Characteristics as Hysteresis Accuracy is ±1.5%. Expanding what is shown in Table 8-1, below are a few voltage hysteresis examples that include the hysteresis accuracy: Undervoltage (UV) Channel VITN = 0.8 V Voltage Hysteresis (VHYS) = 5% = 40 mV Hysteresis Accuracy = ±1.5% = 39.4 mV or 40.6 mV Release Voltage = VITN + VHYS = 839.4 mV to 840.6 mV Overvoltage (OV) Channel VITP = 8 V Voltage Hysteresis (VHYS) = 2 V Hysteresis Accuracy = ±1.5% = 1.97 V or 2.03 V Release Voltage = VITN - VHYS = 5.97 V to 6.03 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 21 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3.3 Output Logic Configurations TPS3760 is a single channel device that has a single input sense pin and a single reset pin. The single channel is available as Open-Drain and Push-Pull. The available output logic configuration combinations are shown in Table 8-2. Table 8-2. TPS3760 Output Logic DESCRIPTION NOMENCLATURE VALUE GPN TPS3760 (+ topology) CHANNEL CONFIGURATION TPS3760A UV OD L Topology (OV and UV only) • • • • • • UV = Undervoltage OV = Overvoltage PP = Push-Pull OD = Open-Drain L = Active low H = Active high TPS3760B UV PP L TPS3760C UV OD H TPS3760D UV PP H TPS3760E OV OD L TPS3760F OV PP L TPS3760G OV OD H TPS3760H OV PP H 8.3.3.1 Open-Drain Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at the correct interface voltage levels. To select the right pull-up resistor consider system VOH and the (Ilkg) current provided in the electrical characteristics, high resistors values will have a higher voltage drop affecting the output voltage high. The open-drain output can be connected as a wired-AND logic with other open-drain signals such as another TPS3760 open-drain output pin. 8.3.3.2 Push-Pull Push-Pull output does not require an external resistor since is the output is internally pulled-up to VDD during VOH condition and output will be connected to GND during VOH condition. 8.3.3.3 Active-High (RESET) RESET (active-high), denoted with no bar above the pin label. RESET remains low (VOL, deasserted) as long as sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. To assert a reset sense pins needs to meet the condition below: • • For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN). For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP). 8.3.3.4 Active-Low (RESET) RESET (active low) denoted with a bar above the pin label. RESET remains high voltage (VOH, deasserted) (open-drain variant VOH is measured against the pullup voltage) as long as sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. To assert a reset sense pins needs to meet the condition below: • For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN). • For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP). 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3.4 User-Programmable Reset Time Delay TPS3760 has adjustable reset release time delay with external capacitors. • • A capacitor in CTR / MR programs the reset time delay of the output. No capacitor on this pin gives the fastest reset delay time indicated in the Section 7.6. 8.3.4.1 Reset Time Delay Configuration The time delay (tCTR) can be programmed by connecting a capacitor between CTR pin and GND. The relationship between external capacitor CCTR_EXT (typ) and the time delay tCTR (typ) is given by Equation 1. tCTR (typ) = -ln (0.28) x RCTR (typ) x CCTR_EXT (typ) + tCTR (no cap) (1) RCTR (typ) = is in kilo ohms (kOhms) CCTR_EXT (typ) = is given in microfarads (μF) tCTR (typ) = is the reset time delay (ms) The reset delay varies according to three variables: the external capacitor (CCTR_EXT), CTR pin internal resistance (RCTR) provided in Section 7, and a constant. The minimum and maximum variance due to the constant is show in Equation 2 and Equation 3: tCTR (min) = -ln (0.31) x RCTR (min) x CCTR_EXT (min) + tCTR (no cap (min)) (2) tCTR (max) = -ln (0.25) x RCTR (max) x CCTR_EXT (max) + tCTR (no cap (max)) (3) The recommended maximum reset delay capacitor for the TPS3760 is limited to 10 μF as this ensures enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) due to capacitor leakage and system noise can cause the the internal circuit to trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the presence of system noise. When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or duration of the voltage fault needs to be greater than 5% of the programmed reset time delay. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 23 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3.5 User-Programmable Sense Delay TPS3760 has adjustable sense release time delay with external capacitors. • • A capacitor in CTS programs the excursion detection on SENSE. No capacitor on these pins gives the fastest detection time indicated in the Section 7.6. 8.3.5.1 Sense Time Delay Configuration The time delay (tCTS) can be programmed by connecting a capacitor between CTS pin and GND. The relationship between external capacitor CCTS_EXT (typ) and the time delay tCTS (typ) is given by Equation 4. tCTS (typ) = -In (0.28) x RCTS (typ) x CCTS_EXT (typ) + tCTS (no cap) (4) RCTS = is in kilo ohms (kOhms) CCTS_EXT = is given in microfarads (μF) tCTS = is the sense time delay (ms) The sense delay varies according to three variables: the external capacitor (CCTS_EXT), CTS pin internal resistance (RCTS) provided in Electrical Characteristics, and a constant. The minimum and maximum variance due to the constant is show in Equation 5 and Equation 6: tCTS (min) = -ln (0.31) x RCTS (min) x CCTS_EXT (min) + tCTS (no cap (min)) (5) tCTS (max) = -ln (0.25) x RCTS (max) x CCTS_EXT (max) + tCTSx (no cap (max)) (6) The recommended maximum sense delay capacitor for the is limited to 10 μF as this ensures enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the presence of system noise. When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected time delay. A larger delay capacitor can be used so long as the capacitor has enough time between fault events to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or time duration between fault events needs to be greater than 10% of the programmed sense time delay. 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3.6 Manual RESET (CTR / MR) Input The manual reset input allows a processor or other logic circuits to initiate a reset. In this section MR is a generic reference to (CTR / MR). A logic low on MR causes RESET to assert on reset output. After MR is left floating, RESET will release the reset if the voltage at SENSE pin is at nominal voltage. MR should not be driven high, this pin should be left floating or connected to a capacitor to GND, this pin can be left unconnected if is not used. If the logic driving the MR cannot tri-state (floating and GND) then a logic-level FET should be used as illustrated in Figure 8-8. Low Voltage High Voltage VDD MCU CTR GPIO Low or Floa ng Reset Delay Ac
ve low Logic Figure 8-8. Manual Reset Implementation SENSE VOLTAGE WITH IN THRESHOLD VITN < VSENSE < VITP VSENSE CTR/MR < VMR MR floating or connected to capacitor MR floating or connected to capacitor RESET Active-High RESET Active-Low Figure 8-9. Manual Reset Timing Diagram Table 8-3. MR Functional Table MR SENSE ON NOMINAL VOLTAGE RESET STATUS Low Yes Reset asserted Floating Yes Fast reset release when SENSE voltage goes back to nominal voltage Capacitor Yes Programmable reset time delay High Yes NOT Recommended Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 25 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.3.7 RESET Latch Mode The TPS3760 features a output latch mode on the RESET/RESET pin when connecting the LATCH pin to common ground. A pull-down resistor, 10 kΩ, is recommended to limit current consumption of the system. In latch mode, if the RESET/RESET pin is low or triggers low and less than 1.4V is applied to the LATCH pin, the RESET/RESET pin stays asserted regardless if VSENSE goes within the acceptable voltage boundaries (VSENSE > VITP + Vhyst for UV or VSENSE < VITN - Vhyst for OV). To unlatch the device a voltage greater than 2.1 V for greater than 3 μs is applied to the LATCH pin. This is recommended to maintain a proper unlatch. The RESET/RESET pin triggers high after the duration of tctr. TI recommends using a series resistance to limit current when an unlatch voltage is applied. VDD(MIN) Vpor VITP VITN VSENSE LATCH UNDEFINED TCTR TCTR TCTR RESET Figure 8-10. Latch Timing Diagram 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 8.4 Device Functional Modes Table 8-4. Undervoltage Detect Functional Mode Truth Table SENSE CTR (1) / MR PIN VDD PIN OUTPUT (2) (RESET PIN) SENSE > VITN(UV) Open or capacitor connected VDD > VDD(MIN) High SENSE > VITN(UV) SENSE < VITN(UV) Open or capacitor connected VDD > VDD(MIN) Low Undervoltage Detection SENSE < VITN(UV) SENSE > VITN(UV) Open or capacitor connected VDD > VDD(MIN) Low Normal Operation SENSE < VITN(UV) SENSE > VITN(UV) + HYS Open or capacitor connected VDD > VDD(MIN) High Manual Reset SENSE > VITN(UV) SENSE > VITN(UV) Low VDD > VDD(MIN) Low UVLO Engaged SENSE > VITN(UV) SENSE > VITN(UV) Open or capacitor connected VPOR < VDD < VDD(MIN) Low Below VPOR, Undefined Output SENSE > VITN(UV) SENSE > VITN(UV) Open or capacitor connected VDD < VPOR Undefined DESCRIPTION PREVIOUS CONDITION CURRENT CONDITION Normal Operation SENSE > VITN(UV) Undervoltage Detection (1) (2) Reset time delay is ignored in the truth table. Open-drain active low output requires an external pull-up resistor to a pull-up voltage. Table 8-5. Overvoltage Detect Functional Mode Truth Table SENSE CTR (1) / MR PIN VDD PIN OUTPUT (2) (RESET PIN) SENSE < VITN(OV) Open or capacitor connected VDD > VDD(MIN) High SENSE < VITN(OV) SENSE > VITN(OV) Open or capacitor connected VDD > VDD(MIN) Low Overvoltage Detection SENSE > VITN(OV) SENSE < VITN(OV) Open or capacitor connected VDD > VDD(MIN) Low Normal Operation SENSE > VITN(OV) SENSE < VITN(OV) - HYS Open or capacitor connected VDD > VDD(MIN) High Manual Reset SENSE < VITN(OV) SENSE < VITN(OV) Low VDD > VDD(MIN) Low UVLO Engaged SENSE < VITN(OV) SENSE < VITN(OV) Open or capacitor connected VPOR < VDD < UVLO Low Below VPOR, Undefined Output SENSE < VITN(OV) SENSE < VITN(OV) Open or capacitor connected VDD < VPOR Undefined DESCRIPTION PREVIOUS CONDITION CURRENT CONDITION Normal Operation SENSE < VITN(OV) Overvoltage Detection (1) (2) Reset time delay is ignored in the truth table. Open-drain active low output requires an external pull-up resistor to a pull-up voltage. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 27 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The following sections describe in detail how to properly use this device. As this device has many applications and setups, there are many situations that this datasheet can not characterize in detail and will vary from these applications depending on the requirements of the final application 9.2 Adjustable Voltage Thresholds Equation 7 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends using the 0.8 V voltage threshold device when using an adjustable voltage variant. This variant bypasses the internal resistor ladder. For example, consider a 12 V rail being monitored VMON for undervoltage (UV) using of the TPS3760A012DYYR variant. Using Equation 7 and shown in Equation 8, R1 is the top resistor of the resistor divider that is between VMON and VSENSE, R2 is the bottom resistor that is between VSENSE and GND, VMON is the voltage rail that is being monitored and VSENSE is the input threshold voltage. The monitored UV threshold, denoted as VMON-, where the device will assert a reset signal occurs when VSENSE = VIT-(UV) or, for this example, VMON- = 10.8V which is 90% from 12 V. Using Equation 7 and assuming R2 = 10kΩ , R1 can be calculated shown in Equation 8 where IR1 is represented in Equation 9: VSENSE = VMON- × (R2 ÷ (R1 + R2)) (7) R1 = (VMON- - VSENSE) ÷ IR1 (8) IR1 = IR2 = VSENSE ÷ R2 (9) Substituting Equation 9 into Equation 8 and solving for R1 in Equation 7, R1 = 125kΩ. The TPS3760A012DYYR is typically meant to monitor a 0.8 V rail with ±2% voltage threshold hysteresis. For the reset signal to become deasserted, VMON would need to go above VIT- + VHYS. For this example, VMON = 11.016 V when the reset signal becomes deasserted. There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the values for the design specifications. The internal SENSE resistance RSENSE can be calculated by the SENSE voltage VSENSE divided by the SENSE current ISENSE as shown in Equation 11. VSENSE can be calculated using Equation 7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 10. 28 ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2) (10) RSENSE = VSENSE ÷ ISENSE (11) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 VDD VMON VDD R1 VDD VSENSE2 10 kΩ RESET SENSE TPS3760 R2 CTS CTR GND Figure 9-1. Adjustable Voltage Threshold with External Resistor Dividers 9.3 Typical Application 9.3.1 Design 1: Off-Battery Monitoring This application is intended for the initial power stage in applications with the 12 V batteries. Variation of the battery voltage is common between 9 V and 16 V. Furthermore, if cold-cranking and load dump conditions are considered, voltage transients can occur as low as 3 V and as high as 42 V. In this design example, we are highlighting the ability for low power, direct off-battery voltage supervision. Figure 11-1 illustrates an example of how the TPS3760 is monitoring the battery voltage while being powered by it, as well. DC/DC MCU VDD VDD RESET SENSE MCU Flag GPIO TPS3760 GND GND Backup Vba
Boost Converter Figure 9-2. TPS3760 Overvoltage Supervisor with Direct Off-Battery Monitoring Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 29 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 9.3.1.1 Design Requirements This design requires voltage supervision on a 12 V power supply voltage rail with possibility of the 12 V rail rising up as high as 42 V. The undervoltage fault occurs when the power supply voltage drops below 7.7 V. PARAMETER DESIGN REQUIREMENT DESIGN RESULT Power Rail Voltage Supervision Monitor 12-V power supply for undervoltage condition, trigger a undervoltage fault at 7.7 V. TPS3760 provides voltage monitoring with 1.5% max accuracy with adjustable/non-adjustable variations. Maximum Input Power Operate with power supply input up to 42 V. The TPS3760 can support a VDD of up to 65 V. Output logic voltage Open-Drain Output Topology An open-drain output is recommended to provide the correct reset signal, but a push-pull can also be used. Maximum system current consumption 2 µA max when power supply is at 12 V typical TPS3760 allows for IQ to remain low with support of up to 65 V. This allows for no external resistor divider to be required. Voltage Monitor Accuracy Maximum voltage monitor accuracy of 1.5%. The TPS3760 has 1.5% maximum voltage monitor accuracy. Delay when returning from fault condition RESET delay of at least 12.8 ms when returning from a undervoltage fault. CCTR = 10 nF sets 12.8 ms delay 9.3.1.2 Detailed Design Procedure The primary advantage of this application is being able to directly monitor a voltage on an automotive battery without needing external an resistor dividers on the SENSE input. This keeps the overall IQ of the design low while still achieving the desired rail monitoring. Voltage rail monitoring is done by connecting the SENSE input directly to the battery rail after the TVS protection diodes. The TPS3760 that is being used in this example is a fixed voltage variant where theSENSE threshold voltage has been set internally. Word of caution, the TVS protection diodes must be chosen such that the transient voltages on the monitored rails do not exceed the absolute max limit listed in Section 7.1. To use this configuration, the specific voltage threshold variation of the device must be chosen according to the application. In this configuration, the '77' variation must be chosen for 7.7 V as shown in Section 5. The device being able to handle 65 V on VDD means the monitored voltage rail can go as high as 42 V for the application transients and not violate the recommended maximum for the supervisor as it usually would. This is useful when monitoring a voltage rail that has a wide range that may go much higher than the nominal rail voltage such as in this case. Good design practice recommends using a 0.1 µF capacitor on the VDD pin and this capacitance may need to increase if using an adjustable version with a resistor divider. 30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 9.3.1.3 Application Curves V_SENSE RESET_B Figure 9-3. Undervoltage Reset Waveform V_SENSE RESET_B Figure 9-4. Undervoltage Recovery Waveform Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 31 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 10 Power Supply Recommendations These devices are designed to operate from an input supply with a voltage range between 1.4 V (VPOR) to 65 V (maximum operation). Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin. 10.1 Power Dissipation and Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. The maximum continuous allowable power dissipation for the device in a given package can be calculated using Equation 12: PD-MAX = ((TJ-MAX – TA) / RθJA) (12) The actual power being dissipated in the device can be represented by Equation 13: PD = VDD × IDD + pRESET (13) pRESET is calculated by Equation 14 or Equation 15 pRESET (PUSHPULL) = VDD - VRESET x IRESET (14) pRESET (OPEN-DRAIN) = VRESET x IRESET (15) Equation 12 and Equation 13 establish the relationship between the maximum power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present, the maximum ambient temperature (TA-MAX) may be increased. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature (TA-MAX) may have to be de-rated. TA-MAX is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by Equation 16: TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) 32 (16) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 11 Layout 11.1 Layout Guidelines • • • • • • Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin. To further improve the noise immunity on the SENSE pins, placing a 10 nF to 100 nF capacitor between the SENSE pin and GND can reduce the sensitivity to transient voltages on the monitored signal. If a capacitor is used on CTS or CTR, place these components as close as possible to the respective pins. If the capacitor adjustable pins are left unconnected, make sure to minimize the amount of parasitic capacitance on the pins to less than 5 pF. For open-drain variants, place the pull-up resistors on RESET as close to the pin as possible. When laying out metal traces, separate high voltage traces from low voltage traces as much as possible. If high and low voltage traces need to run close by, spacing between traces should be greater than 20 mils (0.5 mm). Do not have high voltage metal pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or traces. 11.2 Layout Example The layout example in Figure 11-1 shows how the TPS3760 is laid out on a printed circuit board (PCB) with user-defined delays. CVDD 1 VDD NC 14 2 NC 13 GND TPS3760 3 Monitored Voltage 12 NC NC DYY Package NC 4 11 NC 5 10 6 9 7 8 CSENSE GND Reset Flag NC GND RPU VPULL-UP Vias used to connect pins for application-specific connections Figure 11-1. TPS3760 Recommended Layout Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 33 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 11.3 Creepage Distance Per IEC 60664 Creepage is the shortest distance between two conductive parts or as shown in Figure 11-2 the distance between high voltage conductive parts and grounded parts, the floating conductive part is ignored and subtracted from the total distance. b a A B C Figure 11-2. Creepage Distance Figure 11-2 details • • • • 34 A = Left pins (high voltage) B = Central pad (conductive not internally connected, can be left floating or connected to GND) C = Right pins (low voltages) Creepage distance = a + b Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 12 Device and Documentation Support 12.1 Device Nomenclature Section 5 shows how to decode the function of the device based on its part number Table 12-1 shows possible voltage options per channel. Contact TI sales representatives or on TI's E2E forum for details and availability of other options; minimum order quantities apply. Table 12-1. Voltage Options 100 mV STEPS 400 mV STEPS 500 mV STEPS 1 V STEPS NOMENCLATURE VOLTAGE OPTIONS NOMENCLATURE VOLTAGE OPTIONS NOMENCLATURE VOLTAGE OPTIONS NOMENCLATURE VOLTAGE OPTIONS NOMENCLATURE VOLTAGE OPTIONS 01 800 mV (divider bypass) 70 7.0 V A0 10.4 V D0 20.5 V F0 31.0 V 27 2.7 V 71 7.1 V A1 10.8 V D1 21.0 V F1 32.0 V 28 2.8 V 72 7.2 V A2 11.2 V D2 21.5 V F2 33.0 V 29 2.9 V 73 7.3 V A3 11.6 V D3 22.0 V F3 34.0 V 30 3.0 V 74 7.4 V A4 12.0 V D4 22.5 V F4 35.0 V 31 3.1 V 75 7.5 V A5 12.4 V D5 23.0 V F5 36.0 V 32 3.2 V 76 7.6 V A6 12.8 V D6 23.5 V 33 3.3 V 77 7.7 V A7 13.2 V D7 24.0 V 34 3.4 V 78 7.8 V A8 13.6 V D8 24.5 V 35 3.5 V 79 7.9 V A9 14.0 V D9 25.0 V 36 3.6 V 80 8.0 V B0 14.4 V E0 25.5 V 37 3.7 V 81 8.1 V B1 14.8 V E1 26.0 V 38 3.8 V 82 8.2 V B2 15.2 V E2 26.5 V 39 3.9 V 83 8.3 V B3 15.6 V E3 27.0 V 40 4.0 V 84 8.4 V B4 16.0 V E4 27.5 V 41 4.1 V 85 8.5 V B5 16.4 V E5 28.0 V 42 4.2 V 86 8.6 V B6 16.8 V E6 28.5 V 43 4.3 V 87 8.7 V B7 17.2 V E7 29.0 V 44 4.4 V 88 8.8 V B8 17.6 V E8 29.5 V 45 4.5 V 89 8.9 V B9 18.0 V E9 30.0 V 46 4.6 V 90 9.0 V C0 18.4 V 47 4.7 V 91 9.1 V C1 18.8 V 48 4.8 V 92 9.2 V C2 19.2 V 49 4.9 V 93 9.3 V C3 19.6 V 50 5.0 V 94 9.4 V C4 20.0 V 51 5.1 V 95 9.5 V 52 5.2 V 96 9.6 V 53 5.3 V 97 9.7 V 54 5.4 V 98 9.8 V 55 5.5 V 99 9.9 V 56 5.6 V 00 10.0 V 57 5.7 V 58 5.8 V 59 5.9 V 60 6.0 V 61 6.1 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 35 TPS3760 www.ti.com SBVS420A – MARCH 2022 – REVISED SEPTEMBER 2023 Table 12-1. Voltage Options (continued) 100 mV STEPS NOMENCLATURE VOLTAGE OPTIONS 62 6.2 V 63 6.3 V 64 6.4 V 65 6.5 V 66 6.6 V 67 6.7 V 68 6.8 V 69 6.9 V NOMENCLATURE 400 mV STEPS VOLTAGE OPTIONS NOMENCLATURE VOLTAGE OPTIONS 500 mV STEPS NOMENCLATURE VOLTAGE OPTIONS 1 V STEPS NOMENCLATURE VOLTAGE OPTIONS 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS3760 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3760A012DYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A012 Samples TPS3760E012DYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 E012 Samples TPS3760E565DYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 E565 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of