TPS3806I33QDBVRQ1

TPS3806I33-Q1 www.ti.com SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 Dual Voltage Detector With Adjustable Hysteresis Check for Samples: TPS3806I33-Q1 FEATURES 1 • • • • • • • DESCRIPTION Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C4B Dual Voltage Detector With Adjustable Hysteresis, 3.3-V Adjustable and 2-V Adjustable Assured Reset at VDD = 0.8 V Supply Current: 3 µA Typical at VDD = 3.3 V Independent Open-Drain Reset Outputs 6-Pin SOT-23 Package The TPS3806I33-Q1 integrates two independent voltage detectors for battery voltage monitoring. During power on, the device asserts RESET and RSTSENSE when supply voltage VDD or the voltage at the LSENSE input becomes higher than 0.8 V. Thereafter, the supervisory circuit monitors VDD and LSENSE, keeping RESET and RSTSENSE active as long as VDD and LSENSE remain below the threshold voltage, VIT. As soon as VDD or LSENSE rises above the threshold voltage VIT, the device deasserts RESET or RSTSENSE, respectively. The TPS3806I33-Q1 device has a fixed-sense threshold voltage VIT set by an internal voltage divider at VDD and an adjustable second-LSENSE input. In addition, one can set an upper voltage threshold at HSENSE to allow a wide adjustable hysteresis window. The devices are available in a 6-pin SOT-23 package. Characterization of the TPS3806I33-Q1 device is for operation over a temperature range of –40°C to 125°C. APPLICATIONS • • • Voltage Supervisor Voltage Detector Battery Monitor TPS3806I33-Q1 DBV PACKAGE (TOP VIEW) 1 6 HSENSE GND 2 5 LSENSE RESET 3 4 VDD RSTSENSE VDD R1 3.6 V Li-lon Cell RESET R4 R5 TPS3806I33-Q1 LSENSE RSTSENSE HSENSE GND R2 R3 Typical Operating Circuit 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS3806I33-Q1 SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) (1) TA PACKAGE QUANTITY PART NUMBER TOP-SIDE SYMBOL STATUS –40°C to 125°C DBV (SOT-23) Reel of 3000 TPS3806I33QDBVRQ1 PZHQ Active For the most-current package and ordering information, see the Package Option Addendum located at the end of this data sheet or refer to the TI Web site at www.ti.com. TPS380 6 I 33 DBV R Reel Package Nominal Supply Voltage Nominal Threshold Voltage Functionality Family ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage, VDD (2) All other pins (2) TPS3806I33-Q1 UNIT 7 V –0.3 to 7 V 5 mA Maximum high-output current, IOH –5 mA Input clamp current, IIK (VI < 0 or VI > VDD) ±10 mA Output clamp current, IOK (VO < 0 or VO > VDD) ±10 mA Operating free-air temperature range, TA –40 to 125 °C Storage temperature range, Tstg –65 to 150 °C 2 kV 750 V Maximum low-output current, IOL Electrostatic discharge rating, ESD (1) (2) 2 Human-body model (HBM) AEC-Q100 Classification Level H2 Charged-device model (CDM) AEC-Q100 Classification Level C4B Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. For reliable operation, the device must not be continuously operated at 7 V for more than t = 1000 h. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 TPS3806I33-Q1 www.ti.com SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 THERMAL INFORMATION TPS3806I33-Q1 THERMAL METRIC (1) DBV UNIT 6 PINS Junction-to-ambient thermal resistance (2) θJA (3) 188.9 °C/W θJCtop Junction-to-case (top) thermal resistance 130.9 °C/W θJB Junction-to-board thermal resistance (4) 34.2 °C/W ψJT Junction-to-top characterization parameter (5) 25.4 °C/W ψJB Junction-to-board characterization parameter (6) 33.8 °C/W θJCbot Junction-to-case (bottom) thermal resistance (7) N/A °C/W (1) (2) (3) (4) (5) (6) (7) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD Input voltage, VI Operating free-air temperature range, TA MAX UNIT 1.3 6 V 0 VDD + 0.3 V –40 125 °C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 3 TPS3806I33-Q1 SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 1.5 V, IOL = 1 mA VOL Low-level output voltage VDD = 3.3 V, IOL = 2 mA 0.3 V 0.2 V VDD = 6 V, IOL = 3 mA Power-up reset voltage (1) VDD ≥ 0.8 V, IOL = 50 µA LSENSE TA = 25°C TPS3806I33-Q1 VIT LSENSE Negative-going input threshold voltage (2) TA = 0°C to 70°C TPS3806I33-Q1 LSENSE TA = –40°C to 125°C TPS3806I33-Q1 Vhys Hysteresis II Input current IOH High-level output current IDD Supply current Ci Input capacitance (1) (2) 1.198 1.207 1.216 2.978 3 3.022 1.188 1.207 1.226 2.952 3 3.048 1.183 1.207 1.231 2.94 3 3.06 1.2 V < VIT < 2.5 V 60 2.5 V < VIT < 3.5 V 90 LSENSE, HSENSE –25 VDD = VIT + 0.2 V, VOH = VDD V mV 25 nA 300 nA VDD = 3.3 V, output unconnected 3 5 VDD = 6 V, output unconnected 4 6 VI = 0 V to VDD 1 µA pF The lowest supply voltage at which RESET becomes active. tr,VDD ≥ 15 µs/V To ensure best stability of the threshold voltage, place a bypass capacitor (ceramic, 0.1 µF) near the supply terminals. SWITCHING CHARACTERISTICS at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C PARAMETER tPHL tPLH TEST CONDITIONS Propagation (delay) time, high-to-low-level output VDD to RESET delay Propagation (delay) time, low-to-high-level output VDD to RESET delay LSENSE to RSTSENSE delay MIN TYP MAX UNIT 5 100 µs 5 100 µs VIH = 1.05 x VIT, VIL = 0.95 x VIT HSENSE to RSTSENSE delay TIMING REQUIREMENTS at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C PARAMETER tw 4 Pulse duration TEST CONDITIONS At VDD At SENSE VIH = 1.05 x VIT, VIL = 0.95 x VIT Submit Documentation Feedback MIN 5.5 TYP MAX UNIT µs Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 TPS3806I33-Q1 www.ti.com SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 VDD VIT(HSENSE) VIT(LSENSE) VIT,VDD+Vhys VIT(VDD) 0.8 V RSTSENSE RESET = Undefined Table 2. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION GND 2 I Ground HSENSE 6 I Adjustable hysteresis input LSENSE 5 I Adjustable sense input RESET 3 O Active-low open-drain reset output (from VDD) RSTSENSE 1 O Active-low open-drain reset output (from LSENSE) VDD 4 I Input supply voltage and fixed sense input FUNCTION AND TRUTH TABLE TPS3806I33-Q1 VDD > VIT RESET LSENSE > VIT 0 L 0 RSTSENSE L 1 H 1 H Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 5 TPS3806I33-Q1 SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM TPS3806 LSENSE _ HSENSE RSTSENSE + R1 _ VDD R2 RESET + GND Reference Voltage of 1.207 V Detailed Description Operation The TPS3806I33-Q1 monitors battery voltage and asserts RESET when a battery becomes discharged below a certain threshold voltage. A comparator monitors the battery voltage via an external resistor divider. When the voltage at the LSENSE input drops below the internal reference voltage, the RSTSENSE output pulls low. The output remains low until the battery is replaced, or recharged above a second higher trip-point, set at HSENSE. One can monitor a second voltage at VDD. The independent RESET output pulls low when the voltage at VDD drops below the fixed threshold voltage. Because the TPS3806I33-Q1 outputs are open-drain MOSFETs, most applications may require a pullup resistor. Programming the Threshold Voltage Levels Calculate the low-voltage threshold at LSENSE according to Equation 1: V (LSENSE) +V ref ) R2 ) R3Ǔ ǒR1 R2 ) R3 (1) where Vref = 1.207 V Calculate the high-voltage threshold at HSENSE as shown in Equation 2: V (HSENSE) +V ref ) R3Ǔ ǒR1 ) R2 R3 (2) where Vref = 1.207 V To minimize battery current draw, TI recommends using 1 MΩ as the total resistor value R(tot), with R(tot) = R1 + R2 + R3. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 TPS3806I33-Q1 www.ti.com SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS SUPPLY CURRENT versus SUPPLY VOLTAGE LOW-LEVEL OUTPUT VOLTAGE versus LOW-LEVEL OUTPUT CURRENT 6 1.60 V(HSENSE) < V(LSENSE) RESET = Open RSTSENSE = Open 4 3 85°C 25°C 2 0°C −40°C 1 VDD = 1.5 V V(SENSE) = Low 1.40 VOL − Low-Level Output Voltage − V I DD − Supply Current − µ A 5 1.20 85°C 1.00 25°C 0.80 0°C 0.60 −40°C 0.40 0.20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 6 0 1 VDD − Supply Voltage − V LOW-LEVEL OUTPUT VOLTAGE versus LOW-LEVEL OUTPUT CURRENT 4 5 LOW-LEVEL OUTPUT VOLTAGE versus LOW-LEVEL OUTPUT CURRENT 3.5 0.50 VDD = 1.5 V V(SENSE) = Low 0.40 85°C 0.35 25°C 0.30 0°C 0.25 VDD = 6 V V(SENSE) = Low 3 VOL − Low-Level Output Voltage − V 0.45 VOL − Low-Level Output Voltage − V 3 IOL − Low-Level Output Current − mA Figure 2. Figure 1. −40°C 0.20 0.15 0.10 0.05 0 2 85°C 2.5 25°C 2 0°C −40°C 1.5 1 0.5 Expanded View 0 0.5 1 1.5 2 2.5 3 0 0 5 IOL − Low-Level Output Current − mA Figure 3. 10 15 20 25 30 35 40 45 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 50 IOL − Low-Level Output Current − mA Figure 4. 7 TPS3806I33-Q1 SLVSBW8A – MARCH 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 1 VDD = 6 V V(SENSE) = Low VOL − Low-Level Output Voltage − V 0.9 85°C 0.8 25°C 0.7 0°C 0.6 −40°C 0.5 0.4 0.3 0.2 Expanded View 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL − Low-Level Output Current − mA VIT − Normalized Input Threshold Voltage VIT(TA) / VIT(25°C) LOW-LEVEL OUTPUT VOLTAGE versus LOW-LEVEL OUTPUT CURRENT NORMALIZED INPUT THRESHOLD VOLTAGE versus FREE-AIR TEMPERATURE AT VDD 1.005 RESET = 100 kΩ to VDD 1.004 1.003 1.002 1.001 1 0.999 0.998 0.997 0.996 0.995 −40 −20 MINIMUM PULSE DURATION AT VDD versus VDD THRESHOLD OVERDRIVE VOLTAGE 60 80 10 tw − Minimum Pulse Duration at LSENSE − µs tw − Minimum Pulse Duration at VDD − µs 40 MINIMUM PULSE DURATION AT LSENSE versus LSENSE THRESHOLD OVERDRIVE VOLTAGE 10 9 8 7 6 5 4 3 2 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VDD − Threshold Overdrive Voltage − V Figure 7. 8 20 TA − Free-Air Temperature at VDD − °C Figure 6. Figure 5. 0 0 1 9 8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 LSENSE − Threshold Overdrive Voltage − V Figure 8. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS3806I33-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS3806I33QDBVRQ1 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PZHQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of