TPS3808
TPS3808
ZHCSM34L – MAY 2004 – REVISED SEPTEMBER
2020
ZHCSM34L – MAY 2004 – REVISED SEPTEMBER 2020
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TPS3808 低静态电流、可编程延迟监控电路
1 特性
3 说明
• 上电复位发生器具有可调节延迟时间：1.25ms 至
10s
• 超低静态电流：2.4μA（典型值）
• 高阈值精度：0.5% 典型值
• 提供适用于标准电压轨的 0.9V 至 5V 固定阈值电压
且可调节电压低至 0.4V
• 手动复位 (MR) 输入
• 开漏复位 输出
• 温度范围：–40°C 至 125°C
• 小型 SOT-23 和 2mm × 2mm WSON 封装
TPS3808 系列微处理器监控电路可监控从 0.4V 至 5V
的系统电压，并在 SENSE 电压 降至预设阈值以下或
手 动 复 位 (MR) 引 脚 降 至 逻 辑 低 电 平 时 ， 将 开 漏
RESET 信号置为有效。在 SENSE 电压 和手动复位
(MR) 返回值超出相应阈值时，RESET 输出将在用户
可调延迟时间内保持低电平。
2 应用
•
•
•
•
•
DSP 或微控制器应用
笔记本电脑和台式机
PDA 和手持式产品
便携式和电池供电类产品
FPGA 和 ASIC 应用
TPS3808 器件使用精密电压基准，可在 V IT ≤3.3V 时
达到 0.5% 的阈值精度。通过断开 C T 引脚，可将复位
延迟时间设置为 20ms；通过使用电阻将 C T 引脚连接
至 V DD，可将复位延迟时间设置为 300ms，或通过将
C T 引脚连接到外部电容器，用户可在 1.25ms 至 10s
之间调整复位延迟时间。TPS3808 器件具有超低的典
型静态电流，为 2.4μA，因此非常适合电池供电类应
用。它采用 SOT-23 和 2mm × 2mm WSON 封装，额
定工作温度范围为 –40°C 至 125°C (TJ)。
器件信息
封装 (1)
器件型号
TPS3808
(1)
1.2 V
3.3 V
TPS3808G12
TPS3808G33
VI/O
VCORE
DSP
MR
RESET
CT
GND
典型应用
IDD (mA)
SENSE VDD
GND
2.90mm x 1.60mm
WSON (6)
2.00mm x 2.00mm
4.0
SENSE VDD
CT
SOT-23 (6)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
-40°C
25°C
85°C
125°C
3.5
RESET
封装尺寸（标称值）
3.0
2.5
GPIO
GND
2.0
1.5
1.5
2.5
4.5
3.5
5.5
6.5
VDD (V)
电源电流与电源电压间的关系
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
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English
Data
Sheet:
SBVS050
Product Folder Links: TPS3808
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TPS3808
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Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Voltage Thresholds.............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................7
7.7 Typical Characteristics................................................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................13
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................17
12.1 Device Support....................................................... 17
12.2 Documentation Support.......................................... 17
12.3 Support Resources................................................. 17
12.4 Trademarks............................................................. 17
12.5 Electrostatic Discharge Caution..............................17
12.6 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision K (October 2015) to Revision L (September 2020)
Page
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
Changes from Revision J (August 2008) to Revision K (October 2015)
Page
• 添加了 ESD 等级 表、特性说明 部分、器件功能模式、应用和实现 部分、电源相关建议 部分、布局 部分、器
件和文档支持 部分以及机械、封装和可订购信息 部分。移动了开关特性 表、时序图和相关的真值表。.......... 1
• Changed 图 9-1; removed capacitor shown on CT .......................................................................................... 14
2
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5 Device Voltage Thresholds
The following table shows the nominal rail to be monitored and the corresponding threshold voltage of the
device.
(1)
PART NUMBER
NOMINAL SUPPLY VOLTAGE(1)
THRESHOLD VOLTAGE (VIT)
TPS3808G01
Adjustable
0.405 V
TPS3808G09
0.9 V
0.84 V
TPS3808G12
1.2 V
1.12 V
TPS3808G125
1.25 V
1.16 V
TPS3808G15
1.5 V
1.40 V
TPS3808G18
1.8 V
1.67 V
TPS3808G19
1.9 V
1.77 V
TPS3808G25
2.5 V
2.33 V
TPS3808G30
3V
2.79 V
TPS3808G33
3.3 V
3.07 V
TPS3808G50
5V
4.65 V
Custom threshold voltages from 0.82 V to 3.3 V, 4.4 V to 5 V are available through the use of
factory EEPROM programming. Minimum order quantities apply. Contact the factory for details and
availability.
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6 Pin Configuration and Functions
RESET
VDD
VDD
6
1
GND
2
5
SENSE
MR
3
4
CT
图 6-1. DBV Package 6-Pin SOT-23 Top View
1
SENSE
2
CT
3
THERMAL
PAD
6
RESET
5
GND
4
MR
图 6-2. DRV Package 6-Pin (2.00 mm × 2.00 mm)
WSON With Thermal Pad Top View
表 6-1. Pin Functions
PIN
NAME
4
SOT-23
WSON
I/O
DESCRIPTION
Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ
resistor or leaving it open results in fixed delay times (see 节 7.5). Connecting this pin to a
ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See 节
8.3.2 for more information.
CT
4
3
I
GND
2
5
—
MR
3
4
I
Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to VDD by a
90-kΩ pull-up resistor.
Ground
RESET
1
6
O
RESET is an open-drain output that is driven to a low-impedance state when RESET is
asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is
set to a logic low). RESET remains low (asserted) for the reset period after both SENSE
is above VIT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should
be used on this pin, and allows the reset pin to attain voltages higher than VDD.
SENSE
5
2
I
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops
below the threshold voltage VIT, then RESET is asserted.
VDD
6
1
I
Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor
close to this pin.
Thermal
Pad
—
Pad
—
Thermal Pad. Connect to ground plane to enhance thermal performance of package.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Voltage
Current
Temperature
(1)
(2)
MIN
MAX
UNIT
VDD
–0.3
7
V
VCT
–0.3
VDD + 0.3
V
VRESET, VMR, VSENSE
–0.3
7
V
RESET pin
–5
5
mA
Operating junction, TJ (2)
–40
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Input supply range
1.7
6.5
V
VSENSE
SENSE pin voltage
0
6.5
V
V(Ct)
CT pin voltage
VDD
V
V MR
MR pin voltage
0
6.5
V
V RESET
RESET pin voltage
0
6.5
V
I RESET
RESET pin current
0.0003
5
mA
7.4 Thermal Information
TPS3808
THERMAL
METRIC(1)
DBV (SOT-23)
DRV (WSON)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
180.9
178.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
117.8
95.6
°C/W
RθJB
Junction-to-board thermal resistance
27.8
135
°C/W
ψJT
Junction-to-top characterization parameter
1.12
6.3
°C/W
ψJB
Junction-to-board characterization parameter
27.3
136.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
7.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless
otherwise noted. Typical values are at TJ = 25°C(1).
PARAMETER
–40°C < TJ < 125°C
Input supply range
VDD
IDD
0°C < TJ < 85°C
Supply current (current into VDD pin)
Low-level output voltage
VOL
Power-up reset
VPOR
TEST CONDITIONS
voltage(2)
6
1.7
6.5
V
6.5
V
VDD = 6.5 V, RESET not asserted
MR, RESET, CT open
2.7
6
μA
1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA
0.3
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA
0.4
VOL (max) = 0.2 V, I RESET = 15 μA
0.8
–2%
±1%
2%
–1.5%
±0.5%
1.5%
–2%
±1%
2%
VIT ≤ 3.3 V
–40°C < TJ < 85°C
–
1.25%
±0.5%
1.25%
3.3 V < VIT ≤ 5.0 V
–40°C < TJ < 85°C
–1.5%
±0.5%
1.5%
1.5%
3%
1%
2.5%
TPS3808G01
Hysteresis on VIT pin
R MR
MR Internal pullup resistance
Fixed versions
70
TPS3808G01
VSENSE = VIT
Fixed versions
VSENSE = 6.5 V
UNIT
1.65
5
3.3 V < VIT ≤ 5.0 V
VHYS
90
Input current at
SENSE pin
IOH
RESET leakage current
V RESET = 6.5 V, RESET not asserted
CIN
Input capacitance, any CT pin
pin
Other pins
VIN = 0 V to VDD
5
VIN = 0 V to 6.5 V
5
VIL
MR logic low input
VIH
MR logic high input
V
VIT
kΩ
25
–25
ISENSE
(1)
(2)
MAX
2.4
VIT ≤ 3.3 V
VIT
TYP
VDD = 3.3 V, RESET not asserted
MR, RESET, CT open
TPS3808G01
Negative-going input
threshold accuracy
MIN
1.7
nA
μA
300
nA
pF
0
0.3 VDD
0.7 VDD
VDD
V
The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15 μs/V.
RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin.
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7.6 Switching Characteristics
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless
otherwise noted. Typical values are at TJ = 25°C.(1)
PARAMETER
tw
TEST CONDITIONS
SENSE
Input pulse width to
RESET
MR
CT = VDD
RESET delay time
20
VIH = 0.7 VDD, VIL = 0.3 VDD
0.001
See 图 7-1
CT = 100 pF
CT = 180 nF
(1)
TYP
VIH = 1.05 VIT, VIL = 0.95 VIT
CT = Open
td
MIN
MAX UNIT
μs
12
20
28
180
300
420
0.75
1.25
1.75
0.7
1.2
1.7
ms
s
Propagation delay
MR to RESET
VIH = 0.7 VDD, VIL = 0.3 VDD
150
ns
High-to-low level RESET
delay
SENSE to RESET
VIH = 1.05 VIT, VIL = 0.95 VIT
20
μs
RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin.
VDD
0.8V
0.0V
RESET
tD = Reset Delay
tD
tD
tD
= Undefined State
SENSE
VIT + VHYS
VIT
MR
0.7VDD
0.3VDD
Time
图 7-1. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing
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7.7 Typical Characteristics
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF, unless otherwise noted.
4.0
100
3.5
+125°C
+85°C
2.5
2.0
+25°C
1.5
10
RESET Timeout (sec)
IDD (mA)
3.0
1.0
−40°C, +25°C, +125°C
1
0.1
0.01
−40°C
0.5
0.001
0.0001
0
0
1
2
3
4
5
6
7
0.001
0.01
VDD (V)
图 7-2. Supply Current vs Supply Voltage
Transient Duration below VIT (ms)
Normalized RESET Timeout Period (%)
6
4
2
0
−2
−4
−6
−8
RESET OCCURS
ABOVE THE CURVE
10
1
−10
−30
−10
10
30
50
70
90
110
0
130
5
10
图 7-4. Normalized RESET Time-Out Period vs
Temperature (CT = Open, CT = VDD, CT = Any)
20
25
30
35
40
45
50
图 7-5. Maximum Transient Duration at Sense vs
Sense Threshold Overdrive Voltage
4.5
VOL Low−Level RESET Voltage (V)
1.0
0.8
0.6
Normalized VIT (%)
15
Overdrive (%VIT)
Temperature (°C)
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
4.0
3.5
3.0
2.5
2.0
VDD = 1.8 V
1.5
1.0
0.5
0
−30
−10
10
30
50
70
90
110
130
0
Temperature (°C)
图 7-6. Normalized Sense Threshold Voltage (VIT)
vs Temperature
8
10
100
8
−50
1
图 7-3. RESET Time-Out Period vs CT
10
−50
0.1
CT (mF)
0.5
1.0
1.5
2.0
2.5
RESET Current (mA)
3.0
3.5
4.0
图 7-7. Low-Level RESET Voltage vs RESET
Current
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VOL Low−Level RESET Voltage (V)
0.8
0.7
0.6
0.5
0.4
VDD = 3.3 V
0.3
0.2
0.1
VDD = 6.5 V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
RESET Current (mA)
图 7-8. Low-Level RESET Voltage vs RESET Current
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8 Detailed Description
8.1 Overview
The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the
SENSE pin voltage drops below V IT or the manual reset ( MR) is driven low. The RESET output remains
asserted for a user-adjustable time after both the manual reset ( MR) and SENSE voltages return above their
respective thresholds.
8.2 Functional Block Diagram
VDD
VDD
VDD
VDD
TPS3808G01
Adjustable Version
90 kW
90 kW
RESET
MR
RESET
MR
SENSE
Reset
Logic
Timer
SENSE
Reset
Logic
Timer
R1
CT
CT
R2
0.4 V
VREF
0.4 V
VREF
R1 + R2 = 4 MW
GND
GND
Adjustable Voltage Version
Fixed Voltage Version
8.3 Feature Description
A broad range of voltage threshold and reset delay time adjustments are available for the TPS3808 device,
allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set
from 0.82 V to 3.3 V or from 4.4 V to 5 V, while the TPS3808G01 can be set to any voltage above 0.405 V using
an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD results
in a 300-ms reset delay, whereas leaving the C T pin open yields a 20-ms reset delay. In addition, connecting a
capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s.
8.3.1 SENSE Input
The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops
below V IT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET
assertions and de-assertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the
SENSE input to reduce sensitivity to transients and layout parasitics.
The TPS3808 device is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
is dependent on threshold overdrive, as shown in (图 7-5).
The TPS3808G01 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in 图 8-1.
10
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VIN
VOUT
VDD
VIT¢ = (1 +
R1
R1
) 0.405
R2
TPS3808G01
SENSE
RESET
1nF
R2
GND
图 8-1. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage
8.3.2 Selecting the RESET Delay Time
The TPS3808 has three options for setting the RESET delay time as shown in 图 8-2. 图 8-2 (a) shows the
configuration for a fixed 300-ms typical delay time by tying C T to V DD; a resistor from 40 kΩ to 200 kΩ must be
used. Supply current is not affected by the choice of resistor. 图 8-2 (b) shows a fixed 20-ms delay time by
leaving the C T pin open. 图 8-2 (c) shows a ground referenced capacitor connected to C T for a user-defined
program time between 1.25 ms and 10 s.
3.3V
3.3V
50kΩ
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
TPS3808G33
TPS3808G33
TPS3808G33
CT
CT
RESET
RESET
CT
RESET
CT
300ms Delay
20ms Delay
Delay (s) = CT (nF) + 0.5 x 10−3 (s)
175
(c)
(b)
(a)
图 8-2. Configuration Used to Set the RESET Delay Time
The capacitor C T should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor
is present. The capacitor value for a given delay time can be calculated using 方程式 1.
C T (nF) = t D (s) – 0.5 × 10 - 3 (s) × 175
[
]
(1)
The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the
external capacitor to 1.23 V. When a RESET is asserted, the capacitor is discharged. When the RESET
conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When
the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such
as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay
time.
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8.3.3 Manual RESET ( MR) Input
The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on
MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is
de-asserted after the user-defined reset delay expires. Note that MR is internally tied to V DD using a 90-kΩ
resistor, so this pin can be left unconnected if MR is not used.
See 图 8-3 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR
does not go fully to V DD, there is some additional current draw into V DD as a result of the internal pullup resistor
on MR. To minimize current draw, a logic-level FET can be used as illustrated in 图 8-4.
1.2V
3.3V
SENSE
V DD
SENSE V DD
TPS3808G12
TPS3808G33
RESET
V CORE
DSP
MR
RESET
CT
V I/O
CT
GND
GND
GPIO
GND
图 8-3. Using MR to Monitor Multiple System Voltages
3.3V
V DD SENSE
90kW
MR
TPS3808xxx
GND
图 8-4. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD
8.3.4 RESET Output
RESET remains high (unasserted) as long as SENSE is above its threshold (V IT) and the manual reset ( MR) is
logic high. If either SENSE falls below V IT or MR is driven low, RESET is asserted, driving the RESET pin to a
low impedance.
Once MR is again logic high and SENSE is above V IT + V HYS (the threshold hysteresis), a delay circuit is
enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET
pin goes to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be
used to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6.5 V). The pullup
resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.
12
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8.4 Device Functional Modes
表 8-1. Truth Table
MR
SENSE > VIT
RESET
L
0
L
L
1
L
H
0
L
H
1
H
8.4.1 Normal Operation (VDD > VDD(min))
When V DD is greater than V DD(min), the RESET signal is determined by the voltage on the SENSE pin and the
logic state of MR.
• MR high: When the voltage on VDD is greater than 1.7 V for a time of the selected tD, the RESET signal
corresponds to the voltage on SENSE relative to VIT.
• MR low: in this mode, RESET is held low regardless of the value of the SENSE pin.
8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
When the voltage on VDD is less than the device VDD(min) voltage, and greater than the power-on reset voltage (V
POR), the RESET signal is asserted and low impedance, respectively, regardless of the voltage on the SENSE
pin.
8.4.3 Below Power-On Reset (VDD < VPOR)
When the voltage on V DD is lower than the required voltage (V POR) needed to internally pull the asserted output
to GND, RESET is undefined and should not be relied upon for proper device function.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
A typical application of the TPS3808G25 used with a 2.5-V processor is shown in 图 9-1. The open-drain RESET
output is typically connected to the RESET input of a microprocessor. A pullup resistor must be used to hold this
line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8 V, but this
characteristic is normally not a problem because most microprocessors do not function below this voltage.
2.5 V
SENSE VDD
TPS3808G25
MR
CT
RESET
GND
VDDSHV 1, 3, 6, 7, 9
1 MW
OMAP1510
RESPWRON
GND
图 9-1. Typical Application of the TPS3808 With an OMAP Processor
9.2.1 Design Requirements
The TPS3808 is intended to drive the RESET input of a microprocessor. The RESET pin is pulled high with a
1-MΩ resistor and the reset delay time is controlled by C T depending on the reset requirement times of the
microprocessor. In this case, CT is left open for a typical reset delay time of 20 ms.
9.2.2 Detailed Design Procedure
The primary constraint for this application is the reset delay time. In this case, because C T is open, it is set to
20 ms. A 0.1-µF decoupling capacitor is connected to the V DD pin and a 1-MΩ resistor is used to pull up the
RESET pin high. The MR pin can be connected to an external signal if desired.
9.2.2.1 Immunity to SENSE Pin Voltage Transients
The TPS3808 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
depends on threshold overdrive. Threshold overdrive is defined by how much the V SENSE exceeds the specified
threshold, and is important to know because the smaller the overdrive, the slower the RESET response.
Threshold overdrive is calculated as a percent of the threshold in question, as shown in 方程式 2:
Overdrive = | (VSENSE / VIT – 1) × 100% |
(2)
where:
• VIT is the threshold voltage.
图 9-2 shows this relationship.
14
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9.2.3 Application Curve
Transient Duration below VIT (µs)
100
RESET OCCURS
ABOVE THE CURVE
10
1
0
5
10
15
20
25
30
35
40
45
50
Overdrive (%VIT)
图 9-2. Maximum Transient Duration at SENSE vs SENSE Threshold Overdrive Voltage
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.7 V and 6.5 V. Use
a low-impedance power supply to eliminate inaccuracies caused by current changes during the voltage
reference refresh.
11 Layout
11.1 Layout Guidelines
Make sure the connection to the VDD pin is low impedance. Place a 0.1-µF ceramic capacitor near the VDD pin. If
no capacitor is connected to the C T pin, parasitic capacitance on this pin should be minimized so the RESET
delay time is not adversely affected.
11.2 Layout Example
The layout example in 图 11-1 shows how the TPS3808 is laid out on a printed circuit board (PCB) for a 20-ms
delay.
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VDD
RESET
VDD
CIN
GND
SENSE
MR
CT
GND
Vias used to connect pins for application-specific connections
图 11-1. Layout Example for a 20-ms Delay
16
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS3808.
The TPS3808G01DBVEVM evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
12.2 Documentation Support
12.2.1 Related Documentation
The following related documents are available for download at www.ti.com:
• Application note. Optimizing Resistor Dividers at a Comparator Input. Literature number SLVA450.
• Application note. Sensitivity Analysis for Power Supply Design. Literature number SLVA481.
• TPS3808G01DBVEVM Evaluation Module User Guide. Literature number SBVU015.
12.3 Support Resources
TI E2E ™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
FX1077
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
HPA00489DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DRVRG4
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G09DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G09DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G09DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G09DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G125DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAC
TPS3808G125DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAC
TPS3808G125DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAC
TPS3808G12DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3808G12DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DRVTG4
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G15DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G18DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G19DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CHP
TPS3808G19DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CHP
TPS3808G25DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
(1)
TPS3808G25DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVRG4
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVTG4
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G30DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G33DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SEC
TPS3808G33DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SEC
TPS3808G50DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
TPS3808G50DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
TPS3808G50DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
TPS3808G50DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
The marketing status values are defined as follows:
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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