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TPS3808
SBVS050K – MAY 2004 – REVISED OCTOBER 2015
TPS3808 Low-Quiescent-Current, Programmable-Delay Supervisory Circuit
1 Features
3 Description
•
The TPS3808 family of microprocessor supervisory
circuits monitors system voltages from 0.4 V to 5 V,
asserting an open-drain RESET signal when the
SENSE voltage drops below a preset threshold or
when the manual reset (MR) pin drops to a logic low.
The RESET output remains low for the useradjustable delay time after the SENSE voltage and
manual reset (MR) return above the respective
thresholds.
1
•
•
•
•
•
•
•
Power-On Reset Generator with Adjustable Delay
Time: 1.25 ms to 10 s
Very Low Quiescent Current: 2.4 μA Typical
High Threshold Accuracy: 0.5% Typ
Fixed Threshold Voltages for Standard Voltage
Rails from 0.9 V to 5 V and Adjustable Voltage
Down to 0.4 V Are Available
Manual Reset (MR) Input
Open-Drain RESET Output
Temperature Range: –40°C to 125°C
Small SOT-23 and 2-mm × 2-mm WSON
Packages
2 Applications
•
•
•
•
•
DSP or Microcontroller Applications
Notebook and Desktop Computers
PDAs and Hand-Held Products
Portable and Battery-Powered Products
FPGA and ASIC Applications
The TPS3808 device uses a precision reference to
achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The
reset delay time can be set to 20 ms by
disconnecting the CT pin, 300 ms by connecting the
CT pin to VDD using a resistor, or can be useradjusted between 1.25 ms and 10 s by connecting
the CT pin to an external capacitor. The TPS3808
device has a very low typical quiescent current of
2.4 μA, so it is well-suited to battery-powered
applications. It is available in the SOT-23 and 2-mm ×
2-mm WSON packages, and is fully specified over a
temperature range of –40°C to 125°C (TJ).
Device Information(1)
PART NUMBER
TPS3808
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm x 1.60 mm
WSON (6)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
1.2 V
Supply Current vs Supply Voltage
3.3 V
4.0
-40°C
25°C
85°C
125°C
SENSE VDD
SENSE VDD
TPS3808G12
TPS3808G33
RESET
GND
VCORE
DSP
3.0
2.5
MR
RESET
CT
VI/O
IDD (mA)
3.5
CT
GND
GPIO
GND
2.0
1.5
1.5
2.5
4.5
3.5
5.5
6.5
VDD (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3808
SBVS050K – MAY 2004 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Voltage Thresholds...................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (August 2008) to Revision K
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. Moved Switching Characteristics table, timing diagram,
and related truth table............................................................................................................................................................. 1
•
Changed Figure 13; removed capacitor shown on CT ........................................................................................................ 14
2
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5 Device Voltage Thresholds
The following table shows the nominal rail to be monitored and the corresponding threshold voltage of the
device.
(1)
PART NUMBER
NOMINAL SUPPLY VOLTAGE (1)
THRESHOLD VOLTAGE (VIT)
TPS3808G01
Adjustable
0.405 V
TPS3808G09
0.9 V
0.84 V
TPS3808G12
1.2 V
1.12 V
TPS3808G125
1.25 V
1.16 V
TPS3808G15
1.5 V
1.40 V
TPS3808G18
1.8 V
1.67 V
TPS3808G19
1.9 V
1.77 V
TPS3808G25
2.5 V
2.33 V
TPS3808G30
3V
2.79 V
TPS3808G33
3.3 V
3.07 V
TPS3808G50
5V
4.65 V
Custom threshold voltages from 0.82 V to 3.3 V, 4.4 V to 5 V are available through the use of factory
EEPROM programming. Minimum order quantities apply. Contact the factory for details and
availability.
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SBVS050K – MAY 2004 – REVISED OCTOBER 2015
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6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DRV Package
6-Pin (2.00 mm × 2.00 mm) WSON With Thermal Pad
Top View
RESET
1
6
VDD
GND
2
5
SENSE
4
CT
MR
3
VDD
1
SENSE
2
CT
3
THERMAL
PAD
6
RESET
5
GND
4
MR
Pin Functions
PIN
NAME
SOT-23
WSON
I/O
DESCRIPTION
Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ
resistor or leaving it open results in fixed delay times (see Electrical Characteristics).
Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable
delay time. See the Selecting the RESET Delay Time section for more information.
CT
4
3
I
GND
2
5
—
MR
3
4
I
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pull-up resistor.
Ground
RESET
1
6
O
RESET is an open-drain output that is driven to a low-impedance state when RESET is
asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is
set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is
above VIT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be
used on this pin, and allows the reset pin to attain voltages higher than VDD.
SENSE
5
2
I
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops
below the threshold voltage VIT, then RESET is asserted.
VDD
6
1
I
Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close
to this pin.
Thermal
Pad
—
Pad
—
4
Thermal Pad. Connect to ground plane to enhance thermal performance of package.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
Voltage
Current
Temperature
(1)
(2)
(1)
MIN
MAX
UNIT
VDD
–0.3
7
V
VCT
–0.3
VDD + 0.3
V
VRESET, VMR, VSENSE
–0.3
7
V
RESET pin
–5
5
mA
Operating junction, TJ (2)
–40
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Input supply range
1.7
VSENSE
SENSE pin voltage
0
V(Ct)
CT pin voltage
VMR
MR pin voltage
VRESET
IRESET
NOM
MAX
UNIT
6.5
V
6.5
V
VDD
V
0
6.5
V
RESET pin voltage
0
6.5
RESET pin current
0.0003
5
V
mA
7.4 Thermal Information
TPS3808
THERMAL METRIC (1)
DBV (SOT-23)
DRV (WSON)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
180.9
178.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
117.8
95.6
°C/W
RθJB
Junction-to-board thermal resistance
27.8
135
°C/W
ψJT
Junction-to-top characterization parameter
1.12
6.3
°C/W
ψJB
Junction-to-board characterization parameter
27.3
136.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
7.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless
otherwise noted. Typical values are at TJ = 25°C (1).
PARAMETER
VDD
Input supply range
IDD
Low-level output voltage
VPOR
Power-up reset voltage
MIN
0°C < TJ < 85°C
Supply current (current into VDD pin)
VOL
TEST CONDITIONS
–40°C < TJ < 125°C
(2)
VDD = 6.5 V, RESET not asserted
MR, RESET, CT open
2.7
6
CIN
Input capacitance,
any pin
VIL
MR logic low input
VIH
MR logic high input
(1)
(2)
6
μA
1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA
0.3
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA
0.4
VOL (max) = 0.2 V, IRESET = 15 μA
±1%
2%
–1.5%
±0.5%
1.5%
–2%
±1%
2%
–1.25%
±0.5%
1.25%
–1.5%
±0.5%
1.5%
1.5%
3%
1%
2.5%
TPS3808G01
Fixed versions
70
TPS3808G01
VSENSE = VIT
Fixed versions
VSENSE = 6.5 V
V
0.8
–2%
–40°C < TJ < 85°C
MR Internal pullup resistance
RESET leakage current
V
–40°C < TJ < 85°C
RMR
IOH
6.5
3.3 V < VIT ≤ 5.0 V
Hysteresis on VIT pin
Input current at
SENSE pin
1.65
VIT ≤ 3.3 V
VHYS
ISENSE
V
5
3.3 V < VIT ≤ 5.0 V
UNIT
6.5
2.4
VIT ≤ 3.3 V
Negative-going input
threshold accuracy
MAX
VDD = 3.3 V, RESET not asserted
MR, RESET, CT open
TPS3808G01
VIT
TYP
1.7
90
–25
kΩ
25
nA
300
nA
1.7
VRESET = 6.5 V, RESET not asserted
CT pin
VIN = 0 V to VDD
5
Other pins
VIN = 0 V to 6.5 V
5
VIT
μA
pF
0
0.3 VDD
0.7 VDD
VDD
V
RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin.
The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15 μs/V.
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7.6 Switching Characteristics
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless
otherwise noted. Typical values are at TJ = 25°C. (1)
PARAMETER
tw
Input pulse width to
RESET
TEST CONDITIONS
20
MR
VIH = 0.7 VDD, VIL = 0.3 VDD
0.001
CT = VDD
RESET delay time
See Figure 1
CT = 100 pF
CT = 180 nF
(1)
TYP
VIH = 1.05 VIT, VIL = 0.95 VIT
CT = Open
td
MIN
SENSE
MAX
μs
12
20
28
180
300
420
0.75
1.25
1.75
1.2
1.7
0.7
UNIT
ms
s
Propagation delay
MR to RESET
VIH = 0.7 VDD, VIL = 0.3 VDD
150
ns
High-to-low level RESET
delay
SENSE to RESET
VIH = 1.05 VIT, VIL = 0.95 VIT
20
μs
RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin.
VDD
0.8V
0.0V
RESET
tD = Reset Delay
tD
tD
tD
= Undefined State
SENSE
VIT + VHYS
VIT
MR
0.7VDD
0.3VDD
Time
Figure 1. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing
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7.7 Typical Characteristics
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF, unless otherwise noted.
100
4.0
3.5
IDD (mA)
RESET Timeout (sec)
+125°C
3.0
+85°C
2.5
2.0
+25°C
1.5
1.0
10
−40°C, +25°C, +125°C
1
0.1
0.01
−40°C
0.5
0.001
0.0001
0
0
1
2
3
4
5
6
7
0.001
0.01
VDD (V)
Transient Duration below VIT (ms)
Normalized RESET Timeout Period (%)
8
6
4
2
0
−2
−4
−6
−8
RESET OCCURS
ABOVE THE CURVE
10
1
−10
−30
−10
10
30
50
70
90
110
0
130
5
10
15
20
25
30
35
40
45
50
Overdrive (%VIT)
Temperature (°C)
Figure 4. Normalized RESET Time-Out Period vs
Temperature (CT = Open, CT = VDD, CT = Any)
Figure 5. Maximum Transient Duration at Sense vs Sense
Threshold Overdrive Voltage
1.0
4.5
VOL Low−Level RESET Voltage (V)
0.8
0.6
Normalized VIT (%)
10
100
−50
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
−50
4.0
3.5
3.0
2.5
2.0
VDD = 1.8 V
1.5
1.0
0.5
0
−30
−10
10
30
50
70
90
110
130
0
0.5
1.0
Temperature (°C)
Figure 6. Normalized Sense Threshold Voltage (VIT) vs
Temperature
8
1
Figure 3. RESET Time-Out Period vs CT
Figure 2. Supply Current vs Supply Voltage
10
A.
0.1
CT (mF)
1.5
2.0
2.5
RESET Current (mA)
3.0
3.5
4.0
Figure 7. Low-Level RESET Voltage vs RESET Current
RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin.
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Typical Characteristics (continued)
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF, unless otherwise noted.
VOL Low−Level RESET Voltage (V)
0.8
0.7
0.6
0.5
0.4
VDD = 3.3 V
0.3
0.2
0.1
VDD = 6.5 V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
RESET Current (mA)
Figure 8. Low-Level RESET Voltage vs RESET Current
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8 Detailed Description
8.1 Overview
The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the
SENSE pin voltage drops below VIT or the manual reset (MR) is driven low. The RESET output remains asserted
for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above their respective
thresholds.
8.2 Functional Block Diagram
VDD
VDD
VDD
VDD
TPS3808G01
Adjustable Version
90 kW
90 kW
RESET
MR
RESET
MR
SENSE
Reset
Logic
Timer
SENSE
Reset
Logic
Timer
R1
CT
CT
R2
0.4 V
VREF
0.4 V
VREF
R1 + R2 = 4 MW
GND
GND
Adjustable Voltage Version
Fixed Voltage Version
8.3 Feature Description
A broad range of voltage threshold and reset delay time adjustments are available for the TPS3808 device,
allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set
from 0.82 V to 3.3 V or from 4.4 V to 5 V, while the TPS3808G01 can be set to any voltage above 0.405 V using
an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD results
in a 300-ms reset delay, whereas leaving the CT pin open yields a 20-ms reset delay. In addition, connecting a
capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s.
8.3.1 SENSE Input
The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops
below VIT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET
assertions and de-assertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the
SENSE input to reduce sensitivity to transients and layout parasitics.
The TPS3808 device is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
is dependent on threshold overdrive, as shown in (Figure 5).
The TPS3808G01 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 9.
10
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Feature Description (continued)
VIN
VOUT
VDD
VIT¢ = (1 +
R1
R1
) 0.405
R2
TPS3808G01
SENSE
RESET
R2
1nF
GND
Figure 9. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage
8.3.2 Selecting the RESET Delay Time
The TPS3808 has three options for setting the RESET delay time as shown in Figure 10. Figure 10 (a) shows
the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must
be used. Supply current is not affected by the choice of resistor. Figure 10 (b) shows a fixed 20-ms delay time by
leaving the CT pin open. Figure 10 (c) shows a ground referenced capacitor connected to CT for a user-defined
program time between 1.25 ms and 10 s.
3.3V
3.3V
50kΩ
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
TPS3808G33
TPS3808G33
TPS3808G33
CT
CT
RESET
RESET
CT
RESET
CT
300ms Delay
20ms Delay
Delay (s) = CT (nF) + 0.5 x 10−3 (s)
175
(c)
(b)
(a)
Figure 10. Configuration Used to Set the RESET Delay Time
The capacitor CT should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor
is present. The capacitor value for a given delay time can be calculated using Equation 1.
C T (nF) = t D (s) – 0.5 × 10 - 3 (s) × 175
(1)
[
]
The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the
external capacitor to 1.23 V. When a RESET is asserted, the capacitor is discharged. When the RESET
conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When
the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such
as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay
time.
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Feature Description (continued)
8.3.3 Manual RESET (MR) Input
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on
MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is
de-asserted after the user-defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ
resistor, so this pin can be left unconnected if MR is not used.
See Figure 11 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving
MR does not go fully to VDD, there is some additional current draw into VDD as a result of the internal pullup
resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 12.
1.2V
3.3V
SENSE
V DD
SENSE V DD
TPS3808G12
TPS3808G33
RESET
CT
MR
CT
GND
RESET
GND
V I/O
V CORE
DSP
GPIO
GND
Figure 11. Using MR to Monitor Multiple System Voltages
3.3V
V DD SENSE
90kW
MR
TPS3808xxx
GND
Figure 12. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD
8.3.4 RESET Output
RESET remains high (unasserted) as long as SENSE is above its threshold (VIT) and the manual reset (MR) is
logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a
low impedance.
Once MR is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), a delay circuit is enabled
that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes
to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be used to
allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6.5 V). The pullup resistor
should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.
12
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8.4 Device Functional Modes
Table 1. Truth Table
MR
SENSE > VIT
RESET
L
0
L
L
L
1
H
0
L
H
1
H
8.4.1 Normal Operation (VDD > VDD(min))
When VDD is greater than VDD(min), the RESET signal is determined by the voltage on the SENSE pin and the
logic state of MR.
• MR high: When the voltage on VDD is greater than 1.7 V for a time of the selected tD, the RESET signal
corresponds to the voltage on SENSE relative to VIT.
• MR low: in this mode, RESET is held low regardless of the value of the SENSE pin.
8.4.2
Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
When the voltage on VDD is less than the device VDD(min) voltage, and greater than the power-on reset voltage
(VPOR), the RESET signal is asserted and low impedance, respectively, regardless of the voltage on the SENSE
pin.
8.4.3 Below Power-On Reset (VDD < VPOR)
When the voltage on VDD is lower than the required voltage (VPOR) needed to internally pull the asserted output
to GND, RESET is undefined and should not be relied upon for proper device function.
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Product Folder Links: TPS3808
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TPS3808
SBVS050K – MAY 2004 – REVISED OCTOBER 2015
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
A typical application of the TPS3808G25 used with a 2.5-V processor is shown in Figure 13. The open-drain
RESET output is typically connected to the RESET input of a microprocessor. A pullup resistor must be used to
hold this line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8 V, but this
characteristic is normally not a problem because most microprocessors do not function below this voltage.
2.5 V
SENSE VDD
TPS3808G25
MR
CT
RESET
GND
VDDSHV 1, 3, 6, 7, 9
1 MW
OMAP1510
RESPWRON
GND
Figure 13. Typical Application of the TPS3808 With an OMAP Processor
9.2.1 Design Requirements
The TPS3808 is intended to drive the RESET input of a microprocessor. The RESET pin is pulled high with a
1-MΩ resistor and the reset delay time is controlled by CT depending on the reset requirement times of the
microprocessor. In this case, CT is left open for a typical reset delay time of 20 ms.
9.2.2 Detailed Design Procedure
The primary constraint for this application is the reset delay time. In this case, because CT is open, it is set to
20 ms. A 0.1-µF decoupling capacitor is connected to the VDD pin and a 1-MΩ resistor is used to pull up the
RESET pin high. The MR pin can be connected to an external signal if desired.
9.2.2.1 Immunity to SENSE Pin Voltage Transients
The TPS3808 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
depends on threshold overdrive. Threshold overdrive is defined by how much the VSENSE exceeds the specified
threshold, and is important to know because the smaller the overdrive, the slower the RESET response.
Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 2:
Overdrive = | (VSENSE / VIT – 1) × 100% |
where:
•
VIT is the threshold voltage.
(2)
Figure 14 shows this relationship.
14
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TPS3808
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SBVS050K – MAY 2004 – REVISED OCTOBER 2015
Typical Application (continued)
9.2.3 Application Curve
Transient Duration below VIT (µs)
100
RESET OCCURS
ABOVE THE CURVE
10
1
0
5
10
15
20
25
30
35
40
45
50
Overdrive (%VIT)
Figure 14. Maximum Transient Duration at SENSE vs SENSE Threshold Overdrive Voltage
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.7 V and 6.5 V. Use
a low-impedance power supply to eliminate inaccuracies caused by current changes during the voltage reference
refresh.
11 Layout
11.1 Layout Guidelines
Make sure the connection to the VDD pin is low impedance. Place a 0.1-µF ceramic capacitor near the VDD pin. If
no capacitor is connected to the CT pin, parasitic capacitance on this pin should be minimized so the RESET
delay time is not adversely affected.
11.2 Layout Example
The layout example in Figure 15 shows how the TPS3808 is laid out on a printed circuit board (PCB) for a 20-ms
delay.
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TPS3808
SBVS050K – MAY 2004 – REVISED OCTOBER 2015
www.ti.com
Layout Example (continued)
VDD
RESET
VDD
CIN
GND
SENSE
MR
CT
GND
Vias used to connect pins for application-specific connections
Figure 15. Layout Example for a 20-ms Delay
16
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Product Folder Links: TPS3808
TPS3808
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SBVS050K – MAY 2004 – REVISED OCTOBER 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS3808.
The TPS3808G01DBVEVM evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
12.2 Documentation Support
12.2.1 Related Documentation
The following related documents are available for download at www.ti.com:
• Application note. Optimizing Resistor Dividers at a Comparator Input. Literature number SLVA450.
• Application note. Sensitivity Analysis for Power Supply Design. Literature number SLVA481.
• TPS3808G01DBVEVM Evaluation Module User Guide. Literature number SBVU015.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
900-0380801
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
FX1077
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
HPA00385DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
HPA00489DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DRVRG4
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G01DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVW
TPS3808G09DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G09DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G09DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G09DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVV
TPS3808G125DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAC
TPS3808G125DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAC
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS3808G125DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAC
TPS3808G12DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DRVRG4
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G12DRVTG4
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVY
TPS3808G15DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G15DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVS
TPS3808G18DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS3808G18DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G18DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVR
TPS3808G19DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CHP
TPS3808G19DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CHP
TPS3808G25DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVRG4
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G25DRVTG4
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVQ
TPS3808G30DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS3808G30DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G30DRVTG4
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVP
TPS3808G33DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVO
TPS3808G33DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SEC
TPS3808G33DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SEC
TPS3808G50DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
TPS3808G50DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
TPS3808G50DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
TPS3808G50DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3808 :
• Automotive: TPS3808-Q1
• Enhanced Product: TPS3808-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS3808G01DBVR
SOT-23
DBV
6
3000
180.0
8.4
TPS3808G01DBVR
SOT-23
DBV
6
3000
178.0
TPS3808G01DBVT
SOT-23
DBV
6
250
178.0
TPS3808G01DBVT
SOT-23
DBV
6
250
TPS3808G01DRVR
WSON
DRV
6
TPS3808G01DRVR
WSON
DRV
TPS3808G01DRVT
WSON
DRV
TPS3808G01DRVT
WSON
TPS3808G09DBVR
TPS3808G09DBVR
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
3000
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
DRV
6
250
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
SOT-23
DBV
6
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G09DBVT
SOT-23
DBV
6
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G09DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G125DBVR
SOT-23
DBV
6
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G125DBVT
SOT-23
DBV
6
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G12DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G12DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G12DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G12DRVR
WSON
DRV
6
3000
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2017
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS3808G12DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G12DRVT
WSON
DRV
6
250
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
TPS3808G15DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G15DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G15DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G15DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G18DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G18DBVR
SOT-23
DBV
6
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G18DBVT
SOT-23
DBV
6
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G18DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G18DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G18DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G19DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G19DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G25DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G25DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G25DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G25DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G30DBVR
SOT-23
DBV
6
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G30DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G30DBVT
SOT-23
DBV
6
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS3808G30DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G30DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G30DRVR
WSON
DRV
6
3000
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
TPS3808G30DRVT
WSON
DRV
6
250
178.0
8.4
2.25
2.25
1.0
4.0
8.0
Q2
TPS3808G30DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G33DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G33DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G33DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G33DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS3808G50DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS3808G50DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS3808G01DBVR
SOT-23
DBV
6
3000
210.0
185.0
35.0
TPS3808G01DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G01DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G01DBVT
SOT-23
DBV
6
250
210.0
185.0
35.0
TPS3808G01DRVR
WSON
DRV
6
3000
205.0
200.0
33.0
TPS3808G01DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G01DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G01DRVT
WSON
DRV
6
250
205.0
200.0
33.0
TPS3808G09DBVR
SOT-23
DBV
6
3000
210.0
185.0
35.0
TPS3808G09DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G09DBVT
SOT-23
DBV
6
250
210.0
185.0
35.0
TPS3808G09DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G125DBVR
SOT-23
DBV
6
3000
203.0
203.0
35.0
TPS3808G125DBVT
SOT-23
DBV
6
250
203.0
203.0
35.0
TPS3808G12DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G12DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G12DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G12DRVR
WSON
DRV
6
3000
205.0
200.0
33.0
TPS3808G12DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G12DRVT
WSON
DRV
6
250
205.0
200.0
33.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2017
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS3808G15DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G15DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G15DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G15DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G18DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G18DBVR
SOT-23
DBV
6
3000
210.0
185.0
35.0
TPS3808G18DBVT
SOT-23
DBV
6
250
210.0
185.0
35.0
TPS3808G18DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G18DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G18DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G19DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G19DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G25DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G25DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G25DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G25DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G30DBVR
SOT-23
DBV
6
3000
210.0
185.0
35.0
TPS3808G30DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G30DBVT
SOT-23
DBV
6
250
210.0
185.0
35.0
TPS3808G30DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G30DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G30DRVR
WSON
DRV
6
3000
205.0
200.0
33.0
TPS3808G30DRVT
WSON
DRV
6
250
205.0
200.0
33.0
TPS3808G30DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G33DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G33DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TPS3808G33DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS3808G33DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS3808G50DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS3808G50DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
Pack Materials-Page 4
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1±0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4X 0.65
4
7
1.6±0.1
6
1
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A
C
B
4222173/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222173/A 12/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/A 12/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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