TPS3808G33DBVT

TPS3808 TPS3808 SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 www.ti.com TPS3808 Low-Quiescent-Current, Programmable-Delay Supervisory Circuit 1 Features 3 Description • The TPS3808 family of microprocessor supervisory circuits monitors system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset ( MR) pin drops to a logic low. The RESET output remains low for the useradjustable delay time after the SENSE voltage and manual reset ( MR) return above the respective thresholds. • • • • • • • Power-On Reset Generator with Adjustable Delay Time: 1.25 ms to 10 s Very Low Quiescent Current: 2.4 μA Typical High Threshold Accuracy: 0.5% Typ Fixed Threshold Voltages for Standard Voltage Rails from 0.9 V to 5 V and Adjustable Voltage Down to 0.4 V Are Available Manual Reset ( MR) Input Open-Drain RESET Output Temperature Range: –40°C to 125°C Small SOT-23 and 2-mm × 2-mm WSON Packages 2 Applications • • • • • DSP or Microcontroller Applications Notebook and Desktop Computers PDAs and Hand-Held Products Portable and Battery-Powered Products FPGA and ASIC Applications The TPS3808 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be user-adjusted between 1.25 ms and 10 s by connecting the CT pin to an external capacitor. The TPS3808 device has a very low typical quiescent current of 2.4 μA, so it is wellsuited to battery-powered applications. It is available in the SOT-23 and 2-mm × 2-mm WSON packages, and is fully specified over a temperature range of – 40°C to 125°C (TJ). Device Information PART NUMBER TPS3808 (1) 1.2 V 3.3 V TPS3808G12 TPS3808G33 VI/O VCORE DSP MR RESET CT GND Typical Application IDD (mA) SENSE VDD GND 2.90 mm x 1.60 mm WSON (6) 2.00 mm x 2.00 mm 4.0 SENSE VDD CT BODY SIZE (NOM) SOT-23 (6) For all available packages, see the orderable addendum at the end of the data sheet. -40°C 25°C 85°C 125°C 3.5 RESET PACKAGE (1) 3.0 2.5 GPIO GND 2.0 1.5 1.5 2.5 4.5 3.5 5.5 6.5 VDD (V) Supply Current vs Supply Voltage An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS3808 1 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Voltage Thresholds.............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics.............................................6 7.6 Switching Characteristics............................................7 7.7 Typical Characteristics................................................ 8 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................13 9 Application and Implementation.................................. 14 9.1 Application Information............................................. 14 9.2 Typical Application.................................................... 14 10 Power Supply Recommendations..............................15 11 Layout........................................................................... 15 11.1 Layout Guidelines................................................... 15 11.2 Layout Example...................................................... 15 12 Device and Documentation Support..........................17 12.1 Device Support....................................................... 17 12.2 Documentation Support.......................................... 17 12.3 Support Resources................................................. 17 12.4 Trademarks............................................................. 17 12.5 Electrostatic Discharge Caution..............................17 12.6 Glossary..................................................................17 13 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (October 2015) to Revision L (September 2020) Page • Updated the numbering format for tables, figures and cross-references throughout the document...................1 Changes from Revision J (August 2008) to Revision K (October 2015) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Moved Switching Characteristics table, timing diagram, and related truth table............................................................ 1 • Changed Figure 9-1; removed capacitor shown on CT ....................................................................................14 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 5 Device Voltage Thresholds The following table shows the nominal rail to be monitored and the corresponding threshold voltage of the device. (1) PART NUMBER NOMINAL SUPPLY VOLTAGE(1) THRESHOLD VOLTAGE (VIT) TPS3808G01 Adjustable 0.405 V TPS3808G09 0.9 V 0.84 V TPS3808G12 1.2 V 1.12 V TPS3808G125 1.25 V 1.16 V TPS3808G15 1.5 V 1.40 V TPS3808G18 1.8 V 1.67 V TPS3808G19 1.9 V 1.77 V TPS3808G25 2.5 V 2.33 V TPS3808G30 3V 2.79 V TPS3808G33 3.3 V 3.07 V TPS3808G50 5V 4.65 V Custom threshold voltages from 0.82 V to 3.3 V, 4.4 V to 5 V are available through the use of factory EEPROM programming. Minimum order quantities apply. Contact the factory for details and availability. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 3 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 6 Pin Configuration and Functions RESET VDD VDD 6 1 GND 2 5 SENSE MR 3 4 CT Figure 6-1. DBV Package 6-Pin SOT-23 Top View 1 SENSE 2 CT 3 THERMAL PAD 6 RESET 5 GND 4 MR Figure 6-2. DRV Package 6-Pin (2.00 mm × 2.00 mm) WSON With Thermal Pad Top View Table 6-1. Pin Functions PIN NAME 4 SOT-23 WSON I/O DESCRIPTION Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Section 7.5). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See Section 8.3.2 for more information. CT 4 3 I GND 2 5 — MR 3 4 I Driving the manual reset pin ( MR) low asserts RESET. MRis internally tied to VDD by a 90kΩ pull-up resistor. Ground RESET 1 6 O RESETis an open-drain output that is driven to a low-impedance state when RESETis asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MRpin is set to a logic low). RESETremains low (asserted) for the reset period after both SENSE is above VIT and MRis set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. SENSE 5 2 I This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. VDD 6 1 I Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin. Thermal Pad — Pad — Thermal Pad. Connect to ground plane to enhance thermal performance of package. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted) (1) Voltage Current Temperature (1) (2) MIN MAX UNIT VDD –0.3 7 V VCT –0.3 VDD + 0.3 V VRESET, VMR, VSENSE –0.3 7 V RESET pin –5 5 mA Operating junction, TJ (2) –40 150 °C Storage, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. As a result of the low dissipated power in this device, it is assumed that TJ = TA. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD Input supply range 1.7 VSENSE SENSE pin voltage 0 V(Ct) CT pin voltage NOM MAX UNIT 6.5 V 6.5 V VDD V V MR MR pin voltage 0 6.5 V V RESET RESET pin voltage 0 6.5 V I RESET RESET pin current 0.0003 5 mA 7.4 Thermal Information TPS3808 THERMAL METRIC(1) DBV (SOT-23) DRV (WSON) 6 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 180.9 178.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 117.8 95.6 °C/W RθJB Junction-to-board thermal resistance 27.8 135 °C/W ψJT Junction-to-top characterization parameter 1.12 6.3 °C/W ψJB Junction-to-board characterization parameter 27.3 136.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 7.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 5 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 7.5 Electrical Characteristics 1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C(1). PARAMETER VDD –40°C < TJ < 125°C Input supply range IDD TEST CONDITIONS 0°C < TJ < 85°C Supply current (current into VDD pin) VOL Low-level output voltage VPOR Power-up reset voltage(2) Negative-going input threshold accuracy MAX 1.7 6.5 V 6.5 V 2.4 5 VDD = 6.5 V, RESETnot asserted MR, RESET, CT open 2.7 6 μA 1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA 0.3 1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA 0.4 VOL (max) = 0.2 V, I RESET = 15 μA 0.8 VIT ≤ 3.3 V 3.3 V < VIT ≤ 5.0 V –2% ±1% 2% –1.5% ±0.5% 1.5% –2% ±1% 2% VIT ≤ 3.3 V –40°C < TJ < 85°C –1.25% ±0.5% 1.25% 3.3 V < VIT ≤ 5.0 V –40°C < TJ < 85°C –1.5% ±0.5% 1.5% 1.5% 3% 1% 2.5% TPS3808G01 Hysteresis on VIT pin R MR MR Internal pullup resistance ISENSE Input current at SENSE pin IOH RESET leakage current V RESET = 6.5 V, RESET not asserted CIN Input capacitance, any CT pin pin Other pins VIN = 0 V to VDD 5 VIN = 0 V to 6.5 V 5 VIL MR logic low input VIH MR logic high input Fixed versions 70 TPS3808G01 VSENSE = VIT Fixed versions VSENSE = 6.5 V UNIT 1.65 VHYS (1) (2) 6 TYP VDD = 3.3 V, RESETnot asserted MR, RESET, CT open TPS3808G01 VIT MIN 90 –25 V VIT kΩ 25 1.7 nA μA 300 nA pF 0 0.3 VDD 0.7 VDD VDD V The lowest supply voltage (VDD) at which RESETbecomes active. Trise(VDD) ≥ 15 μs/V. RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 7.6 Switching Characteristics 1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.(1) PARAMETER tw Input pulse width to RESET TEST CONDITIONS VIH = 1.05 VIT, VIL = 0.95 VIT 20 MR VIH = 0.7 VDD, VIL = 0.3 VDD 0.001 CT = VDD RESET delay time See Figure 7-1 CT = 100 pF CT = 180 nF (1) TYP SENSE CT = Open td MIN MAX UNIT μs 12 20 28 180 300 420 0.75 1.25 1.75 0.7 1.2 1.7 ms s Propagation delay MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD 150 ns High-to-low level RESET delay SENSE to RESET VIH = 1.05 VIT, VIL = 0.95 VIT 20 μs RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin. VDD 0.8V 0.0V RESET tD = Reset Delay tD tD tD = Undefined State SENSE VIT + VHYS VIT MR 0.7VDD 0.3VDD Time Figure 7-1. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 7 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 7.7 Typical Characteristics At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF, unless otherwise noted. 4.0 100 3.5 IDD (mA) RESET Timeout (sec) +125°C 3.0 +85°C 2.5 2.0 +25°C 1.5 1.0 10 −40°C, +25°C, +125°C 1 0.1 0.01 −40°C 0.5 0.001 0.0001 0 0 1 2 3 4 5 6 7 0.001 0.01 VDD (V) Transient Duration below VIT (ms) Normalized RESET Timeout Period (%) 100 8 6 4 2 0 −2 −4 −6 −8 RESET OCCURS ABOVE THE CURVE 10 1 −10 −30 −10 10 30 50 70 90 110 0 130 5 10 Figure 7-4. Normalized RESET Time-Out Period vs Temperature (CT = Open, CT = VDD, CT = Any) 20 25 30 35 40 45 50 Figure 7-5. Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage 4.5 VOL Low−Level RESET Voltage (V) 1.0 0.8 0.6 Normalized VIT (%) 15 Overdrive (%VIT) Temperature (°C) 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 4.0 3.5 3.0 2.5 2.0 VDD = 1.8 V 1.5 1.0 0.5 0 −30 −10 10 30 50 70 90 110 130 0 Temperature (°C) Figure 7-6. Normalized Sense Threshold Voltage (VIT) vs Temperature 8 10 Figure 7-3. RESET Time-Out Period vs CT 10 −50 1 CT (mF) Figure 7-2. Supply Current vs Supply Voltage −50 0.1 0.5 1.0 1.5 2.0 2.5 RESET Current (mA) 3.0 3.5 4.0 Figure 7-7. Low-Level RESET Voltage vs RESET Current Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 VOL Low−Level RESET Voltage (V) 0.8 0.7 0.6 0.5 0.4 VDD = 3.3 V 0.3 0.2 0.1 VDD = 6.5 V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 RESET Current (mA) Figure 7-8. Low-Level RESET Voltage vs RESET Current Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 9 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 8 Detailed Description 8.1 Overview The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below VIT or the manual reset ( MR) is driven low. The RESET output remains asserted for a user-adjustable time after both the manual reset ( MR) and SENSE voltages return above their respective thresholds. 8.2 Functional Block Diagram VDD VDD VDD VDD TPS3808G01 Adjustable Version 90 kW 90 kW RESET MR RESET MR SENSE Reset Logic Timer SENSE Reset Logic Timer R1 CT CT R2 0.4 V VREF 0.4 V VREF R1 + R2 = 4 MW GND GND Adjustable Voltage Version Fixed Voltage Version 8.3 Feature Description A broad range of voltage threshold and reset delay time adjustments are available for the TPS3808 device, allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set from 0.82 V to 3.3 V or from 4.4 V to 5 V, while the TPS3808G01 can be set to any voltage above 0.405 V using an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD results in a 300-ms reset delay, whereas leaving the CT pin open yields a 20-ms reset delay. In addition, connecting a capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s. 8.3.1 SENSE Input The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops below VIT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET assertions and de-assertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics. The TPS3808 device is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients is dependent on threshold overdrive, as shown in (Figure 7-5). The TPS3808G01 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 8-1. 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 VIN VOUT VDD VIT¢ = (1 + R1 R1 ) 0.405 R2 TPS3808G01 SENSE RESET 1nF R2 GND Figure 8-1. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage 8.3.2 Selecting the RESET Delay Time The TPS3808 has three options for setting the RESET delay time as shown in Figure 8-2. Figure 8-2 (a) shows the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be used. Supply current is not affected by the choice of resistor. Figure 8-2 (b) shows a fixed 20-ms delay time by leaving the CT pin open. Figure 8-2 (c) shows a ground referenced capacitor connected to CT for a userdefined program time between 1.25 ms and 10 s. 3.3V 3.3V 50kΩ 3.3V SENSE VDD SENSE VDD SENSE VDD TPS3808G33 TPS3808G33 TPS3808G33 CT CT RESET RESET CT RESET CT 300ms Delay 20ms Delay Delay (s) = CT (nF) + 0.5 x 10−3 (s) 175 (c) (b) (a) Figure 8-2. Configuration Used to Set the RESET Delay Time The capacitor CT should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using Equation 1. C T (nF) = t D (s) – 0.5 × 10 - 3 (s) × 175 [ ] (1) The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the external capacitor to 1.23 V. When a RESET is asserted, the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay time. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 11 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 8.3.3 Manual RESET ( MR) Input The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is de-asserted after the user-defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ resistor, so this pin can be left unconnected if MR is not used. See Figure 8-3 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR does not go fully to VDD, there is some additional current draw into VDD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 8-4. 1.2V 3.3V SENSE V DD SENSE V DD TPS3808G12 TPS3808G33 RESET V CORE DSP MR RESET CT V I/O CT GND GND GPIO GND Figure 8-3. Using MR to Monitor Multiple System Voltages 3.3V V DD SENSE 90kW MR TPS3808xxx GND Figure 8-4. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD 8.3.4 RESET Output RESET remains high (unasserted) as long as SENSE is above its threshold (VIT) and the manual reset ( MR) is logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a low impedance. Once MR is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), a delay circuit is enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be used to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6.5 V). The pullup resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line. 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 8.4 Device Functional Modes Table 8-1. Truth Table MR SENSE > VIT RESET L 0 L L 1 L H 0 L H 1 H 8.4.1 Normal Operation (VDD > VDD(min)) When VDD is greater than VDD(min), the RESET signal is determined by the voltage on the SENSE pin and the logic state of MR. • • MR high: When the voltage on VDD is greater than 1.7 V for a time of the selected tD, the RESET signal corresponds to the voltage on SENSE relative to VIT. MR low: in this mode, RESET is held low regardless of the value of the SENSE pin. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min)) When the voltage on VDD is less than the device VDD(min) voltage, and greater than the power-on reset voltage (VPOR), the RESET signal is asserted and low impedance, respectively, regardless of the voltage on the SENSE pin. 8.4.3 Below Power-On Reset (VDD < VPOR) When the voltage on VDD is lower than the required voltage (VPOR) needed to internally pull the asserted output to GND, RESET is undefined and should not be relied upon for proper device function. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 13 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The following sections describe in detail how to properly use this device, depending on the requirements of the final application. 9.2 Typical Application A typical application of the TPS3808G25 used with a 2.5-V processor is shown in Figure 9-1. The open-drain RESET output is typically connected to the RESET input of a microprocessor. A pullup resistor must be used to hold this line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8 V, but this characteristic is normally not a problem because most microprocessors do not function below this voltage. 2.5 V SENSE VDD TPS3808G25 MR CT RESET GND VDDSHV 1, 3, 6, 7, 9 1 MW OMAP1510 RESPWRON GND Figure 9-1. Typical Application of the TPS3808 With an OMAP Processor 9.2.1 Design Requirements The TPS3808 is intended to drive the RESET input of a microprocessor. The RESET pin is pulled high with a 1-MΩ resistor and the reset delay time is controlled by CT depending on the reset requirement times of the microprocessor. In this case, CT is left open for a typical reset delay time of 20 ms. 9.2.2 Detailed Design Procedure The primary constraint for this application is the reset delay time. In this case, because CT is open, it is set to 20 ms. A 0.1-µF decoupling capacitor is connected to the VDD pin and a 1-MΩ resistor is used to pull up the RESET pin high. The MR pin can be connected to an external signal if desired. 9.2.2.1 Immunity to SENSE Pin Voltage Transients The TPS3808 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients depends on threshold overdrive. Threshold overdrive is defined by how much the VSENSE exceeds the specified threshold, and is important to know because the smaller the overdrive, the slower the RESET response. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 2: Overdrive = | (VSENSE / VIT – 1) × 100% | (2) where: • VIT is the threshold voltage. Figure 9-2 shows this relationship. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 9.2.3 Application Curve Transient Duration below VIT (µs) 100 RESET OCCURS ABOVE THE CURVE 10 1 0 5 10 15 20 25 30 35 40 45 50 Overdrive (%VIT) Figure 9-2. Maximum Transient Duration at SENSE vs SENSE Threshold Overdrive Voltage 10 Power Supply Recommendations These devices are designed to operate from an input supply with a voltage range between 1.7 V and 6.5 V. Use a low-impedance power supply to eliminate inaccuracies caused by current changes during the voltage reference refresh. 11 Layout 11.1 Layout Guidelines Make sure the connection to the VDD pin is low impedance. Place a 0.1-µF ceramic capacitor near the VDD pin. If no capacitor is connected to the CT pin, parasitic capacitance on this pin should be minimized so the RESET delay time is not adversely affected. 11.2 Layout Example The layout example in Figure 11-1 shows how the TPS3808 is laid out on a printed circuit board (PCB) for a 20ms delay. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 15 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 VDD RESET VDD CIN GND SENSE MR CT GND Vias used to connect pins for application-specific connections Figure 11-1. Layout Example for a 20-ms Delay 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 TPS3808 www.ti.com SBVS050L – MAY 2004 – REVISED SEPTEMBER 2020 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.1.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS3808. The TPS3808G01DBVEVM evaluation module (and related user guide) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 12.2 Documentation Support 12.2.1 Related Documentation The following related documents are available for download at www.ti.com: • Application note. Optimizing Resistor Dividers at a Comparator Input. Literature number SLVA450. • Application note. Sensitivity Analysis for Power Supply Design. Literature number SLVA481. • TPS3808G01DBVEVM Evaluation Module User Guide. Literature number SBVU015. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS3808 17 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) FX1077 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DRVRG4 ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G01DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVW Samples TPS3808G09DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVV Samples TPS3808G09DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVV Samples TPS3808G09DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVV Samples TPS3808G09DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVV Samples TPS3808G125DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAC Samples TPS3808G125DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAC Samples TPS3808G125DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAC Samples TPS3808G12DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVY Samples TPS3808G12DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVY Samples TPS3808G12DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVY Samples TPS3808G12DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVY Samples TPS3808G12DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AVY Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 19-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3808G12DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AVY Samples TPS3808G12DRVTG4 ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVY Samples TPS3808G15DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVS Samples TPS3808G15DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVS Samples TPS3808G15DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVS Samples TPS3808G15DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVS Samples TPS3808G15DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVS Samples TPS3808G15DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVS Samples TPS3808G18DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVR Samples TPS3808G18DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVR Samples TPS3808G18DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVR Samples TPS3808G18DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVR Samples TPS3808G18DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVR Samples TPS3808G18DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVR Samples TPS3808G19DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CHP Samples TPS3808G19DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CHP Samples TPS3808G25DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVQ Samples TPS3808G25DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVQ Samples TPS3808G25DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVQ Samples TPS3808G25DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVQ Samples TPS3808G25DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVQ Samples Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 19-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS3808G25DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVQ Samples TPS3808G30DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVP Samples TPS3808G30DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVP Samples TPS3808G30DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVP Samples TPS3808G30DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVP Samples TPS3808G30DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AVP Samples TPS3808G30DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AVP Samples TPS3808G33DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVO Samples TPS3808G33DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVO Samples TPS3808G33DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVO Samples TPS3808G33DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVO Samples TPS3808G33DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SEC Samples TPS3808G33DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SEC Samples TPS3808G50DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVN Samples TPS3808G50DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVN Samples TPS3808G50DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVN Samples TPS3808G50DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AVN Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of