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TPS3820-Q1, TPS3823-Q1, TPS3824-Q1, TPS3825-Q1, TPS3828-Q1
SGLS143D – DECEMBER 2002 – REVISED JULY 2019
TPS382x-xx-Q1 Voltage Monitor With Watchdog Timer
1 Features
3 Description
•
•
For all new designs with TPS3820-xx-Q1, use the
TPS3820-xxQPDBVRQ1 part number. The TPS3820xxQP is functionally equivalent and a replacement to
the TPS3820xxQ. The TPS3820-xxQDBVRQ1 is not
recommended for new designs (NRND).
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 Qualified With the Following Results:
– Device temperature grade 1: –40°C to 125°C
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
ESD protection exceeds 2000 V Per MIL-STD883, Method 3015; using human body model (C =
100 pF, R = 1500 Ω)
Power-on reset generator with fixed delay time of
200 ms (TPS3823/4/5/8-xx-Q1) or 25 ms
(TPS3820-xx-Q1)
Manual reset input (TPS3820/3/5/8-xx-Q1)
Reset output available in active-low
(TPS3820/3/4/5-xx-Q1), Active-High (TPS3824/5xx-Q1), and open drain (TPS3828-xx-Q1)
Supply voltage supervision range:
2.5 V, 3 V, 3.3 V, 5 V
Watchdog timer (TPS3820/3/4/8-xx-Q1)
Supply current of 15 μA (Typical)
5-Pin SOT-23 package
Temperature range: −40°C to 125°C
•
•
•
•
•
•
Automotive DSPs, microcontrollers, or
microprocessors
Industrial equipment
Programmable controls
Automotive systems
Portable and battery-powered equipment
Intelligent instruments
Wireless communications systems
Typical Application Schematic
3.3 V
100 nF
VDD
RESET
VDD
RESET
TPS3823-33-Q1
WDI
MR
GND
Device Information(1)
PART NUMBER
2 Applications
•
The TPS382x-xx-Q1 family of supervisors provide
circuit initialization and timing supervision, primarily
for DSP and processor-based systems. During power
on, RESET asserts when the supply voltage VDD
becomes greater than 1.1 V. Thereafter, the supply
voltage supervisor monitors VDD and keeps RESET
active low as long as VDD remains below the
threshold voltage, VIT−. An internal timer delays the
return of the output to the inactive state (high) to
ensure proper system reset. The delay time, td, starts
after VDD has risen above the threshold voltage VIT−.
When the supply voltage drops below the threshold
voltage VIT−, the output becomes active (low) again.
No external components are required. All the devices
of this family have a fixed-sense threshold voltage,
VIT–, set by an internal voltage divider. The TPS382xxx-Q1 family also offers watchdog time out options of
200 ms (TPS3820-xx-Q1) and 1.6 s (TPS3823/4/8xx-Q1).
MSP430C325
I/O
GND
TPS382x-xx-Q1
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Normalized Input Threshold Voltage vs
Free-Air Temperature
Normalized Input Threshold Voltage −V IT (TA), VIT (25°C)
1
1.001
1
0.999
0.998
0.997
0.996
0.995
−40
−15
10
35
60
85
TA − Free-Air Temperature − °C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3820-Q1, TPS3823-Q1, TPS3824-Q1, TPS3825-Q1, TPS3828-Q1
SGLS143D – DECEMBER 2002 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2015) to Revision D
•
Page
For all new designs, use the TPS3820-33QPDBVRQ1 and TPS3820-50QPDBVRQ1.TPS3820-xxQP is functionally
equivalent and a replacement to the TPS3820xxQ................................................................................................................ 1
Changes from Revision B (June 2008) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added AEC-Q100 Qualified information and Temperature Range to Features .................................................................... 1
•
Added -Q1 to all applicable part numbers ............................................................................................................................. 1
•
Added FIXED DELAY TIME column to table ........................................................................................................................ 3
2
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
5 Device Comparison Table
DEVICE
RESET
TPS3820-xx-Q1
TPS3823-xx-Q1
TPS3824-xx-Q1
Push-pull
TPS3825-xx-Q1
Push-pull
RESET
WDI
MR
FIXED DELAY
TIME
Push-pull
X
X
25 ms
Push-pull
X
X
200 ms
X
Push-pull
TPS3828-xx-Q1
Open-drain
X
200 ms
X
200 ms
X
200 ms
6 Pin Configuration and Functions
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3828-xx-Q1: DBV
PACKAGE
5-Pin SOT-23
Top View
RESET
1
GND
2
MR
3
TPS3824-xx-Q1: DBV PACKAGE
5-Pin SOT-23
Top View
VDD
5
4
WDI
RESET
1
GND
2
RESET
3
5
VDD
4
WDI
TPS3825-xx-Q1: DBV PACKAGE
5-Pin SOT-23
Top View
RESET
1
GND
2
RESET
3
5
VDD
4
MR
Pin Functions
PIN
NAME
GND
TPS3820‑‑xx‑‑Q1,
TPS3823‑‑xx‑‑Q1,
TPS3828‑‑xx‑‑Q1
2
TPS3824‑‑xx‑‑Q1 TPS3825‑‑xx‑‑Q1
2
2
I/O
—
DESCRIPTION
Ground connection
MR
3
—
4
I
Manual-reset input. Pull low to force a reset. RESET
remains low as long as MR is low and for the time-out
period after MR goes high. Leave unconnected or
connect to VDD when unused.
RESET
—
3
3
O
Active-high reset output. Either push-pull or open-drain
output stage.
RESET
1
1
1
O
Active-low reset output. Either push-pull or open-drain
output stage.
VDD
5
5
5
I
Supply voltage. Powers the device and monitors its own
voltage.
I
Watchdog timer input. If WDI remains high or low longer
than the time-out period, then reset is triggered. The
timer clears when reset is asserted or when WDI sees a
rising edge or a falling edge. If unused, the WDI
connection must be high impedance to prevent it from
causing a reset event.
WDI
4
4
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Voltage
Current
MIN
MAX
VDD
–0.3
6
RESET, RESET, MR, WDI
–0.3
(VDD + 0.3)
Maximum low output, IOL
–5
5
Maximum high output, IOH
–5
5
–10
10
Output range (VO < 0 or VO > VDD), IOK
Continuous total power dissipation
Temperature
(1)
(2)
UNIT
V
mA
See Thermal Information
Operating free-air, TA
–40
125
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
VDD
Supply voltage
VI
Input voltage
VIH
High-level input voltage at MR and WDI
VIL
Low-level input voltage
Δt/ΔV
Input transition rise and fall rate at MR or WDI
TA
Operating free-air temperature range
NOM
MAX
UNIT
1.1
5.5
V
0
VDD + 0.3
V
0.7 × VDD
V
0.3 × VDD
–40
V
100
ns/V
125
°C
7.4 Thermal Information
TPS382x-xx-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
209.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
72.8
°C/W
RθJB
Junction-to-board thermal resistance
36.7
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
35.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
7.5 Electrical Characteristics
over operating junction temperature range (unless otherwise noted)
PARAMETER
RESET
High-level output
voltage
VOH
RESET
TEST CONDITIONS
TPS382x-25-Q1
VDD = VIT− + 0.2 V, IOH = –20 μA
TPS382x-30-Q1
TPS382x-33-Q1
VDD = VIT− + 0.2 V, IOH = –30 μA
TPS382x-50-Q1
VDD = VIT− + 0.2 V IOH = –120 μA
TPS3824-25-Q1
TPS3825-25-Q1
VDD ≥ 1.8 V, IOH = –100 μA
MIN
MAX
UNIT
0.8 × VDD
VDD − 1.5 V
V
TPS3824-30-Q1
TPS3825-30-Q1
TPS3824-33-Q1
TPS3825-33-Q1
TYP
0.8 × VDD
VDD ≥ 1.8 V, IOH = –150 μA
TPS3824-50-Q1
TPS3825-50-Q1
TPS3824-25-Q1
TPS3825-25-Q1
RESET
Low-level output
voltage
VOL
RESET
TPS3824-30-Q1
TPS3825-30-Q1
TPS3824-33-Q1
TPS3825-33-Q1
VDD = VIT− + 0.2 V, IOL = 1 mA
VDD = VIT− + 0.2 V, IOL = 1.2 mA
V
TPS3824-50-Q1
TPS3825-50-Q1
VDD = VIT− + 0.2 V, IOL = 3 mA
TPS382x-25-Q1
VDD = VIT− – 0.2 V, IOL = 1 mA
TPS382x-30-Q1
TPS382x-33-Q1
TPS382x-50-Q1
Power-up reset voltage (1)
0.4
VDD = VIT− – 0.2 V, IOL = 1.2 mA
0.45
VDD = VIT− – 0.2 V, IOL = 3 mA
VDD ≥ 1.1 V, IOL = 20 μA
0.4
TPS382x-25-Q1
2.21
2.25
2.3
2.59
2.63
2.69
2.88
2.93
3
TPS382x-50-Q1
4.49
4.55
4.64
TPS382x-25-Q1
2.19
2.25
2.3
2.55
2.63
2.69
2.84
2.93
3
4.44
4.55
4.64
TPS382x-30-Q1
TPS382x-33-Q1
Negative-going input
threshold voltage (2)
VIT−
TPS382x-30-Q1
TPS382x-33-Q1
TA = 0°C to 85°C
TA = –40°C to 125°C
TPS382x-50-Q1
V
V
TPS382x-25-Q1
TPS382x-30-Q1
Vhys
Hysteresis at VDD input
IIH(AV)
Average high-level input current
IIL(AV)
Average low-level input current
IIH
High-level input current
IIL
Low-level input current
30
mV
TPS382x-33-Q1
TPS382x-50-Q1
50
WDI = VDD, time average (DC = 88%)
120
WDI = 0.3 V, VDD = 5.5 V time average (DC = 12%)
–15
WDI
WDI = VDD
140
190
MR
MR = VDD × 0.7, VDD = 5.5 V
–40
–60
WDI
WDI = 0.3 V, VDD = 5.5 V
140
190
MR
MR = 0.3 V, VDD = 5.5 V
–110
–160
WDI
µA
µA
µA
TPS382x-25-Q1
IOS
Output short-circuit
current (3)
IDD
Supply current
RESET
TPS382x-30-Q1
TPS382x-33-Q1
–400
VDD = VIT, max + 0.2 V, VO = 0 V
TPS382x-50-Q1
–800
WDI, MR, and outputs unconnected
15
Internal pullup resistor at MR
Ci
(1)
(2)
(3)
Input capacitance at MR, WDI
µA
VI = 0 V to 5.5 V
25
µA
52
kΩ
5
pF
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 μs/V.
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near the supply terminals.
The RESET short-circuit current is the maximum pullup current when RESET is driven low by a microprocessor bidirectional reset pin.
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7.6 Timing Requirements
At RL = 1 MΩ, CL = 50 pF, and TJ = 25°C, unless otherwise noted.
MIN
tw
Pulse width
TYP
MAX
UNIT
at VDD
VDD = VIT− + 0.2 V, VDD = VIT– – 0.2 V
6
at MR
VDD ≥ VIT− + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
1
μs
at WDI
VDD ≥ VIT− + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
100
ns
μs
7.7 Switching Characteristics
At RL = 1 MΩ, CL = 50 pF, and TA = 25°C, unless otherwise noted.
PARAMETER
ttout
Watchdog time out
TPS3823/4/8-xx-Q1
TPS3820-xx-Q1
td
Delay time
tPHL
Propagation (delay) time,
high-to-low-level output
tPLH
TPS3823/4/5/8-xx-Q1
Propagation (delay) time,
low-to-high-level output
VDD
TEST CONDITIONS
TPS3820-xx-Q1
MIN
TYP
MAX
UNIT
VDD ≥ VIT− + 0.2 V
See Figure 1
112
200
300
ms
0.9
1.6
2.5
s
VDD ≥ VIT− + 0.2 V
See Figure 1
15
25
37
120
200
300
MR to RESET delay
(TPS3820/3/5/8-xx-Q1)
VDD ≥ VIT− + 0.2 V,
VIL = 0.3 × VDD,
VIH = 0.7 × VDD
0.1
VDD to RESET delay
VIL = VIT– – 0.2 V,
VIH = VIT– + 0.2 V
25
MR to RESET delay
(TPS3824/5-xx-Q1)
VDD ≥ VIT− + 0.2 V,
VIL = 0.3 × VDD,
VIH = 0.7 × VDD
0.1
VDD to RESET delay
(TPS3824/5-xx-Q1)
VIL = VIT– – 0.2 V,
VIH = VIT– + 0.2 V
25
ms
µs
µs
VIT1.1 V
td
td
tt(out)
td
undefined
undefined
RESET
WDI
Figure 1. Delay and Time Out Timing Diagram
6
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
Normalized Input Threshold Voltage −V IT (TA), VIT (25°C)
7.8 Typical Characteristics
19
1.001
1
15
13
0.999
TPS382x-33-Q1
11
0.998
9
7
0.997
5
0.996
3
1
0.995
−40
−15
10
60
35
85
TA − Free-Air Temperature − °C
í1
í0.5
VOL − Low-Level Output Voltage − V
VDD = 5.5 V
WDI = Open
0
−40°C
−100
85°C
−150
−200
−1
2.5
3.5
4.5
5.5
6.5
VDD = 2.66 V
WDI = Open
MR = Open
2.5
2
1.5
85°C
1
−40°C
0.5
0
0
1
2
3
4
5
0
6
2
1
3
4
5
6
7
8
9
10
IOL − Low-Level Output Current − mA
VI − Input Voltage at MR − V
Figure 4. Input Current vs Input Voltage at MR
Figure 5. Low-Level Output Voltage vs Low-Level Output
Current
6
3.5
VDD = 3.2 V
WDI = Open
MR = Open
3
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
1.5
3
50
−50
0.5
Figure 3. Supply Current vs Supply Voltage
Figure 2. Normalized Input Threshold Voltage vs Free-Air
Temperature at VDD
I I − Input Current − µ A
MR = Open
WDI = Open
TA = 25°C
17
2.5
−40°C
2
1.5
85°C
1
0.5
0
VDD = 5.5 V
WDI = Open
MR = Open
5
4
−40°C
3
85°C
2
1
0
0
−50
−100
−150
−200
−250
IOH − High-Level Output Current − µA
Figure 6. High-Level Output Voltage vs High-Level Output
Current
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0
−100
−200
−300
−400
−500
−600
−700
IOH − High-Level Output Current − µA
Figure 7. High-Level Output Voltage vs High-Level Output
Current
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Typical Characteristics (continued)
t w − Minimum Pulse Duration at VDD − µs
10
WDI = Open
MR = Open
8
6
4
2
0
0
200
400
600
800
1000
VDD − Threshold Overdrive − mV
Figure 8. Minimum Pulse Duration at VDD vs VDD Threshold Overdrive
8
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
8 Detailed Description
8.1 Overview
The TPS382x-xx-Q1 family of supervisors provide circuit initialization and timing supervision. Optional
configurations include devices with active-high and active-low output signals (TPS3824/5-xx-Q1), devices with a
watchdog timer (TPS3820/3/4/8-xx-Q1), and devices with manual reset (MR) pins (TPS3820/3/5/8-xx-Q1).
RESET asserts when the supply voltage, VDD, rises above 1.1 V. For devices with active-low output logic, the
device monitors VDD and keeps RESET low as long as VDD remains below the negative threshold voltage, VIT−.
For devices with active-high output logic, RESET remains high as long as VDD remains below VIT−. An internal
timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td,
starts after VDD rises above the positive threshold voltage (VIT− + VHYS). When the supply voltage drops below
VIT−, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage,
VIT–, set by an internal voltage divider, so no external components are required.
The TPS382x-xx-Q1 family is designed to monitor supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The devices are
available in a 5-pin SOT-23 package and are characterized for operation over a temperature range of −40°C to
125°C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated circuits.
8.2 Functional Block Diagram
VDD
+
_
52 kW
RESET
RESET
Logic
(1)
RESET
VREF
MR
(2)
Auto-Reset
Oscillator
40 kW
WDI
(3)
(1)
TPS3824/5-xx-Q1
(2)
TPS3820/3/5/8-xx-Q1
(3)
TPS3820/3/4/8-xx-Q1
Transition
Detector
Watchdog
Timer Logic
8.3 Feature Description
8.3.1 Manual Reset (MR)
The MR input allows an external logic signal from processors, logic circuits, and/or discrete sensors to force a
reset signal regardless of VDD with respect to VIT– or the state of the watchdog timer. A low level at MR causes
the reset signals to become active.
8.3.2 Active High or Active Low Output
All TPS382x-xx-Q1 devices have an active-low logic output (RESET), while the TPS3824/5-xx-Q1 devices also
include an active-high logic output (RESET).
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Feature Description (continued)
8.3.3 Push-Pull or Open-Drain Output
All TPS382x-xx-Q1 devices, except for TPS3828-xx-Q1, have push-pull outputs. TPS3828-xx-Q1 devices have
an open-drain output.
8.3.4 Watchdog Timer (WDI)
TPS3820/3/4/8-xx-Q1 devices have a watchdog timer that must be periodically triggered by either a positive or
negative transition at WDI to avoid a reset signal being issued. When the supervising system fails to retrigger the
watchdog circuit within the time-out interval, ttout, RESET becomes active for the time period td. This event also
reinitializes the watchdog timer.
The watchdog timer can be disabled by disconnecting the WDI pin from the system. If the WDI pin detects that it
is in a high-impedance state the TPS3820/3/4/8-xx-Q1 will generate its own WDI pulse to ensure that RESET
does not assert. If this behavior is not desired place a 1-kΩ resistor from WDI to ground. This resistor will help
ensure that the TPS3820/3/4/8-xx-Q1 detects that WDI is not in a high-impedance state.
In applications where the input to the WDI pin is active (transitioning high and low) when the TPS3820/3/4/8-xxQ1 is asserting RESET, RESET will be stuck at a logic low after the input voltage returns above VIT–. If the
application requires that input to WDI be active when the reset signal is asserted, then use a FET to decouple
the WDI signal. An external FET decouples the WDI signal by disconnecting the WDI input when RESET is
asserted. For more details on this, see Decoupling WDI During Reset Event for more details.
8.4 Device Functional Modes
The device functions according to the inputs and outputs in Table 1.
Table 1. Function Table
INPUTS
(1)
(2)
10
(1)
OUTPUTS
VDD > VIT
RESET
RESET (2)
L
0
L
H
MR
L
1
L
H
H
0
L
H
H
1
H
L
TPS3820/3/5/8-xx-Q1
TPS3824/5-xx-Q1
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS382x-xx-Q1 family of devices are very small supervisory circuits that monitor fixed supply voltages of
2.5 V, 3 V, 3.3 V, and 5 V. The TPS382x-xx-Q1 family operates from 1.1 V to 5.5 V. Orderable options include
versions with either push-pull or open-drain outputs, versions that use active-high or active-low logic for output
signals, versions with a manual reset pin, and versions with a watchdog timer. See the Device Comparison Table
for an overview of device options.
9.2 Typical Applications
9.2.1 Supply Rail Monitoring with Watchdog Time-out and 200-ms Delay
The TPS3823-xx-Q1 can be used to monitor the supply rail for devices such as microcontrollers. The
downstream device is enabled by the TPS3823-xx-Q1 once the voltage on the supply pin (VDD) is above the
internal threshold voltage (VIT– + VHYS). The downstream device is disabled by the TPS3823-xx-Q1 when VDD
falls below the threshold voltage minus the hysteresis voltage (VIT–). The TPS3823-xx-Q1 also issues a reset
signal if the WDI input is not periodically triggered by a positive or negative transition at WDI. When the
supervising system fails to retrigger the watchdog circuit within the time-out interval, ttout, RESET becomes active
for the time period td.
Some applications require a shorter reset signal than the 200 ms that most of the TPS382x-xx-Q1 family provide.
In these cases, the TPS3820-xx-Q1is a good choice because it has a delay time of only 25 ms. If an open-drain
output is needed, replace the TPS3823-xx-Q1 with the TPS3828-xx-Q1 (if the WDI input must be active while
RESET is low, see Decoupling WDI During Reset Event). Figure 9 shows the TPS3823-33-Q1 in a typical
application.
3.3 V
100 nF
VDD
RESET
VDD
RESET
TPS3823-33-Q1
WDI
MR
GND
MSP430C325
I/O
GND
Figure 9. Supply Rail Monitoring With Watchdog Time-out
9.2.1.1 Design Requirements
The TPS3823-33-Q1 must drive the enable pin of a MSP430C325 using a logic-high signal to signify that the
supply voltage is above the minimum operating voltage of the device and monitor the I/O pin to determine if the
microcontroller is operating correctly.
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
Determine which version of the TPS382x-xx-Q1 family best suits the functional performance required.
If the input supply is noisy, include an input capacitor to help avoid unwanted changes to the reset signal.
9.2.1.3 Application Curve
t w − Minimum Pulse Duration at VDD − µs
10
WDI = Open
MR = Open
8
6
4
2
0
0
200
400
600
800
1000
VDD − Threshold Overdrive − mV
Figure 10. Minimum Pulse Duration at VDD vs VDD Threshold Overdrive
9.2.2 Decoupling WDI During Reset Event
If the application requires that the input to WDI is active when the reset signal is asserted, Figure 11 shows how
to decouple WDI from the active signal using an N-channel FET. The N-channel FET is placed in series with the
WDI pin, with the gate of the FET connected to the RESET output.
3.3 V
VDD
VDD
RESET
RESET
TPS3820-33-Q1
MR
WDI
Microprocessor
I/O
GND
GND
Figure 11. WDI Example
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range from 1.1 V to 5.5 V. Though
not required, it is good analog design practice to place a 0.1-μF ceramic capacitor close to the VDD pin if the input
supply is noisy.
12
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
11 Layout
11.1 Layout Guidelines
Follow these guidelines to lay out the printed-circuit-board (PCB) that is used for the TPS382x-xx-Q1 family of
devices.
• Place the VDD decoupling capacitor (CVDD) close to the device.
• Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the
maximum VDD voltage.
11.2 Layout Example
Pullup
Voltage
CVDD
RESET
Flag
TPS3828-xx-Q1
1
5
2
MR
Signal
3
4
WDI
Signal
Figure 12. Example Layout (DBV Package)
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• Latching a Voltage Supervisor (Reset IC)
• Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs)
• Disabling the Watchdog Timer for TI's Family of Supervisors
12.1.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS3820-Q1
Click here
Click here
Click here
Click here
Click here
TPS3823-Q1
Click here
Click here
Click here
Click here
Click here
TPS3824-Q1
Click here
Click here
Click here
Click here
Click here
TPS3825-Q1
Click here
Click here
Click here
Click here
Click here
TPS3828-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14
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SGLS143D – DECEMBER 2002 – REVISED JULY 2019
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
2T28-33QDBVRG4Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDIQ
2U3824-33QDBVRG4Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAVQ
TPS3820-33QDBVRQ1
NRND
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDEQ
TPS3820-33QPDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
33PQ
TPS3820-50DBVRQ1G4
NRND
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PKG4
TPS3820-50QDBVRQ1
NRND
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDDQ
TPS3820-50QPDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
50PQ
TPS3823-25QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAPQ
TPS3823-33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PARQ
TPS3823-50QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PASQ
TPS3824-33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAVQ
TPS3824-50QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAWQ
TPS3825-33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDGQ
TPS3828-33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDIQ
TPS3828-50QDBVRG4Q
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDHQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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