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TPS3840-Q1
SNVSBA1B – APRIL 2019 – REVISED APRIL 2020
TPS3840-Q1 Automotive Nano IQ Voltage Supervisor With MR and Programmable Delay
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C7B
Wide operating voltage : 1.5 V to 10 V
– Use external resistors to extend Vin range
Nano supply current : 350 nA (Typ), 700 nA (Max)
Fixed threshold voltage (VIT-)
– Threshold from 1.6 V to 4.9 V in 0.1-V steps
– High accuracy: 1% (Typ), 1.5% (Max)
– Built-in hysteresis (VIT+)
– 1.6 V < VIT- ≤ 3.0 V = 100 mV (typical)
– 3.1 V ≤ VIT- < 4.9 V = 200 mV (typical)
Fast start-up delay (tSTRT): 350 µs (Max)
Programmable capacitor-based reset time delay:
– tD: 50 µs (no capacitor) to 6.2 s (10-µF)
Active-low manual reset (MR)
Three output topologies:
– TPS3840DL-Q1: open-drain, active-low
(RESET)
– TPS3840PL-Q1: push-pull, active-low
(RESET)
– TPS3840PH-Q1: push-pull, active-high
(RESET)
Package: 5-pin SOT-23 (DBV)
•
Automotive head unit and cluster
Automotive display, integrated cockpit and driver
monitoring
Telematics control unit and emergency call
3 Description
The TPS3840-Q1 family of voltage supervisors or
reset ICs can operate at high voltage levels while
maintaining very low quiescent current across the
whole VDD and temperature range. TPS3840-Q1
offers best combination of low power consumption,
high accuracy and low propagation delay (tp_HL= 30
µs typical).
Reset output signal is asserted when the voltage at
VDD drops below the negative voltage threshold (VIT-)
or when manual reset is pulled to a low logic (VMR_L).
Reset signal is cleared when VDD rise above VIT- plus
hysteresis (VIT+) and manual reset (MR) is floating or
above VMR_H and the reset time delay (tD) expires.
Reset time delay can be programmed by connecting
a capacitor between CT pin and ground. For a fast
reset CT pin can be left floating.
Additional features: Low power-on reset voltage
(VPOR), built-in glitch immunity protection for MR and
VDD, built-in hysteresis, low open-drain output
leakage current (ILKG(OD)). TPS3840-Q1 is a perfect
voltage
monitoring
solution
for
automotive
applications and battery-powered / low power
applications.
Device Information(1)
PART NUMBER
TPS3840-Q1
PACKAGE
SOT-23 (5) (DBV)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For package details, see the mechanical drawing addendum
at the end of the data sheet.
Typical Application Circuit
3.3V
1.8V
VCORE
VDD
MR
TPS3840PL18
CT
Microcontroller
VDD
RESET
GND
MR
VI/O
RESET
RESET
TPS3840DL30
CT
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3840-Q1
SNVSBA1B – APRIL 2019 – REVISED APRIL 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Device Nomenclature............................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2019) to Revision B
Page
•
Changed equation 5 and 6 ................................................................................................................................................... 17
•
Added section describing further details on capacitor. ........................................................................................................ 18
•
Deleted non-relevant application design. ............................................................................................................................ 22
Changes from Original (April 2019) to Revision A
•
2
Page
Advance Information to Production Data Release ................................................................................................................ 1
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5 Device Comparison
Figure 1 shows the device nomenclature to determine the device variant. Other voltages from Table 3 at the end
of datasheet can be sampled upon request, please contact TI sales representative for details.
TPS3840 XX XX XXX Q1
OUTPUT TYPE
DL: Open-Drain Active-Low
PL: Push-Pull Active-Low
PH: Push-Pull Active-High
Threshold Voltage
16: 1.6V
17: 1.7V
...
49: 4.9V
See Device
Threshold Table
Package
DBV: SOT-23
Figure 1. Device Nomenclature
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6 Pin Configuration and Functions
DBV Package
5-Pin
TPS3840PL-Q1, TPS3840DL-Q1 Top View
RESET
1
VDD
5
DBV Package
5-Pin
TPS3840PH-Q1 Top View
CT
RESET
1
VDD
2
GND
3
5
CT
4
MR / NC
2
GND
3
MR / NC
4
Not to scale
Not to scale
Pin Functions
PIN
NAME
TPS3840PL-Q1,
TPS3840DL-Q1
TPS3840PH-Q1
I/O
DESCRIPTION
RESET
N/A
1
O
Active-High Output Reset Signal: This pin is driven high
when either the MR pin is driven to a logic low or VDD
voltage falls below the negative voltage threshold (VIT-).
RESET remains high (asserted) for the delay time period (tD)
after both MR is floating or above VMR_L and VDD voltage
rise above VIT+.
RESET
1
N/A
O
Active-Low Output Reset Signal: This pin is driven logic
when either the MR pin is driven to a logic low or VDD
voltage falls below the negative voltage threshold (VIT-).
RESET remains low (asserted) for the delay time period (tD)
after both MR is floating or above VMR_L and VDD voltage
rise above VIT+.
VDD
2
2
I
Input Supply Voltage. TPS3840-Q1 monitors VDD voltage
GND
3
3
_
Ground
MR / NC
4
4
I
Manual Reset. Pull this pin to a logic low (VMR_L) to assert a
reset signal in the output pin. After the MR pin is left floating
or pull to VMR_H the output goes to the nominal state after the
reset delay time(tD) expires. MR can be left floating when
not in use. NC stands for "No Connection" or floating.
CT
5
5
-
Capacitor Time Delay Pin. The CT pin offers a userprogrammable delay time. Connect an external capacitor on
this pin to adjust time delay. When not in use leave pin
floating for the smallest fixed time delay.
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (1)
Voltage
Current
(2)
(3)
MAX
–0.3
12
RESET (TPS3840PL)
–0.3
VDD + 0.3
RESET (TPS3840PH)
–0.3
VDD + 0.3
RESET (TPS3840DL)
–0.3
12
MR (2)
–0.3
12
CT
–0.3
5.5
RESET pin and RESET pin
Temperature (3)
(1)
MIN
VDD
±70
Operating junction temperature, TJ
–40
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
± 2000
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
± 750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Input supply voltage
1.5
10
VRESET, VRESET
RESET pin and RESET pin voltage
0
10
V
IRESET, IRESET
RESET pin and RESET pin current
0
±5
mA
TJ
Junction temperature (free air temperature)
–40
125
°C
0
VDD
V
VMR
(1)
(1)
Manual reset pin voltage
V
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
7.4 Thermal Information
TPS3840
THERMAL METRIC (1)
DBV (SOT23-5)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
187.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
109.2
°C/W
RθJB
Junction-to-board thermal resistance
92.8
°C/W
ψJT
Junction-to-top characterization parameter
35.4
°C/W
ψJB
Junction-to-board characterization parameter
92.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF
and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
10
V
VIT-
Negative-going input threshold accuracy (1)
-40°C to 125°C
–1.5
1.5
1
1.5
%
VHYS
Hysteresis on VIT- pin
VIT- = 3.1 V to 4.9 V
175
200
225
mV
VHYS
Hysteresis on VIT- pin
VIT- = 1.6 V to 3.0 V
75
100
125
mV
IDD
Supply current into VDD pin
VDD = 1.5 V < VDD < 10 V
VDD > VIT+ (2)
TA = -40°C to 125°C
300
700
nA
VMR_L
Manual reset logic low input (3)
600
mV
VMR_H
Manual reset logic high input (3)
RMR
Manual reset internal pull-up resistance
RCT
CT pin internal resistance
0.7VDD
V
100
350
500
kΩ
650
kΩ
VOL(max) = 200 mV
IOUT(Sink) = 200 nA
300
mV
1.5 V < VDD < 5 V
VDD < VITIOUT(Sink) = 2 mA
200
mV
TPS3840PL (Push-Pull Active-Low)
VPOR
Power on Reset Voltage (4)
Low level output voltage
VOL
High level output voltage
VOH
1.5 V < VDD < 5 V
VDD > VIT+ (2)
IOUT(Source) = 2 mA
0.8VDD
V
5 V < VDD < 10 V
VDD > VIT+ (2)
IOUT(Source) = 5 mA
0.8VDD
V
TPS3840PH (Push-Pull Active-High)
VPOR
VOL
Power on Reset Voltage (4)
VOH, IOUT(Source) = 500 nA
950
mV
200
mV
Low level output voltage
1.5 V < VDD < 5 V
VDD > VIT+ (2)
IOUT(Sink) = 2 mA
1.5 V < VDD < 5 V
VDD > VIT+ (2)
IOUT(Sink) = 5 mA
200
mV
High level output voltage
VOH
1.5 V < VDD < 5 V, VDD < VIT-,
IOUT(Source) = 2 mA
0.8VDD
V
TPS3840DL(Open-Drain)
VPOR
Low level output voltage
VOL
Ilkg(OD)
(1)
(2)
(3)
(4)
6
Power on Reset Voltage (4)
Open-Drain output leakage current
VOL(max) = 0.2 V
IOUT (Sink) = 5.6 uA
950
mV
1.5 V < VDD < 5 V
VDD < VITIOUT(Sink) = 2 mA
200
mV
90
nA
RESET pin in High Impedance,
VDD = VRESET = 5.5 V
VIT+ < VDD
VIT- threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.
VIT+ = VHYS + VITIf the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR
VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate ≤ 100mV/µs
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7.6 Timing Requirements
At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF
and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted.
Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
tSTRT
Startup Delay (1)
CT pin open
tP_HL
Propagation detect delay for VDD falling
below VIT-
VDD = VIT+ to (VIT-) - 10% (2)
MIN
TYP
MAX
UNIT
100
220
350
µs
15
30
µs
50
µs
CT pin = open
Reset time delay (3)
tD
CT pin = 10 nF
6.2
ms
CT pin = 1 µF
619
ms
10
µs
300
ns
700
ns
tD
ms
5% VIT- overdrive (4)
tGI_VIT-
Glitch immunity VIT-
tMR_PW
MR pin pulse duration to initiate reset
tMR_RES
Propagation delay from MR low to reset
VDD = 4.5 V, MR < VMR_L
Delay from release MR to deasert reset
VDD = 4.5 V,
MR = VMR_L to VMR_H
tMR_tD
(1)
(2)
(3)
(4)
When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is release after the startup delay (tSTRT), a
capacitor at CT pin will add tD delay to tSTRT time
tP_HL measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants.
The MIN and MAX reset time delay with external capacitor depends on RCT and is calculated using Equation 5 and Equation 6 in
Section 8.3.2
Overdrive % = [(VDD/ VIT-) - 1] × 100%
VDD
VIT+
VITVDD(MIN)
VPOR
tSTRT + tD
RESET
tP_HL
tD
tP_HL
tSTRT + tD
VOH
VOL
(1)
tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then
tD programmed time will be added to the startup time, VDD slew rate = 100 mV / µs.
(2)
Open-Drain timing diagram assumes pull-up resistor is connected to RESET
Figure 4. Timing Diagram TPS3840DL-Q1 (Open-Drain Active-Low)
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VIT+
VITVDD(MIN)
VDD
VPOR
tP_HL
tSTRT + tD
RESET
tD
tP_HL
tSTRT + tD
VOH
VOL
(3)
tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then
tD programmed time will be added to the startup time. VDD slew rate = 100 mV / µs.
Figure 5. Timing Diagram TPS3840PL-Q1 (Push-Pull Active-Low)
VIT+
VITVDD(MIN)
VDD
VPOR
tSTRT + tD
tP_HL
tD
tP_HL
tSTRT + tD
VOH
RESET
VOL
(4)
tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then
tD programmed time will be added to the total startup time. VDD slew rate = 100 mV / µs.
Figure 6. Timing Diagram TPS3840PH-Q1 (Push-Pull Active-High)
8
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7.7 Typical Characteristics
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
0.6
0.6
25°C
-40°C
125°C
0.55
0.5
0.5
0.45
0.45
0.4
IDD (µA)
0.4
IDD (µA)
25°C
-40°C
125°C
0.55
0.35
0.3
0.25
0.35
0.3
0.25
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
1
2
3
4
5
6
VDD (V)
7
8
9
10
1
Figure 7. Supply Current vs Supply Voltage for
TPS3840DL49-Q1
4
5
6
VDD (V)
7
8
9
10
IDDv
0.6
25°C
-40°C
125°C
0.5
0.5
0.4
DL16
DL29
DL49
0.3
VIT- Accuracy (%)
0.45
0.4
IDD (µA)
3
Figure 8. Supply Current vs Supply Voltage for
TPS3840PL49-Q1
0.6
0.55
0.35
0.3
0.25
0.2
0.1
0
-0.1
-0.2
0.2
-0.3
0.15
-0.4
0.1
-0.5
-0.6
-40
0.05
1
2
3
4
5
6
VDD (V)
7
8
9
10
0.4
20
40
60
80
Temperature (°C)
100
120
140
VIT_
0.6
PL16
PL28
PL49
0.5
0.4
PH16
PH30
PH49
0.3
VIT- Accuracy (%)
0.3
0.2
0.1
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
-0.6
-40
0
Figure 10. Negative-going Input Threshold Accuracy over
Temperature for TPS3840DL-Q1
0.6
0.5
-20
IDDv
Figure 9. Supply Current vs Supply Voltage for
TPS3840PH49-Q1
VIT- Accuracy (%)
2
IDDv
-20
0
20
40
60
80
Temperature (°C)
100
120
140
-0.6
-40
-20
VIT_
Figure 11. Negative-going Input Threshold Accuracy over
Temperature for TPS3840PL-Q1
0
20
40
60
80
Temperature (°C)
100
120
140
VIT_
Figure 12. Negative-going Input Threshold Accuracy over
Temperature for TPS3840PH-Q1
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
20
20
DL16
DL29
DL49
10
5
0
-5
-10
-15
-20
-40
10
5
0
-5
-10
-15
-20
0
20
40
60
80
Temperature (°C)
100
120
-20
-40
140
-20
0
20
Vhys
Figure 13. Input Threshold VIT- Hysteresis Accuracy for
TPS3840DL-Q1
40
60
80
Temperature (°C)
100
120
140
Vhys
Figure 14. Input Threshold VIT- Hysteresis Accuracy for
TPS3840PL-Q1
20
10
PH16
PH30
PH49
15
25°C
-40°C
125°C
9
8
10
7
5
VRESET (V)
VHYS Accuracy (%)
PL16
PL28
PL49
15
VHYS Accuracy (%)
VHYS Accuracy (%)
15
0
-5
6
5
4
3
2
-10
1
-15
-20
-40
0
-1
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0
Figure 15. Input Threshold VIT- Hysteresis Accuracy for
TPS3840PH-Q1
3
4
5
6
VDD (V)
7
8
9
10
VRES
5.5
25°C
-40°C
125°C
9
8
25°C
-40°C
125°C
5
4.5
7
4
6
3.5
VRESET (V)
VRESET (V)
2
Figure 16. Output Voltage vs Input Voltage for
TPS3840DL49-Q1
10
5
4
3
2
3
2.5
2
1.5
1
1
0
0.5
-1
0
0
1
2
3
4
5
6
VDD (V)
7
8
9
10
0
1
VRES
Figure 17. Output Voltage vs Input Voltage for
TPS3840PL49-Q1
10
1
Vhys
2
3
4
5
6
VDD (V)
7
8
9
10
VRES
Figure 18. Output Voltage vs Input Voltage for
TPS3840PH49-Q1
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
0.055
140
25°C
-40°C
125°C
120
25°C
-40°C
125°C
0.05
0.045
100
VOL (V)
VOL (V)
0.04
80
60
0.035
0.03
40
0.025
20
0.02
0.015
1.5
0
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
3
3.5
VDD (V)
4
4.5
5
VOLv
0.055
140
25°C
-40°C
125°C
120
100
0.045
80
0.04
60
0.035
40
0.03
20
0.025
0
0.02
0.015
1.5
-20
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
60
VOL (V)
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
2.5
3
3.5
VDD (V)
3.5
4
4.5
5
4.5
5
VOLv
0.09
0.085
0.08
0.075
0.07
0.065
0.06
0.055
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
25°C
-40°C
125°C
5
5.5
VOL_
Figure 23. Low Level Output Voltage vs IRESET for
TPS3840PH49-Q1
4
Figure 22. Low Level Output Voltage vs VDD for
TPS3840PL49-Q1
25°C
-40°C
125°C
70
2
VOL_
Figure 21. Low Level Output Voltage vs IRESET for
TPS3840PL49-Q1
80
25°C
-40°C
125°C
0.05
VOL (V)
VOL (V)
2.5
Figure 20. Low Level Output Voltage vs VDD for
TPS3840DL49-Q1
Figure 19. Low Level Output Voltage vs IRESET for
TPS3840DL49-Q1
VOL (V)
2
VOL_
6
6.5
7
7.5
8
VDD (V)
8.5
9
9.5
10 10.5
VOLv
Figure 24. Low Level Output Voltage vs VDD for
TPS3840PH49-Q1
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
5
10
25°C
-40°C
125°C
9.975
9.95
4.5
25°C
-40°C
125°C
4
9.9
VOH (V)
VOH (V)
9.925
9.875
9.85
3.5
3
2.5
9.825
2
9.8
1.5
9.775
1
1.5
9.75
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
25°C
-40°C
125°C
1.55
4.5
4
4.5
5
VOHv
25°C
-40°C
125°C
4
VOH (V)
1.5
VOH (V)
3
3.5
VDD (V)
5
1.6
1.45
1.4
3.5
3
2.5
1.35
2
1.3
1.5
1
1.5
1.25
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
2.25
3
3.5
VDD (V)
4
4.5
5
VOHv
2.75
DL16
DL29
DL49
2.5
2.25
V_MR_L (V)
2
1.75
1.5
2
1.5
1.25
1
1
0.75
0.75
-20
0
20
40
60
80
Temperature (°C)
100
120
140
PL16
PL28
PL49
1.75
1.25
0.5
-40
2.5
Figure 28. High Level Output Voltage Over Temperature for
TPS3840PH49-Q1
2.75
2.5
2
VOH_
Figure 27. High Level Output Voltage vs IRESET for
TPS3840PH49-Q1
V_MR_L (V)
2.5
Figure 26. High Level Output Voltage over Temperature for
TPS3840PL49-Q1
Figure 25. High Level Output Voltage vs IRESET for
TPS3840PL49-Q1
0.5
-40
-20
MR_L
Figure 29. Manual Reset Logic Low Voltage Threshold Over
Temperature for TPS3840DL-Q1
12
2
VOH_
0
20
40
60
80
Temperature (°C)
100
120
140
MR_L
Figure 30. Manual Reset Logic Low Voltage Threshold Over
Temperature for TPS3840PL-Q1
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
2.75
2.75
2.5
2.25
PH16
PH230
PH49
2.5
2.25
V_MR_H (V)
V_MR_L (V)
2
1.75
1.5
1.25
-20
0
20
40
60
80
Temperature (°C)
100
120
0
20
40
60
80
Temperature (°C)
100
120
140
MR_H
Figure 32. Manual Reset Logic High Voltage Threshold Over
Temperature for TPS3840DL-Q1
2.75
PL16
PL28
PL49
2.5
PH16
PH30
PH49
2.25
V_MR_H (V)
2.25
2
1.75
1.5
2
1.75
1.5
1.25
1.25
1
1
0.75
-40
-20
MR_L
2.75
V_MR_H (V)
1.5
0.75
-40
140
Figure 31. Manual Reset Logic Low Voltage Threshold Over
Temperature for TPS3840PH-Q1
-20
0
20
40
60
80
Temperature (°C)
100
120
0.75
-40
140
-20
0
20
MR_H
Figure 33. Manual Reset Logic High Voltage Threshold Over
Temperature for TPS3840PL-Q1
40
60
80
Temperature (°C)
100
120
140
MR_H
Figure 34. Manual Reset Logic High Voltage Threshold Over
Temperature for TPS3840PH-Q1
22
478
25°C
-40°C
125°C
21
20
476
474
19
DL49
PL49
PH49
472
R_CT (kohm)
Glitch Immunity (µs)
1.75
1
0.75
2.5
2
1.25
1
0.5
-40
DL16
DL29
DL49
18
17
16
470
468
466
15
464
14
462
13
460
12
5
10
15
20
25
30
35
Overdrive (%)
40
45
50
458
-40
-20
Glit
Figure 35. Glitch Immunity on VIT- vs Overdrive (Data Taken
with TPS3840PL28-Q1)
0
20
40
60
80
Temperature (°C)
100
120
140
RCTv
Figure 36. CT Pin Internal Resistance Over Temperature
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
15
215
DL49
PL49
PH49
DL49
PL49
PH49
210
t_D no Capacitor (µs)
205
t_STRT (µs)
200
195
190
185
180
12
9
6
175
170
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
3
-40
140
Figure 37. Startup Delay Over Temperature
500
3500
3000
t_D (ms)
20
40
60
80
Temperature (°C)
100
120
140
Dela
600
25°C
-40°C
125°C
tD with Capacitor (ms)
4000
0
Figure 38. Reset Time Delay with No Capacitor Over
Temperature
5000
4500
-20
Star
2500
2000
1500
1000
25°C
-40°C
125°C
400
300
200
100
500
0
0.01 0.02
0.05
0.1
0.2 0.3 0.5
Capacitor (µF)
1
2
0
0.01
3 4 5 67 10
Figure 39. Reset Time Delay vs Capacitor Value (Data Taken
with TPS3840PL16-Q1)
0.3
0.5 0.7
1
Dela
17.25
25°C
-40°C
125°C
4.5
4
DL49
PL49
PH49
17
16.75
16.5
3.5
t_P_HL (µs)
tD with Capacitor (s)
0.050.07 0.1
0.2
Capacitor Value (µF)
Figure 40. Reset Time Delay vs Small Capacitor Values
(Data Taken with TPS3840PL16-Q1)
5
3
2.5
2
16.25
16
15.75
15.5
1.5
15.25
1
15
0.5
1
2
3
4
5
Capacitor Value (µF)
6
7
8 9 10
14.75
-40
-20
Dela
Figure 41. Reset Time Delay vs Large Capacitor Values
(Data Taken with TPS3840PL16-Q1)
14
0.02 0.03
Dela
0
20
40
60
80
Temperature (°C)
100
120
140
TPHL
Figure 42. Propagation Detect Time Delay for VDD Falling
Below VIT- (High-to-Low) Over Temperature
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
465
460
3.5
3.45
450
t_MR_ tD (µs)
T_MR_RES (ns)
455
3.55
DL49
PL49
PH49
445
440
435
430
3.4
3.35
3.3
3.25
425
3.2
420
3.15
415
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
DL49
PL49
PH49
3.1
-40
-20
MR_r
Figure 43. Propagation Time Delay from MR Asserted to
Reset Over Temperature
0
20
40
60
80
Temperature (°C)
100
120
140
MRde
Figure 44. Propagation Time Delay from MR Release to
Deasserted Reset Over Temperature
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8 Detailed Description
8.1 Overview
The TPS3840-Q1 is a family of wide VDD and nano-quiescent current voltage detectors with fixed threshold
voltage. TPS3840-Q1 features include programable reset time delay using external capacitor, active-low manual
reset, 1% typical monitor threshold accuracy with hysteresis and glitch immunity.
Fixed negative threshold voltages (VIT-) can be factory set from 1.6 V to 4.9 V (see Table 3 for available options).
TPS3840-Q1 is available in SOT-23 5 pin industry standard package.
8.2 Functional Block Diagram
VDD
Push-Pull variants
RMR
VDD
VDD
MR / NC
RESET
RCT
Subreg
RESET
VDD
Voltage
Divider
+
±
VREF
GND
GND
CT / NC
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8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator to indicate when VDD falls below the fixed threshold voltage.
VDD also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other
control logic blocks. Good design practice involve placing a 0.1 uF to 1 uF bypass capacitor at VDD input for
noisy applications to ensure enough charge is available for the device to power up correctly.
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Feature Description (continued)
8.3.1.1 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis
(VHYS) the output reset is deasserted after tD delay.
Hystersis Width
Hystersis Width
RESET
RESET
VIT-
VIT-
VIT+
VIT+
VDD
VDD
Figure 45. Hysteresis Diagram
8.3.1.2 VDD Transient Immunity
The TPS3840-Q1 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends
on both pulse duration and overdrive. Overdrive is defined by how much VDD deviates from the specified
threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1.
Overdrive = | (VDD / VIT- – 1) × 100% |
(1)
VDD
VIT+
VITOverdrive
Pulse
Duration
Figure 46. Overdrive vs Pulse Duration
8.3.2 User-Programmable Reset Time Delay
The reset time delay can be set to a minimum value of 50 µs by leaving the CT pin floating, or a maximum value
of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmed
by connecting a capacitor no larger than 10 µF between CT pin and GND.
The relationship between external capacitor (CCT_EXT) in F at CT pin and the time delay (tD) in seconds is given
by Equation 2.
tD = -ln (0.29) x RCT x CCT_EXT + tD (no cap)
Equation 2 is simplified to Equation 3 by plugging RCT and tD(no
(2)
cap)
given in Electrical Characteristics section:
tD = 618937 x CCT_EXT + 50 µs
(3)
Equation 4 solves for external capacitor value (CCT_EXT) in units of F where tD is in units of seconds
CCT_EXT = (tD- 50 µs) ÷ 618937
(4)
The reset delay varies according to three variables: the external capacitor variance (CCT), CT pin internal
resistance (RCT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum
variance due to the constant is shown in Equation 5 and Equation 6.
s tD (minimum) = -ln (0.36) x RCT (min) x CCT (min) + tD (no cap, min)
tD (maximum) = -ln (0.26) x RCT (max) x CCT (max) + tD (no cap, max)
(5)
(6)
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Feature Description (continued)
The recommended maximum delay capacitor for the TPS3840 is limited to 10 µF as this ensures there is enough
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before
the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and
the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has
enough time to fully discharge during the duration of the voltage fault.
8.3.3 Manual Reset (MR) Input
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR
with pulse duration longer than tMR_RES will causes reset output to assert. After MR returns to a logic high (VMR_H)
and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than
VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to
either VDD or GND. VMR must not be higher than VDD voltage.
VDD
VIT+
VIT-
RESET
VIT+
VHYS
VHYS
VITtP_HL
tD
tMR_tD
tMR_RES
MR
VMR_H
VMR_L
tMR_PW
Reset not asserted
Pulse width less than tMR_PW
Figure 47. Timing Diagram MR and RESET (TPS3840DL-Q1)
8.3.4 Output Logic
8.3.4.1 RESET Output, Active-Low
RESET (Active-Low) applies to TPS3840DL-Q1 (Open-Drain) and TPS3840PL-Q1 (Push-Pull) hence the "L" in
the device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and
the MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then
RESET is asserted.
When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for the
specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high
voltage (VOH).
The TPS3840DL-Q1 (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to
hold RESET pin high. Connect the pull-up resistor to the desired pull-up voltage source and RESET can be
pulled up to any voltage up to 10 V independent of the VDD voltage. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual VOL, the
output capacitive loading, and the output leakage current (ILKG(OD)).
The Push-Pull variants (TPS3840PL and TPS3840PH), denoted with "P" in the device name, does not require a
pull-up resistor.
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Feature Description (continued)
8.3.4.2 RESET Output, Active-High
RESET (active-high), denoted with no bar above the pin label, applies only to TPS3840PH-Q1 push-pull activehigh version. RESET remains low (deasserted) as long as VDD is above the threshold (VIT-) and the manual
reset signal (MR) is logic high or floating. If VDD falls below the negative threshold (VIT-) or if MR is driven low,
then RESET is asserted driving the RESET pin to high voltage (VOH).
When MR is again logic high and VDD is above VIT+ the delay circuit will hold RESET high for the specified reset
time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to low voltage (VOL ).
8.4 Device Functional Modes
Table 1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic low is
represented by "L".
Table 1. Truth Table
(1)
VDD
MR
RESET
RESET
VDD < VPOR
Ignored
Undefined
Undefined
VPOR < VDD < VIT- (1)
Ignored
H
L
VDD ≥ VIT-
L
H
L
VDD ≥ VIT-
H
L
H
VDD ≥ VIT-
Floating
L
H
When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and output reset is held asserted until VDD falls below VPOR.
8.4.1 Normal Operation (VDD > VDD(min))
When VDD is greater than VDD(min), the reset signal is determined by the voltage on the VDD pin with respect to
the trip point (VIT-) and the logic state of MR.
• MR high: the reset signal corresponds to VDD with respect to the threshold voltage.
• MR low: in this mode, the reset is asserted regardless of the threshold voltage.
8.4.2
VDD Between VPOR and VDD(min)
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage (VPOR),
the reset signal is asserted.
8.4.3 Below Power-On-Reset (VDD < VPOR)
When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the
asserted output low or high and reset voltage level is undefined.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
A typical application for the TPS3840-Q1 is voltage rail monitoring and power-up sequencing as shown in
Figure 48. The TPS3840-Q1 can be used to monitor any rail above 1.6 V. In this design application, two
TPS3840-Q1 devices monitor two separate voltage rails and sequences the rails upon power-up. The
TPS3840PL30-Q1 is used to monitor the 3.3-V main power rail and the TPS3840DL16-Q1 is used to monitor the
1.8-V rail provided by the LDO for other system peripherals. The RESET output of the TPS3840PL30-Q1 is
connected to the ENABLE input of the LDO. A reset event is initiated on either voltage supervisor when the VDD
voltage is less than VIT- or when MR is driven low by an external source.
LDO
VDD
EN
3.3V
1 µF
1.8 V
1 µF
10NŸ
VDD
MR
MR
TPS3840PL30
CT
GND
VCORE
Microcontroller
VDD
RESET
VI/O
RESET
RESET
TPS3840DL16
NC
CT
GND
0.047µF
Figure 48. TPS3840-Q1 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram
9.2.1.1 Design Requirements
This design requires voltage supervision on two separate rails: 3.3-V and 1.8-V rails. The voltage rail needs to
sequence upon power up with the 3.3-V rail coming up first followed by the 1.8-V rail at least 25 ms after.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Two Rail Voltage Supervision
Monitor 3.3-V and 1.8-V rails
Two TPS3840-Q1 devices provide voltage monitoring with 1%
accuracy with device options available in 0.1 V variations
Voltage Rail Sequencing
Power up the 3.3-V rail first followed
by 1.8-V rail 25 ms after
The CT capacitor on TPS38240PL28 is set to 0.047 µF for a
reset time delay of 29 ms typical
Output logic voltage
3.3-V Open-Drain
3.3-V Open-Drain
Maximum device current
consumption
1 µA
Each TPS3840-Q1 requires 350 nA typical
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9.2.1.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS3840-Q1 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V
increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to
trigger determines the correct voltage supervisor variant to choose. In this example, the first TPS3840-Q1
triggers when the 3.3-V rail falls to 3.0 V. The second TPS3840-Q1 triggers a reset when the 1.8-V rail falls to
1.6 V. The secondary constraint for this application is the reset time delay that must be at least 25 ms to allow
the microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.8-V
rail is enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance.
For applications with ambient temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and
solving for CCT in Equation 2. Solving Equation 2 for 25 ms gives a minimum capacitor value of 0.04 µF which is
rounded up to a standard value 0.047 µF to account for capacitor tolerance.
A 1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor
is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5
mA limit found in the Recommended Operating Conditions: RPull-up = VPull-up ÷ 5 mA. For this design, a standard
10-kΩ pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the
pull-up resistor, the higher VOL. The MR pin can be connected to an external signal if desired or left floating if not
used due to the internal pull-up resistor to VDD.
9.2.1.3 Application Curves
VDD
30ms delay from VDD (3.3V) to LDO Enable set by 0.047µF on CT of TPS3840PL30
RESET
(LDO Enable)
VOUT (LDO)
Negligible delay from LDO Enable to 1.8V VOUT
Figure 49. Startup Sequence Highlighting the Delay Between 3.3V and 1.8V Rails
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9.2.2 Design 2: Automotive Off-Battery Monitoring
The initial power stage in automotive applications starts with the 12 V battery. Variation of the battery voltage is
common between 9 V and 16 V. Furthermore, If cold-cranking and load dump conditions are considered, voltage
transients can occur as low as 3 V and as high as 42V. In this design example, we are highlighting the ability for
low power , direct off-battery voltage supervision. Figure 50 illustrates an example of how the TPS3840-Q1 is
monitoring the battery voltage while being powered by it as well. For more information, read this application
report on how to achieve nano-amp IQ voltage supervision in automotive, wide-vin applications.
Figure 50. Fast Start Undervoltage Supervisor with Level-Shifted Input
22
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9.2.2.1 Design Requirements
This design requires voltage supervision on a 12-V power supply voltage rail with possibility of the 12-V rail rising
up as high as 42 V. The undervoltage fault occurs when the power supply voltage drops below 7.7 V.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Power Rail Voltage Supervision
Monitor 12-V power supply for undervoltage
condition, trigger a undervoltage fault at 7.7 V.
TPS3840-Q1 provides voltage monitoring with 1%
accuracy with device options available in 0.1 V
variations. Resistor dividers are calculated based
on device variant and desired threshold voltage.
Maximum Input Power
Operate with power supply input up to 42 V.
The TPS3840-Q1 limits VDD to 10 V but can
monitor voltages higher than the maximum VDD
voltage with the use of an external resistor divider.
Output logic voltage
Open-Drain Output Topology
Due to large variance in battery voltage, an opendrain output is recommended to provide the correct
reset signal.
35 uA when power supply is at 12 V typical
TPS3840-Q1 requires 350 nA (typical) and the
external resistor divider will also consume current.
There is a tradeoff between current consumption
and voltage monitor accuracy but generally set the
resistor divider to consume 100 times current into
VDD.
Voltage Monitor Accuracy
Typical voltage monitor accuracy of 2.5%.
The TPS3840-Q1 has 1% typical voltage monitor
accuracy. By decreasing the ratio of resistor
values, the resistor divider will consume more
current but the accuracy will increase. The resistor
tolerance also needs to be accounted for.
Delay when returning from fault
condition
RESET delay of at least 200 ms when returning
from a undervoltage fault.
CCT = 0.33 µF sets 204 ms delay
Maximum system current
consumption
9.2.2.2 Detailed Design Procedure
The primary constraint for this application is monitoring a 12-V rail while preventing the VDD pin on TPS3840-Q1
from exceeding the recommended maximum of 10 V. This is accomplished by sizing the resistor divider so that
when the 12-V rail drops to 7.7 V, the VDD pin for TPS3840-Q1 will be at 1.6 V which is the VIT- threshold for
triggering a undervoltage condition for TPS3840DL16-Q1 as shown in Equation 7. Reasonably sized resistors
were selected for the voltage divider. While selecting lower resistor values may increase current, this allows for
additional accuracy from the resistor divider.
Vrail_trigger = VIT- x (R2 ÷ (R1 + R2))
(7)
where Vrail_trigger is the trigger voltage of the rail being monitored, VIT- is the falling threshold on the VDD pin of
TPS3840, and R1 and R2 are the top and bottom resistors of the external resistor divider. VIT- is fixed per device
variant and is 1.6 V for TPS3840DL16-Q1. Substituting in the values from Figure 50, the undervoltage trigger
threshold for the rail is set to 7.7 V. Given that R1 = 100 kΩ, R2 = 26.2 kΩ.
Because the undervoltage trigger of 10 V on the rail corresponds to 1.6 V undervoltage threshold trigger of the
TPS3840-Q1 device, there is room for the rail to rise up while maintaining less than 10 V on the VDD pin of the
TPS3840-Q1. Equation 8 shows the maximum rail voltage that still meets the 10 V maximum at the VDD pin for
TPS3840-Q1.
Vrail_max = 10 V x (26.2 kΩ ÷ (100 kΩ + 26.2 kΩ)) = 48.168 V
(8)
This means the monitored voltage rail can go as high as 48.168 V and not violate the recommended maximum
for the VDD pin on TPS3840-Q1. This is useful when monitoring a voltage rail that has a wide range that may go
much higher than the nominal rail voltage such as in this case. Notice that the resistor values chosen are less
than 100kΩ to preserve the accuracy set by the internal resistor divider. Good design practice recommends using
a 0.1-µF capacitor on the VDD pin and this capacitance may need to increase when using an external resistor
divider.
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9.2.2.3 Application Curves: TPS3840EVM
These application curves are taken with the TPS3840EVM using the TPS3840-Q1. Please see the TPS3840EVM
User Guide for more information. The scope of the test below was to ensure that normal operation was
maintained under typical cold crank and load dump conditions. This was verified by observing the input changing
to its minimum and maximum value and the output remained both defined and accurate.
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Figure 51. TPS3840-Q1 Warm-Start Test Pulse
Figure 52. TPS3840-Q1 Cold-Start Test Pulse
Figure 53. TPS3840-Q1 Cold Crank Test Pulse
Figure 54. TPS3840-Q1 Load Dump Test Pulse
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10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.5 V and 10 V. TI
recommends an input supply capacitor between the VDD pin and GND pin. This device has a 12-V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 12 V, additional precautions must be taken.
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a minimum 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected
to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
>0.1-µF ceramic capacitor as near as possible to the VDD pin.
• If a CCT capacitor is used, place these components as close as possible to the CT pin. If the CT pin is left
unconnected, make sure to minimize the amount of parasitic capacitance on the pin to
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