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TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
具有 MR 和可编程延迟的 TPS3840 毫微功耗高输入电压监控器
1 特性
•
•
1
•
•
•
•
•
•
•
3 说明
宽工作电压范围：1.5V 至 10V
毫微电源电流：300nA（典型值）、700nA（最大
值）
固定阈值电压 (VIT-)
– 阈值范围为 1.6V 至 4.9V（阶跃为 0.1V）
– 高精度：1%（典型值）、1.5%（最大值）
– 内置的迟滞 (VIT+)
– 1.6V < VIT- ≤ 3.0V = 100mV（典型值）
– 3.1V ≤ VIT- < 4.9V = 200mV（典型值）
快速启动延迟 (tSTRT)：220µs（典型值）、350µs
（最大值）
可编程复位延时时间 (tD)：
– 50µs（无电容器）至 6.2s (10µF)
低电平有效手动复位 (MR)
三种输出拓扑：
– TPS3840DL：漏极开路，低电平有效
(RESET)，需要上拉电阻器
– TPS3840PL：推挽，低电平有效 (RESET)
– TPS3840PH：推挽，高电平有效 (RESET)
宽温度范围：-40°C 至 +125°C
封装：SOT23-5 (DBV)
•
•
•
•
当 VDD 上的电压降至负电压阈值 (VIT-) 以下或手动复位
(MR) 被拉至低逻辑 (VMR_L) 时，会将复位输出信号置
位。当 VDD 升至 VIT- 加迟滞 (VIT+) 以上以及手动复位
悬空或高于 VMR_H 且复位延时时间 (tD) 已过期时，会
将复位信号清除。可以通过在 CT 引脚和地之间连接一
个电容器对复位延时时间进行编程。对于快速复位，可
以将 CT 引脚悬空。
其他 特性：用于 MR 和 VDD 的内置毛刺抑制保护以及
内置迟滞、低漏极开路输出漏电流 (ILKG(OD))。
器件信息(1)
器件型号
封装
TPS3840
2 应用
•
宽输入电压范围允许在不使用外部组件的情况下监控
9V 电压轨或电池，在使用外部电阻器的情况下监控
24V 电压轨。毫微级 Iq 可以在低功耗应用中延长电池
寿命 ， 并在使用外部电阻器时最大限度降低电流消
耗。快速启动延迟允许在系统的其余部分上电之前检测
电压故障，因此可以在危险的启动故障状况下实现最高
的安全性。低上电复位电压 (VPOR) 可防止错误复位、
过早启用或开启下一个器件，并能够在上电和断电期间
正确控制晶体管。
电网基础设施：断路器、智能仪表、其他监控和保
护设备
工厂自动化：现场发送器、PLC。
楼宇自动化：防火安全、烟雾探测器和 HVAC
电子销售点
便携式电池供电型系统
封装尺寸（标称值）
SOT-23 (5) (DBV)
2.90mm × 1.60mm
(1) 有关封装详细信息，请参阅数据表末尾的机械制图附录。
典型应用电路
TPS3840 典型电源电流
0.5
DL49
PL49
PH49
9V
1 µF
0.4
MR
RESET
TPS3840DL49
CT
Vout
DC/DC
GND
EN
5V
IDD (µA)
Vin
VDD
0.3
0.2
0.1
0
1
2
3
4
5
6
VDD (V)
7
8
9
10
IDDv
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSB03
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 器件和文档支持 ..................................................... 29
12.1
12.2
12.3
12.4
12.5
器件命名规则.........................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
29
30
30
30
30
13 机械、封装和可订购信息 ....................................... 30
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (July 2019) to Revision C
•
Page
Changed Device Comparison Table ...................................................................................................................................... 3
Changes from Revision A (May 2019) to Revision B
Page
•
Updated Device Comparison Table ....................................................................................................................................... 3
•
Updated Functional Block Diagram ..................................................................................................................................... 16
•
已更改 equation 5 and 6 ....................................................................................................................................................... 17
•
Updated Application Design #2 ............................................................................................................................................ 22
Changes from Original (December 2018) to Revision A
Page
•
已更改 将数据表从“预告信息”更改为“生产数据”...................................................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
5 Device Comparison Table
Device Comparison Table shows the available (Active) device variants and variants releasing soon (Preview).
Other voltages from 表 3 at the end of datasheet can be sample upon request, please contact TI sales
representative for details.
PART NUMBER
OUTPUT TOPOLOGY
THRESHOLD (Vit-) (V)
HYSTERESIS (mV)
Status
TPS3840DL18
Open-Drain, Active-Low
1.8
100
Active
TPS3840DL20
Open-Drain, Active-Low
2.0
100
Active
TPS3840PL20
Push-Pull, Active-Low
2.0
100
Active
TPS3840DL22
Open-Drain, Active-Low
2.2
100
Active
TPS3840PL25
Push-Pull, Active-Low
2.5
100
Active
TPS3840DL27
Open-Drain, Active-Low
2.7
100
Active
TPS3840PL27
Push-Pull, Active-Low
2.7
100
Active
TPS3840DL28
Open-Drain, Active-Low
2.8
100
Active
TPS3840PL28
Push-Pull, Active-Low
2.8
100
Active
TPS3840DL29
Open-Drain, Active-Low
2.9
100
Active
TPS3840DL30
Open-Drain, Active-Low
3.0
100
Active
TPS3840PL30
Push-Pull, Active-Low
3.0
100
Active
TPS3840PH30
Push-Pull, Active-High
3.0
100
Active
TPS3840PL43
Push-Pull, Active-Low
4.3
200
Active
TPS3840DL45
Open-Drain, Active-Low
4.5
200
Active
TPS3840PL45
Push-Pull, Active-Low
4.5
200
Active
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
TPS3840PL, TPS3840DL Top View
RESET
1
VDD
5
DBV Package
5-Pin SOT-23
TPS3840PH Top View
CT
RESET
1
VDD
2
GND
3
5
CT
4
MR / NC
2
GND
3
4
MR / NC
Not to scale
Not to scale
Pin Functions
PIN
NAME
TPS3840PL,
TPS3840DL
TPS3840PH
I/O
RESET
N/A
1
O
Active-High Output Reset Signal: This pin is driven high when either the MR
pin is driven to a logic low or VDD voltage falls below the negative voltage
threshold (VIT-). RESET remains high (asserted) for the delay time period (tD)
after both MR is floating or above VMR_L and VDD voltage rise above VIT+.
RESET
1
N/A
O
Active-Low Output Reset Signal: This pin is driven logic when either the MR
pin is driven to a logic low or VDD voltage falls below the negative voltage
threshold (VIT-). RESET remains low (asserted) for the delay time period (tD)
after both MR is floating or above VMR_L and VDD voltage rise above VIT+.
VDD
2
2
I
Input Supply Voltage. TPS3840 monitors VDD voltage
GND
3
3
_
Ground
MR / NC
4
4
I
Manual Reset. Pull this pin to a logic low (VMR_L) to assert a reset signal in the
output pin. After the MR pin is left floating or pull to VMR_H the output goes to the
nominal state after the reset delay time(tD) expires. MR can be left floating
when not in use. NC stands for "No Connection" or floating.
CT
5
5
-
Capacitor Time Delay Pin. The CT pin offers a user-programmable delay time.
Connect an external capacitor on this pin to adjust time delay. When not in use
leave pin floating for the smallest fixed time delay.
4
DESCRIPTION
Copyright © 2018–2019, Texas Instruments Incorporated
TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (1)
Voltage
Current
(2)
(3)
MAX
–0.3
12
RESET (TPS3840PL)
–0.3
VDD + 0.3
RESET (TPS3840PH)
–0.3
VDD + 0.3
RESET (TPS3840DL)
–0.3
12
MR (2)
–0.3
12
CT
–0.3
5.5
RESET pin and RESET pin
Temperature (3)
(1)
MIN
VDD
±70
Operating junction temperature, TJ
–40
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
± 2000
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
± 750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Input supply voltage
1.5
10
VRESET, VRESET
RESET pin and RESET pin voltage
0
10
V
IRESET, IRESET
RESET pin and RESET pin current
0
±5
mA
TJ
Junction temperature (free air temperature)
–40
125
°C
0
VDD
V
VMR
(1)
(1)
Manual reset pin voltage
V
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
7.4 Thermal Information
TPS3840
THERMAL METRIC (1)
DBV (SOT23-5)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
187.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
109.2
°C/W
RθJB
Junction-to-board thermal resistance
92.8
°C/W
ψJT
Junction-to-top characterization parameter
35.4
°C/W
ψJB
Junction-to-board characterization parameter
92.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
7.5 Electrical Characteristics
At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF
and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
10
V
VIT-
Negative-going input threshold accuracy (1)
-40°C to 125°C
–1.5
1.5
1
1.5
%
VHYS
Hysteresis on VIT- pin
VIT- = 3.1 V to 4.9 V
175
200
225
mV
VHYS
Hysteresis on VIT- pin
VIT- = 1.6 V to 3.0 V
75
100
125
mV
IDD
Supply current into VDD pin
VDD = 1.5 V < VDD < 10 V
VDD > VIT+ (2)
TA = -40°C to 125°C
300
700
nA
VMR_L
Manual reset logic low input (3)
600
mV
VMR_H
Manual reset logic high input (3)
RMR
Manual reset internal pull-up resistance
RCT
CT pin internal resistance
0.7VDD
V
100
350
500
kΩ
650
kΩ
VOL(max) = 200 mV
IOUT(Sink) = 200 nA
300
mV
1.5 V < VDD < 5 V
VDD < VITIOUT(Sink) = 2 mA
200
mV
TPS3840PL (Push-Pull Active-Low)
VPOR
Power on Reset Voltage (4)
Low level output voltage
VOL
High level output voltage
VOH
1.5 V < VDD < 5 V
VDD > VIT+ (2)
IOUT(Source) = 2 mA
0.8VDD
V
5 V < VDD < 10 V
VDD > VIT+ (2)
IOUT(Source) = 5 mA
0.8VDD
V
TPS3840PH (Push-Pull Active-High)
VPOR
VOL
Power on Reset Voltage (4)
VOH, IOUT(Source) = 500 nA
950
mV
200
mV
Low level output voltage
1.5 V < VDD < 5 V
VDD > VIT+ (2)
IOUT(Sink) = 2 mA
1.5 V < VDD < 5 V
VDD > VIT+ (2)
IOUT(Sink) = 5 mA
200
mV
High level output voltage
VOH
1.5 V < VDD < 5 V, VDD < VIT-,
IOUT(Source) = 2 mA
0.8VDD
V
TPS3840DL(Open-Drain)
VPOR
Low level output voltage
VOL
Ilkg(OD)
(1)
(2)
(3)
(4)
6
Power on Reset Voltage (4)
Open-Drain output leakage current
VOL(max) = 0.2 V
IOUT (Sink) = 5.6 uA
950
mV
1.5 V < VDD < 5 V
VDD < VITIOUT(Sink) = 2 mA
200
mV
90
nA
RESET pin in High Impedance,
VDD = VRESET = 5.5 V
VIT+ < VDD
VIT- threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.
VIT+ = VHYS + VITIf the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR
VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate ≤ 100mV/µs
Copyright © 2018–2019, Texas Instruments Incorporated
TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
7.6 Timing Requirements
At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF
and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted.
Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
tSTRT
Startup Delay (1)
CT pin open
tP_HL
Propagation detect delay for VDD falling
below VIT-
VDD = VIT+ to (VIT-) - 10% (2)
MIN
TYP
MAX
UNIT
100
220
350
µs
15
30
µs
50
µs
CT pin = open
tD
Reset time delay
CT pin = 10 nF
6.2
ms
CT pin = 1 µF
619
ms
10
µs
300
ns
700
ns
tD
ms
5% VIT- overdrive (3)
tGI_VIT-
Glitch immunity VIT-
tMR_PW
MR pin pulse duration to initiate reset
tMR_RES
Propagation delay from MR low to reset
VDD = 4.5 V, MR < VMR_L
Delay from release MR to deasert reset
VDD = 4.5 V,
MR = VMR_L to VMR_H
tMR_tD
(1)
(2)
(3)
When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is release after the startup delay (tSTRT), a
capacitor at CT pin will add tD delay to tSTRT time
tP_HL measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants.
Overdrive % = [(VDD/ VIT-) - 1] × 100%
VIT+
VIT-
VDD
VDD(MIN)
VPOR
tSTRT + tD
RESET
tP_HL
tD
tP_HL
tSTRT + tD
VOH
VOL
(1)
tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then
tD programmed time will be added to the startup time, VDD slew rate = 100 mV / µs.
(2)
Open-Drain timing diagram assumes pull-up resistor is connected to RESET
(3)
RESET output is undefined when VDD is < VPOR
图 3. Timing Diagram TPS3840DL (Open-Drain Active-Low)
版权 © 2018–2019, Texas Instruments Incorporated
7
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
VIT+
VITVDD(MIN)
VDD
VPOR
tP_HL
tSTRT + tD
RESET
tD
tP_HL
tSTRT + tD
VOH
VOL
(4)
tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then
tD programmed time will be added to the startup time. VDD slew rate = 100 mV / µs.
(5)
RESET output is undefined when VDD < VPOR and limited to VOL for VDD slew rate = 100 mV / µs
图 4. Timing Diagram TPS3840PL (Push-Pull Active-Low)
VIT+
VITVDD(MIN)
VDD
VPOR
tSTRT + tD
tP_HL
tD
tP_HL
tSTRT + tD
VOH
RESET
VOL
(6)
tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then
tD programmed time will be added to the total startup time. VDD slew rate = 100 mV / µs.
图 5. Timing Diagram TPS3840PH (Push-Pull Active-High)
8
版权 © 2018–2019, Texas Instruments Incorporated
TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
7.7 Typical Characteristics
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
0.6
0.6
25°C
-40°C
125°C
0.55
0.5
0.5
0.45
0.45
0.4
IDD (µA)
IDD (µA)
0.4
0.35
0.3
0.25
0.3
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
2
3
4
5
6
VDD (V)
7
8
9
10
1
2
3
4
IDDv
5
6
VDD (V)
7
8
9
10
IDDv
图 6. Supply Current vs Supply Voltage for TPS3840DL49
图 7. Supply Current vs Supply Voltage for TPS3840PL49
0.6
0.6
25°C
-40°C
125°C
0.55
0.5
0.5
0.4
DL16
DL29
DL49
0.3
VIT- Accuracy (%)
0.45
0.4
IDD (µA)
0.35
0.25
1
0.35
0.3
0.25
0.2
0.1
0
-0.1
-0.2
0.2
-0.3
0.15
-0.4
0.1
-0.5
-0.6
-40
0.05
1
2
3
4
5
6
VDD (V)
7
8
9
10
0.4
20
40
60
80
Temperature (°C)
100
120
140
VIT_
0.6
PL16
PL28
PL49
0.5
0.4
PH16
PH30
PH49
0.3
VIT- Accuracy (%)
0.3
0.2
0.1
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
-0.6
-40
0
图 9. Negative-going Input Threshold Accuracy over
Temperature for TPS3840DLXX
0.6
0.5
-20
IDDv
图 8. Supply Current vs Supply Voltage for TPS3840PH49
VIT- Accuracy (%)
25°C
-40°C
125°C
0.55
-20
0
20
40
60
80
Temperature (°C)
100
120
140
VIT_
图 10. Negative-going Input Threshold Accuracy over
Temperature for TPS3840PLXX
版权 © 2018–2019, Texas Instruments Incorporated
-0.6
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
VIT_
图 11. Negative-going Input Threshold Accuracy over
Temperature for TPS3840PHXX
9
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接
接下页)
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
20
20
DL16
DL29
DL49
10
5
0
-5
-10
-15
10
5
0
-5
-10
-15
-20
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-20
-40
140
-20
0
20
Vhys
图 12. Input Threshold VIT- Hysteresis Accuracy for
TPS3840DLXX
40
60
80
Temperature (°C)
100
120
140
Vhys
图 13. Input Threshold VIT- Hysteresis Accuracy for
TPS3840PLXX
20
10
PH16
PH30
PH49
15
25°C
-40°C
125°C
9
8
10
7
5
VRESET (V)
VHYS Accuracy (%)
PL16
PL28
PL49
15
VHYS Accuracy (%)
VHYS Accuracy (%)
15
0
-5
6
5
4
3
2
-10
1
-15
0
-20
-40
-1
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0
图 14. Input Threshold VIT- Hysteresis Accuracy for
TPS3840PHXX
3
4
5
6
VDD (V)
7
8
9
10
VRES
5.5
25°C
-40°C
125°C
9
8
25°C
-40°C
125°C
5
4.5
7
4
6
3.5
VRESET (V)
VRESET (V)
2
图 15. Output Voltage vs Input Voltage for TPS3840DL49
10
5
4
3
2
3
2.5
2
1.5
1
1
0
0.5
-1
0
0
1
2
3
4
5
VDD (V)
6
7
8
9
10
VRES
图 16. Output Voltage vs Input Voltage for TPS3840PL49
10
1
Vhys
0
1
2
3
4
5
6
VDD (V)
7
8
9
10
VRES
图 17. Output Voltage vs Input Voltage for TPS3840PH49
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TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
Typical Characteristics (接
接下页)
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
0.055
140
25°C
-40°C
125°C
120
25°C
-40°C
125°C
0.05
0.045
100
VOL (V)
0.04
VOL (V)
80
60
0.03
40
0.025
20
0.02
0.015
1.5
0
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
2.5
3
3.5
VDD (V)
4
4.5
5
VOLv
图 19. Low Level Output Voltage vs VDD for TPS3840DL49
0.055
140
25°C
-40°C
125°C
120
100
0.045
80
0.04
60
0.035
40
0.03
20
0.025
0
0.02
0.015
1.5
-20
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
60
VOL (V)
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
VOL_
图 22. Low Level Output Voltage vs IRESET for TPS3840PH49
版权 © 2018–2019, Texas Instruments Incorporated
2.5
3
3.5
VDD (V)
4
4.5
5
VOLv
图 21. Low Level Output Voltage vs VDD for TPS3840PL49
25°C
-40°C
125°C
70
2
VOL_
图 20. Low Level Output Voltage vs IRESET for TPS3840PL49
80
25°C
-40°C
125°C
0.05
VOL (V)
VOL (V)
2
VOL_
图 18. Low Level Output Voltage vs IRESET for TPS3840DL49
VOL (V)
0.035
0.09
0.085
0.08
0.075
0.07
0.065
0.06
0.055
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
25°C
-40°C
125°C
5
5.5
6
6.5
7
7.5
8
VDD (V)
8.5
9
9.5
10 10.5
VOLv
图 23. Low Level Output Voltage vs VDD for TPS3840PH49
11
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接
接下页)
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
5
10
25°C
-40°C
125°C
9.975
9.95
4.5
25°C
-40°C
125°C
4
9.9
VOH (V)
VOH (V)
9.925
9.875
9.85
3.5
3
2.5
9.825
2
9.8
1.5
9.775
1
1.5
9.75
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
25°C
-40°C
125°C
1.55
4.5
4
4.5
5
VOHv
25°C
-40°C
125°C
4
VOH (V)
1.5
VOH (V)
3
3.5
VDD (V)
5
1.6
1.45
1.4
3.5
3
2.5
1.35
2
1.3
1.5
1
1.5
1.25
0
0.5
1
1.5
2
2.5
3
IRESET (mA)
3.5
4
4.5
5
2.25
3
3.5
VDD (V)
4
4.5
5
VOHv
2.75
DL16
DL29
DL49
2.5
2.25
V_MR_L (V)
2
1.75
1.5
1.75
1.5
1.25
1
1
0.75
0.75
-20
0
20
40
60
80
Temperature (°C)
100
120
140
MR_L
图 28. Manual Reset Logic Low Voltage Threshold over
Temperature for TPS3840DLXX
PL16
PL28
PL49
2
1.25
0.5
-40
2.5
图 27. High Level Output Voltage over Temperature for
TPS3840PH49
2.75
2.5
2
VOH_
图 26. High Level Output Voltage vs IRESET for TPS3840PH49
V_MR_L (V)
2.5
图 25. High Level Output Voltage over Temperature for
TPS3840PL49
图 24. High Level Output Voltage vs IRESET for TPS3840PL49
12
2
VOH_
0.5
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
MR_L
图 29. Manual Reset Logic Low Voltage Threshold over
Temperature for TPS3840PLXX
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TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
Typical Characteristics (接
接下页)
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
2.75
2.75
2.5
2.25
PH16
PH230
PH49
2.5
2.25
V_MR_H (V)
V_MR_L (V)
2
1.75
1.5
1.25
-20
0
20
40
60
80
Temperature (°C)
100
120
0
20
40
60
80
Temperature (°C)
100
120
140
MR_H
图 31. Manual Reset Logic High Voltage Threshold over
Temperature for TPS3840DLXX
2.75
PL16
PL28
PL49
2.5
PH16
PH30
PH49
2.25
V_MR_H (V)
2.25
2
1.75
1.5
2
1.75
1.5
1.25
1.25
1
1
0.75
-40
-20
MR_L
2.75
V_MR_H (V)
1.5
0.75
-40
140
图 30. Manual Reset Logic Low Voltage Threshold over
Temperature for TPS3840PHXX
-20
0
20
40
60
80
Temperature (°C)
100
120
0.75
-40
140
-20
0
20
MR_H
图 32. Manual Reset Logic High Voltage Threshold over
Temperature for TPS3840PLXX
40
60
80
Temperature (°C)
100
120
140
MR_H
图 33. Manual Reset Logic High Voltage Threshold over
Temperature for TPS3840PHXX
22
478
25°C
-40°C
125°C
21
20
DL49
PL49
PH49
476
474
19
472
R_CT (kohm)
Glitch Immunity (µs)
1.75
1
0.75
2.5
2
1.25
1
0.5
-40
DL16
DL29
DL49
18
17
16
470
468
466
15
464
14
462
13
460
12
5
10
15
20
25
30
35
Overdrive (%)
40
45
50
Glit
图 34. Glitch Immunity on VIT- vs Overdrive (Data Taken with
TPS3840PL28)
版权 © 2018–2019, Texas Instruments Incorporated
458
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
RCTv
图 35. CT Pin Internal Resistance over Temperature
13
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接
接下页)
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
15
215
210
t_D no Capacitor (µs)
205
t_STRT (µs)
DL49
PL49
PH49
DL49
PL49
PH49
200
195
190
185
180
12
9
6
175
170
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
3
-40
140
图 36. Startup Delay over Temperature
500
3500
t_D (ms)
20
40
60
80
Temperature (°C)
100
120
140
Dela
600
25°C
-40°C
125°C
tD with Capacitor (ms)
4000
0
图 37. Reset Time Delay with No Capacitor over
Temperature
5000
4500
-20
Star
3000
2500
2000
1500
1000
25°C
-40°C
125°C
400
300
200
100
500
0
0.01 0.02
0.05
0.1
0.2 0.3 0.5
Capacitor (µF)
1
2
0
0.01
3 4 5 67 10
图 38. Reset Time Delay vs Capacitor Value (Data Taken
with TPS3840PL16)
0.3
0.5 0.7
1
Dela
17.25
25°C
-40°C
125°C
4.5
4
DL49
PL49
PH49
17
16.75
16.5
3.5
t_P_HL (µs)
tD with Capacitor (s)
0.050.07 0.1
0.2
Capacitor Value (µF)
图 39. Reset Time Delay vs Small Capacitor Values (Data
Taken with TPS3840PL16)
5
3
2.5
2
16.25
16
15.75
15.5
1.5
15.25
1
15
0.5
1
2
3
4
5
Capacitor Value (µF)
6
7
8 9 10
Dela
图 40. Reset Time Delay vs Large Capacitor Values (Data
Taken with TPS3840PL16)
14
0.02 0.03
Dela
14.75
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
TPHL
图 41. Propagation Detect Time Delay for VDD Falling Below
VIT- (High-to-Low) over Temperature
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TPS3840
www.ti.com.cn
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
Typical Characteristics (接
接下页)
Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpullup = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
465
460
3.45
450
445
440
435
430
3.4
3.35
3.3
3.25
425
3.2
420
3.15
415
-40
DL49
PL49
PH49
3.5
t_MR_ tD (µs)
T_MR_RES (ns)
455
3.55
DL49
PL49
PH49
-20
0
20
40
60
80
Temperature (°C)
100
120
140
MR_r
图 42. Propagation Time Delay from MR Asserted to Reset
over Temperature
版权 © 2018–2019, Texas Instruments Incorporated
3.1
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
MRde
图 43. Propagation Time Delay from MR Release to
Deasserted Reset over Temperature
15
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS3840 is a family of wide VDD and nano-quiescent current voltage detectors with fixed threshold voltage.
TPS3840 features include programable reset time delay using external capacitor, active-low manual reset, 1%
typical monitor threshold accuracy with hysteresis and glitch immunity.
Fixed negative threshold voltages (VIT-) can be factory set from 1.6 V to 4.9 V (see the Device Comparison Table
for available options). TPS3840 is available in SOT-23 5 pin industry standard package.
8.2 Functional Block Diagram
VDD
Push-pull variants
RMR
VDD
VDD
MR / NC
RCT
VDD
Voltage
Divider
RESET
(PPH)
RESET
(PPL, DL)
+
±
VREF
GND
CT / NC
Copyright © 2019, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator to indicate when VDD falls below the fixed threshold voltage.
VDD also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other
control logic blocks. Good design practice involve placing a 0.1 uF to 1 uF bypass capacitor at VDD input for
noisy applications to ensure enough charge is available for the device to power up correctly.
16
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TPS3840
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ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
Feature Description (接
接下页)
8.3.1.1 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis
(VHYS) the output reset is deasserted after tD delay.
Hystersis Width
Hystersis Width
RESET
RESET
VIT-
VIT-
VIT+
VIT+
VDD
VDD
图 44. Hysteresis Diagram
8.3.1.2 VDD Transient Immunity
The TPS3840 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends on
both pulse duration and overdrive. Overdrive is defined by how much VDD deviates from the specified threshold.
Threshold overdrive is calculated as a percent of the threshold in question, as shown in 公式 1.
Overdrive = | (VDD / VIT- – 1) × 100% |
(1)
VDD
VIT+
VITOverdrive
Pulse
Duration
图 45. Overdrive vs Pulse Duration
8.3.2 User-Programmable Reset Time Delay
The reset time delay can be set to a minimum value of 50 µs by leaving the CT pin floating, or a maximum value
of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmed
by connecting a capacitor no larger than 10 µF between CT pin and GND.
The relationship between external capacitor (CCT_EXT) in µF at CT pin and the time delay (tD) in seconds is given
by 公式 2.
tD = -ln (0.29) x RCT x CCT_EXT + tD (no cap)
公式 2 is simplified to 公式 3 by plugging RCT and tD(no
(2)
cap)
given in Electrical Characteristics section:
tD = 618937 x CCT_EXT + 50 µs
(3)
公式 4 solves for external capacitor value (CCT_EXT) in units of µF where tD is in units of seconds
CCT_EXT = (tD- 50 µs) ÷ 618937
(4)
The reset delay varies according to three variables: the external capacitor variance (CCT), CT pin internal
resistance (RCT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum
variance due to the constant is shown in Equation 5 and Equation 6.
tD (minimum) = -ln (0.36) x RCT (min) x CCT (min) + tD (no cap, min)
tD (maximum) = -ln (0.26) x RCT (max) x CCT (max) + tD (no cap, max)
版权 © 2018–2019, Texas Instruments Incorporated
(5)
(6)
17
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
Feature Description (接
接下页)
The recommended maximum delay capacitor for the TPS3840 is limited to 10 µF as this ensures there is enough
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before
the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and
the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has
enough time to fully discharge during the duration of the voltage fault.
8.3.3 Manual Reset (MR) Input
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR
with pulse duration longer than tMR_RES will causes reset output to assert. After MR returns to a logic high (VMR_H)
and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than
VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to
either VDD or GND. VMR should not be higher than VDD voltage.
VDD
VIT+
VIT-
RESET
VIT+
VHYS
VHYS
VITtP_HL
tD
tMR_tD
tMR_RES
MR
VMR_H
VMR_L
Reset not asserted
tMR_PW
Pulse width less than tMR_PW
图 46. Timing Diagram MR and RESET (TPS3840DL)
8.3.4 Output Logic
8.3.4.1 RESET Output, Active-Low
RESET (Active-Low) applies to TPS3840DL (Open-Drain) and TPS3840PL (Push-Pull) hence the "L" in the
device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and the
MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then
RESET is asserted.
When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for the
specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high
voltage (VOH).
The TPS3840DL (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to hold
RESET pin high. Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up
to any voltage up to 10 V independent of the VDD voltage. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual VOL, the
output capacitive loading, and the output leakage current (ILKG(OD)).
The Push-Pull variants (TPS3840PL and TPS3840PH), denoted with "P" in the device name, does not require a
pull-up resistor
18
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TPS3840
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ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
Feature Description (接
接下页)
8.3.4.2 RESET Output, Active-High
RESET (active-high), denoted with no bar above the pin label, applies only to TPS3840PH push-pull active-high
version. RESET remains low (deasserted) as long as VDD is above the threshold (VIT-) and the manual reset
signal (MR) is logic high or floating. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then
RESET is asserted driving the RESET pin to high voltage (VOH).
When MR is again logic high and VDD is above VIT+ the delay circuit will hold RESET high for the specified reset
time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to low voltage (VOL )
8.4 Device Functional Modes
表 1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic low is
represented by "L".
表 1. Truth Table
(1)
VDD
MR
RESET
RESET
VDD < VPOR
Ignored
Undefined
Undefined
VPOR < VDD < VIT- (1)
Ignored
H
L
VDD ≥ VIT-
L
H
L
VDD ≥ VIT-
H
L
H
VDD ≥ VIT-
Floating
L
H
When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and output reset is held asserted until VDD falls below VPOR.
8.4.1 Normal Operation (VDD > VDD(min))
When VDD is greater than VDD(min), the reset signal is determined by the voltage on the VDD pin with respect to
the trip point (VIT-) and the logic state of MR.
• MR high: the reset signal corresponds to VDD with respect to the threshold voltage.
• MR low: in this mode, the reset is asserted regardless of the threshold voltage.
8.4.2
VDD Between VPOR and VDD(min)
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage (VPOR),
the reset signal is asserted.
8.4.3 Below Power-On-Reset (VDD < VPOR)
When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the
asserted output low or high and reset voltage level is undefined.
版权 © 2018–2019, Texas Instruments Incorporated
19
TPS3840
ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
A typical application for the TPS3840 is voltage rail monitoring and power-up sequencing as shown in 图 47. The
TPS3840 can be used to monitor any rail above 1.6 V. In this design application, two TPS3840 devices monitor
two separate voltage rails and sequences the rails upon power-up. The TPS3840PL30 is used to monitor the 3.3V main power rail and the TPS3840DL16 is used to monitor the 1.8-V rail provided by the LDO for other system
peripherals. The RESET output of the TPS3840PL30 is connected to the ENABLE input of the LDO. A reset
event is initiated on either voltage supervisor when the VDD voltage is less than VIT- or when MR is driven low by
an external source.
LDO
VDD
EN
3.3V
1 µF
1.8 V
1 µF
10NŸ
VDD
MR
MR
TPS3840PL30
CT
GND
VCORE
Microcontroller
VDD
RESET
VI/O
RESET
RESET
TPS3840DL16
NC
CT
GND
0.047µF
图 47. TPS3840 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram
20
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TPS3840
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ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
Typical Application (接
接下页)
9.2.1.1 Design Requirements
This design requires voltage supervision on two separate rails: 3.3-V and 1.8-V rails. The voltage rail needs to
sequence upon power up with the 3.3-V rail coming up first followed by the 1.8-V rail at least 25 ms after.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Two Rail Voltage Supervision
Monitor 3.3-V and 1.8-V rails
Two TPS3840 devices provide voltage monitoring
with 1% accuracy with device options available in
0.1 V variations
Voltage Rail Sequencing
Power up the 3.3-V rail first followed by 1.8-V rail
25 ms after
The CT capacitor on TPS38240PL28 is set to
0.047 µF for a reset time delay of 29 ms typical
Output logic voltage
3.3-V Open-Drain
3.3-V Open-Drain
Maximum device current
consumption
1 µA
Each TPS3840 requires 350 nA typical
9.2.1.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS3840 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V
increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to
trigger determines the correct voltage supervisor variant to choose. In this example, the first TPS3840 triggers
when the 3.3-V rail falls to 3.0 V. The second TPS3840 triggers a reset when the 1.8-V rail falls to 1.6 V. The
secondary constraint for this application is the reset time delay that must be at least 25 ms to allow the
microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.8-V rail is
enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance. For
applications with ambient temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and
solving for CCT in 公式 2. Solving 公式 2 for 25 ms gives a minimum capacitor value of 0.04 µF which is rounded
up to a standard value 0.047 µF to account for capacitor tolerance.
A 1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor
is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5
mA limit found in the Recommended Operating Conditions: RPull-up = VPull-up ÷ 5 mA. For this design, a standard
10-kΩ pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the
pull-up resistor, the higher VOL. The MR pin can be connected to an external signal if desired or left floating if not
used due to the internal pull-up resistor to VDD.
9.2.1.3 Application Curves
VDD
30ms delay from VDD (3.3V) to LDO Enable set by 0.047µF on CT of TPS3840PL30
RESET
(LDO Enable)
VOUT (LDO)
Negligible delay from LDO Enable to 1.8V VOUT
图 48. Startup Sequence Highlighting the Delay Between 3.3V and 1.8V Rails
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9.2.2 Design 2: Battery Voltage and Temperature Monitor
A typical application for the TPS3840 is battery voltage and temperature monitoring. The TPS3840 is offered in
active-low or active-high output topologies and can operate above or below the voltage threshold meaning the
device can be used as an undervoltage monitor as shown in 图 49 or overvoltage monitor as shown in 图 50.
The TPS3840 can be used to monitor any rail above 1.6 V. In this design application, one TPS3840DL30
monitors the 3.3-V battery voltage rail and triggers an active-low reset fault condition if the battery voltage falls
below the 3-V threshold. For overvoltage monitoring, another TPS3840DL30 monitors a 2.8-V battery and
triggers a logic high at the 3-V threshold plus 100 mV hysteresis so at 3.1 V. Both applications monitor the
battery temperature using TMP303, a push-pull, active-high temperature switch. A temperature fault is triggered if
the battery temperature falls outside of a defined window temperature range set by the TMP303 variant chosen.
3.3V
10Ÿ
VCORE
VS
Microcontroller
VDD
TMP303
RESET
MR
SOH
FAULT
TPS3840DL30
HYSTSET0
OUT
HYSTSET1
GND
CT
GND
10µF
图 49. Low Battery Voltage and Window Temperature Monitoring Solution
2.8V
100k
Battery Charger
VDD
NC
MR
VS
RESET
TPS3840DL30
CT
10µF
GND
TMP303
OFF
ON
SOH
HYSTSET0
OUT
HYSTSET1
GND
图 50. Overvoltage and Window Temperature Monitoring Solution
9.2.2.1 Design Requirements
This design requires voltage and temperature supervision on a battery voltage rail and the requirements may
differ depending on if undervoltage or overvoltage monitoring is required. For this design, both requirements are
considered to show the flexibility of the TPS3840 device. The first application example shown in 图 49 uses
TPS3840DL30, an open-drain active-low voltage supervisor to monitoring undervoltage and TMP303, a push-pull
active-high window temperature switch to monitor under and over temperature. For the undervoltage application,
the TPS3840DL30 is operating in the inactive logic high region so an overvoltage fault occurs when the battery
voltage falls below VIT- = 3.0 V or when the battery temperature is outside the range from 0°C to 60°C. The
second application example uses TPS3840DL30 operating in the active-low region to monitor overvoltage and
TMP303 to monitor under and over temperature. For the overvoltage requirement, the fault occurs when the
battery voltage rises above 3.1 V or when the battery temperature is outside the range from 0°C to 60°C.
22
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ZHCSJ38C – DECEMBER 2018 – REVISED AUGUST 2019
PARAMETER
DESIGN REQUIREMENT
Monitor 3.3-V battery for undervoltage condition
Battery Voltage Supervision
Battery Temperature Supervision
Monitor 2.8-V battery for overvoltage condition
TMP303A monitors temperature within 0°C to 60°C
Monitor battery temperature between 0°C and 60°C
with 1°C resolution. Note this is a push-pull, activewith 1°C resolution for undervoltage design
high output device.
Undervoltage: Active-Low, Open-Drain
Output Topology
DESIGN RESULT
TPS3840 provides voltage monitoring with 1%
accuracy with device options available in 0.1 V
variations. TPS3840DL30 triggers a reset when
VDD falls below 3 V. TPS3840PH30 triggers a
reset when VDD rises above 3 V plus hysteresis
setting the overvoltage threshold to 3.1 V.
Overvoltage: Active-High, Push-Pull
TPS3840 is offered in Active-Low Open-drain,
Active-Low Push-Pull, and Active-High Push-Pull
topologies
Maximum device current
consumption
10 µA
TPS3840 requires 350 nA (typical) and TMP303
requires 3.5 µA (typical)
Delay when returning from fault
condition
Delay of at least 6 seconds when returning from
the fault to prevent operation in fault conditions
CCT = 10 µF sets 6.18 second delay
9.2.2.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the battery supply voltage.
The TPS3840 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V increments. Depending
on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the
correct voltage supervisor variant to choose. In this design example, the TPS3840DL30 is chosen for both the
undervoltage and overvoltage monitoring. For undervoltage monitoring, the undervoltage fault occurs when the
3.3-V rail falls to 3 V and for the overvoltage monitoring, the overvoltage fault occurs when the 2.8-V rail rises
above the 3-V threshold (VIT-) plus 100mV hysteresis (VHYS). It's important to note that in the undervoltage
application, the TPS3840 RESET output is logic high during normal conditions whereas in the overvoltage
application, the TPS3840 RESET output is logic low during normal conditions which is the reason a single device
can be used for either type of monitoring depending on the logic required at the output. The opposite RESET
output logic is offered in the push-pull, active-high device TPS3840PH noted with the RESET output. The
secondary constraint for this application is the battery temperature monitoring accomplished by the TMP303A.
Typical Lithium Ion battery discharge temperature range is 0°C to 60°C which is accomplished by the 'A' variante
of TMP303A. The TMP303A triggers a fault to the MR pin of the TPS3840 or directly to the battery charger
whenever the temperature is outside of the temperature range. The TMP303A offers 1°C resolution to meet the
high resolution requirement. Because the undervoltage monitor design uses TMP303A, a push-pull active-high
output device, an additional inverter is required before the MR pin because during normal operation, the TMP303
output is low but the MR pin must be logic high during normal operation. If using two TPS3840 devices for both
undervoltage and overvoltage monitoring on the same battery, only one single temperature monitoring device is
required. The last constraint is the RESET/RESET time delay set by CCT. For applications with ambient
temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and solving for CCT in 公式 2. By
choosing a standard 10% capacitor value of 10 µF ensures the RESET/RESET time delay will be at least 6
seconds. Note: active-low devices use the output label RESET and active-high devices use the output label
RESET.
A 0.1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up
resistor is only required for the Open-Drain device variants and is calculated to maintain the RESET current
within the ±5 mA limit found in the Recommended Operating Conditions: RPull-up = VPull-up ÷ 5 mA. For this design,
a 1-MΩ pull-up resistor is selected to minimize current draw when RESET is asserted and to prevent the battery
from unnecessary discharge. Keep in mind the lowering the pull-up resistor, increases VOL and IOUT. The MR pin
is used for a second fault condition provided by the temperature switch.
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9.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
A typical application for the TPS3840 is a fast startup undervoltage supervisor that operates with an input power
supply higher than the recommended maximum of 10 V through the use of a resistor divider at the input as
shown in 图 51. The TPS3840 can be used to monitor any rail above 1.6 V and only requires maximum 350 µs
upon startup before the device can begin monitoring a voltage. In this design application, a TPS3840 monitors a
12-V rail and triggers a reset fault condition if the voltage rail voltage drops below 10 V using a TPS3840 device
with VIT- of 4.9 V. This design also accounts for a wide input range in the case the 12-V rail rises higher, the
resistor divider is set so that the voltage at the VDD pin never exceeds 10 V. The resistor values must not be so
large that the external resistor divider affects the accuracy or operation of the device. TPS3840 is available in
both active-low and active-high topologies providing the flexibility to monitor undervoltage or overvoltage with
either output logic. This design uses the active-low, open-drain TPS3840DL49 variant so that when the
undervoltage condition occurs, that is when the voltage at VDD pin falls below the voltage threshold set by the
external resistor divider, the output transitions to logic-low and can be used to flag an undervoltage condition or
used to connect to the ENABLE of the next device to shut it off as a logic low on an ENABLE pin typically
disables the device. In this design, the output of the TPS3840 simply connects to a MCU to flag an undervoltage
condition.
3.3V
12V
10.5NŸ
125NŸ
VCORE
10NŸ
Microcontroller
VDD
NC
MR
RESET
RESET
TPS3840DL49
CT
GND
0.33µF
图 51. Fast Start Undervoltage Supervisor with Level-shifted Input
9.2.3.1 Design Requirements
This design requires voltage supervision on a 12-V power supply voltage rail with possibility of the 12-V rail rising
up as high as 18 V. The undervoltage fault occurs when the power supply voltage drops below 10 V.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Power Rail Voltage Supervision
Monitor 12-V power supply for undervoltage
condition, trigger a undervoltage fault at 10 V.
TPS3840 provides voltage monitoring with 1%
accuracy with device options available in 0.1 V
variations. The TPS3840 monitors voltages above
1.6 V.
Maximum Input Power
Operate with power supply input up to 18 V.
The TPS3840 limits VDD to 10 V but can monitor
voltages higher than the maximum VDD voltage
with the use of an external resistor divider.
Output logic voltage
3.3-V Open-Drain
3.3-V Open-Drain
Maximum device current
consumption
35 µA when power supply is at 18 V maximum
TPS3840 requires 350 nA (typical) and the external
resistor divider will also consume current. There is
a tradeoff between current consumption and
voltage monitor accuracy but generally set the
resistor divider to consume 100 times current into
VDD.
Voltage Monitor Accuracy
Typical voltage monitor accuracy of 2.5%. This
allows the voltage threshold to range between
11.75 V and 10.25 V.
The TPS3840 has 1% typical voltage monitor
accuracy. By decreasing the ratio of resistor
values, the resistor divider will consume more
current but the accuracy will increase. The resistor
tolerance also needs to be accounted for.
Delay when returning from fault
condition
RESET delay of at least 200 ms when returning
from a undervoltage fault.
CCT = 0.33 µF sets 204 ms delay
24
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9.2.3.2 Detailed Design Procedure
The primary constraint for this application is monitoring a 12-V rail while preventing the VDD pin on TPS3840
from exceeding the recommended maximum of 10 V. This is accomplished by sizing the resistor divider so that
when the 12-V rail drops to 10 V, the VDD pin for TPS3840 will be at 4.9 V which is the VIT- threshold for
triggering a undervoltage condition for TPS3840DL49 as shown in 公式 7.
Vrail_trigger = VIT- x (Rbottom ÷ (Rtop + Rbottom))
(7)
where Vrail_trigger is the trigger voltage of the rail being monitored, VIT- is the falling threshold on the VDD pin of
TPS3840, and Rtop and Rbottom are the top and bottom resistors of the external resistor divider. VIT- is fixed per
device variant and is 4.9 V for TPS3840DL49. Substituting in the values from 图 51, the undervoltage trigger
threshold for the rail is set to 10.045 V.
Since the undervoltage trigger of 10 V on the rail corresponds to 4.9 V undervoltage threshold trigger of the
TPS3840 device, there is plenty of room for the rail to rise up while maintaining less than 10 V on the VDD pin of
the TPS3840. 公式 8 shows the maximum rail voltage that still meets the 10 V maximum at the VDD pin for
TPS3840.
Vrail_max = 10 x (10,000 ÷ (10,500 + 10,000)) = 20.5 V
(8)
This means the monitored voltage rail can go as high as 20.5 V and still not violate the recommended maximum
for the VDD pin on TPS3840. This is useful when monitoring a voltage rail that has a wide range that may go
much higher than the nominal rail voltage such as in this case with the specification that the 12-V rail can go as
high as 18 V. Notice that the resistor values chosen are less than 100kΩ to preserve the accuracy set by the
internal resistor divider. Good design practice recommends using a 0.1-µF capacitor on the VDD pin and this
capacitance may need to increase when using an external resistor divider.
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TPS3840
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9.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
A typical application for the TPS3840 is to monitor a voltage rail and switch the power to a back-up battery if the
main supply is in undervoltage condition. Because systems that utilize a back-up battery tend to require low
quiescent current, TPS3840 serves as the perfect solution as this device only requires 350 nA typically. The
TPS3840 monitors the main power rail via the VDD pin and when the main power rail falls, the RESET output
asserts causing a switch to close on the back-up battery rail. The diodes provide an ORing logic function to
prevent reverse leakage and to allow either rail to connect to the output depending on the status of the main
voltage rail.
5V
System
Output
+
±
3.3V
Vbat
VDD
NC
MR
RESET
TPS3840PL30
NC
CT
GND
图 52. Voltage Monitor with Back-up Battery Switchover Solution
9.2.4.1 Design Requirements
This design requires voltage supervision on a 5-V main supply voltage rail and when the main rail fails, switch to
a back-up battery supply to prevent complete power loss in the system. The System Output must remain above
1.8 V even when the main supply completely fails. The design requires less than 500 nA of total current
consumption and must prevent battery leakage when the battery is not being used. When the system is using the
back-up battery and the main supply voltage rail comes back up, the system must switch back to the main power
supply in less than 100 µs to save battery power.
PARAMETER
DESIGN REQUIREMENT
Monitor 5-V main supply for undervoltage
Main Supply Voltage Supervision condition. When main supply drops below 3 V,
switch to back-up battery.
DESIGN RESULT
TPS3840 provides voltage monitoring with 1%
accuracy with device options available in 0.1 V
variations. This design uses TPS3840PL30 to set
the undervoltage trigger at 3 V.
Batck-up Battery Switchover
When undervoltage occurs on the main supply
voltage rail, switch to the back-up batter.
When undervoltage occurs on the main supply rail,
the PMOS switch closes allowing the back-up
battery to connect to the system output. The diodes
prevent reverse leakage and allow either power
supply to connect to the system output.
Main Power Supply to Back-up
Battery Switch Response Time
No more than 50 µs to switch to the back-up
battery when the main power supply falls to
undervoltage condition.
TPS3840 provides a propagation delay for VDD
falling below the undervoltage threshold (tP_HL) of
50 µs maximum to meet the requirement.
Back-up Battery to Main Power
Supply Switch Back Response
Time
Less than 100 µs when switching from back-up
battery back to main power supply when
undervoltage condition is removed.
By leaving MR disconnected, the RESET delay is
set to a maximum of 50 µs to meet the
requirement.
Device Current Consumption
500 nA
TPS3840 requires 350 nA (typical)
System Output must remain above 1.8 V in all
cases
When the main 5-V rail is connected, the System
Output will be the rail voltage minus a diode
voltage drop so at least 3 V - 0.7 V ~ 2.3 V. When
the voltage rail drops below 3 V, the back-up
battery switches into the system and the System
Output becomes the battery voltage minus a diode
voltage drop so 3.3 V - 0.7 V ~ 2.6 V. The
threshold at which the battery switches into the
system directly depends on the TPS3840 variant
chosen.
System Output Voltage
26
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9.2.4.2 Detailed Design Procedure
The primary constraints for this application are choosing the correct device variant for the monitored voltage and
deciding the preferred solution to switch the back-up battery in and out of the system. For this design, the
TPS3840PL30 provides an active-low, push-pull output topology that turns on the PFET when the 5-V rail
monitored by VDD drops to 3.0 V. The diodes logically OR the power supply with the back-up battery and
prevents reverse current leakage. Using this solution, the System Output remains above 1.8 V in all
circumstances unless both the 5-V rail and back-up battery fail. The System Output voltage will follow the 5-V rail
minus a diode drop until the 5-V rail drops to 3 V then the back-up battery switches into the system providing 3.3
V minus a diode drop to the System Output. When the 5-V rail comes back above 3.1 V accounting for
hysteresis, the PFET turns off to disconnect the back-up battery from the system. Since this design disconnects
the battery when not being used, this solution maximizes battery life.
9.2.5 Application Curve: TPS3840EVM
These application curves are taken with the TPS3840EVM. Please see the TPS3840EVM User Guide for more
information.
VDD
VDD
Reset Delay (tD) = 5.8 ms
Reset Delay (tD) = 22 µs
RESET
RESET
图 53. TPS3840EVM RESET Time Delay (tD) with No
Capacitor
图 54. TPS3840EVM RESET Time Delay (tD) with
0.01-µF Capacitor
VDD
Reset Delay (tD)= 654 ms
RESET
图 55. TPS3840EVM RESET Time Delay (tD) with 1-µF Capacitor
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www.ti.com.cn
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.5 V and 10 V. TI
recommends an input supply capacitor between the VDD pin and GND pin. This device has a 12-V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 12 V, additional precautions must be taken.
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a minimum 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected
to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
>0.1-µF ceramic capacitor as near as possible to the VDD pin.
• If a CCT capacitor is used, place these components as close as possible to the CT pin. If the CT pin is left
unconnected, make sure to minimize the amount of parasitic capacitance on the pin to
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