TPS3850-Q1
SBVS264B – JANUARY 2017 – REVISED SEPTEMBER 2021
TPS3850-Q1 Precision Voltage Supervisor with Programmable Window Watchdog
Timer
1 Features
3 Description
•
The TPS3850-Q1 combines a precision voltage
supervisor with a programmable window watchdog
timer. The TPS3850-Q1 window comparator achieves
0.8% accuracy (–40°C to +125°C) for both
overvoltage (VIT+(OV)) and undervoltage (VIT–(UV))
thresholds on the SENSE pin. The TPS3850-Q1
also includes accurate hysteresis on both thresholds,
making the device ideal for use with tight tolerance
systems. The supervisor RESET delay can be set
by factory-programmed default delay settings, or
programmed by an external capacitor. The factoryprogrammed RESET delay features a 9.5% accuracy,
high-precision delay timing.
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
Functional Safety-capable
– Documentation available to aid functional safety
system design
Input voltage range: VDD = 1.6 V to 6.5 V
0.8% Voltage threshold accuracy (Maximum)
Low supply current: IDD = 10 µA (typical)
User-programmable watchdog timeout
User-programmable reset delay
Factory programmed precision watchdog and reset
timers
Open-drain outputs
Precision over- and undervoltage monitoring:
– Supports common rails from 0.9 V to 5.0 V
– 4% and 7% Fault windows available
– 0.5% Hysteresis
Watchdog disable feature
Available in a small 3-mm × 3-mm, 10-Pin VSON
package
2 Applications
On-board (OBC) & wireless charger
Driver monitoring
Digital cockpit processing unit
Adas domain controller
Automotive telematics control unit
The TPS3850-Q1 is available in a small 3.00-mm ×
3.00-mm, 10-pin VSON package. The TPS3850-Q1
features wettable flanks for easy optical inspection.
Device Information
PACKAGE (1)
PART NUMBER
TPS3850-Q1
(1)
BODY SIZE (NOM)
VSON (10)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
0.5
1.8V
Unit 1
Unit 2
1.2V
VCORE
TPS3850-Q1
SENSE
VDD
SET1
RESET
SET0
WDO
CRST
WDI
CWD
GND
Unit 3
Unit 4
Unit 5
Average
0.3
VI/O
Microcontroller
Accuracy (%)
•
•
•
•
•
The TPS3850-Q1 includes a programmable window
watchdog timer for a wide variety of applications. The
dedicated watchdog output ( WDO) enables increased
resolution to help determine the nature of fault
conditions. The window watchdog timeouts can be
set by factory-programmed default delay settings, or
programmed by an external capacitor. The watchdog
can be disabled via logic pins to avoid undesired
watchdog timeouts during the development process.
RESET
NMI
GPIO
0.1
-0.1
GND
-0.3
Copyright © 2016, Texas Instruments Incorporated
Typical Application Circuit
-0.5
-50
-25
0
25
50
Temperature (qC)
75
100
125
Overvoltage Threshold (VIT+(OV)) Accuracy vs
Temperature
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3850-Q1
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SBVS264B – JANUARY 2017 – REVISED SEPTEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Timing Diagrams......................................................... 7
6.8 Typical Characteristics.............................................. 10
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagrams....................................... 13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................21
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 27
9 Power Supply Recommendations................................33
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Documentation Support.......................................... 35
11.3 Receiving Notification of Documentation Updates.. 35
11.4 Support Resources................................................. 35
11.5 Trademarks............................................................. 36
11.6 Electrostatic Discharge Caution.............................. 36
11.7 Glossary.................................................................. 36
12 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2017) to Revision B (July 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Removed "±15% Accurate WDT and RST Delays"............................................................................................ 1
• Added "Functional Safety-capable" bullet...........................................................................................................1
• Updated the Applications to link to the website.................................................................................................. 1
• Added "on the SENSE pin" for clarification.........................................................................................................1
• Updated ESD Ratings.........................................................................................................................................4
• Changed ICWD min and max spec ......................................................................................................................5
• Changed VCWD min and max spec .................................................................................................................... 5
• Added a footnote to for tINIT ............................................................................................................................... 6
• Created a separate section for Timing Diagram................................................................................................. 7
• Added explanation about capacitors for tWDU. ...............................................................................................24
• Changed minimum and maximum limits on tWDU from 0.85 and 1.15 to 0.905 and 1.095 respectively .......... 24
• Changed 0.85 to 0.905 in Equation 14 and 1.15 to 1.05 in Equation 15.......................................................... 31
Changes from Revision * (January 2017) to Revision A (April 2017)
Page
• Changed 0.000381 to 0.000324 in Equation 11 .............................................................................................. 28
• Changed Equation 17 and Equation 18 so that ISENSE is no longer in the denominator ................................. 32
• Deleted J row from Device Nomenclature table............................................................................................... 35
2
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5 Pin Configuration and Functions
VDD
1
CWD
2
Pad
10
SENSE
9
RESET
8
WDO
SET0
3
CRST
4
7
WDI
GND
5
6
SET1
Not to scale
Figure 5-1. DRC Package
3-mm × 3-mm VSON-10
Top View
Table 5-1. Pin Functions
PIN
NAME
CRST
DESCRIPTION
NO.
I/O
4
I
Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout
period. This pin can also be connected by a 10-kΩ pullup resistor to VDD, or left unconnected (NC) for various
factory-programmed reset timeout options; see the CRST Delay section.
When using an external capacitor, use Equation 3 to determine the reset timeout.
Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin
and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected
(NC) further enables the selection of the preset watchdog timeouts; see the Section 6.6 table.
When using a capacitor, the TPS3850-Q1 determines the window watchdog upper boundary with Equation 6.
The lower watchdog boundary is set by the SET pins, see Table 8-5 and the CWD Functionality section for
additional information.
CWD
2
I
GND
5
—
Ground pin
RESET
9
O
Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to VDD. RESET goes low when the voltage
at the SENSE pin goes below the undervoltage threshold (VIT-(UV)) or above the overvoltage threshold (VIT+
(OV)). When the voltage level at the SENSE pin is within the normal operating range, the RESET timeout
counter starts. At timer completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset voltage (VPOR). Above VPOR, RESET goes low and remains low until the
monitored voltage is within the correct operating range (between VIT-(UV) and VIT(+OV)) and the RESET timeout
is complete.
SENSE
10
I
SENSE input to monitor the voltage rail. Connect this pin to the supply rail that must be monitored.
SET0
3
I
Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;
see the Section 6.6 table.
SET1
6
I
Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;
see the Section 6.6 table.
VDD
1
I
Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.
WDI
7
I
Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper
(tWDU(min)) window boundaries in order for WDO to not assert.
When the watchdog is not in use, the SETx pins can be used to disable the watchdog. The input at WDI is
ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is
disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.
WDO
8
O
Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to VDD. WDO goes low (asserts) when
a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs,
WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a
high-impedance state.
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
Thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
VDD
–0.3
7
V
Output voltage
RESET, WDO
–0.3
7
V
SET0, SET1, WDI, SENSE
–0.3
7
CWD, CRST
–0.3
VDD + 0.3(3)
Voltage ranges
Output pin current
RESET, WDO
Input current (all pins)
Continuous total power dissipation
Temperature
(1)
(2)
(3)
V
±20
mA
±20
mA
See Section 6.4
Operating junction, TJ (2)
–40
150
Operating free-air, TA (2)
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
TJ = TA as a result of the low dissipated power in this device.
The absolute maximum rating is VDD + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Supply pin voltage
1.6
6.5
V
VSENSE
Input pin voltage
0
6.5
V
VSET0
SET0 pin voltage
0
6.5
V
VSET1
SET1 pin voltage
0
6.5
V
0.1(1)
1000(1)
nF
11
kΩ
1000(2)
nF
CCRST
RESET delay capacitor
CRST
Pullup resistor to VDD
CCWD
Watchdog timing capacitor
CWD
Pullup resistor to VDD
9
10
11
kΩ
RPU
Pullup resistor, RESET and WDO
1
10
100
kΩ
IRST
RESET pin current
10
mA
IWDO
Watchdog output current
10
mA
TJ
Junction temperature
125
°C
(1)
(2)
4
NOM
9
10
0.1(2)
–40
Using a CCRST capacitor of 0.1 nF or 1000 nF gives a reset delay of 703 µs or 3.22 seconds, respectively.
Using a CCWD capacitor of 0.1 nF or 1000 nF gives a tWDU(typ) of 62.74 ms or 77.45 seconds, respectively.
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6.4 Thermal Information
TPS3850-Q1
THERMAL
METRIC(1)
UNIT
DRC (VSON)
10 PINS
RθJA
Junction-to-ambient thermal resistance
47.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.4
°C/W
RθJB
Junction-to-board thermal resistance
22.3
°C/W
ψJT
Junction-to-top characterization parameter
1.4
°C/W
ψJB
Junction-to-board characterization parameter
22.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at 1.6 V ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ ≤ +125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL CHARACTERISTICS
VDD (1) (2) (3)
Supply voltage
IDD
Supply current
1.6
10
6.5
V
19
µA
0.8
V
RESET FUNCTION
VPOR (2)
Power-on-reset voltage
VUVLO (1)
Undervoltage lockout voltage
VIT+(OV)
Overvoltage SENSE threshold accuracy,
entering RESET
VIT+(nom)–0.8%
VIT+(nom)+0.8%
VIT-(UV)
Undervoltage SENSE threshold accuracy,
entering RESET
VIT-(nom)–0.8%
VIT-(nom)+0.8%
VIT(ADJ)
Falling SENSE threshold voltage,
adjustable version only
VHYST
Hysteresis voltage
ICRST
CRST pin charge current
VCRST
CRST pin threshold voltage
IRESET = 15 µA, VOL(MAX) = 0.25 V
1.35
CRST = 0.5 V
V
0.3968
0.4
0.4032
V
0.2%
0.5%
0.8%
337
375
413
nA
1.192
1.21
1.228
V
WINDOW WATCHDOG FUNCTION
ICWD
CWD pin charge current
VCWD
CWD pin threshold voltage
VOL
RESET, WDO output low
VDD = 5 V, ISINK = 3 mA
ID
RESET, WDO output leakage current
VDD = 1.6 V, VRESET, = VWDO = 6.5 V
VIL
Low-level input voltage (SET0, SET1)
VIH
High-level input voltage (SET0, SET1)
VIL(WDI)
Low-level input voltage (WDI)
VIH(WDI)
High-level input voltage (WDI)
ISENSE
(1)
(2)
(3)
SENSE pin idle current
CWD = 0.5 V
347
375
403
nA
1.196
1.21
1.224
V
0.4
V
1
µA
0.25
V
0.8
V
0.3 × VDD
0.8 × VDD
TPS3850Xyy(y), VSENSE = 5.0 V,
VDD = 3.3 V
TPS3850H01 only, VSENSE = 5.0 V,
VDD = 3.3 V
V
V
2.1
–50
2.5
µA
50
nA
When VDD falls below VUVLO, RESET is driven low.
When VDD falls below VPOR, RESET and WDO are undefined.
During power-on, VDD must be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.
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6.6 Timing Requirements
at 1.6 V ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ ≤ +125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
MIN
TYP
MAX
UNIT
GENERAL
tINIT
CWD, CRST pin evaluation period(1)
381
µs
tSET
Time required between changing the SET0 and SET1 pins
500
µs
1
µs
300
µs
SET0, SET1 pin setup time
Startup delay(2)
RESET FUNCTION
tRST
Reset timeout period
tRST-DEL
VSENSE to RESET delay
CRST = NC
170
200
230
ms
CRST = 10 kΩ to VDD
8.5
10
11.5
ms
VDD = 5 V, VSENSE = VIT+(OV) + 2.5%
35
VDD = 5 V, VSENSE = VIT-(UV) – 2.5%
17
CWD = programmable, SET0 = 0, SET1 = 0(3)
1/8
CWD = programmable, SET0 = 1, SET1 = 1(3)
1/2
µs
WINDOW WATCHDOG FUNCTION
WD ratio
Window watchdog ratio of
lower boundary to upper
boundary
CWD = programmable, SET0 = 0, SET1 =
1(3) (4)
19.1
22.5
25.9
ms
CWD = NC, SET0 = 0, SET1 = 1
1.48
1.85
2.22
ms
CWD = NC, SET0 = 1, SET1 = 0
Window watchdog lower
boundary
tWDL
680
800
920
ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 0
7.65
9.0
10.35
ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 1
7.65
9.0
10.35
ms
1.48
1.85
2.22
ms
CWD = NC, SET0 = 0, SET1 = 0
46.8
55.0
63.3
ms
CWD = NC, SET0 = 0, SET1 = 1
23.375
27.5
31.625
ms
CWD = NC, SET0 = 1, SET1 = 1
1600
1840
ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 0
92.7
109.0
125.4
ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 1
165.8
195.0
224.3
ms
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 1
tWD-del
(1)
(2)
(3)
(4)
6
Watchdog disabled
1360
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 0
tWD-setup
Watchdog disabled
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 1
CWD = NC, SET0 = 1, SET1 = 0
Window watchdog upper
boundary
Watchdog disabled
CWD = NC, SET0 = 1, SET1 = 1
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 0
tWDU
3/4
CWD = NC, SET0 = 0, SET1 = 0
Setup time required for the device to respond to changes on WDI after being
enabled
Watchdog disabled
9.35
11.0
12.65
ms
150
µs
Minimum WDI pulse duration
50
ns
WDI to WDO delay
50
ns
Refer to Section 8.1.1.2
During power-on, VDD must be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.
0 refers to VSET ≤ VIL, 1 refers to VSET ≥ VIH.
If this watchdog ratio is used, then tWDL(max) can overlap tWDU(min).
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6.7 Timing Diagrams
VDD
VUVLO
VPOR
VIT-(UV) + VHYST
SENSE
VIT-(UV)
tRST
tRST
tRST-DEL
tWDL < t < tWDU (1)
RESET
t < tWDU
t < tWDU
WDI
X
X
t < tWDL
WDO
tRST
A.
See Figure 6-2 for WDI timing requirements.
Figure 6-1. Timing Diagram
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Early Fault
WDI
WDO
Correct Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Window
Window
Timing
tWDL(min)
tWDL(typ)
tWDL(max)
tWDU(min)
tWDU(typ)
tWDU(max)
= Tolerance Window
Figure 6-2. TPS3850-Q1 Window Watchdog Timing
8
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VDD/
SENSE
RESET
tRST-DEL
tRST
SET0
tSET
tWD-setup
SET1
RATIO
1:8
Disabled
1:8
1:2
Figure 6-3. Changing SET0 and SET1 Pins
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6.8 Typical Characteristics
all curves are taken at TA = 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)
0.5
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
Unit 1
Unit 2
0.1
-0.1
-0.3
0.1
-0.1
-0.3
-0.5
-50
-25
0
25
50
Temperature (qC)
75
100
-0.5
-50
125
Figure 6-4. VIT+(OV) Accuracy vs Temperature
Unit 3
Unit 4
Unit 5
Average
25
50
Temperature (qC)
Unit 1
Unit 2
75
100
125
Unit 3
Unit 4
Unit 5
Average
0.3
Accuracy (%)
0.3
Accuracy (%)
0
0.5
Unit 1
Unit 2
0.1
-0.1
-0.3
0.1
-0.1
-0.3
-0.5
-50
-25
0
25
50
Temperature (qC)
75
100
-0.5
-50
125
Figure 6-6. VIT-(OV) Accuracy vs Temperature
-25
0
25
50
Temperature (qC)
75
100
125
Figure 6-7. VIT+(UV) Accuracy vs Temperature
25
25
20
20
Frequency (%)
Frequency (%)
-25
Figure 6-5. VIT-(UV) Accuracy vs Temperature
0.5
15
10
5
15
10
5
0
0
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2
VIT+(OV) Accuracy (%)
0.3
0.4
0.5
Includes G and H versions; with 1.2-V, 1.8-V, 3.0-V, 3.3-V, and
5-V thresholds; total units = 41,111
Figure 6-8. VIT+(OV) Accuracy Histogram
10
Unit 5
Average
0.3
Accuracy (%)
Accuracy (%)
0.3
Unit 3
Unit 4
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2
VIT-(UV) Accuracy (%)
0.3
0.4
0.5
Includes G and H versions; with 1.2-V, 1.8-V, 3.0-V, 3.3-V, and
5-V thresholds; total units = 41,111
Figure 6-9. VIT-(UV) Accuracy Histogram
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6.8 Typical Characteristics (continued)
380
16
376
12
Supply Current (PA)
CWD Charging Current (nA)
all curves are taken at TA = 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)
372
368
8
-40qC
0qC
25qC
105qC
125qC
4
1.6 V
6.5 V
364
-50
-25
0
25
50
Temperature (qC)
75
100
0
125
0
Figure 6-10. CWD Charging Current vs Temperature
2
3
4
VDD (V)
6
7
1.6
-40qC
0qC
25qC
105qC
125qC
1.4
1.2
-40qC
0qC
25qC
105qC
125qC
1.4
1.2
1
VOL (V)
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
0
1
2
3
4
5
6
0
1
2
IRESET (mA)
VDD = 1.6 V
3
IRESET (mA)
4
5
6
VDD = 6.5 V
Figure 6-12. Low-Level RESET Voltage vs RESET Current
Figure 6-13. Low-Level RESET Voltage vs RESET Current
90
90
-40qC
0qC
25qC
105qC
-40qC
0qC
125qC
70
Propagation Delay (Ps)
Propagation Delay (Ps)
5
Figure 6-11. Supply Current vs Power-Supply Voltage
1.6
VOL (V)
1
50
30
25qC
105qC
125qC
70
50
30
10
10
1
2
3
4
Overdrive (%)
5
6
7
1
2
VDD = 1.6 V, VIT+(OV) = 0.936 V
Figure 6-14. Propagation Delay vs Overdrive
3
4
Overdrive (%)
5
6
7
VDD = 6.5 V, VIT+(OV) = 0.936 V
Figure 6-15. Propagation Delay vs Overdrive
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6.8 Typical Characteristics (continued)
all curves are taken at TA = 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)
40
40
25qC
105qC
125qC
-40qC
0qC
30
Propagation Delay (Ps)
Propagation Delay (Ps)
-40qC
0qC
20
10
0
30
20
10
2
3
4
Overdrive (%)
5
6
7
1
2
VDD = 1.6 V, VIT-(UV) = 0.864 V
35
35
30
25
20
15
5
-50
-25
0
25
50
Temperature (qC)
Overdrive = 6%
Overdrive = 7%
75
100
SENSE Glitch Immunity (Ps)
SENSE Glitch Immunity (Ps)
40
10
4
Overdrive (%)
5
6
30
25
20
15
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
10
5
-50
125
-25
VDD = 1.6 V, VIT+(OV) = 0.936 V
0
25
50
Temperature (qC)
Overdrive = 6%
Overdrive = 7%
75
100
Figure 6-19. SENSE Glitch Immunity vs Temperature
40
40
Overdrive = 6%
Overdrive = 7%
35
SENSE Glitch Immunity (Ps)
35
30
25
20
15
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
Overdrive = 6%
Overdrive = 7%
30
25
20
15
10
10
5
-50
125
VDD = 6.5 V, VIT+(OV) = 0.936 V
Figure 6-18. SENSE Glitch Immunity vs Temperature
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
7
Figure 6-17. Propagation Delay vs Overdrive
40
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
3
VDD = 6.5 V, VIT-(UV) = 0.864 V
Figure 6-16. Propagation Delay vs Overdrive
SENSE Glitch Immunity (Ps)
125qC
0
1
-25
0
25
50
Temperature (qC)
75
100
125
5
-50
-25
VDD = 1.6 V, VIT-(UV) = 0.864 V
Figure 6-20. SENSE Glitch Immunity vs Temperature
12
25qC
105qC
0
25
50
Temperature (qC)
75
100
125
VDD = 6.5 V, VIT-(UV) = 0.864 V
Figure 6-21. SENSE Glitch Immunity vs Temperature
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7 Detailed Description
7.1 Overview
The TPS3850-Q1 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes
a precision voltage supervisor with both overvoltage (VIT+(OV)) and undervoltage (VIT-(UV)) thresholds that
achieve 0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3850-Q1
includes accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems
where voltage supervisors must ensure a RESET before the minimum and maximum supply tolerance of the
microprocessor or system-on-a-chip (SoC) is reached.
7.2 Functional Block Diagrams
VDD
VDD
SENSE
R1
RESET
R2
Precision
Clock
R3
Reference
0.4 V
VDD
WDO
State
Machine
Cap
Control
CWD
VDD
CRST
Cap
Control
WDI
SET0 SET1
GND
RTOTAL = R1 + R2 + R3 = 4.5 MΩ.
Figure 7-1. Fixed Version Block Diagram
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VDD
VDD
SENSE
RESET
Reference
Precision
Clock
0.4 V
VDD
WDO
State
Machine
Cap
Control
CWD
VDD
CRST
Cap
Control
WDI
SET0 SET1
GND
Figure 7-2. Adjustable Version Block Diagram
7.3 Feature Description
7.3.1 CRST
The CRST pin provides the user the functionality of both high-precision, factory-programmed, reset delay
timing options and user-programmable, reset delay timing. The CRST pin can be pulled up to VDD through
a resistor, have an external capacitor to ground, or can be left unconnected. The configuration of the CRST
pin is re-evaluated by the device every time the voltage on the SENSE line enters the valid window (VIT+(UV) <
VSENSE < VIT-(OV)). The pin evaluation is controlled by an internal state machine that determines which option
is connected to the CRST pin. The sequence of events takes 381 μs (tINIT) to determine if the CRST pin is left
unconnected, pulled up through a resistor, or connected to a capacitor. If the CRST pin is being pulled up to
VDD, then a 10-kΩ pullup resistor is required.
7.3.2 RESET
The RESET pin features a programmable reset delay time that can be adjusted from 703 µs to 3.22 seconds
when using adjustable capacitor timing. RESET is an open-drain output that should be pulled up through a 1-kΩ
to 100-kΩ pullup resistor. When VDD is above VDD (min), RESET remains high (not asserted) when the SENSE
voltage is between the positive threshold (VIT+(OV)) and the negative threshold (VIT-(UV)). If SENSE falls below
VIT-(UV) or rises above VIT+(OV), then RESET is asserted, driving the RESET pin to a low-impedance state.
When SENSE comes back into the valid window, a RESET delay circuit is enabled that holds RESET low
for a specified reset delay period (tRST). This tRST period is determined by what is connected to the CRST
pin; see Figure 8-1. When the reset delay has elapsed, the RESET pin goes to a high-impedance state and
uses a pullup resistor to hold RESET high. The pullup resistor must be connected to the proper voltage rail
14
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to allow other devices to be connected at the correct interface voltage. To ensure proper voltage levels, give
some consideration when choosing the pullup resistor values. The pullup resistor value is determined by output
logic low voltage (VOL), capacitive loading, and leakage current (ID); see the Section 8.1.1 section for more
information.
7.3.3 Over- and Undervoltage Fault Detection
The TPS3850-Q1 features both overvoltage detection and undervoltage detection. This detection is achieved
through the combination of two comparators with a precision voltage reference and a trimmed resistor
divider (fixed versions only). The SENSE pin is used to monitor the critical voltage rail; this configuration
optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and performance
specifications. Both comparators also include built-in hysteresis that provides some noise immunity and ensures
stable operation. If the voltage on the SENSE pin drops below VIT-(UV), then RESET is asserted (driven low).
When the voltage on the SENSE pin is between the positive and negative threshold voltages, RESET deasserts
after the user-defined RESET delay time, as shown in Figure 7-3.
The SENSE input can vary from GND to 6.5 V, regardless of the device supply voltage used. Although not
required in most cases, for noisy applications, good analog-design practice is to place a 1-nF to 100-nF bypass
capacitor at the SENSE pin to reduce sensitivity to transient voltages on the monitored signal.
Overvoltage Limit VIT+(OV)
VIT-(OV) = VIT+(OV) - VHYST
VSENSE
VIT+(UV) = VIT-(UV) + VHYST
tRST
tRST-DEL
tRST
tRST-DEL
RESET
tRST-DEL
VIT-(UV)
tRST-DEL
Undervoltage Limit
Figure 7-3. Window Comparator Timing Diagram
7.3.4 Adjustable Operation Using the TPS3850H01Q1
The adjustable version (TPS3850H01Q1) can be used to monitor any voltage rail down to 0.4 V using the
circuit illustrated in Figure 7-4. When using the TPS3850H01Q1, the device does not function as a window
comparator; instead, the device only monitors the undervoltage threshold. To monitor a user-defined voltage, the
target threshold voltage for the monitored supply (VMON) and the resistor divider values can be calculated by
using Equation 1 and Equation 2, respectively:
VMON
§
R1 ·
VIT(ADJ) u ¨ 1
¸
© R2 ¹
(1)
Equation 1 can be used to calculate either the negative threshold or the positive threshold by replacing VITx with
either VITN or VITN + VHYST, respectively.
RTOTAL = R1 + R2
(2)
Large resistor values minimize current consumption; however, the input bias current of the device degrades
accuracy if the current through the resistors is too low. Therefore, choosing an RTOTAL value so that the current
through the resistor divider is at least 100 times larger than the maximum SENSE pin current (ISENSE) ensures
a good degree of accuracy; see the IQ vs Accuracy Tradeoff In Designing Resistor Divider Input To A Voltage
Supervisor (SLVA450) for more details on sizing input resistors.
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VMON
VDD
TPS3850-Q1
R1
SENSE
R2
VDD
SET1
RESET
SET0
WDO
CRST
WDI
CWD
GND
WDI
Copyright © 2016, Texas Instruments Incorporated
Figure 7-4. Adjustable Voltage Monitor
7.3.5 Window Watchdog
7.3.5.1 SET0 and SET1
When changing the SET0 or SET1 pins, there are two cases to consider: enabling and disabling the watchdog,
and changing the SET0 or SET1 pins when the watchdog is enabled. In case 1 where the watchdog is being
enabled or disabled, the changes take effect immediately. However, in case 2, a RESET event must occur in
order for the changes to take place.
7.3.5.1.1 Enabling the Window Watchdog
The TPS3850-Q1 features the ability to enable and disable the watchdog timer. This feature allows the user to
start with the watchdog timer disabled and then enable the watchdog timer using the SET0 and SET1 pins. The
ability to enable and disable the watchdog is useful to avoid undesired watchdog trips during initialization and
shutdown. When the SETx pins are changed to disable the watchdog timer, changes on the pins are responded
to immediately (as shown in Figure 7-5). When the watchdog goes from disabled to enabled, there is a 150 μs
(tWD-setup) transition period where the device does not respond to changes on WDI. After this 150-μs period, the
device begins to respond to changes on WDI again.
VDD/
SENSE
RESET
SET0
tWD-setup
SET1
RATIO
1:8
Disabled
1:8
Figure 7-5. Enabling the Watchdog Timer
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7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
When using the TPS3850-Q1 with fixed timing options, if the watchdog is disabled and reenabled while WDO
is asserted (logic low) the watchdog performs as described in the Section 7.3.5.1.1 section. However, if there is
a capacitor on the CRST pin, and the watchdog is disabled and reenabled when WDO is asserted (logic low),
then the watchdog behaves as shown in Figure 7-6. When the watchdog is disabled, WDO goes high impedance
(logic high). However, when the watchdog is enabled again, the tRST period must expire before the watchdog
resumes normal operation.
VDD/
SENSE
RESET
tWDU
tWDU
WDO
tRST
SET1
Disabling and
Enabling
watchdog
SET0
There is no WDI signal in this figure, WDI is always at GND.
Figure 7-6. Enabling and Disabling the Watchdog Timer During a WDO Reset Event
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7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation
The SET0 and SET1 pins can be used to control the window watchdog ratio of the lower boundary to the upper
boundary. There are four possible modes for the watchdog (see Table 8-5): disabled, 1:8 ratio, 3:4 ratio, and 1:2
ratio. If SET0 = 1 and SET1 = 0, then the watchdog is disabled. When the watchdog is disabled, WDO does not
assert and the TPS3850-Q1 functions as a normal supervisor. The SET0 and SET1 pins can be changed when
the device is operational, but cannot be changed at the same time. If these pins are changed when the device
is operational, then there must be a 500-µs (tSET) delay between switching the two pins. If SET0 and SET1
are used to change the reset timing, then a reset event must occur before the new timing condition is latched.
This reset can be triggered by SENSE rising above VIT+(OV) or below VIT-(UV), or by bringing VDD below VUVLO.
Figure 7-7 shows how the SET0 and SET1 pins do not change the watchdog timing option until a reset event
has occurred.
VDD/
SENSE
RESET
tRST-DEL
tRST
SET0
tSET
SET1
RATIO
1:8
1:2
Figure 7-7. Changing SET0 and SET1 Pins
18
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7.3.6 Window Watchdog Timer
This section provides information for the window watchdog modes of operation. A window watchdog is typically
employed in safety-critical applications where a traditional watchdog timer is inadequate. In a traditional
watchdog, there is a maximum time in which a pulse must be issued to prevent the reset from occurring.
However, in a window watchdog the pulse must be issued between a maximum lower window time (tWDL(max))
and the minimum upper window time (tWDU(min)) set by the CWD pin and the SET0 and SET1 pins. Table 8-5
describes how tWDU can be used to calculate the timing of tWDL. The tWDL timing can also be changed by
adjusting the SET0 and SET1 pins. Figure 7-8 shows the valid region for a WDI pulse to be issued to prevent the
WDO from being triggered and being pulled low.
Early Fault
WDI
WDO
Correct Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Window
Window
Timing
tWDL(min)
tWDL(typ)
tWDL(max)
tWDU(min)
tWDU(typ)
tWDU(max)
= Tolerance Window
Figure 7-8. TPS3850-Q1 Window Watchdog Timing
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7.3.6.1 CWD
The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing
options and user-programmable watchdog timing. The TPS3850-Q1 features three options for setting the
watchdog window: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the
CWD pin unconnected. The configuration of the CWD pin is evaluated by the device every time VSENSE enters
the valid window (VIT+(UV) < V SENSE < V IT-(OV)). The pin evaluation is controlled by an internal state machine that
determines which option is connected to the CWD pin. The sequence of events takes 381 μs (tINIT) to determine
if the CWD pin is left unconnected, pulled up through a resistor, or connected to a capacitor. If the CWD pin is
being pulled up to VDD using a pullup resistor, then a 10-kΩ resistor is required.
7.3.6.2 WDI Functionality
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of
the input signal. For the first pulse, the watchdog functions as a traditional watchdog timer; thus, the first pulse
must be issued before tWDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always
issue the WDI pulse within the window of tWDL(max) and tWDU(min). If the pulse is issued in this region, then WDO
remains unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. To ensure there is no increase in IDD, drive the WDI pin to either VDD
or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD)
because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all
signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and
no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.
7.3.6.3 WDO Functionality
The TPS3850-Q1 features a window watchdog timer with an independent watchdog output ( WDO). The
independent watchdog output provides the flexibility to flag a fault in the watchdog timing without performing
an entire system reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When
asserted, WDO remains down for tRST. When the RESET signal is asserted (low), the WDO pin goes to a
high-impedance state. When RESET is unasserted, the window watchdog timer resumes normal operation and
WDO can be used again.
20
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7.4 Device Functional Modes
Table 7-1 summarizes the functional modes of the TPS3850-Q1.
Table 7-1. Device Functional Modes
VDD
WDI
WDO
SENSE
RESET
VDD < VPOR
—
—
—
Undefined
VPOR ≤ VDD < VUVLO
Ignored
High
—
Low
Ignored
High
VSENSE < VIT+(UV) (1)
(1)
VDD ≥ VDD (min)
(1)
(2)
(3)
VSENSE > VIT-(OV)
Low
Ignored
High
tWDL(max) ≤ tpulse (3) ≤ tWDU(min)
High
VIT-(UV) < VSENSE < VIT+(OV) (2)
High
Low
tWDL(max) > tpulse (3)
Low
VIT-(UV) < VSENSE < VIT+(OV) (2)
High
tWDU(min) < tpulse (3)
Low
VIT-(UV) < VSENSE < VIT+(OV) (2)
High
When VSENSE has not entered the valid window.
When VSENSE is in the valid window.
Where tpulse is the time between falling edges on WDI.
7.4.1 VDD is Below VPOR ( VDD < VPOR)
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely
depends on the load that the RESET pin is experiencing.
7.4.2 Above Power-On-Reset But Less Than UVLO (VPOR ≤ VDD < VUVLO)
When VDD is less than VUVLO, and greater than or equal to VPOR, the RESET signal is asserted (logic low)
regardless of the voltage on the SENSE pin. When RESET is asserted, the watchdog output WDO is in a
high-impedance state regardless of the WDI signal that is input to the device.
7.4.3 Above UVLO But Less Than VDD (min) (VUVLO ≤ VDD < VDD (min))
When VDD is less than VDD (min) and greater than or equal to VUVLO, the RESET signal responds to changes on
the SENSE pin, but the accuracy can be degraded.
7.4.4 Normal Operation (VDD ≥ VDD (min))
When VDD is greater than or equal to VDD (min), the RESET signal is determined by VSENSE. When RESET is
asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The following sections describe in detail proper device implementation, depending on the final application
requirements.
8.1.1 CRST Delay
The TPS3850-Q1 features three options for setting the reset delay (tRST): connecting a capacitor to the CRST
pin, connecting a pullup resistor to VDD, and leaving the CRST pin unconnected. Figure 8-1 shows a schematic
drawing of all three options. To determine which option is connected to the CRST pin, an internal state machine
controls the internal pulldown device and measures the pin voltage. This sequence of events takes 381 μs (tINIT)
to determine which timing option is used. Every time RESET is asserted, the state machine determines what is
connected to the pin.
TPS3850-Q1
VDD
TPS3850-Q1
VDD
VDD
VDD
VDD
VDD
10 k
375 nA
TPS3850-Q1
375 nA
375 nA
CRST
CRST
CRST
CCRST
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
Cap
Control
Floating
CRST
10 NŸ 5HVLVWRU
to VDD
Figure 8-1. CRST Charging Circuit
8.1.1.1 Factory-Programmed Reset Delay Timing
To use the factory-programmed timing options, the CRST pin must either be left unconnected or pulled up to
VDD through a 10-kΩ pullup resistor. Using these options enables a high-precision, 15% accurate reset delay
timing, as shown in Table 8-1.
Table 8-1. Reset Delay Time for Factory-Programmed Reset Delay Timing
CRST
RESET DELAY TIME (tRST)
UNIT
MIN
TYP
MAX
NC
170
200
230
ms
10 kΩ to VDD
8.5
10
11.5
ms
22
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8.1.1.2 Programmable Reset Delay Timing
The TPS3850-Q1 uses a CRST pin charging current (ICRST) of 375 nA. When using an external capacitor, the
rising RESET delay time can be set to any value between 700 µs (CCRST = 100 pF) and 3.2 seconds (CCRST =
1 µF). The typical ideal capacitor value needed for a given delay time can be calculated using Equation 3, where
CCRST is in microfarads and tRST is in seconds:
tRST = 3.22 × CCRST + 0.000381
(3)
To calculate the minimum and maximum-reset delay time use Equation 4 and Equation 5, respectively.
tRST(min) = 2.8862 × CCRST + 0.000324
(4)
tRST(max) = 3.64392 × CCRST + 0.000438
(5)
The slope of Equation 3 is determined by the time the CRST charging current (ICRST) takes to charge the
external capacitor up to the CRST comparator threshold voltage (VCRST). When RESET is asserted, the
capacitor is discharged through the internal CRST pulldown resistor. When the RESET conditions are cleared,
the internal precision current source is enabled and begins to charge the external capacitor; when VCRST = 1.21
V, RESET is unasserted. Note that to minimize the difference between the calculated RESET delay time and the
actual RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize
parasitic board capacitance around this pin. Table 8-2 lists the reset delay time ideal capacitor values for CCRST.
Table 8-2. Reset Delay Time for Common Ideal Capacitor Values
RESET DELAY TIME (tRST)
CCRST
UNIT
MIN(1)
TYP
MAX(1)
100 pF
0.61
0.70
0.80
ms
1 nF
3.21
3.61
4.08
ms
10 nF
29.2
32.6
36.8
ms
100 nF
1 μF
(1)
289
323
364
ms
2886
3227
3644
ms
Minimum and maximum values are calculated using ideal capacitors.
8.1.2 CWD Functionality
The TPS3850-Q1 features three options for setting the watchdog window: connecting a capacitor to the CWD
pin, connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. Figure 8-2 shows a schematic
drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected
(high impedance), then the factory-programmed watchdog timeouts are enabled; see the table. Otherwise, the
watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.
TPS3850-Q1
VDD
TPS3850-Q1
VDD
TPS3850-Q1
VDD
VDD
375 nA
VDD
VDD
375 nA
375 nA
10 k
CWD
CWD
CWD
CCWD
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
Cap
Control
CWD
10 NŸ 5HVLVWRU
Unconnected
to VDD
Copyright © 2016, Texas Instruments Incorporated
Figure 8-2. CWD Charging Circuit
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8.1.2.1 Factory-Programmed Timing Options
If using the factory-programmed timing options (listed in Table 8-3), the CWD pin must either be unconnected
or pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, factory
programmed watchdog timing.
Table 8-3. Factory-Programmed Watchdog Timing
INPUT
CWD
NC
10 kΩ to VDD
WATCHDOG LOWER BOUNDARY (tWDL)
SET0
SET1
MIN
TYP
MAX
0
0
19.1
22.5
0
1
1.48
1.85
1
0
1
1
680
800
920
0
0
7.65
9.0
0
1
7.65
9.0
1
0
1
1
WATCHDOG UPPER BOUNDARY (tWDU)
TYP
25.9
46.8
55.0
63.3
ms
2.22
23.375
27.5
31.625
ms
Watchdog disabled
1.85
MAX
Watchdog disabled
1360
1600
1840
ms
10.35
92.7
109.0
125.4
ms
10.35
165.8
195.0
224.3
ms
12.65
ms
Watchdog disabled
1.48
UNIT
MIN
Watchdog disabled
2.22
9.35
11.0
8.1.2.2 Adjustable Capacitor Timing
Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected
to CWD, then a 375-nA, constant-current source charges CCWD until VCWD = 1.21 V. The TPS3850-Q1
determines the window watchdog upper boundary with the formula given in Equation 6, where CCWD is in
microfarads and tWDU is in seconds.
tWDU(typ) = 77.4 × CCWD + 0.055
(6)
The TPS3850-Q1 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that Equation
6 is for ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum
of tWDU can decrease and the maximum of tWDU can increase by the capacitor tolerance. To allow for a valid
watchdog window, choose a capacitor with tolerance such that tWDU(min) and tWDL(max) do not overlap. For the
most accurate timing, use ceramic capacitors with COG dielectric material. As shown in Table 8-4, when using
the minimum capacitor of 100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitor, the
watchdog upper boundary is 77.455 seconds. If a CCWD capacitor is used, Equation 6 can be used to set tWDU
the window watchdog upper boundary. The window watchdog lower boundary is dependent on the SET0 and
SET1 pins because these pins set the window watchdog ratio of the lower boundary to upper boundary; Table
8-5 shows how tWDU can be used to calculate tWDL based on the SET0 and SET1 pins.
8.1.2.3
Table 8-4. tWDU Values for Common Ideal Capacitor Values
CCWD
100 pF
1 nF
10 nF
100 nF
1 µF
(1)
24
WATCHDOG UPPER BOUNDARY (tWDU)
UNIT
MIN(1)
TYP
MAX(1)
56.77
62.74
68.7
ms
119.82
132.4
144.98
ms
750
829
908
ms
7054
7795
8536
ms
70096
77455
84814
ms
Minimum and maximum values are calculated using ideal capacitors.
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Table 8-5. Programmable CWD Timing
INPUT
CWD
CCWD
WATCHDOG LOWER BOUNDARY (tWDL)
SET0
SET1
0
0
1
0
1
1
WATCHDOG UPPER BOUNDARY (tWDU)
MAX
MIN
TYP
0
tWDU(min)x 0.125
tWDU x 0.125
tWDU(max) x 0.125 0.905 x tWDU(typ)
tWDU(typ) 1.095 x tWDU(typ)
s
1
tWDU(min) x 0.75
tWDU x 0.75
tWDU(max) x 0.75 0.905 x tWDU(typ)
tWDU(typ) 1.095 x tWDU(typ)
s
Watchdog disabled
tWDU(min) x 0.5
tWDU x 0.5
TYP
MAX
UNIT
MIN
Watchdog disabled
tWDU(max) x 0.5 0.905 x tWDU(typ)
tWDU(typ) 1.095 x tWDU(typ)
s
8.1.3 Adjustable SENSE Configuration
The TPS3850H01Q1 has an undervoltage supervisor that can monitor voltage rails greater than 0.4 V. Table
8-6 contains 1% resistor values for creating a voltage divider to monitor common rails from 0.5 V to 12 V
with a threshold of 4% and 10%. These resistor values can be scaled to decrease the amount of current
flowing through the resistor divider, but increasing the resistor values also decreases the accuracy of the resistor
divider. General practice is for the current flowing through the resistor divider to be 100 times greater than the
current going into the SENSE pin. This practice ensures the highest possible accuracy. Equation 7 can be used
to calculate the resistors required in the resistor divider. Figure 8-3 shows the block diagram for adjustable
operation.
VMON
§
R1 ·
VIT(ADJ) u ¨ 1
¸
© R2 ¹
(7)
Table 8-6. SENSE Resistor Divider Values
4% THRESHOLD
INPUT VOLTAGE (V)
10% THRESHOLD
R1 (kΩ)
R2 (kΩ)
THRESHOLD
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
THRESHOLD
VOLTAGE (V)
16.2
80.6
0.48
10
80.6
0.45
0.8
75
80.6
0.77
64.9
80.6
0.72
0.9
93.1
80.6
0.86
82.5
80.6
0.81
1.2
150
80.6
1.14
137
80.6
1.08
1.8
267
80.6
1.73
249
80.6
1.64
2.5
402
80.6
2.40
374
80.6
2.26
3
499
80.6
2.88
464
80.6
2.70
3.3
562
80.6
3.19
523
80.6
2.99
5
887
80.6
4.80
825
80.6
4.49
12
2260
80.6
11.62
2100
80.6
10.82
0.5
VDD
Reference
VMON
RESET
0.4 V
R1
RESET
TIMING
SENSE
R2
Figure 8-3. Adjustable Voltage Divider
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8.1.4 Overdrive on the SENSE Pin
The propagation delay from exceeding the threshold to RESET being asserted is dependent on two conditions:
the amplitude of the voltage on the SENSE pin relative to the threshold, (ΔV1 and ΔV2), and the length of time
that the voltage is above or below the trip point (t1 and t2). If the voltage is just over the trip point for a long period
of time, then RESET asserts and the output is pulled low. However, if the SENSE voltage is just over the trip
point for a few nanoseconds, then the RESET does not assert and the output remains high. The time required
for RESET to assert can be changed by increasing the time that the SENSE voltage goes over the trip point.
Equation 8 shows how to calculate the percentage overdrive.
Overdrive = | ( VSENSE / VITx – 1) × 100% |
(8)
In Equation 8, VITx corresponds to the SENSE threshold trip point. If VSENSE exceeds the positive threshold,
then VIT+(OV) is used. VIT-(UV) is used when VSENSE falls below the negative threshold. In Figure 8-4, t1 and
t2 correspond to the amount of time that the SENSE voltage is over the threshold. The response time versus
overdrive for VIT+(OV) and VIT-(UV) is illustrated in Figure 6-14 and Figure 6-17, respectively.
The TPS3850-Q1 is relatively immune to short positive and negative transients on the SENSE pin because of
the overdrive voltage curve; see Figure 6-20 and Figure 6-21.
ûV1
t1
SENSE Voltage
VIT+(OV)
VSENSE
VIT-(UV)
ûV2
t2
Time
Figure 8-4. Overdrive Voltage on the SENSE Pin
26
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8.2 Typical Applications
8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
A typical application for the TPS3850-Q1 is shown in Figure 8-5. The TPS3850G12Q1 is used to monitor the
1.2-V, VCORE rail powering the microcontroller.
1.8V
TPS3850-Q1
SENSE
10 NŸ
10 NŸ
1.2V
VCORE
VDD
SET1
RESET
SET0
WDO
CRST
WDI
CWD
GND
VI/O
Microcontroller
RESET
NMI
GPIO
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 8-5. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.1.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Reset delay
Minimum reset delay of 250 ms
Minimum reset delay of 260 ms, reset delay of
322 ms (typical)
Watchdog window
Functions with a 200-Hz pulse-width modulation
(PWM) signal with a 50% duty cycle
Leaving the CWD pin unconnected with SET0 = 0
and SET1 = 1 produces a window with a tWDL(max)
of 2.2 ms and a tWDU(min) of 22 ms
Output logic voltage
1.8-V CMOS
1.8-V CMOS
Monitored rail
1.2 V within ±5%
Maximum device current
consumption
200 µA
Worst-case VIT+(OV) 1.257 V (4.8%)
Worst-case VIT-(UV) 1.142 V (4.7%)
10 µA of current consumption, typical worst-case of
199 µA when WDO or RESET is asserted
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Monitoring the 1.2-V Rail
The window comparator allows for precise voltage supervision of common rails between 0.9 V and 5.0 V. This
application calls for very tight monitoring of the rail with only ±5% of variation allowed on the rail. To ensure
this requirement is met, the TPS3850G12Q1 was chosen for its ±4% thresholds. To calculate the worst-case for
VIT+(OV) and VIT-(UV), the accuracy must also be taken into account. The worst-case for VIT+(OV) can be calculated
by Equation 9:
VIT+(OV)(Worst-Case) = VIT+(OV)typ × 1.048 = 1.2 × 1.048 = 1.257 V
(9)
The worst case for VIT-(UV) can be calculated using Equation 10:
VIT–(UV)(Worst-Case) = VIT–(UV)typ × 0.952 = 1.2 × 0.952 = 1.142 V
(10)
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8.2.1.2.2 Meeting the Minimum Reset Delay
The TPS3850-Q1 features three options for setting the reset delay: connecting a capacitor to the CRST pin,
connecting a pullup resistor, and leaving the CRST pin unconnected. If the CRST pin is either unconnected
or pulled up the minimum timing requirement cannot be met, thus an external capacitor must be connected
to the CRST pin. Because a minimum time is required, the worst-case scenario is a supervisor with a high
CRST charging current (ICRST) and a low CRST comparator threshold (VCRST). For applications with ambient
temperatures ranging from –40°C to +125°C, CCRST can be calculated using ICRST(MAX), VCRST(MIN), and solving
for CCRST in Equation 11:
CRST(min) _ ideal
tRST(min) 0.000324
2.8862
0.25 0.000324
2.8862
(11)
When solving Equation 11, the minimum capacitance required at the CRST pin is 0.086 μF. If standard
capacitors with ±10% tolerances are used, then the minimum CRST capacitor required can be found in Equation
12:
CRST(min)
CRST(min) _ ideal
1 Ctolerance
0.086 PF
1 0.1
(12)
Solving Equation 12 where Ctolerance is 0.1 or 10%, the minimum CCRST capacitor is 0.096 μF. This value is
then rounded up to the nearest standard capacitor value, so a 0.1-μF capacitor must be used to achieve this
reset delay timing. If voltage and temperature derating are being considered, then also include these values in
Ctolerance.
8.2.1.2.3 Setting the Watchdog Window
In this application, the window watchdog timing options are based on the PWM signal that is provided to the
TPS3850-Q1. A window watchdog setting must be chosen such that the falling edge of the PWM signal always
falls within the window. A nominal window must be designed with tWDL(max) less than 5 ms and tWDU(min) greater
than 5 ms. There are several options that satisfy this window option. An external capacitor can be placed on the
CWD pin and calculated to have a sufficient window. Another option is to use one of the factory-programmed
timing options. An additional advantage of choosing one of the factory-programmed options is the ability to
reduce the number of components required, thus reducing overall BOM cost. Leaving the CWD pin unconnected
(NC) with SET0 = 0 and SET1 = 1 produces a tWDL(max) of 2.22 ms and a tWDU(min) of 23.375 ms; see Figure
8-10.
28
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8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor
The TPS3850-Q1 uses an open-drain configuration for the RESET circuit, as shown in Figure 8-6. When the
FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts
to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be
chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key
specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST),
and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the
voltage on the reset pin below 0.4 V with IRST kept below 10 mA. For this example, with a VPU of 1.8 V, a resistor
must be chosen to keep IRST below 200 μA because this value is the maximum consumption current allowed. To
ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180
μA when RESET or WDO is asserted. As illustrated in Figure 6-12, the RESET current is at 180 μA and the
low-level output voltage is approximately zero.
VDD
RESET
RESET
CONTROL
Figure 8-6. Open-Drain RESET Configuration
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8.2.1.3 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
VDD
500mV/div
SENSE
200mV/div
SENSE
1.2578 V
1.1576 V
WDO
RESET
500mV/div
VUVLO = 1.4 V
VDD
500mV/div
RESET
500mV/div
VPOR = .404V
100ms/div
Figure 8-8. Window Comparator Thresholds
Entering a Valid Window
50ms/div
Figure 8-7. Startup Waveform
VDD
2V/div
VDD
2V/div
SENSE
2V/div
SENSE
2V/div
WDO
2V/div
WDO
2V/div
WDI
2V/div
WDI
2V/div
22 ms
2.2 ms
5ms
10ms/div
5ms/div
Figure 8-10. Window Watchdog Timing
Figure 8-9. 200-Hz WDI Pulse
SENSE
200mV/div
VDD
500mV/div
RESET
500mV/div
50ms/div
Figure 8-11. Typical RESET Delay Timing
30
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8.2.2 Design 2: Using the TPS3850H01Q1 to Monitor a 0.7-V Rail With an Adjustable Window Watchdog
Timing
A typical application for the TPS3850H01Q1 is shown in Figure 8-12.
3.3 V
TPS3890-Q1
VDD
SENSE
MR
80.6 k
100 k
100 k
TPS3850-Q1
SENSE
VDD
VCORE
3.3 V
SET0
VI/O
Microcontroller
RESET
RESET
SET1
RESET
CT
6.8 µF
100 k
51.1 k
0.7 V
WDO
NMI
WDI
GPIO
CRST
GND
GND
GND
CWD
2.2 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-12. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.2.1 Design Requirements
PARAMETER
Reset delay
DESIGN REQUIREMENT
Minimum RESET delay of 150 ms
DESIGN RESULT
Minimum RESET delay of 170 ms
Watchdog disable for initialization Watchdog must remain disabled for 7 seconds until
7.21 seconds (typ)
period
logic enables the watchdog timer
Watchdog window
250 ms, maximum
tWDL(max) = 135 ms, tWDU(min) = 181 ms
Output logic voltage
3.3-V CMOS
3.3-V CMOS
VITN (max) 0.667 V (–4.7%)
Monitored rail
0.7 V, with 7% threshold
VITN (typ) 0.65 V (–6.6%)
VITN (min) 0.641 V (–8.5%)
Maximum device current
consumption
(1)
10 µA of current consumption typical, worst-case of
52 μA when WDO or RESET is asserted(1)
50 µA
Only includes the current consumption of the TPS3850-Q1.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Meeting the Minimum Reset Delay
The design goal for the RESET delay time can be achieved by either using an external capacitor or the CRST
pin can be left unconnected. To minimize component count, the CRST pin is left unconnected. For CRST = NC,
the minimum delay is 170 ms, which is greater than the minimum required RESET delay of 150 ms.
8.2.2.2.2 Setting the Window Watchdog
As illustrated in Figure 8-2, there are three options for setting the window watchdog. The design specifications
in this application require the programmable timing option (external capacitor connected to CWD). When a
capacitor is connected to the CWD pin, the window is governed by Equation 13. Equation 13 is only valid for
ideal capacitors, any temperature or voltage derating must be accounted for separately.
CCWD PF
t WDU 0.055
77.4
0.25 0.055
77.4
0.0025 PF
(13)
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The nearest standard capacitor value to 2.5 nF is 2.2 nF. Selecting 2.2 nF for the CCWD capacitor gives the
following minimum and maximum timing parameters:
3
t WDU(MIN)
0.905 u t WDU(TYP)
0.905 u 77.4 u 2.2 u 10
t WDL(MAX)
0.5 u t WDU(MAX)
0.5 u ª1.05 u 77.4 u 2.2 u 10
¬
0.055
3
203.88 ms
0.055 º
¼
118 ms
(14)
(15)
Capacitor tolerance also influences tWDU(MIN) and tWDL(MAX). Select a ceramic COG dielectric capacitor for high
accuracy. For 2.2 nF, COG capacitors are readily available with a 5% tolerance, resulting in a 5% decrease in
tWDU(MIN) and a 5% increase in tWDL(MAX), giving 181 ms and 135 ms, respectively. A falling edge must be issued
within this window.
8.2.2.2.3 Watchdog Disabled During the Initialization Period
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the
initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored
by the TPS3850-Q1. To achieve this setup, SET0 must start at VDD and SET1 must start at GND. In this
design, SET0 is simply tied to VDD and SET1 is controlled by a TPS3890-Q1 supervisor. In this application, the
TPS3890-Q1 was chosen to monitor VDD as well, which means that RESET on the TPS3890-Q1 stays low until
VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the CT capacitor on the
TPS3890-Q1. With this approach, the RESET delay can be adjusted from a minimum of 25 µs to a maximum
of 30 seconds. For this design, a minimum delay of 7 seconds is needed until the watchdog timer is enabled.
The CT capacitor calculation (see the TPS3890-Q1 data sheet) yields an ideal capacitance of 6.59 µF, giving a
closest standard ceramic capacitor value of 6.8 µF. When connecting a 6.8-µF capacitor from CT to GND, the
typical delay time is 7.21 seconds. Figure 8-13 illustrates the typical startup waveform for this circuit when the
watchdog input is off. Figure 8-13 illustrates that when the watchdog is disabled, the WDO output remains high.
See the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.
8.2.2.2.4 Calculating the Sense Resistor
There are three key specifications to keep in mind when calculating the resistor divider values (R1 and R2, see
Figure 7-4 or Figure 8-3): voltage threshold (VIT(ADJ)), resistor tolerance, and the SENSE pin current (ISENSE).
To ensure that no accuracy is lost because of ISENSE, the current through the resistor divider must be 100 times
greater than ISENSE. Starting with R2 = 80.6 kΩ provides a 5-µA resistor divider current when VSENSE = 0.4 V. To
calculate the nominal resistor values, use Equation 16:
VITN
VIT(ADJ)
R1
VIT(ADJ)
R2
(16)
where
•
•
VITN is the monitored falling threshold voltage and
VIT(ADJ) is the threshold voltage on the SENSE pin
Solving Equation 16 for R1 gives the nearest 1% resistor of 51.1 kΩ. Now, plug R1 back into Equation 16 to get
the monitored threshold. With these resistor values, the nominal threshold is 0.65 V or 6.6%.
To calculate the minimum and maximum threshold variation including the tolerances of the resistors, threshold
voltage, and sense current, use Equation 17 and Equation 18.
VITN(min)
VITN(max)
32
VIT(ADJ)min
§ VIT(ADJ)min
R1(min) ¨
¨ R2(max)
©
VIT(ADJ)max
§ VIT(ADJ)max
R1(max) ¨
¨ R2(min)
©
·
ISENSE(min) ¸
¸
¹
0.641 V
·
ISENSE(max) ¸
¸
¹
(17)
0.667 V
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where
•
•
•
VITN is the falling monitored threshold voltage
VIT(ADJ) is the sense voltage threshold and
ISENSE is the sense pin current
The calculated tolerance on R1 and R2 is 1%.
8.2.2.3 Application Curves
VDD
2V/div
VDD
2V/div
158 ms
WDI
2V/div
RESET
2V/div
7.6 seconds
WDO
2V/div
SET1
2V/div
RESET
2V/div
WDO
2V/div
50ms/div
Figure 8-14. Typical WDI Signal
1s/div
Figure 8-13. Startup Without a WDI Signal
9 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
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10 Layout
10.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
• If a CCRST capacitor or pullup resistor is used, place these components as close as possible to the CRST pin.
If the CRST pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
• If a CCWD capacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If
the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
• Place the pullup resistors on RESET and WDO as close to the pin as possible.
10.2 Layout Example
CVDD
GND Plane
Vin
RPU1
Vin
CCWD
CCRST
VDD
1
10
SENSE
CWD
2
9
RESET
SET0
3
8
WDO
CRST
4
7
WDI
GND
5
6
SET1
RPU2
Vin
Denotes a via.
Figure 10-1. Typical Layout for the TPS3850-Q1
34
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
The TPS3850EVM-781 Evaluation Module can be used to evaluate this part.
11.1.2 Device Nomenclature
Table 11-1. Device Nomenclature
DESCRIPTION
NOMENCLATURE
VALUE
TPS3850
(high-accuracy supervisor with window watchdog)
—
—
G
VIT+(OV) = 4%; VIT– (UV) = –4%
H
VIT+(OV) = 7%; VIT– (UV) = –7%
01
0.4 V
X
(nominal thresholds as a percent of the nominal
monitored voltage)
yy(y)
(nominal monitored voltage option)
09
0.9 V
115
1.15 V
12
1.2 V
18
1.8 V
25
2.5 V
30
3.0 V
33
3.3 V
50
5.0 V
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
• TPS3890-Q1 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay
• Optimizing Resistor Dividers at a Comparator Input
• TPS3850EVM-781 Evaluation Module
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS3850-Q1
35
TPS3850-Q1
www.ti.com
SBVS264B – JANUARY 2017 – REVISED SEPTEMBER 2021
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS3850-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3850G09QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850BB
TPS3850G12QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850CB
TPS3850G18QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850DB
TPS3850G25QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850EB
TPS3850G30QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850FB
TPS3850G33QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850GB
TPS3850G50QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850HB
TPS3850H01QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
(850AA, 850AB)
TPS3850H09QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850JB
TPS3850H12QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850KB
TPS3850H18QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850LB
TPS3850H25QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850MB
TPS3850H30QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850NB
TPS3850H33QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850PB
TPS3850H50QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
850RB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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