TPS3851
SBVS300A – NOVEMBER 2016 – REVISED SEPTEMBER 2021
TPS3851 Precision Voltage Supervisor with Integrated Watchdog Timer
1 Features
3 Description
•
•
•
•
•
•
The TPS3851 combines a precision voltage
supervisor with a programmable watchdog timer. The
TPS3851 comparator achieves a 0.8% accuracy
(–40°C to +125°C) for the undervoltage (VITN)
threshold on the VDD pin. The TPS3851 also includes
accurate hysteresis on the undervoltage threshold
making the device ideal for use with tight tolerance
systems. The supervisor RESET delay features a
15% accuracy, high-precision delay timing.
•
•
•
2 Applications
•
•
•
•
•
•
The TPS3851 includes a programmable watchdog
timer for a wide variety of applications. The dedicated
watchdog output (WDO) enables increased resolution
to help determine the nature of fault conditions.
The watchdog timeouts can be programmed either
by an external capacitor, or by factory-programmed
default delay settings. The watchdog can be disabled
via logic pins to avoid undesired watchdog timeouts
during the development process.
TPS3851 is available in a small 3.00-mm × 3.00-mm,
8-pin VSON package.
WLAN/Wi-Fi access point
Wireless security camera
IP network camera
String inverter
Blood pressure monitor
Electricity meter
Device Information
(1)
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
TPS3851
VSON (8)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
0.5
1.8 V
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
VDD
TPS3851
Microcontroller
VDD
SET1
RESET
WDO
MR
WDI
CWD
GND
RESET
Accuracy (%)
•
•
Input voltage range: VDD = 1.6 V to 6.5 V
0.8% Voltage threshold accuracy
Low quiescent current: IDD = 10 µA (typical)
User-programmable watchdog timeout
Open-drain outputs
Precision undervoltage monitoring:
– Supports common rails from 1.8 V to 5.0 V
– 4% and 7% Undervoltage thresholds available
– 0.5% Hysteresis
Watchdog disable feature
Factory-programmed precision watchdog and
reset timers
Manual reset input (MR)
Available in a small 3-mm × 3-mm, 8-Pin VSON
package
Junction operating temperature range:
–40°C to +125°C
0.1
-0.1
NMI
-0.3
GPIO
GND
Copyright © 2016, Texas Instruments Incorporated
Fully Integrated Microcontroller Supervisory
Circuit
-0.5
-50
-25
0
25
50
Temperature (qC)
75
100
125
Undervoltage Threshold (VITN) Accuracy vs
Temperature
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3851
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SBVS300A – NOVEMBER 2016 – REVISED SEPTEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Timing Diagrams......................................................... 7
6.8 Typical Characteristics................................................ 8
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 Receiving Notification of Documentation Updates.. 23
11.4 Support Resources................................................. 23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution.............................. 23
11.7 Glossary.................................................................. 23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (November 2016) to Revision A (September 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Removed "±15% Accurate WDT and RST Delays"............................................................................................ 1
• Added "on the VDD pin"..................................................................................................................................... 1
• Changed VESD values to ±4000 V and ±1000 V................................................................................................. 4
• Changed ICWD min and max spec ......................................................................................................................5
• Changed VCWD min and max spec .................................................................................................................... 5
• Added a footnote to for tINIT ............................................................................................................................... 6
• Updated tWDU min and max multipliers from 0.85 and 1.15 to 0.905 and 1.095 respectively...........................16
• Updated tWDU min and max values for all capacitors........................................................................................16
• Updated equation 6 and 7 to replace 0.85 and 1.15 with 0.905 and 1.095 respectively.................................. 19
2
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5 Pin Configuration and Functions
VDD
1
CWD
2
MR
3
GND
4
Thermal
Pad
8
RESET
7
WDO
6
WDI
5
SET1
Not to scale
Figure 5-1. DRB Package: TPS3851
3-mm × 3-mm VSON-8
Top View
Table 5-1. Pin Functions
NAME
NO.
I/O
DESCRIPTION
Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this pin and
ground. Connecting via a 10-kΩ resistor to VDD or leaving unconnected further enables the selection of the preset
watchdog timeouts; see the CWD Functionality section.
The TPS3851 determines the watchdog timeout using either Equation 1 or Equation 2 with standard or extended
timing, respectively.
CWD
2
I
GND
4
—
MR
3
I
Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains
low for a fixed reset delay (tRST) time after MR is deasserted (high).
Ground pin
RESET
8
O
Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). RESET goes
low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the
RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the
monitored voltage is within the correct operating range (above VITN+VHYST) and the RESET timeout is complete.
SET1
5
I
Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog timeouts; see
the SET1 section.
VDD
1
I
Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI
6
I
Watchdog input. A falling edge must occur at WDI before the timeout (tWD) expires.
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when RESET
or WDO are low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI cannot be left
unconnected and must be driven to either VDD or GND.
WDO
7
O
Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). WDO goes
low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout
occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a
high-impedance state.
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
Thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage range
VDD
–0.3
7
V
Output voltage range
RESET, WDO
–0.3
7
V
SET1, WDI, MR
–0.3
7
CWD
–0.3
VDD + 0.3 (3)
Voltage ranges
Output pin current
RESET, WDO
Input current (all pins)
Continuous total power dissipation
Temperature
(1)
(2)
(3)
V
±20
mA
±20
mA
See Section 6.4
Operating junction, TJ (2)
–40
150
Operating free-air, TA (2)
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Assume that TJ = TA as a result of the low dissipated power in this device.
The absolute maximum rating is VDD + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply pin voltage
VSET1
SET1 pin voltage
4
MAX
UNIT
1.6
6.5
V
0
6.5
V
(1) (2)
(1) (2)
nF
kΩ
CCWD
Watchdog timing capacitor
CWD
Pullup resistor to VDD
9
10
11
RPU
Pullup resistor, RESET and WDO
1
10
100
kΩ
IRESET
RESET pin current
10
mA
IWDO
Watchdog output current
10
mA
TJ
Junction temperature
125
°C
(1)
(2)
0.1
TYP
–40
1000
Using standard timing with a CCWD capacitor of 0.1 nF or 1000 nF gives a tWD(typ) of 0.704 ms or 3.23 seconds, respectively.
Using extended timing with a CCWD capacitor of 0.1 nF or 1000 nF gives a tWD(typ) of 62.74 ms or 77.45 seconds, respectively.
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6.4 Thermal Information
TPS3851
THERMAL METRIC
(1)
UNIT
DRB (VSON)
8 PINS
RθJA
Junction-to-ambient thermal resistance
50.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.6
°C/W
RθJB
Junction-to-board thermal resistance
25.8
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
25.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
at VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T A ≤ 125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩ for each output; typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL CHARACTERISTICS
VDD (1) (2) (3)
Supply voltage
IDD
Supply current
1.6
10
6.5
V
19
µA
0.8
V
RESET FUNCTION
VPOR (2)
Power-on reset voltage
VUVLO (1)
Undervoltage lockout voltage
VITN
Undervoltage threshold accuracy, entering
VDD falling
RESET
VHYST
Hysteresis voltage
VDD rising
0.2%
0.5%
0.8%
IMR
MR pin internal pullup current
VMR = 0 V
500
620
700
nA
nA
IRESET = 15 µA, VOL(MAX) = 0.25 V
1.35
VITN – 0.8%
V
VITN + 0.8%
WATCHDOG FUNCTION
ICWD
CWD pin charge current
VCWD
CWD pin threshold voltage
VOL
RESET, WDO output low
VDD = 5 V, ISINK = 3 mA
ID
RESET, WDO output leakage current,
open-drain
VDD = VITN + VHYST,
VRESET = VWDO = 6.5 V
VIL
Low-level input voltage ( MR, SET1)
VIH
High-level input voltage ( MR, SET1)
VIL(WDI)
Low-level input voltage (WDI)
VIH(WDI)
High-level input voltage (WDI)
(1)
(2)
(3)
CWD = 0.5 V
347
375
403
1.196
1.21
1.224
V
0.4
V
1
µA
0.25
V
0.8
V
0.3 × VDD
0.8 × VDD
V
V
When VDD falls below VUVLO, RESET is driven low.
When VDD falls below VPOR, RESET and WDO are undefined.
During power-on, VDD must be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD.
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6.6 Timing Requirements
at VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T A ≤ 125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩ for each output; typical values are at TA = 25°C
MIN
NOM
MAX UNIT
GENERAL
CWD pin evaluation period (1)
tINIT
Minimum MR, SET1 pin pulse duration
Startup delay
(2)
381
µs
1
µs
300
µs
RESET FUNCTION
tRST
Reset timeout period
tRST-DEL VDD to RESET delay
170
200
VDD = VITN + VHYST + 2.5%
35
VDD = VITN – 2.5%
17
tMR-DEL MR to RESET delay
230
ms
µs
200
ns
WATCHDOG FUNCTION
CWD = NC, SET1 = 0 (4)
CWD = NC, SET1 = 1
tWD
Watchdog timeout
(3)
(4)
CWD = 10 kΩ to VDD,
SET1 = 0 (4)
CWD = 10 kΩ to VDD,
SET1 = 1 (4)
tWD-
tWD-del
6
1360
1600
1840
ms
230
ms
Watchdog disabled
170
200
Setup time required for device to respond to changes on WDI after
being enabled
setup
(1)
(2)
(3)
(4)
Watchdog disabled
150
µs
Minimum WDI pulse duration
50
ns
WDI to WDO delay
50
ns
Refer to Section 8.1.1.2
During power-on, VDD must be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD
The fixed watchdog timing covers both standard and extended versions.
SET1 = 0 means VSET1 < VIL; SET1 = 1 means VSET1 > VIH.
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6.7 Timing Diagrams
VITN + VHYST
VDD
VITN
VPOR
tRST
VITN
tRST
tRST-DEL
RESET
t < tWD t = tWD (1)
t < tWD
WDI
X
X
WDO
tRST
A.
See Figure 6-2 for WDI timing requirements.
Figure 6-1. Timing Diagram
WDI
Correct
Operation
WDO
WDI
Late Fault
WDO
Timing
Valid
Region
tWD(MIN)
tWD(TYP)
tWD(MAX)
= Tolerance Window
Figure 6-2. Watchdog Timing Diagram
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6.8 Typical Characteristics
all typical characteristics curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless other wise noted)
0.7
Manual Reset Threshold (V)
Supply Current (PA)
16
12
8
-40qC
0qC
25qC
105qC
125qC
4
1
2
3
4
VDD (V)
5
6
0.5
0.4
0.3
-50
0
0
0.6
7
VIL
VIH
-25
0
25
50
Temperature (qC)
75
100
125
VDD = 1.6 V
Figure 6-3. Supply Current vs VDD
Figure 6-4. MR Threshold vs Temperature
0.5
380
Unit 3
Unit 4
Unit 5
Average
0.3
376
Accuracy (%)
CWD Charging Current (nA)
Unit 1
Unit 2
372
0.1
-0.1
368
-0.3
1.6 V
6.5 V
364
-50
-25
0
25
50
Temperature (qC)
75
100
-0.5
-50
125
-25
Figure 6-5. CWD Charging Current vs Temperature
0
25
50
Temperature (qC)
75
100
125
TPS3851G18, VITN = 1.728 V
Figure 6-6. VITN + VHYST Accuracy vs Temperature
0.5
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 1
Unit 2
Unit 5
Average
Accuracy (%)
Accuracy (%)
0.1
-0.1
0.1
-0.1
-0.3
-0.3
-25
0
25
50
Temperature (qC)
75
100
125
-0.5
-50
TPS3851G18, VITN = 1.728 V
-25
0
25
50
Temperature (qC)
75
100
125
TPS3851G50, VITN = 4.8 V
Figure 6-7. VITN Accuracy vs Temperature
8
Unit 5
Average
0.3
0.3
-0.5
-50
Unit 3
Unit 4
Figure 6-8. VITN + VHYST Accuracy vs Temperature
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6.8 Typical Characteristics (continued)
all typical characteristics curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless other wise noted)
50
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
45
0.3
40
Frequency (%)
Accuracy (%)
35
0.1
-0.1
30
25
20
15
-0.3
10
5
-0.5
-50
0
-25
0
25
50
Temperature (qC)
75
100
125
-0.8
TPS3851G50, VITN = 4.8 V
-0.6
-0.4 -0.2
0
0.2
0.4
VITN + VHYST Accuracy (%)
0.6
0.8
Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V
thresholds; total units = 36,627
Figure 6-9. VITN Accuracy vs Temperature
Figure 6-10. VITN + VHYST Accuracy Histogram
80
50
45
40
60
Frequency (%)
Frequency (%)
35
30
25
20
40
15
20
10
5
0
0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
VITN Accuracy (%)
0.6
0.8
0.2
0.5
Hysteresis (%)
0.8
Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V
thresholds; total units = 36,627
Includes G and H versions; 1.8-V, 2.5-V, 3.0-V, 3.3-V, and 5-V
thresholds; total units = 36,627
Figure 6-12. Hysteresis Histogram
Figure 6-11. VITN Accuracy Histogram
1.6
1.6
-40qC
0qC
25qC
105qC
125qC
1.4
1.2
-40qC
0qC
25qC
105qC
125qC
1.4
1.2
1
VOL (V)
1
VOL (V)
0.35
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
0
1
2
3
4
5
IRESET (mA)
3
IRESET (mA)
VDD = 1.6 V
VDD = 6.5 V
Figure 6-13. Low-Level RESET Voltage vs RESET Current
6
0
1
2
4
5
6
Figure 6-14. Low-Level RESET Voltage vs RESET Current
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6.8 Typical Characteristics (continued)
all typical characteristics curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless other wise noted)
50
100
-40qC
0qC
90
25qC
105qC
125qC
80
70
60
50
40
30
30
25
20
15
10
10
5
0
2
4
6
Overdrive (%)
8
0
10
0
2
TPS3851G18 entering undervoltage
4
6
Overdrive (%)
10
Figure 6-16. Propagation Delay vs Overdrive
210
210
-40qC
0qC
205
Propagation Delay (ms)
Propagation Delay (ms)
8
TPS3851G50 entering undervoltage
Figure 6-15. Propagation Delay vs Overdrive
200
195
-40qC
0qC
25qC
105qC
25qC
105qC
125qC
205
200
195
125qC
190
190
0
2
4
6
Overdrive (%)
8
10
0
2
TPS3851G18 exiting undervoltage
Figure 6-17. Propagation Delay (tRST) vs Overdrive
8
10
Figure 6-18. Propagation Delay (tRST) vs Overdrive
25
Overdrive = 3%
Overdrive = 5%
Overdrive = 7%
Overdrive = 3%
Overdrive = 5%
Overdrive = 7%
Overdrive = 9%
Overdrive = 10%
Glitch Immunity (Ps)
20
15
10
5
-50
4
6
Overdrive (%)
TPS3851G50 exiting undervoltage
25
Glitch Immunity (Ps)
125qC
35
20
0
-25
0
25
50
Temperature (qC)
75
100
125
Overdrive = 9%
Overdrive = 10%
20
15
10
5
-50
VITN = 1.728 V
-25
0
25
50
Temperature (qC)
75
100
125
VITN = 4.8 V
Figure 6-19. High-to-Low Glitch Immunity vs Temperature
10
25qC
105qC
40
Propagation Delay (Ps)
Propagation Delay (Ps)
-40qC
0qC
45
Figure 6-20. High-to-Low Glitch Immunity vs Temperature
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7 Detailed Description
7.1 Overview
The TPS3851 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes a
precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified temperature
range of –40°C to +125°C. In addition, the TPS3851 includes accurate hysteresis on the threshold, making the
device ideal for use with tight tolerance systems where voltage supervisors must ensure a RESET before the
minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached. There are two options
for the watchdog timing standard and extended timing. To get standard timing use the TPS3851Xyy(y)S, for
extended timing use the TPS3851Xyy(y)E.
7.2 Functional Block Diagram
VDD
R1
RESET
R2
Precision
Clock
Reference
VDD
CWD
WDO
State
Machine
Cap
Control
MR
A.
WDI
SET1
GND
Note: R1 + R2 = 4.5 MΩ.
7.3 Feature Description
7.3.1 RESET
Connect RESET to VPU through a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when
VDD is greater than the negative threshold voltage (VITN). If VDD falls below the negative threshold (VITN), then
RESET is asserted, driving the RESET pin to low impedance. When VDD rises above VITN + VHYST, a delay
circuit is enabled that holds RESET low for a specified reset delay period (tRST). When the reset delay has
elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The
pullup resistor must be connected to the proper voltage rail to allow other devices to be connected at the correct
interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor
values. The pullup resistor value is determined by output logic low voltage (VOL), capacitive loading, leakage
current (ID), and the current through the RESET pin IRESET.
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7.3.2 Manual Reset MR
The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and VDD is above VITN + VHYST, RESET is deasserted
after the reset delay time (tRST). If MR is not controlled externally, then MR can either be connected to VDD or left
floating because the MR pin is internally pulled up.
7.3.3 UV Fault Detection
The TPS3851 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is
monitored on the input rail of the device. If VDD drops below VITN, then RESET is asserted (driven low). When
VDD is above VITN + VHYST, RESET deasserts after tRST, as shown in Figure 7-1. The internal comparator has
built-in hysteresis that provides some noise immunity and ensures stable operation. Although not required in
most cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor
close to the VDD pin to reduce sensitivity to transient voltages on the monitored signal.
VDD
VITN + VHYST
tRST
tRST-DEL
RESET
VITN
tRST-DEL
Undervoltage Limit
Figure 7-1. Undervoltage Detection
7.3.4 Watchdog Mode
This section provides information for the watchdog mode of operation.
7.3.4.1 CWD
The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing
options and user-programmable watchdog timing. The TPS3851 features three options for setting the watchdog
timer: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the CWD pin
unconnected. The configuration of the CWD pin is evaluated by the device every time VDD enters the valid
region (VITN + VHYST < VDD). The pin evaluation is controlled by an internal state machine that determines which
option is connected to the CWD pin. The sequence of events typically takes 381 μs (tINIT) to determine if the
CWD pin is left unconnected, pulled-up through a resistor, or connected to a capacitor. If the CWD pin is being
pulled up to VDD, a 10-kΩ resistor is required.
7.3.4.2 Watchdog Input WDI
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge
of the input signal. To ensure proper functionality of the watchdog timer, always issue the WDI pulse before
tWD(min). If the pulse is issued in this region, then WDO remains unasserted. Otherwise, the device asserts WDO,
putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. To ensure there is no increase in IDD, drive the WDI pin to either VDD
or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD)
because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all
signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and
no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.
Figure 7-2 shows the valid region for a WDI pulse to be issued to prevent WDO from being triggered and pulled
low.
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WDI
Correct
Operation
WDO
WDI
Late Fault
WDO
Timing
Valid
Region
tWD(MIN)
tWD(TYP)
tWD(MAX)
= Tolerance Window
Figure 7-2. Watchdog Timing Diagram
7.3.4.3 Watchdog Output WDO
The TPS3851 features a watchdog timer with an independent watchdog output (WDO). The independent
watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an entire system
reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When asserted, WDO
remains low for tRST. When the RESET signal is asserted (low), the WDO pin goes to a high-impedance state.
When RESET is unasserted, the watchdog timer resumes normal operation.
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7.3.4.4 SET1
The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled
and WDI is ignored. If the watchdog timer is disabled, drive the WDI pin to either GND or VDD to ensure that
there is no increase in IDD. When SET1 is logic high, the watchdog operates normally. The SET1 pin can be
changed dynamically; however, if the watchdog is going from disabled to enabled there is a 150-µs setup time
where the watchdog does not respond to changes on WDI, as shown in Figure 7-3.
VDD
RESET
SET1
150 µs
Watchdog
Enabled/Disabled
Enabled
Disabled
Enabled
Figure 7-3. Enabling and Disabling the Watchdog
7.4 Device Functional Modes
Table 7-1 summarises the functional modes of the TPS3851.
Table 7-1. Device Functional Modes
VDD
WDO
RESET
VDD < VPOR
---
---
Undefined
VPOR ≤ VDD < VDD(min)
Ignored
High
Low
VDD(min) ≤ VDD ≤ VITN + VHYST
(1)
(2)
(3)
WDI
(1)
Ignored
High
Low
VDD > VITN (2)
tPULSE < tWD(min) (3)
High
High
VDD > VITN (2)
tPULSE > tWD(min) (3)
Low
High
Only valid before VDD has gone above VITN + VHYST.
Only valid after VDD has gone above VITN + VHYST.
Where tpulse is the time between the falling edges on WDI.
7.4.1 VDD is Below VPOR ( VDD < VPOR)
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely
depends on the load that the RESET pin is experiencing.
7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
When the voltage on VDD is less than VDD(min), and greater than or equal to VPOR, the RESET signal is asserted
(logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the
WDI signal that is input to the device.
7.4.3 Normal Operation (VDD ≥ VDD(min))
When VDD is greater than or equal to VDD(min), the RESET signal is determined by VDD. When RESET is
asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.
14
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The following sections describe in detail proper device implementation, depending on the final application
requirements.
8.1.1 CWD Functionality
The TPS3851 features three options for setting the watchdog timer: connecting a capacitor to the CWD pin,
connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. Figure 8-1 shows a schematic
drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected
(high impedance), then the factory-programmed watchdog timeouts are enabled; see the Section 8.1.1.1 section.
Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.
VDD
TPS3851
TPS3851
VDD
VDD
VDD
10 k
375 nA
VDD
TPS3851
VDD
375 nA
375 nA
CWD
CWD
CWD
CCWD
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
CWD
Unconnected
10 NŸ 5HVLVWRU
to VDD
Figure 8-1. CWD Charging Circuit
8.1.1.1 Factory-Programmed Timing Options
If using the factory-programmed timing options (listed in Table 8-1), the CWD pin must either be unconnected
or pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, 15% accurate
watchdog timing.
Table 8-1. Factory Programmed Watchdog Timing
INPUT
STANDARD AND EXTENDED TIMING WDT (tWD)
CWD
SET1
NC
0
NC
1
10 kΩ to VDD
0
10 kΩ to VDD
1
MIN
TYP
MAX
UNIT
Watchdog disabled
1360
1600
1840
ms
230
ms
Watchdog disabled
170
200
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8.1.1.2 Adjustable Capacitor Timing
Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected
to CWD, then a 375-nA, constant-current source charges CCWD until VCWD = 1.21 V. Table 8-2 shows how
to calculate tWD using Equation 1 and Equation 2 and the SET1 pin. The TPS3851 determines the watchdog
timeout with the formulas given in Equation 1 and Equation 2, where CCWD is in nanofarads and tWD is in
milliseconds.
tWD(standard) (ms) = 3.23 x CCWD (nF) + 0.381 (ms)
(1)
tWD(extended) (ms) = 77.4 x CCWD (nF) + 55 (ms)
(2)
The TPS3851 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that Equation 1
and Equation 2 are for ideal capacitors, capacitor tolerances vary the actual device timing. For the most accurate
timing, use ceramic capacitors with COG dielectric material. If a CCWD capacitor is used, Equation 1 can be
used to set tWD for standard timing. Use Equation 2 to calculate tWD for extended timing. Table 8-3 shows the
minimum and maximum calculated tWD values using an ideal capacitor for both the standard and extended
timing.
Table 8-2. Programmable CWD Timing
INPUT
STANDARD TIMING WDT (tWD)
CWD
SET1
CCWD
0
CCWD
(1)
(2)
1
MIN
TYP
EXTENDED TIMING WDT (tWD)
MAX
MIN
Watchdog disabled
tWD(std) × 0.905
tWD(std)
(1)
TYP
MAX
UNIT
Watchdog disabled
tWD(std) × 1.095
tWD(ext) × 0.905
tWD(ext) (2)
tWD(ext) × 1.095
ms
Calculated from Equation 1 using an ideal capacitor.
Calculated from Equation 2 using an ideal capacitor.
Table 8-3. tWD Values for Common Ideal Capacitor Values
CCWD
(1)
16
STANDARD TIMING WDT (tWD)
MIN(1)
100 pF
0.637
EXTENDED TIMING WDT (tWD)
UNIT
TYP
MAX(1)
MIN(1)
TYP
MAX(1)
0.704
0.771
56.77
62.74
68.7
ms
1 nF
3.268
3.611
3.954
119.82
132.4
144.98
ms
10 nF
29.58
32.68
35.79
750
829
908
ms
100 nF
292.7
323.4
354.1
7054
7795
8536
ms
1 μF
2923
3230
3537
70096
77455
84814
ms
The minimum and maximum values are calculated using an ideal capacitor.
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8.1.2 Overdrive Voltage
Forcing a RESET is dependent on two conditions: the amplitude VDD is beyond the trip point (ΔV1 and ΔV2), and
the length of time that the voltage is beyond the trip point (t1 and t2). If the voltage is just under the trip point for
a long period of time, RESET asserts and the output is pulled low. However, if VDD is just under the trip point for
a few nanoseconds, RESET does not assert and the output remains high. The length of time required for RESET
to assert can be changed by increasing the amount VDD goes under the trip point. If VDD is under the trip point
by 10%, the amount of time required for the comparator to respond is much faster and causes RESET to assert
much quicker than when barely under the trip point voltage. Equation 3 shows how to calculate the percentage
overdrive.
Overdrive = |((VDD / VITX) – 1) × 100% |
(3)
In Equation 3, VITX corresponds to the threshold trip point. If VDD is exceeding the positive threshold,
VITN + VHYST is used. VITN is used when VDD is falling below the negative threshold. In Figure 8-2, t1 and t2
correspond to the amount of time that VDD is over the threshold; the propagation delay versus overdrive for VITN
and VITN + VHYST is illustrated in Figure 6-16 and Figure 6-18, respectively.
The TPS3851 is relatively immune to short positive and negative transients on VDD because of the overdrive
voltage curve.
ûV1
Input Voltage
t1
VITN + VHYST
VDD
VITN
ûV2
t2
Time
Figure 8-2. Overdrive Voltage
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8.2 Typical Application
TPS3890
VDD
SENSE
MR
4.7 µF
100 k
RESET
CT
GND
MR
100 k
TPS3851
VDD
RESET
100 k
1.8 V
RESET
NMI
WDO
SET1
WDI
CWD
GND
2.7 nF
VCORE
Microcontroller
GPIO
GND
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Figure 8-3. Monitoring the Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Watchdog disable for initialization Watchdog must remain disabled for 5 seconds
period
until logic enables the watchdog timer
5.02 seconds (typ)
Output logic voltage
1.8-V CMOS
1.8V CMOS
Monitored rail
1.8 V with a 5% threshold
Worst-case VITN = 1.714 V – 4.7%
Watchdog timeout
10 ms typical
tWD(min) = 7.3 ms, tWD(TYP) = 9.1 ms, tWD(max) = 11 ms
Maximum device current
consumption
50 µA
37 µA when RESET or WDO is asserted (1)
(1)
Only includes the TPS3851G18S current consumption.
8.2.2 Detailed Design Procedure
8.2.2.1 Monitoring the 1.8-V Rail
The undervoltage comparator allows for precise voltage supervision of common rails between 1.8 V and 5.0 V.
This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure
this requirement is met, the TPS3851G18S was chosen for its –4% threshold. To calculate the worst-case for
VITN, the accuracy must also be taken into account. The worst-case for VITN can be calculated by Equation 4:
VITN(Worst Case) = VITN(typ) x 0.992 = 1.8 x 0.96 x 0.992 = 1.714 V
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8.2.2.2 Calculating RESET and WDO Pullup Resistor
The TPS3851 uses an open-drain configuration for the RESET circuit, as shown in Figure 8-4. When the FET
is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts
to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be
chosen to ensure that VOL is below the maximum value. To choose the proper pullup resistor, there are three
key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current
(IRESET), and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able
to bring the voltage on the reset pin below 0.4 V with IRESET kept below 10 mA. For this example, with a VPU of
1.8 V, a resistor must be chosen to keep IRESET below 50 μA because this value is the maximum consumption
current allowed. To ensure this specification is met, a pullup resistor value of 100 kΩ was selected, which sinks a
maximum of 18 μA when RESET or WDO is asserted. As illustrated in Figure 6-13, the RESET current is at
18 μA and the low-level output voltage is approximately zero.
VPU
RESET
RESET
CONTROL
Figure 8-4. RESET Open-Drain Configuration
8.2.2.3 Setting the Watchdog
As illustrated in Figure 8-1 there are three options for setting the watchdog timer. The design specifications
in this application require the programmable timing option (external capacitor connected to CWD). When a
capacitor is connected to the CWD pin, the watchdog timer is governed by Equation 1 for the standard timing
version. Note that only the standard version is capable of meeting this timing requirement. Equation 1 is only
valid for ideal capacitors, any temperature or voltage derating must be accounted for separately.
CCWD (nF) = (tWD(ms) – 0.0381) / 3.23 = (10 – 0.381) / 3.23 = 2.97 nF
(5)
The nearest standard capacitor value to 2.9 nF is 2.7 nF. Selecting 2.7 nF for the CCWD capacitor gives the
following minimum timing parameters:
tWD(MIN) = 0.905 x tWD(TYP) = 0.905 x (3.23 x 2.7 + 0.381) = 8.24 ms
(6)
tWD(MAX) = 1.095 x tWD(TYP) = 1.095 x (3.23 x 2.7 + 0.381) = 9.97 ms
(7)
Capacitor tolerance also influences tWD(MIN) and tWD(MAX). Select a ceramic COG dielectric capacitor for high
accuracy. For 2.7 nF, COG capacitors are readily available with 5% tolerances. This selection results in a 5%
decrease in tWD(MIN) and a 5% increase in tWD(MAX), giving 7.34 ms and 11 ms, respectively. To ensure proper
functionality, a falling edge must be issued before tWD(min). Figure 8-6 illustrates that a WDI signal with a period
of 5 ms keeps WDO from asserting.
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8.2.2.4 Watchdog Disabled During Initialization Period
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the
initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored
by the TPS3851. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a
TPS3890 supervisor. In this application, the TPS3890 was chosen to monitor VDD as well, which means that
the RESET on the TPS3890 stays low until VDD rises above VITN. When VDD comes up, the delay time can
be adjusted through the CT capacitor on the TPS3890. With this approach, the RESET delay can be adjusted
from a minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed
before the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an
ideal capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a
4.7-μF capacitor from CT to GND, the typical delay time is 5 seconds. Figure 8-5 shows that when the watchdog
is disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal, WDO
begins to assert. See the TPS3890 data sheet for detailed information on the TPS3890.
8.2.3 Glitch Immunity
Figure 8-8 shows the high-to-low glitch immunity for the TPS3851G18S with a 7% overdrive with VDD starting at
1.8 V. This curve shows that VDD can go below the threshold for at least 6 µs before RESET asserts.
8.2.4 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
VDD
2V/div
VDD
2V/div
6 seconds
SET1
2V/div
5ms
WDI
2V/div
WDO
2V/div
WDO
2V/div
RESET
2V/div
RESET
2V/div
1s/div
2ms/div
Figure 8-5. Startup Without a WDI Signal
VDD
500mV/div
Figure 8-6. Typical WDI Signal
VDD
500mV/div
6µs
WDO
2V/div
WDO
2V/div
195 ms
RESET
2V/div
RESET
2V/div
50ms/div
Figure 8-7. Typical RESET Delay
20
2µs/div
Figure 8-8. High-to-Low Glitch Immunity
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9 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
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10 Layout
10.1 Layout Guidelines
•
•
•
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
If a CCWD capacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If
the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
Place the pullup resistors on RESET and WDO as close to the pin as possible.
10.2 Layout Example
Vin
RPU1
CVDD
Vin
RPU2
Vin
CCWD
VDD
1
8
RESET
CWD
2
7
WDO
MR
3
6
WDI
GND
4
5
SET1
GND Plane
Denotes a via
Figure 10-1. TPS3851 Recommended Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature
DESCRIPTION
NOMENCLATURE
VALUE
TPS3851
(high-accuracy supervisor with watchdog)
—
—
G
VITN = –4%
H
VITN = –7%
18
1.8 V
25
2.5 V
30
3.0 V
33
3.3 V
50
5.0 V
S
tWD (ms) = 3.23 x CWD (nF) + 0.381 (ms)
E
tWD (ms) = 77.4 x CWD (nF) + 55.2 (ms)
X
(nominal threshold as a percent of the nominal
monitored voltage)
yy(y)
(nominal monitored voltage option)
z
(nominal watchdog timeout period)
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• TPS3890 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay (SLVSD65)
• TPS3851EVM-780 Evaluation Module (SBVU033)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3851G18EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851DD
TPS3851G18EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851DD
TPS3851G18SDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851DC
TPS3851G18SDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851DC
TPS3851G25EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851ED
TPS3851G25EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851ED
TPS3851G30EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851FD
TPS3851G30EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851FD
TPS3851G33EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851GD
TPS3851G33EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851GD
TPS3851G33SDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851GC
TPS3851G33SDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851GC
TPS3851G50EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851HD
TPS3851G50EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851HD
TPS3851G50SDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851HC
TPS3851G50SDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851HC
TPS3851H18EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851LD
TPS3851H18EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851LD
TPS3851H25EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851MD
TPS3851H25EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851MD
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
28-Sep-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3851H30EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851ND
TPS3851H30EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851ND
TPS3851H33EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851PD
TPS3851H33EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851PD
TPS3851H50EDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851RD
TPS3851H50EDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
851RD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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