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TPS3890
SLVSD65A – MARCH 2016 – REVISED MAY 2016
TPS3890
Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay
1 Features
3 Description
•
The TPS3890 is a precision voltage supervisor with
low-quiescent current that monitors system voltages
as low as 1.15 V, asserting an open-drain RESET
signal when the SENSE voltage drops below a preset
threshold or when the manual reset (MR) pin drops to
a logic low. The RESET output remains low for the
user-adjustable delay time after the SENSE voltage
and manual reset (MR) return above the respective
thresholds. The TPS3890 family uses a precision
reference to achieve 1% threshold accuracy. The
reset delay time can be user-adjusted between 40 μs
and 30 s by connecting the CT pin to an external
capacitor. The TPS3890 has a very low quiescent
current of 2.1 μA and is available in a small 1.5-mm ×
1.5-mm package, making the device well-suited for
battery-powered and space-constrained applications.
The device is fully specified over a temperature range
of –40°C to +125°C (TJ).
1
•
•
•
•
•
•
•
•
Power-On-Reset (POR) Generator with Adjustable
Delay Time: 40 μs to 30 s
Very Low Quiescent Current: 2.1 μA (Typical)
High Threshold Accuracy: 1% (max)
Precision Hysteresis
Fixed and Adjustable Threshold Voltages:
– Fixed Thresholds for Standard Rails:
1.2 V to 3.3 V
– Adjustable Down to 1.15 V
Manual Reset (MR) Input
Open-Drain RESET Output
Temperature Range: –40°C to +125°C
Package: 1.5-mm × 1.5-mm WSON
2 Applications
•
•
•
•
•
•
•
•
Device Information(1)
DSPs or Microcontrollers
FPGAs, ASICs
Notebooks, Desktop Computers
Smartphones, Hand-Held Products
Portable, Battery-Powered Products
Solid-State Drives
Set-Top Boxes
Industrial Control Systems
PART NUMBER
TPS3890
PACKAGE
WSON (6)
BODY SIZE (NOM)
1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
VITN Accuracy vs Temperature
0.75
1.8 V
Unit 1
Unit 2
1.2 V
0.5
SENSE
VCORE
VI/O
MR
TPS389012
Microcontroller
RESET
RESET
CT
GND
GND
Accuracy (%)
VDD
Unit 3
Unit 4
Unit 5
Avg
0.25
0
-0.25
-0.5
Copyright © 2016, Texas Instruments Incorporated
-0.75
-50
-25
0
25
50
Temperature (qC)
75
100
125
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3890
SLVSD65A – MARCH 2016 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision A
•
2
Page
Released to production........................................................................................................................................................... 1
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5 Device Comparison Table
PART NUMBER
NOMINAL SUPPLY VOLTAGE
NEGATIVE THRESHOLD (VITN)
POSITIVE THRESHOLD (VITP)
TPS389001
Adjustable
1.15 V
1.157 V
TPS389012
1.2 V
1.15 V
1.157 V
TPS389015
1.5 V
1.44 V
1.449 V
TPS389018
1.8 V
1.73 V
1.740 V
TPS389020
2.0 V
1.90 V
1.911 V
TPS389025
2.5 V
2.40 V
2.414 V
TPS389030
3.0 V
2.89 V
2.907 V
TPS389033
3.3 V
3.17 V
3.189 V
6 Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
SENSE
1
6
RESET
GND
2
5
CT
MR
3
4
VDD
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
5
CT
—
The CT pin offers a user-adjustable delay time. Connecting this pin to a ground-referenced capacitor sets
the RESET delay time to deassert.
tPD(r) (sec) = CCT (µF) × 1.07 + 25 µs (nom).
2
GND
—
Ground
3
MR
I
Driving the manual reset pin (MR) low causes RESET to go low (assert).
6
RESET
O
RESET is an open-drain output that is driven to a low-impedance state when either the MR pin is driven to
a logic low or the monitored voltage on the SENSE pin is lower than the negative threshold voltage (VITN).
RESET remains low (asserted) for the delay time period after both MR is set to a logic high and the
SENSE input is above VITP. A pullup resistor from 10 kΩ to 1 MΩ can be used on this pin.
1
SENSE
I
This pin is connected to the voltage to be monitored. When the voltage on SENSE falls below the
negative threshold voltage VITN, RESET goes low (asserts). When the voltage on SENSE rises above the
positive threshold voltage VITP, RESET goes high (deasserts).
4
VDD
I
Supply voltage pin. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Voltage
Current
Temperature
(1)
MIN
MAX
VDD
–0.3
7
SENSE
–0.3
7
RESET
–0.3
7
MR
–0.3
7
VCT
–0.3
7
RESET
–20
20
Operating junction temperature, TJ
–40
125
Storage temperature, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Power-supply voltage
1.5
5.5
V
VSENSE
SENSE voltage
0
5.5
V
VRESET
RESET pin voltage
0
5.5
V
IRESET
RESET pin current
–5
CIN
Input capacitor, VDD pin
0
CCT
Reset timeout capacitor, CT pin
0
RPU
Pullup resistor, RESET pin
TJ
Junction temperature (free-air temperature)
5
0.1
1
–40
25
mA
µF
22
µF
1000
kΩ
125
℃
7.4 Thermal Information
TPS3890
THERMAL METRIC (1)
DSE (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
321.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
207.9
°C/W
RθJB
Junction-to-board thermal resistance
281.5
°C/W
ψJT
Junction-to-top characterization parameter
42.4
°C/W
ψJB
Junction-to-board characterization parameter
284.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
142.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted); typical values are at VDD = 5.5 V and TJ = 25°C
PARAMETER
VDD
Input supply voltage
VPOR
Power-on reset voltage
TEST CONDITIONS
MIN
VOL(max) = 0.2 V, IRESET = 15 µA
VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 85°C
IDD
Supply current (into VDD pin)
VITN, VITP
ISENSE
Input current
ICT
CT pin charge current
VCT
CT pin comparator threshold voltage
RCT
CT pin pulldown resistance
VIL
Low-level input voltage (MR pin)
VIH
High-level output voltage
Low-level output voltage
ILKG(OD)
(1)
Open-drain output leakage
0.8
V
3.72
5.8
2.29
µA
4
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 105°C
5.2
VDD = 5.5 V, IRESET = 0 mA
6.5
–1%
±0.5%
1%
0.325%
0.575%
0.825%
VSENSE = 5 V
VOL
V
VDD= 3.3 V, IRESET = 0 mA
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 85°C
UNIT
5.5
4.5
(1)
Hysteresis
2.09
MAX
VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 105°C
SENSE input threshold voltage
accuracy
VHYST
TYP
1.5
8
µA
10
100
nA
0.90
1.15
1.35
µA
1.17
1.23
1.29
VSENSE = 5 V, TPS389001,
TPS389012
When RESET is deasserted
V
Ω
200
0.25 × VDD
V
0.7 x VDD
V
VDD ≥ 1.5 V, IRESET = 0.4 mA
0.25
VDD ≥ 2.7 V, IRESET = 2 mA
0.25
VDD ≥ 4.5 V, IRESET = 3 mA
0.3
High impedance,
VSENSE = VRESET = 5.5 V
250
V
nA
VHYST = [(VITP – VITN) / VITN] × 100%.
7.6 Timing Requirements
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, MR = VDD, and 5% input overdrive (1)
(unless otherwise noted); typical values are at VDD = 5.5 V and TJ = 25°C
MIN
NOM
MAX
UNIT
CT = open, VDD = 3.3 V
18
CT = open, VDD = 5.5 V
8
25
µs
µs
tPD(f)
SENSE (falling) to RESET propagation delay
tPD(r)
SENSE (rising) to RESET propagation delay
CT = open, VDD = 3.3 V
tGI(SENSE)
SENSE pin glitch immunity
VDD = 5.5 V
9
tGI(MR)
MR pin glitch immunity
VDD = 5.5 V
100
tMRW
MR pin pulse duration to assert RESET
td(MR)
MR pin low to out delay
250
ns
tSTRT
Startup delay
325
µs
(1)
1
µs
ns
µs
Overdrive = | (VIN / VTHRESH – 1) × 100% |.
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VDD
0.8 V
RESET
tPD(f) =SENSE Falling Propagation Delay
tPD(r) =SENSE Rising Propagation Delay
tPD(r)
tPD(r)
tPD(f)
td(MR)
= Undefined State
SENSE
VITP
VITN
MR
0.7 VDD
0.3 VDD
Time
Figure 1. Timing Diagram
6
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7.7 Typical Characteristics
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
0.75
0.75
Unit 1
Unit 2
Unit 5
Avg
0.25
0
-0.25
-0.25
-0.5
-25
0
25
50
Temperature (qC)
75
100
-0.75
-50
125
-25
0
D001
Figure 2. VITN Accuracy vs Temperature
25
50
Temperature (qC)
75
100
125
D002
Figure 3. VITP Accuracy vs Temperature
12
10
10
8
8
Frequency (%)
Frequency (%)
Unit 5
Avg
0
12
6
4
2
0
-0.25
Unit 3
Unit 4
0.25
-0.5
-0.75
-50
Unit 1
Unit 2
0.5
Accuracy (%)
Accuracy (%)
0.5
Unit 3
Unit 4
6
4
2
-0.15
-0.05
0.05
VITN Accuracy (%)
0.15
0
-0.25
0.25
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
-0.15
-0.05
0.05
VITP Accuracy (%)
0.15
0.25
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
Figure 4. VITN Accuracy Histogram
Figure 5. VITP Accuracy Histogram
15
1.2
1.5 V
5.5 V
12
CT Current (PA)
Frequency (%)
1.15
9
6
1.05
3
0
0.47
1.1
0.51
0.55
0.59
Hysteresis (%)
0.63
0.67
1
-50
-25
0
25
50
Temperature (qC)
75
100
125
D005
Tested at VDD = 1.5 V and VDD = 5.5 V, total tests = 136,348
Figure 6. Hysteresis Histogram
Figure 7. CT Current vs Temperature
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Typical Characteristics (continued)
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
6
6
-40qC
0qC
105qC
125q
-40qC
0qC
5
Supply Current (PA)
Supply Current (PA)
5
25qC
85qC
4
3
2
1
25qC
85qC
105qC
125qC
4
3
2
1
0
0
0
0.5
1
1.5
2
2.5
3
VDD (V)
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
D003
MR = VDD
2.5
3
VDD (V)
3.5
4
4.5
5
5.5
D004
MR = 0 V
Figure 8. Supply Current vs Power-Supply Voltage
Figure 9. Supply Current vs Power-Supply Voltage
3
1
VIL
VIH
VIL
VIH
-25
0
2.75
2.5
MR Threshold (V)
MR Threshold (V)
0.75
0.5
2.25
2
1.75
1.5
0.25
1.25
0
-50
-25
0
25
50
Temperature (qC)
75
100
1
-50
125
D006
100
125
Figure 11. MR Threshold vs Temperature
Figure 10. MR Threshold vs Temperature
600
34
VCC = 1.5 V
VCC = 3.3 V
VCC = 5.5 V
-40qC
0qC
Propagation Delay (Ps)
500
Startup Delay (Ps)
75
VDD = 5.5 V
VDD = 1.5 V
400
300
200
25qC
85qC
125qC
33
32
31
30
100
0
-50
25
50
Temperature (qC)
29
-25
0
25
50
Temperature (qC)
75
100
125
1
10
Overdrive (%)
D008
100
D009
VDD = 5.5 V
Figure 12. Startup Delay vs Temperature
8
Figure 13. Propagation Delay (tPD(r)) vs Overdrive
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Typical Characteristics (continued)
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
34
34
25qC
85qC
125qC
-40qC
0qC
30
33
Propagation Delay (Ps)
Propagation Delay (Ps)
-40qC
0qC
32
31
25qC
85qC
125qC
26
22
18
14
10
30
6
29
2
1
10
Overdrive (%)
100
1
10
Overdrive (%)
D010
VDD = 1.5 V
Figure 15. Propagation Delay (tPD(f)) vs Overdrive
34
32
-40qC
0qC
25qC
85qC
125qC
SENSE Glitch Immunity (Ps)
30
Propagation Delay (Ps)
D011
VDD = 5.5 V
Figure 14. Propagation Delay (tPD(r)) vs Overdrive
26
22
18
14
10
6
1
10
Overdrive (%)
100
Overdrive=3%
Overdrive=5%
Overdrive=10%
31.5
31
30.5
30
29.5
29
-50
2
-25
0
D012
25
50
Temperature (qC)
75
100
125
VDD = 5.5 V
VDD = 1.5 V
Figure 17. Low-to-High Glitch Immunity vs Temperature
Figure 16. Propagation Delay (tPD(f)) vs Overdrive
20
32
Overdrive=3%
Overdrive=5%
Overdrive=10%
31.5
31
30.5
30
29.5
Overdrive=3%
Overdrive=5%
Overdrive=10%
18
SENSE Glitch Immunity (Ps)
SENSE Glitch Immunity (Ps)
100
16
14
12
10
8
6
4
2
29
-50
-25
0
25
50
Temperature (qC)
75
100
125
0
-50
VDD = 1.5 V
-25
0
25
50
Temperature (qC)
75
100
125
D017
VDD = 5.5 V
Figure 18. Low-to-High Glitch Immunity vs Temperature
Figure 19. High-to-Low Glitch Immunity vs Temperature
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Typical Characteristics (continued)
over the operating junction temperature range of –40°C to +125°C, 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise
noted)
1.6
20
Overdrive=3%
Overdrive=5%
Overdrive=10%
16
-40qC
0qC
1.4
25qC
85qC
105qC
125qC
1.2
14
1
12
VOL (V)
SENSE Glitch Immunity (Ps)
18
10
8
0.8
0.6
6
0.4
4
0.2
2
0
-50
0
-25
0
25
50
Temperature (qC)
75
100
0
125
1
2
3
IRESET (mA)
D018
VDD = 1.5 V
4
5
D015
VDD = 5.5 V
Figure 20. High-to-Low Glitch Immunity vs Temperature
Figure 21. Low-Level Output Voltage vs RESET Current
1.6
-40qC
0qC
1.4
25qC
85qC
105qC
125qC
1.2
VOL (V)
1
0.8
0.6
0.4
0.2
0
0
1
2
3
IRESET (mA)
4
5
VDD = 1.5 V
Figure 22. Low-Level Output Voltage vs RESET Current
10
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8 Detailed Description
8.1 Overview
The TPS3890 supervisory product family is designed to assert a RESET signal when either the SENSE pin
voltage drops below VITN or the manual reset (MR) is driven low. The RESET output remains asserted for a useradjustable time after both the manual reset (MR) and SENSE voltages return above their respective thresholds.
8.2 Functional Block Diagram
VDD
VDD
TPS389001
Adjustable Version
RESET
MR
RESET
MR
SENSE
Reset
Logic
Timer
Reset
Logic
Timer
R1
SENSE
CT
CT
R2
1.15 V
1.15 V
VREF
VREF
GND
GND
Adjustable Voltage Version
Fixed Voltage Version
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8.3 Feature Description
The combination of user-adjustable reset delay time with a broad range of threshold voltages allow these devices
to be used in a wide array of applications. Fixed negative threshold voltages (VITN) can be factory set from 1.15 V
to 3.17 V (see the Device Comparison Table for available options), and the adjustable device can be used to
customize the threshold voltage for other application needs by using an external resistor divider. The CT pin
allows the reset delay to be set between 25 μs and 30 s with the use of an external capacitor.
8.3.1 User-Configurable RESET Delay Time
The rising RESET delay time (tPD(r)) can be configured by installing a capacitor connected to the CT pin. The
TPS3890 uses a CT pin charging current (ICT) of 1.15 µA to help counter the effect of capacitor and board-level
leakage currents that can be substantial in certain applications. The rising RESET delay time can be set to any
value between 25 µs (no CCT installed) and 30 s (CCT = 26 µF).
The capacitor value needed for a given delay time can be calculated using Equation 1:
tPD(r) (sec) = CCT × VCT ÷ ICT+ tPD(r)(nom)
(1)
The slope of Equation 1 is determined by the time that the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged
through the internal CT pulldown resistor (RCT). When the RESET conditions are cleared, the internal precision
current source is enabled and begins to charge the external capacitor and when the voltage on this capacitor
reaches 1.22 V, RESET is deasserted. Note that in order to minimize the difference between the calculated
RESET delay time and the actual RESET delay time, use a low-leakage type capacitor (such as a ceramic
capacitor) and minimize parasitic board capacitance around this pin.
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Feature Description (continued)
8.3.2 Manual Reset (MR) Input
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and SENSE is above VITP, RESET is deasserted after
the user-defined reset delay. If MR is not controlled externally, then MR must be connected to VDD. Note that if
the logic signal driving MR is not greater than or equal to VDD, then some additional current flows into VDD and
out of MR and the difference is apparent when comparing Figure 8 and Figure 9.
Figure 23 shows how MR can be used to monitor multiple system voltages when only a single CT capacitor is
needed to set the RESET delay time.
1.2 V
3.3 V
SENSE
VDD
SENSE VDD
TPS389012
TPS389033
V I/O
V CORE
3.3 V
MR
CT
RESET
GND
MR
CT
RESET
GND
DSP
GPIO
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Using MR to Monitor Multiple System Voltages
8.3.3 RESET Output
RESET remains high (deasserted) as long as SENSE is above the positive threshold (VITP) and the manual reset
signal (MR) is logic high. If SENSE falls below the negative threshold (VITN) or if MR is driven low, then RESET is
asserted, driving the RESET pin to a low impedance.
When MR is again logic high and SENSE is above VITP, a delay circuit is enabled that holds RESET low for a
specified reset delay period (tPD(r)). When the reset delay has elapsed, the RESET pin goes to a high-impedance
state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to
enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled
up to any voltage up to 5.5 V, independent of the device supply voltage. To ensure proper voltage levels, give
some consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, the
output capacitive loading, and the output leakage current (ILKG(OD)).
8.3.4 SENSE Input
The SENSE input can vary from ground to 5.5 V (7.0 V, absolute maximum), regardless of the device supply
voltage used. The SENSE pin is used to monitor the critical voltage rail. If the voltage on this pin drops below
VITN, then RESET is asserted. When the voltage on the SENSE pin exceeds the positive threshold voltage,
RESET deasserts after the user-defined RESET delay time.
The internal comparator has built-in hysteresis to ensure well-defined RESET assertions and deassertions even
when there are small changes on the voltage rail being monitored.
The TPS3890 device is relatively immune to short transients on the SENSE pin. Glitch immunity is dependent on
threshold overdrive, as illustrated in Figure 19 for VITN and Figure 18 for VITP. Although not required in most
cases, for noisy applications good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the
SENSE input to reduce sensitivity to transient voltages on the monitored signal.
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Feature Description (continued)
The adjustable version (TPS389001) can be used to monitor any voltage rail down to 1.15 V using the circuit
shown in Figure 24.
VIN
VMON
VDD
MR
R1
TPS389001
RPU
SENSE
R2
RESET
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Using the TPS389001 to Monitor a User-Defined Threshold Voltage
The target threshold voltage for the monitored supply (VITx(MON)) and the resistor divider values can be calculated
by using Equation 2 and Equation 3, respectively:
VITx(MON)= VITx × (1 + R1 ÷ R2)
(2)
Equation 3 can be used to calculate either the negative threshold or the positive threshold by replacing VITx with
either VITN or VITP, respectively.
RTOTAL = R1 + R2
(3)
Resistors with high values minimize current consumption; however, the input bias current of the device degrades
accuracy if the current through the resistors is too low. Therefore, choosing an RTOTAL value so that the current
through the resistor divider is at least 100 times larger than the SENSE input current is simplest. See application
report Optimizing Resistor Dividers at a Comparator Input (SLVA450) for more details on sizing input resistors.
8.3.4.1 Immunity to SENSE Pin Voltage Transients
The TPS3702 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and overdrive (amplitude) of the transient. Overdrive is defined by how much VSENSE
exceeds the specified threshold, and is important to know because the smaller the overdrive, the slower the
response of the outputs (that is, undervoltage and overvoltage). Threshold overdrive is calculated as a percent of
the threshold in question, as shown in Equation 4.
Overdrive = | (VSENSE / VITx – 1) × 100% |
(4)
Figure 17 to Figure 20 illustrate the glitch immunity that the TPS3890 has versus temperature with three different
overdrive voltages. The propagation delay versus overdrive curves (Figure 13 to Figure 16) can be used to
determine how sensitive the TPS3890 family of devices are across an even wider range of overdrive voltages.
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8.4 Device Functional Modes
Table 1 summarizes the various functional modes of the device.
Table 1. Truth Table
(1)
VDD
MR
SENSE
RESET
VDD < VPOR
—
—
Undefined
VPOR < VDD < VDD(MIN) (1)
—
—
L
L
VDD ≥ VDD(MIN)
L
—
VDD ≥ VDD(MIN)
H
VSENSE < VITN
L
VDD ≥ VDD(MIN)
H
VSENSE > VITP
H
When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and RESET is held low until VDD falls below VPOR.
8.4.1 Normal Operation (VDD > VDD(min))
When VDD is greater than VDD(min), the RESET signal is determined by the voltage on the SENSE pin and the
logic state of MR.
• MR high: when the voltage on VDD is greater than 1.5 V, the RESET signal corresponds to the voltage on
the SENSE pin relative to the threshold voltage.
• MR low: in this mode, RESET is held low regardless of the voltage on the SENSE pin.
8.4.2
Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage (VPOR),
the RESET signal is asserted regardless of the voltage on the SENSE pin.
8.4.3 Below Power-On-Reset (VDD < VPOR)
When the voltage on VDD is lower thanVPOR, the device does not have enough voltage to internally pull the
asserted output low and RESET is undefined and must not be relied upon for proper device function.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
A typical application for the TPS389018 is shown in Figure 25. The TPS389018 can be used to monitor the 1.8-V
VDD rail required by the TI Delfino™ microprocessor family. The open-drain RESET output of the TPS389018 is
connected to the XRS input of the microprocessor. A reset event is initiated when the VDD voltage is less than
VITN or when MR is driven low by an external source.
1.8 V
SENSE VDD
TPS389018
External
Reset
MR
CT
1.5 nF
RESET
3.3 V
1 MW
VDD
Delfino MCU
XRS
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 25. TPS3890 Monitoring the Supply Voltage for a Delfino Microprocessor
9.2.1 Design Requirements
The TPS3890 RESET output can be used to drive the reset (XRS) input of a microprocessor. The RESET pin of
the TPS3890 is pulled high with a 1-MΩ resistor; the reset delay time is controlled by the CT capacitor and is set
depending on the reset requirement times of the microprocessor. During power-up, XRS must remain low for at
least 1 ms after VDD reaches 1.5 V for the C2000™ Delfino family of microprocessors. For 100-MHz operation,
the Delfino TMS320F2833x microcontroller uses a supply voltage of 1.8 V that must be monitored by the
TPS3890.
9.2.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS389018 has a negative threshold of 1.73 V and a positive threshold of 1.74 V, making
the device suitable for monitoring a 1.8-V rail. The secondary constraint for this application is the reset delay time
that must be at least 1 ms to allow the Delfino microprocessor enough time to startup up correctly. Because a
minimum time is required, the worst-case scenario is a supervisor with a high CT charging current (ICT) and a low
CT comparator threshold (VCT). For applications with ambient temperatures ranging from –40°C to +125°C, CCT
can be calculated using ICT(Max), VCT(MIN), and solving for CCT in Equation 1 such that the minimum capacitance
required at the CT pin is 1.149 nF. If standard capacitors with ±20% tolerances are used, then the CT capacitor
must be 1.5 nF or larger to ensure that the 1-ms delay time is met.
A 0.1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice and a 1-MΩ
resistor is used as the RESET pullup resistor to minimize the current consumption when RESET is asserted. The
MR pin can be connected to an external signal if desired or connected to VDD if not used.
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Typical Application (continued)
9.2.3 Application Curve
600
VCC = 1.5 V
VCC = 3.3 V
VCC = 5.5 V
Startup Delay (Ps)
500
400
300
200
100
0
-50
-25
0
25
50
Temperature (qC)
75
100
125
D008
Figure 26. Startup Delay vs Temperature
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.5 V and 5.5 V. An
input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device has a 7-V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 7 V, additional precautions must be taken.
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11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1µF ceramic capacitor near the VDD pin. If a capacitor is not connected to the CT pin, then minimize parasitic
capacitance on this pin so the RESET delay time is not adversely affected.
11.2 Layout Example
The layout example in shows how the TPS3890 is laid out on a printed circuit board (PCB) with a user-defined
delay.
RPU
SENSE
RESET
CCT
GND
CT
MR
VDD
CIN
GND
Vias used to connect pins for application-specific connections
Figure 27. Recommended Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
The following related documents are available for download at www.ti.com:
• Optimizing Resistor Dividers at a Comparator Input, SLVA450
• Sensitivity Analysis for Power Supply Design, SLVA481
• Getting Started With TMS320C28x Digital Signal Controllers, SPRAAM0
• TPS3890EVM-775 Evaluation Module User Guide, SBVU030
• C2000 Delfino Family of Microprocessors
• TMS320F2833x microcontroller, SPRS439
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
Delfino, C2000, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS389001DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2V
TPS389001DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2V
TPS389012DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2W
TPS389012DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2W
TPS389015DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2X
TPS389015DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2X
TPS389018DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2Y
TPS389018DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2Y
TPS389020DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2Y
TPS389020DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2Y
TPS389025DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2Z
TPS389025DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
2Z
TPS389030DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
3A
TPS389030DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
3A
TPS389033DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
3B
TPS389033DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
3B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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