Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
TPS389x Single-Channel, Adjustable Voltage Monitor in Ultra-Small Package
1 Features
3 Description
•
•
•
•
•
•
•
The TPS3895, TPS3896, TPS3897, and TPS3898
devices (TPS389x) are a family of very small
supervisory circuits that monitor voltages greater than
500 mV with a 0.25% (typical) threshold accuracy
and offer adjustable delay time using external
capacitors. The TPS389x family also has a logic
enable pin (ENABLE or ENABLE) to power on and off
the output. With the TPS3895, for example, when the
input voltage pin (SENSE) rises above the threshold,
and the ENABLE pin is high, then the output pin
(SENSE_OUT) goes high after the capacitoradjustable delay time. When SENSE falls below the
threshold or ENABLE is low, then SENSE_OUT goes
low. For truth tables, see Table 1 and Table 2.
1
•
•
Very Small USON (1.45 mm × 1.00 mm) Package
Adjustable Threshold Down to 500 mV
Threshold Accuracy: 1% Over Temperature
Capacitor-Adjustable Delay Time
Low Quiescent Current: 6 µA (Typical)
External Enable Input
Open-Drain (Rated at 18 V) and Push-Pull Output
Options
Temperature Range: –40°C to 125°C
Pin-for-Pin Compatible With MAX6895/6/7/8
2 Applications
•
•
•
•
•
For TPS389xA versions, both SENSE and ENABLE
have a capacitor-adjustable delay. The output asserts
after this capacitor-adjustable delay when both
SENSE and ENABLE inputs are good. The
TPS389xP devices have a small, 0.2-µs propagation
delay from when the enable pin asserts to when the
output pin asserts, provided SENSE is above the
threshold.
DSPs, Microcontrollers, and Microprocessors
Notebook and Desktop Computers
PDAs and Handheld Products
Portable and Battery-Powered Products
FPGAs and ASICs
All devices operate from 1.7 V to 6.5 V and have a
typical quiescent current of 6 µA with an open-drain
output rated at 18 V. The TPS389x is available in an
ultra-small USON package and is fully specified over
the temperature range of TJ = –40°C to 125°C.
Device Information(1)
PART NUMBER
TPS389x
PACKAGE
USON (6)
BODY SIZE (NOM)
1.45 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Sense Threshold Voltage vs Temperature
507
VCC = 1.7 V, VIT+
VCC = 3.3 V, VIT+
VCC = 6.5 V, VIT+
VCC = 1.7 V, VIT+ − VHYS
VCC = 3.3 V, VIT+ − VHYS
VCC = 6.5 V, VIT+ − VHYS
VIT+, VIT+ − VHYS (mV)
505
503
501
499
497
495
493
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
G004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
9
Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
9.2 Typical Applications ................................................ 16
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision A (September 2011) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed paragraph 1 of Description section; revised for clarification .................................................................................. 1
•
Changed Pin Configuration and Functions section; updated table format, renamed pin packages to meet new
standards ............................................................................................................................................................................... 4
2
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
5 Device Comparison Table
DEVICE
ENABLE
OUTPUT
INPUT (SENSE) DELAY
ENABLE DELAY
TPS3895A
Active high
Active high, push-pull
Capacitor adjustable
Capacitor adjustable
TPS3895P
Active high
Active high, push-pull
Capacitor adjustable
0.2 µs
TPS3896A
Active low
Active low, push-pull
Capacitor adjustable
Capacitor adjustable
TPS3896P
Active low
Active low, push-pull
Capacitor adjustable
0.2 µs
TPS3897A
Active high
Active high, open drain
Capacitor adjustable
Capacitor adjustable
TPS3897P
Active high
Active high, open drain
Capacitor adjustable
0.2 µs
TPS3898A
Active low
Active low, open drain
Capacitor adjustable
Capacitor adjustable
TPS3898P
Active low
Active low, open drain
Capacitor adjustable
0.2 µs
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
3
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
6 Pin Configuration and Functions
DRY Package: TPS3895, TPS3897
6-Pin USON
Top View
ENABLE
1
6
VCC
GND
2
5
CT
SENSE
3
4
SENSE_OUT
DRY Package: TPS3896, TPS3898
6-Pin USON
Top View
ENABLE
1
6
VCC
GND
2
5
CT
SENSE
3
4
SENSE_OUT
Pin Functions
PIN
USON
NAME
CT
TPS3895/
TPS3897
5
ENABLE
1
I/O
DESCRIPTION
I
Capacitor-adjustable delay. The CT pin offers a user-adjustable delay time. Connecting
this pin to a ground referenced capacitor sets the delay time for SENSE rising above
0.5 V to SENSE_OUT asserting (or ENABLE asserting to SENSE_OUT asserting for A
version devices).
tpd(r) (s) = [CCT (µF) × 4] + 40 µs
I
Active high input. Driving ENABLE low immediately makes SENSE_OUT go low,
independent of V(SENSE). With V(SENSE) already above VIT+, drive ENABLE high to
make SENSE_OUT go high after the capacitor-adjustable delay time (A version) or 0.2
µs (P version).
Active low input. Driving ENABLE high immediately makes SENSE_OUT go high,
independent of V(SENSE). With V(SENSE) already above VIT+, drive ENABLE low to make
SENSE_OUT go low after the capacitor-adjustable delay time (A version) or 0.2 µs (P
version).
TPS3896/
TPS3898
5
—
ENABLE
—
1
I
GND
2
2
—
SENSE
3
3
I
This pin is connected to the voltage that is monitored with the use of an external
resistor. The output asserts after the capacitor-adjustable delay time when V(SENSE)
rises above 0.5 V and ENABLE is asserted. The output deasserts after a minimal
propagation delay (16 µs) when V(SENSE) falls below VIT+ – Vhys.
O
SENSE_OUT is an open-drain and push-pull output that is immediately driven low after
V(SENSE) falls below (VIT+ – Vhys) or the ENABLE input is low. SENSE_OUT goes high
after the capacitor-adjustable delay time when V(SENSE) is greater than VIT+ and the
ENABLE pin is high. Open-drain devices (TPS3897/8) can be pulled up to 18 V
independent of VCC; pullup resistors are required for these devices.
SENSE_OUT
4
—
Ground
SENSE_OUT
—
4
O
SENSE_OUT is an open-drain and push-pull output that is immediately driven high
after V(SENSE) falls below (VIT+ – Vhys) or the ENABLE input is high. SENSE_OUT goes
low after the capacitor-adjustable delay time when V(SENSE) is greater than VIT+ and the
ENABLE pin is low. Open-drain devices (TPS3897/8) can be pulled up to 18 V
independent of VCC; pullup resistors are required for these devices.
VCC
6
6
I
Supply voltage input. Connect a 1.7-V to 6.5-V supply to VCC to power the device. It is
good analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
4
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
Voltage (2)
Current
(2)
MAX
–0.3
7
CT
–0.3
VCC + 0.3
ENABLE, SENSE, SENSE_OUT (push-pull)
–0.3
7
SENSE_OUT (open drain)
–0.3
20
SENSE_OUT (push-pull)
–0.3
UNIT
V
7
SENSE_OUT
Temperature
(1)
MIN
VCC
±10
Operating junction, TJ
–40
125
Storage, Tstg
–65
150
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Input supply voltage
1.7
6.5
V
VENABLE, VENABLE
ENABLE and ENABLE pin voltage
0
6.5
V
VSENSE
SENSE pin voltage
0
6.5
V
VSENSE_OUT, VSENSE_OUT (open
SENSE_OUT, SENSE_OUT pin voltage
0
18
V
SENSE_OUT, SENSE_OUT pin voltage
0
VCC
V
SENSE_OUT, SENSE_OUT pin current
0.0003
1
drain)
VSENSE_OUT, VSENSE_OUT
(push-pull)
ISENSE_OUT, ISENSE_OUT
mA
7.4 Thermal Information
TPS389x
THERMAL METRIC (1)
DRY (USON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
293.8
RθJC(top)
Junction-to-case (top) thermal resistance
165.1
RθJB
Junction-to-board thermal resistance
160.8
ψJT
Junction-to-top characterization parameter
27.3
ψJB
Junction-to-board characterization parameter
65.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
65.8
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
5
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.7 V < VCC< 6.5 V, unless otherwise noted. Typical
values are at TJ = 25°C and VCC = 3.3 V.
PARAMETER
VCC
Supply voltage range
V(POR)
Power-on reset voltage (1)
TEST CONDITIONS
MIN
TJ = –40°C to 125°C
TJ = 0°C to 85°C
1.65
6.5
VOL (max) = 0.2 V , I(SENSE_OUT) = 15 µA
0.8
VCC = 3.3 V , no load
6
12
VCC = 6.5 V , no load
7
12
0.5
0.505
Supply current (into VCC pin)
VIT+
Positive-going input threshold voltage
V(SENSE) rising
Vhys
Hysteresis voltage
V(SENSE) falling
I(SENSE)
Input current (2)
V(SENSE) = 0 V or VCC
I(CT)
CT pin charge current
260
V(CT)
CT pin comparator threshold voltage
1.18
R(CT)
CT pin pulldown resistance
VIL
Low-level input voltage (ENABLE pin)
VIH
High-level input voltage (ENABLE pin)
UVLO
Undervoltage lockout (3)
VCC falling
Ilkg
Leakage current
ENABLE = VCC or GND
VOL
Low-level output voltage
High-level output voltage (push-pull)
Ilkg(OD)
Open-drain output leakage current
(1)
(2)
(3)
6
MAX
6.5
ICC
VOH
TYP
1.7
0.495
5
–15
V
V
µA
V
mV
15
nA
310
360
nA
1.238
1.299
V
Ω
200
0.4
1.4
V
V
1.3
1.7
V
–100
100
nA
VCC ≥ 1.2 V, ISINK = 90 µA (TPS3895/7 only)
0.3
VCC ≥ 2.25 V, ISINK = 0.5 mA
0.3
VCC ≥ 4.5 V, ISINK = 1 mA
0.4
VCC ≥ 2.25 V, ISOURCE = 0.5 mA
0.8VCC
VCC ≥ 4.5 V, ISOURCE = 1 mA
0.8VCC
V(SENSE_OUT) high impedance = 18 V
UNIT
V
V
300
nA
The lowest supply voltage (VCC) at which output is active (SENSE_OUT is low, SENSE_OUT is high); tr(VCC) > 15 µs/V. Below V(POR),
the output cannot be determined.
Specified by design.
When VCC falls below the UVLO threshold, the output deasserts (SENSE_OUT goes low, SENSE_OUT goes high). Below V(POR), the
output cannot be determined.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
7.6 Timing Requirements
MIN
tpd(r)
SENSE (rising) to SENSE_OUT propagation delay
tpd(f)
SENSE (falling) to SENSE_OUT propagation delay
TYP
UNIT
40
µs
V(SENSE) rising, C(CT) =
0.047 µF
190
ms
16
µs
50
µs
V(SENSE) falling
Start-up delay (1)
tw
MAX
V(SENSE) rising, C(CT) =
open
ENABLE pin minimum pulse duration
1
ENABLE pin glitch rejection
µs
100
ns
td(OFF)
ENABLE to SENSE_OUT delay time (output
disabled)
ENABLE deasserted to
output deasserted
200
ns
td(P)
ENABLE to SENSE_OUT delay time (P version)
ENABLE asserted to output
asserted delay
(P version)
200
ns
ENABLE asserted to output
asserted delay
(A version), C(CT) = open
20
µs
ENABLE asserted to output
asserted delay
(A version), C(CT) = 0.047
µF
190
ms
td(A)
(1)
ENABLE to SENSE_OUT delay time (A version)
During power on, VCC must exceed 1.7 V for at least 50 µs (plus propagation delay time, tpd(r)) before output is in the correct state.
VCC
UVLO
V(POR)
ENABLE
VIT+
VIT+
SENSE
VIT+ - Vhys
SENSE_OUT
tpd(r)
tpd(f)
tpd(r)
td(OFF)
td(A)
Figure 1. TPS3895A and TPS3897A Timing
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
7
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
VCC
www.ti.com
V(POR)
ENABLE
VIT+
VIT+
SENSE
VIT+ - Vhys
SENSE_OUT
tpd(r)
tpd(r)
tpd(f)
td(P)
td(OFF)
Figure 2. TPS3895P and TPS3897P Timing
VCC
V(POR)
ENABLE
VIT+
VIT+
SENSE
VIT+ - Vhys
SENSE_OUT
tpd(r)
tpd(f)
td(OFF)
tpd(r)
td(A)
Figure 3. TPS3896A and TPS3898A Timing
VCC
UVLO
V(POR)
ENABLE
VIT+
VIT+
SENSE
VIT+ - Vhys
SENSE_OUT
tpd(r)
tpd(f)
tpd(r)
td(OFF)
td(P)
Figure 4. TPS3896P and TPS3898P Timing
8
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
7.7 Typical Characteristics
At TA = 25°C, and VCC = 3.3 V, unless otherwise noted.
12
10
9
10
SENSE_OUT Delay (s)
8
ICC (µA)
7
6
5
−40°C
0°C
25°C
85°C
105°C
125°C
4
3
2
1
0
0
1
2
3
4
VCC (V)
5
6
8
6
4
2
0
7
Figure 5. Supply Current vs Supply Voltage
0.5
1
1.5
CCT (µF)
2.5
3
G002
507
195
VCC = 3.3 V
VIT+, VIT+ − VHYS (mV)
194
193
192
VCC = 1.7 V
191
VCC = 1.7 V, VIT+
VCC = 3.3 V, VIT+
VCC = 6.5 V, VIT+
VCC = 1.7 V, VIT+ − VHYS
VCC = 3.3 V, VIT+ − VHYS
VCC = 6.5 V, VIT+ − VHYS
505
190
189
503
501
499
497
188
495
VCC = 6.5 V
187
186
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
493
−40 −25 −10
110 125
G003
Figure 7. SENSE_OUT Time-Out Period vs Temperature
(CCT = 47 nF)
5
20 35 50 65
Temperature (°C)
80
95
110 125
G004
Figure 8. SENSE Threshold Voltage vs Temperature
350
450
400
100
VCC = 1.7 V
350
300
VOL (mV)
SENSE Pulse Duration (µs)
2
Figure 6. SENSE_OUT Time-Out Period vs CCT
196
SENSE_OUT Delay (ms)
0
G001
10
VCC = 3.3 V
250
200
150
100
VCC = 6.5 V
50
1
1
10
Overdrive (%)
100
0
0.1
G005
Figure 9. SENSE Minimum Pulse Duration vs SENSE
Threshold Overdrive Voltage
0.2
0.3
0.4
0.5
0.6
0.7
Output Sink Current (mA)
0.8
0.9
1
G006
Figure 10. Output Voltage Low vs Output Current (0 mA to
1 mA)
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
9
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
Typical Characteristics (continued)
At TA = 25°C, and VCC = 3.3 V, unless otherwise noted.
450
600
400
VCC = 1.7 V
500
VCC = 1.7 V
300
VOL (mV)
VCC − VOH (mV)
350
250
VCC = 3.3 V
200
VCC = 6.5 V
400
VCC = 3.3 V
300
150
100
200
VCC = 6.5 V
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Output Source Current (mA)
0.9
100
−40 −25 −10
1
Figure 11. Output Voltage High vs Output Current
(0 mA to 1 mA)
80
95
110 125
G008
1.6
VCC = 1.7 V
1.4
VCC = 1.7 V
1.2
400
1
VCC = 6.5 V
VCC = 3.3 V
VOL (V)
VCC − VOH (mV)
20 35 50 65
Temperature (°C)
Figure 12. Output Voltage Low at 1 mA vs Temperature
600
500
5
G007
300
0.8
VCC = 6.5 V
0.6
200
0.4
100
VCC = 3.3 V
0.2
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
0
0.5
G009
Figure 13. Output Voltage High at 1 mA vs Temperature
1
1.5
2
2.5 3 3.5 4 4.5
Output Sink Current (mA)
5
5.5
6
G010
Figure 14. Output Voltage Low vs Output Current
7
CCT = open
6
VOH (V)
5
VENABLE
2V/div
VCC = 6.5 V
VCC = 3.3 V
4
3
VSENSE_OUT
2V/div
2
VCC = 1.7 V
1
0
0.5
1
1.5
2 2.5 3 3.5 4 4.5
Output Source Current (mA)
5
5.5
G011
Figure 15. Output Voltage High vs Output Current
10
Time (50ms/div)
6
Figure 16. Enable Power On and Power Off Delay
(TPS3895A)
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
Typical Characteristics (continued)
At TA = 25°C, and VCC = 3.3 V, unless otherwise noted.
VENABLE
2V/div
VSENSE_OUT
2V/div
Time (200ns/div)
Figure 17. Enable Power On and Power Off Delay (TPS3895P)
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
11
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
8 Detailed Description
8.1 Overview
The TPS3895, TPS3896, TPS3897, and TPS3898 devices (TPS389x) are a family of ultra-small supervisory
circuits. The TPS389x is designed to assert the SENSE_OUT or SENSE_OUT signal, as shown in Table 1 and
Table 2. When the SENSE pin rises above 0.5 V and the enable input is asserted (ENABLE = high or ENABLE =
low) , the output asserts (SENSE_OUT goes high or SENSE_OUT goes low) after the capacitor-adjustable delay
time. The SENSE pin can be set to any voltage threshold above 0.5 V using an external resistor divider. A broad
range of output delay times and voltage thresholds can be supported, allowing these devices to be used in wide
array of applications.
Table 1. TPS3895/7 Truth Table
OUTPUT
STATUS
ENABLE = high
CONDITIONS
SENSE < VIT+
SENSE_OUT = low
Output not asserted
ENABLE = low
SENSE < VIT+
SENSE_OUT = low
Output not asserted
ENABLE = low
SENSE > VIT+
SENSE_OUT = low
Output not asserted
ENABLE = high
SENSE > VIT+
SENSE_OUT = high
Output asserted after delay
Table 2. TPS3896/8 Truth Table
OUTPUT
STATUS
ENABLE = low
CONDITIONS
SENSE < VIT+
SENSE_OUT = high
Output not asserted
ENABLE = high
SENSE < VIT+
SENSE_OUT = high
Output not asserted
ENABLE = high
SENSE > VIT+
SENSE_OUT = high
Output not asserted
ENABLE = low
SENSE > VIT+
SENSE_OUT = low
Output asserted after delay
8.2 Functional Block Diagram
VCC
SENSE
Delay
SENSE_OUT
500 mV
ENABLE
GND
CT
Figure 18. TPS3895A Block Diagram
12
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
Functional Block Diagram (continued)
VCC
SENSE_OUT
SENSE
Delay
500 mV
ENABLE
GND
CT
Figure 19. TPS3897A Block Diagram
VCC
SENSE
Delay
SENSE_OUT
500 mV
ENABLE
GND
CT
Figure 20. TPS3895P Block Diagram
VCC
SENSE_OUT
SENSE
Delay
500 mV
ENABLE
GND
CT
Figure 21. TPS3897P Block Diagram
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
13
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
8.3 Feature Description
8.3.1 Input Pin (SENSE)
The SENSE input pin allows any system voltage above 0.5 V to be monitored. If the voltage at the SENSE pin
exceeds VIT+, and provided that the enable pin is asserted (ENABLE = high or ENABLE = low), then the output is
asserted after the capacitor-adjustable delay time elapses. When the voltage at the SENSE pin drops below
(VIT+ – Vhys), then the output is deasserted. The comparator has a built-in hysteresis to ensure smooth output
assertions and deassertions. Although not required in most cases, for extremely noisy applications, it is good
analog design practice to place a 1-nF to 10-nF bypass capacitor at the SENSE input in order to reduce
sensitivity to transients and layout parasitics.
The TPS389x family monitor the voltage at SENSE with the use of external resistor divider, as shown in
Figure 22.
VIN
0.1 mF
VCC
ENABLE
R1
SENSE_OUT
TPS3897
CT
SENSE
R2
RP
GND
VCC1
GPIO
DSP,
CPU,
or
FPGA
GND
Figure 22. Using TPS3897 to Monitor User-Defined Threshold Voltage
The target threshold voltage can be calculated by using Equation 1:
VTARGET = (1+R1/R2) × 0.5 (V)
(1)
When the input voltage (VIN) shown in Figure 22 is greater than VTARGET, then the output is asserted, provided
that the enable pin is asserted (ENABLE = high or ENABLE = low). R1 and R2 can have high values (> 100 kΩ)
to minimize current consumption as a result of a low SENSE input current without adding significant error to the
resistive divider. Refer to application note SLVA450 to learn more about sizing sense-point resistors.
8.3.2 Enable Pin (ENABLE)
The enable input allows an external logic signal from other processors, logic circuits, and/or discrete sensors to
turn on or turn off the output. The TPS3895 and TPS3897 offer an active-high enable input (ENABLE). The
TPS3896 and TPS3898 offer an active-low enable input (ENABLE). Driving ENABLE low (or ENABLE high)
forces SENSE_OUT to go low (or SENSE_OUT to go high). The 0.4-V (maximum) low and 1.4-V (minimum) high
allow ENABLE to be driven with a 1.5-V or greater system supply.
The TPS389x family is available in two versions: the TPS389xA and TPS389xP. For TPS389xA devices with
VSENSE > VIT+, driving ENABLE high (or ENABLE = low) makes SENSE_OUT go high (or SENSE_OUT go low)
after the capacitor-adjustable delay time. For the TPS389xP versions with VSENSE > VIT+, driving ENABLE high
(or ENABLE low) makes SENSE_OUT go high (or SENSE_OUT go low) after a 0.2-µs delay.
8.3.3 Output Pin (SENSE_OUT)
In a typical TPS389x application, the SENSE_OUT or SENSE_OUT outputs are connected to a reset/enable
input of the processor (DSP, CPU, FPGA, ASIC, and so on) or connected to the enable input of a voltage
regulator.
14
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
Feature Description (continued)
The TPS3897 and TPS3898 provide open-drain outputs. Pullup resistors must be used to hold these lines high
when SENSE_OUT is asserted or SENSE_OUT is not asserted. By connecting the pullup resistors to the proper
voltage rails, SENSE_OUT or SENSE_OUT can be connected to other devices at the correct interface voltage
levels. The outputs can be pulled up to 18 V independent of the supply voltage (VCC). To ensure proper voltage
levels, some thought should be given to choosing the correct pullup resistor values. The ability to sink current is
determined by the supply voltage; therefore, if VCC = 5 V and the desired output pullup is 18 V, then to obtain a
sink current of 1 mA or less (as mentioned in the Electrical Characteristics), the pullup resistor value should be
greater than 18 kΩ. By using wired-OR logic, any combination of SENSE_OUT can be merged into one logic
signal.
The TPS3895 and TPS3896 provide push-pull outputs. The logic high level of the outputs is determined by the
VCC pin voltage. With this configuration, pullup resistors are not required and some board area can be saved.
However, all the interface logic levels must be examined. All the SENSE_OUT and SENSE_OUT connections
must be compatible with the VCC pin logic level.
The SENSE_OUT or SENSE_OUT outputs are defined for a VCC voltage higher than 0.8 V. Table 1 and Table 2
are truth tables that describe how the outputs are asserted or deasserted. When the conditions are met, the
device changes state from deasserted to asserted after a preconfigured delay time. However, the transitions from
asserted to deasserted are performed almost immediately with minimal propagation delay of 16 µs (typical).
Figure 1 to Figure 4 show the timing diagrams and describe the relationship between the threshold voltages (VIT+
and Vhys), enable inputs, and respective outputs.
8.3.4 Output Delay Time Pin (CT)
To program a user-defined, adjustable delay time, an external capacitor must be connected between the CT pin
and GND. If the CT pin is left open, there will be a delay of 40 µs. The adjustable delay time can be calculated
through Equation 2:
tpd(r) (s) = [CCT (µF) × 4] + 40 µs
(2)
The reset delay time is determined by the time it takes an on-chip, precision 310-nA current source to charge the
external capacitor to 1.24 V. When SENSE > VIT+ and with ENABLE high (or ENABLE low), the internal current
sources are enabled and begin to charge the external capacitors. When the CTn voltage on a capacitor reaches
1.24 V, the corresponding SENSE_OUT or SENSE_OUT is asserted. Note that a low-leakage type capacitor
(such as ceramic) should be used, and that stray capacitance around this pin may cause errors in the reset delay
time.
8.3.5 Immunity To Sense Pin Voltage Transients
The TPS389x is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
depends on threshold overdrive, as shown in the typical characteristic graph Minimum Pulse Duration vs
Threshold Overdrive Voltage (Figure 9).
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > VDD(min))
When the voltage on VDD is greater than VDD(min), the output corresponds to the voltages on the VDD and
ENABLE pins relative to VIT–.
8.4.2 Below VDD(min) (V(POR) < VDD < VDD(min))
When the voltage on VDD is less than VDD(min) but greater than the power-on reset voltage (V(POR)), the output is
deasserted (VSENSE_OUT is low and VSENSE_OUT is high.
8.4.3
Below Power-On Reset (VDD < V(POR))
When the voltage on VDD is lower than the power-on reset voltage (V(POR)), the output is undefined. Do not rely
on the output for proper device function under this condition.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
15
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS389x family of devices are very small supervisory circuits that monitor voltages greater than 500 mV and
offer an adjustable delay time using external capacitors. The TPS389x family operates from 1.7 V to 6.5 V and
also has an enable pin to power on/off the output. Orderable options include versions with either push-pull or
open-drain outputs as well as versions that use active-high or active-low logic for the output and enable signals.
9.2 Typical Applications
9.2.1 Single-Rail Monitoring
The TPS3895P can be used to monitor the supply rail for devices such as digital signal processors (DSPs),
central processing units (CPUs), or field-programmable gate arrays (FPGAs). The downstream device is enabled
by the TPS3895P once the voltage on the SENSE pin (VSENSE) is above the threshold voltage (VIT+) set by the
resistor divider. The downstream device is disabled by the TPS3895P when VSENSE is falls below the threshold
voltage minus the hysteresis voltage (VIT+ – Vhys).
If active low inputs or outputs are needed, replace the TPS3895P devices with TPS3896P devices. Figure 23
shows the TPS3895P in a typical application.
Microprocessor
I/O
3.3 V
0.1 mF
VCC
ENABLE
R1
(1)
ENABLE
SENSE_OUT
DSP,
CPU,
or
FPGA
TPS3895A
CT
SENSE
R2
VCC
GND
See
Note
(2)
GND
(1)
ENABLE can also be driven with a separate 1.5-V or greater power supply.
(2)
Capacitor is optional. If a capacitor is not used, leave the CT pin open for a 40-µs delay.
Figure 23. TPS3895 Typical Application
9.2.1.1 Design Requirements
The TPS3895P must drive the enable pin of devices using a logic-high signal to signify that the supply voltage is
above the minimum operating voltage of the device.
9.2.1.2 Detailed Design Procedure
Select R1 and R2 so the voltage at SENSE (VSENSE) is above the positive-going threshold voltage (VIT+) at the
supply voltage required for proper device operation (that is, proper operation of the DSP, CPU, FPGA, and so
on). Also, ensure that the current that flows from the supply voltage to ground through the resistor divider is at
least 100 times larger than the input current (ISENSE).
16
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
Typical Applications (continued)
If an output delay time is required, connect a capacitor from CT to GND; see the Output Delay Time Pin (CT)
section for more information. If no CT cap is connected, the delay time is 40 µs.
9.2.1.3 Application Curve
VENABLE
2V/div
VSENSE_OUT
2V/div
Time (200ns/div)
Figure 24. Enable Power On and Power Off Delay (TPS3895P)
9.2.2 Multiple Voltage Monitoring Sequential Delay
Multiple TPS3895As can be used to monitor multiple supply rails with a single output signifying whether or not all
rails are above the respective thresholds. Some applications may need a minimum total delay time that is the
sum of all the delay times of the supply monitor. To achieve this configuration, connect the output of one
TPS3895A to the ENABLE pin of the next TPS3895A, and repeat until the last TPS3895A is connected to the
device that receives the final Wired-AND signal. The downstream device receives a signal from the last
TPS3895A once VSENSE on all SENSE pins is above the VIT+ set by the resistor dividers. The downstream device
is disabled by the last TPS3895A if the voltage on any SENSE pin in the chain falls below (VIT+ – Vhys).
Figure 25 shows an example of a configuration for dual-supply monitoring; this concept can be expanded for as
many rails as a given application requires.
If active low inputs or outputs are needed, replace the TPS3895A devices with TPS3896A devices.
1.2 V
3.3 V
VCC
ENABLE
SENSE_OUT
TPS3895A
ENABLE
SENSE_OUT
DSP,
CPU,
or
FPGA
GND
CT
SENSE
VCC2
GPIO
TPS3895A
CT
SENSE
VCC1
VCC
GND
GND
Figure 25. Multiple Voltage Monitoring Using ENABLE Pin
9.2.2.1 Design Requirements
Two rails must be monitored to ensure that both are above the respective minimum operating voltage for proper
operation pf the device. The TPS3895As must drive a GPIO pin of the final downstream device, and use a logichigh signal to signify that the supply voltages are above the minimum operating voltage of the given device.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
17
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
Typical Applications (continued)
9.2.2.2 Detailed Design Procedure
Select the resistor divider of each TPS3895A so the voltage at SENSE (VSENSE) is above the positive-going
threshold voltage (VIT+) at the point where the monitored voltage is required for proper device operation (that is,
proper operation of the DSP, CPU, FPGA, and so on). Also, ensure that the currents that flow from the monitored
voltage to ground through the resistor dividers are at least 100 times larger than the input current (ISENSE).
If an output delay time is required for any of the TPS3895As, connect a capacitor from the CT pin of that
TPS3895A to GND; see the Output Delay Time Pin (CT) section for more information. If no CT caps are
connected, the delay time is 40 µs for each TPS3895A in the chain. Because each of the ENABLE pins is tied to
the TPS3895A preceding it (other than the first), at a minimum the total delay time is the sum of all the delay
times set by the CT pins in the design.
9.2.2.3 Application Curve
CCT = open
VENABLE
2V/div
VSENSE_OUT
2V/div
Time (50ms/div)
Figure 26. Enable Power On and Power Off Delay (TPS3895A)
9.2.3 Multiple Voltage Monitoring Minimum Delay
Multiple TPS3897Ps can be used to monitor multiple supply rails with a single output that signals if all rails are
above the respective thresholds. Some applications may need a minimum total delay time that is equal to the
delay time of only the final supply monitor to power up. To achieve this configuration, connect the outputs of all
the TPS3897Ps to the device that must receive the final Wired-AND signal and connect that same node to the
appropriate logic-high voltage via a resistor. The downstream device receives a signal once VSENSE on all
SENSE pins are above the VIT+ set by the resistor dividers. The downstream device is disabled if the voltage on
any SENSE pin falls below (VIT+ – Vhys).
See Figure 27 for an example of a configuration for dual-supply monitoring. This concept can be expanded for as
many rails as a given application requires.
If active low inputs/outputs are required, replace the TPS3897P devices with TPS3898P devices.
18
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
Typical Applications (continued)
5V
3.3 V
RP
VCC
ENABLE
SENSE_OUT
TPS3897P
CT
SENSE
VCC1
VCC1
GPIO
DSP,
ASIC,
or
FPGA
GND
GND
3.3 V
VCC
ENABLE
SENSE_OUT
TPS3897P
CT
SENSE
GND
Figure 27. Multiple Voltage Monitoring Using Wired-OR Logic at SENSE_OUT
9.2.3.1 Design Requirements
Two rails must be monitored to ensure that both rails are above the respective minimum operating voltage for
proper operation of the device. The TPS3897Ps must drive a GPIO pin of the final downstream device and use a
logic-high signal to signify that the supply voltages are above the minimum operating voltage of the device.
9.2.3.2 Detailed Design Procedure
Select the resistor divider of each TPS3897P so the voltage at SENSE (VSENSE) is above the positive-going
threshold voltage (VIT+) at the point where the monitored voltage is required for proper device operation (that is,
proper operation of the DSP, CPU, FPGA, and so on). Also, ensure that the currents that flow from the monitored
voltage to ground through the resistor dividers are at least 100 times larger than the input current (ISENSE).
If an output delay time is required for any of the TPS3897Ps, connect a capacitor from the CT pin of that
TPS3897P to GND; see the Output Delay Time Pin (CT) section for more information. If no CT caps are
connected, the delay time is 40 µs.
Determine the logic-high voltage by selecting the voltage that the pullup resistor (denoted RP in Figure 29) is
connected to. Select RP so that current that flows to ground allows for a low-level output voltage that is low
enough for the specific application. See the Output Pin (SENSE_OUT) section for more information.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
19
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
Typical Applications (continued)
9.2.3.3 Application Curves
1.6
VCC = 1.7 V
1.4
1.2
VOL (V)
1
0.8
VCC = 6.5 V
0.6
0.4
VCC = 3.3 V
0.2
0
0.5
1
1.5
2
2.5 3 3.5 4 4.5
Output Sink Current (mA)
5
5.5
6
G010
Figure 28. Output Voltage Low vs Output Current
9.2.4 Voltage Sequencing
TPS3895As can be used to implement voltage rail sequencing by connecting a resistor divider and the SENSE
pin of a TPS3895A to the first rail to be monitored, and then feeding the output from the first TPS3895A to the
ENABLE pin of the next voltage rail. The downstream voltage rail is enabled by the TPS3895A once the voltage
on the SENSE pin (VSENSE) is above the threshold voltage (VIT+) set by the resistor divider. This process can be
repeated for as many rails as the application requires. The downstream voltage rail is disabled by the TPS3895A
when VSENSE falls below the threshold voltage minus the hysteresis voltage (VIT+ – Vhys).
If active low inputs/outputs are required, replace the TPS3895A devices with TPS3896A devices.
See Figure 29 for an example for a system with four voltage rails that must sequence the three LDOs.
20
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
Typical Applications (continued)
5V
Microprocessor
I/O
IN
3.3 V
EN
3.3 V
OUT
LDO
VCC
SENSE
ENABLE
TPS3895A
CT
GND
SENSE_OUT
5V
IN
3.0 V
EN
3.0 V
OUT
LDO
VCC
SENSE
ENABLE
TPS3895A
CT
GND
SENSE_OUT
IN
1.8 V
EN
1.8 V
OUT
LDO
Figure 29. Voltage Sequencing (5 V → 3.3 V → 3 V → 1.8 V)
9.2.4.1 Design Requirements
Three rails must be sequenced to ensure proper start-up sequencing. The TPS3895As must drive the ENABLE
pins of each LDO, and use a logic-high signal to signify that the supply preceding it is above the desired
operating voltage for that rail. The ENABLE pin of the TPS3895As must be controlled by a microprocessor to
allow it to be shut down even when the rails are above the threshold.
9.2.4.2 Detailed Design Procedure
Select the resistor divider of each TPS3895A so the voltage at SENSE (VSENSE) is above the positive-going
threshold voltage (VIT+) at the point where the monitored voltage is required for proper device operation (that is,
proper operation of the DSP, CPU, FPGA, and so on). Also, ensure that the currents that flow from the monitored
voltage to ground through the resistor dividers are at least 100 times larger than the input current (ISENSE).
If an output delay time is required for any of the TPS3895As, connect a capacitor from the CT pin of that
TPS3895A to GND; see the Output Delay Time Pin (CT) section for more information. If no CT caps are
connected, the delay time is 40 µs for each TPS3895A in the chain. Because each of the ENABLE pins is tied to
the TPS3895A that precedes it (other than the first device in the chain), at a minimum the total delay time is the
sum of all the delay times set by the CT pins.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
21
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
Typical Applications (continued)
9.2.4.3 Application Curve
196
SENSE_OUT Delay (ms)
195
VCC = 3.3 V
194
193
192
VCC = 1.7 V
191
190
189
188
VCC = 6.5 V
187
186
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
G003
Figure 30. SENSE_OUT Time-out Period vs Temperature (CCT = 47 nF)
22
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
TPS389
www.ti.com
SBVS172B – JULY 2011 – REVISED APRIL 2015
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range from 1.7 V to 6.5 V. Though
not required, it is good analog design practice to place a 0.1-μF ceramic capacitor close to the VCC pin.
11 Layout
11.1 Layout Guidelines
Follow these guidelines to lay out the printed-circuit-board (PCB) that is used for the TPS389x family of devices.
• Place the VCC decoupling capacitor close to the device.
• Avoid using long traces for the VCC supply node. The VCC capacitor (CVCC), along with parasitic inductance
from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the
maximum VCC voltage.
11.2 Layout Example
Enable
Signal
Input
Supply
TPS3897P
CVCC
1
6
2
5
CCT
3
4
R2
SENSE_OUT
Flag
R1
Monitored
Supply
RP
Pullup
Voltage
Figure 31. TPS3897P Layout Example (DRY Package)
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
23
TPS389
SBVS172B – JULY 2011 – REVISED APRIL 2015
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS389x.
The TPS3897A-6P-EVM047 evaluation module (and related user guide) can be requested at the TI website
through the product folders or purchased directly from the TI eStore.
12.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. SPICE models for the TPS389x are available through the respective device product
folders under Tools & Software.
12.1.2 Device Nomenclature
Table 3. Device Nomenclature
PRODUCT
TPS389wxyyyz
DESCRIPTION
w is output configuration (see Device Comparison Table)
x is different delay from enable pin (see Device Comparison Table)
yyy is package designator
z is package quantity
12.2 Documentation Support
12.2.1 Related Documentation
•
•
Choosing an Appropriate Pullup/Pulldown Resistor for Open Drain Outputs, SLVA485
TPS3897A-6P-EVM047 User's Guide, SLVU524
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS389
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS3895ADRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UN
Samples
TPS3895ADRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UN
Samples
TPS3895PDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UO
Samples
TPS3895PDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UO
Samples
TPS3896ADRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UJ
Samples
TPS3896ADRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UJ
Samples
TPS3896PDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UK
Samples
TPS3896PDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UK
Samples
TPS3897ADRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
Call TI | NIPDAUAG
| NIPDAU
Level-1-260C-UNLIM
-40 to 125
UL
Samples
TPS3897ADRYT
ACTIVE
SON
DRY
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
UL
Samples
TPS3897PDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
UM
Samples
TPS3897PDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
UM
Samples
TPS3898ADRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UH
Samples
TPS3898ADRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UH
Samples
TPS3898PDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UI
Samples
TPS3898PDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UI
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
