TPS40054, TPS40055, TPS40057
SLUS593J – DECEMBER 2003 – REVISED JUNE 2022
TPS4005x Wide-Input Synchronous Buck Controller
1 Features
3 Description
•
The TPS4005x is a family of high-voltage, wideinput (8 V to 40 V), synchronous, step-down
controllers. The TPS4005x family offers design
flexibility with a variety of user-programmable
functions, including soft start, UVLO, operating
frequency, voltage feedforward, high-side current limit,
and loop compensation.
•
•
•
•
•
•
•
•
•
•
•
•
•
New products available
– LM5145 75-V synchronous buck controller with
wide input voltage and duty cycle ranges
– LM5146 100-V synchronous buck DC/DC
controller with wide duty-cycle range
Operating input voltage 8 V to 40 V
Input voltage feedforward compensation
< 1% internal 0.7-V reference
Programmable fixed-frequency up to 1-MHz
voltage mode controller
Internal gate-drive outputs for high-side and
synchronous N-channel MOSFETs
16-pin PowerPAD™ package (RθJC = 2°C/W)
Thermal shutdown
Externally synchronizable
Programmable high-side sense short-circuit
protection
Programmable closed-loop soft start
TPS40054 source only
TPS40055 source and sink
TPS40057 source and sink with VO prebias
The TPS4005x uses voltage feedforward control
techniques to provide good line regulation over the
wide (4:1) input voltage range, and fast response
to input line transients. Near-constant modulator
gain with input variation eases loop compensation.
The externally programmable current limit provides
pulse-by-pulse current limit, as well as hiccup mode
operation using an internal fault counter for longer
duration overloads.
The new products, LM5145 and LM5146, offer
reduced BOM cost, higher efficiency, and reduced
solution size among many other features. Start a
WEBENCH® design with LM5145 and LM5146.
Device Information
2 Applications
•
•
•
Part Number
Power modules
Networking and telecom
Industrial and servers
Package(1)
Body Size (NOM)
HTSSOP (16)
5.00 mm × 4.40 mm
TPS40054
TPS40055
TPS40057
(1)
TPS4005xPWP
1 KFF
ILIM 16
+
2 RT
VIN
±
For all available packages, see the orderable addendum at
the end of the data sheet.
3 BP5
VIN 15
BOOST 14
4 SYNC
HDRV 13
5 SGND
SW 12
6 SS/SD
BP10 11
7 VFB
LDRV 10
8 COMP
PGND
9
+
VO
±
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLUS593J – DECEMBER 2003 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions.........................4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics.............................................5
6.5 Typical Characteristics................................................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes..........................................16
8 Application and Implementation.................................. 17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................28
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Example...................................................... 29
10.3 MOSFET Packaging............................................... 31
11 Device and Documentation Support..........................33
11.1 Device Support........................................................33
11.2 Documentation Support.......................................... 33
11.3 Receiving Notification of Documentation Updates.. 33
11.4 Support Resources................................................. 33
11.5 Trademarks............................................................. 33
11.6 Electrostatic Discharge Caution.............................. 33
11.7 Glossary.................................................................. 33
12 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (December 2014) to Revision J (June 2022)
Page
• Added feature bullet for the LM5145 and LM5146............................................................................................. 1
• Changed all instances of legacy terminology to controller..................................................................................1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Removed all TPS40055-Q1 references and third paragraph from Section 8.2 ............................................... 21
• Removed TPS40055-Q1, TPS40192, TPS40193, and TPS40200 references from Table 11-1 in Device
Support ............................................................................................................................................................ 33
Changes from Revision H (July 2012) to Revision I (December 2014)
Page
• Added Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ............................................................................ 3
2
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SLUS593J – DECEMBER 2003 – REVISED JUNE 2022
5 Pin Configuration and Functions
KFF
1
16
ILIM
RT
2
15
VIN
BP5
3
14
BOOST
SYNC
4
13
HDRV
Thermal Pad
A.
B.
SGND
5
12
SW
SS/SD
6
11
BP10
VFB
7
10
LDRV
COMP
8
9
PGND
For more information on the PWP package, refer to the PowerPAD™ Thermally Enhanced Package application report.
A PowerPAD heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
Figure 5-1. 16-Pin PWP HTSSOP Package (Top View)
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOST
14
O
Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the SW voltage.
Connect a 0.1-µF ceramic capacitor from this pin to the drain of the lower MOSFET.
BP5
3
O
5-V reference. Bypass this pin to ground with a 0.1-µF ceramic capacitor. This pin can be used with an external DC
load of 1 mA or less.
BP10
11
O
10-V reference used for gate drive of the N-channel synchronous rectifier. Bypass this pin with a 1-µF ceramic
capacitor. This pin can be used with an external DC load of 1 mA or less.
COMP
8
O
Output of the error amplifier and input to the PWM comparator. A feedback network is connected from this pin to the
VFB pin to compensate the overall loop. The COMP pin is internally clamped above the peak of the ramp to improve
large signal transient response.
HDRV
13
O
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
ILIM
16
I
Current limit pin. Used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage
drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage
drop (VIN – SW) across the high-side MOSFET during conduction.
KFF
1
I
A resistor is connected from this pin to VIN to program the amount of voltage feedforward and UVLO level. The
current fed into this pin is internally divided and used to control the slope of the PWM ramp.
LDRV
10
O
Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET
off).
PGND
9
RT
2
I
SGND
5
—
Power ground reference for the device. There should be a low-impedance path from this pin to the source or sources
of the lower MOSFET or MOSFETs.
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
Signal ground reference for the device
SS/SD
6
I
Soft-start programming and shutdown pin. A capacitor connected from this pin to ground programs the soft-start
time. The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS/SD
pin is used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD
is approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V.
The controller is considered shut down when VSS/SD is 125 mV or less. The internal circuitry is enabled when VSS/SD
is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output
voltage (VO) decays while the internal circuitry remains active.
SW
12
I
This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40054 also
uses this pin for zero current sensing.
SYNC
4
I
Synchronization input for the device. This pin can be used to synchronize the oscillator to an external controller
frequency. If synchronization is not used, connect this pin to SGND.
VFB
7
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference
voltage, 0.7 V.
VIN
15
I
Supply voltage for the device
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
VIN
Input voltage
MIN
MAX
VFB, SS/SD, SYNC
–0.3
6
VIN, SW
–0.3
45
SW, transient < 50 ns
–2.5
SW, transient < 50 ns, VVIN < 14 V
–0.3
11
COMP, RT, SS/SD
–0.3
6
Output voltage
IO
Output current
TJ
Maximum junction temperature(2)
TJ
Operating junction temperature
KFF
5
RT
200
(2)
mA
µA
150
Tstg Storage temperature range
(1)
V
–5
KFF, with IIN(max) = – 5 mA
VO
UNIT
–40
125
–55
150
°C
°C
Stresses beyond those listed under may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under is not implied. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability.
Device may shut down at junction temperatures below 150°C.
6.2 Recommended Operating Conditions
VIN
Input voltage
TA
Operating free-air temperature
MIN
MAX
8
40
UNIT
V
–40
85
°C
6.3 Thermal Information
TPS4005x
THERMAL METRIC(1)
HTSSOP
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
ψJT
ψJB
RθJCbot
(1)
4
38.3
°C/W
Junction-to-case (top) thermal resistance
28
°C/W
Junction-to-board thermal resistance
9
°C/W
Junction-to-top characterization parameter
0.4
°C/W
Junction-to-board characterization parameter
8.9
°C/W
Junction-to-case (bottom) thermal resistance
2.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Electrical Characteristics
TA = –40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range, VIN
8
40
V
1.5
3
mA
OPERATING CURRENT
IDD
Quiescent current
Output drivers not switching, VFB ≥ 0.75 V
Output voltage
IO ≤ 1 mA
4.7
5
5.2
V
470
520
570
kHz
BP5
VBP5
OSCILLATOR/RAMP GENERATOR
fOSC
Accuracy
8 V ≤ VIN ≤ 40 V
VRAMP
PWM ramp voltage(1)
VPEAK – VVAL
VIH
High-level input voltage, SYNC
VIL
Low-level input voltage, SYNC
ISYNC
Input current, SYNC
DMAX
V
2
5
Pulse width, SYNC
VRT
2
0.8
V
10
µA
50
RT voltage
2.38
Maximum duty cycle
Minimum duty cycle
VFB = 0 V, fSW ≤ 500 kHz
85%
VFB = 0 V, 500 kHz ≤ fSW ≤ 1 MHz(1)
80%
ns
2.5
VFB ≥ 0.75 V
VKFF
Feed-forward voltage
IKFF
Feedforward current operating range(1) (2)
2.58
V
94%
0%
3.35
3.48
20
3.65
V
1100
µA
2.95
µA
SOFT START
ISS/SD
Soft-start source current
1.65
2.35
VSS/SD
Soft-start clamp voltage
tDSCH
Discharge time
CSS/SD = 220 pF
1.6
2.2
2.8
tSS/SD
Soft-start time
CSS/SD = 220 pF, 0 V ≤ VSS/SD ≤ 1.6 V
115
150
215
Output voltage
IO ≤ 1 mA
9
9.6
10.3
8 V ≤ VIN ≤ 40 V, TA = 25°C
0.698
0.7
0.704
8 V ≤ VIN ≤ 40 V, 0°C ≤ TA ≤ 85°C
0.693
0.7
0.707
8 V ≤ VIN ≤ 40 V, -40°C≤ TA ≤ 85°C
0.693
0.7
0.715
3.7
V
µs
BP10
VBP10
V
ERROR AMPLIFIER
VFB
Feedback input voltage
GBW
Gain bandwidth(1)
AVOL
Open loop gain
IOH
IOL
VOH
High-level output voltage
ISOURCE = 500 µA
VOL
Low-level output voltage
ISINK = 500 µA
0.2
0.35
IBIAS
Input bias current
VFB = 0.7 V
100
200
V
3
5
MHz
60
80
dB
High-level output source current
2
4
Low-level output sink current
2
4
3.2
3.5
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mA
V
nA
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SLUS593J – DECEMBER 2003 – REVISED JUNE 2022
TA = –40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8.5
10
11.5
µA
CURRENT LIMIT
ISINK
Current limit sink current
Propagation delay to output
VILIM = 23.7 V, VSW = (VILIM – 0.5 V)
300
VILIM = 23.7 V, VSW = (VILIM – 2 V)
200
time(1)
tON
Switch leading-edge blanking pulse
tOFF
Off time during a fault (soft-start cycle time)
VOS
Offset voltage SW versus ILIM
ns
100
7
TA = 25°C
–90
–70
cycles
–50
VILIM = 23.6 V, 0°C ≤ TA ≤ 85°C
–120
–38
VILIM = 23.6 V, -40°C ≤ TA ≤ 85°C
–120
–20
mV
OUTPUT DRIVER
tLRISE
Low-side driver rise time
tLFALL
Low-side driver fall time
tHRISE
High-side driver rise time
tHFALL
High-side driver fall time
VOH
High-level output voltage, HDRV
IHDRV = –0.1 A (HDRV – SW)
VOL
Low-level ouput voltage, HDRV
IHDRV = 0.1 A (HDRV – SW)
VOH
High-level ouput voltage, LDRV
ILDRV = –0.1 A
VOL
Low-level output voltage, LDRV
ILDRV = 0.1 A
CLOAD = 2200 pF
CLOAD = 2200 pF (HDRV – SW)
VBOOST
–1.5 V
48
96
24
48
48
96
36
72
VBOOST
–1 V
0.75
VBP10
–1.4 V
ns
VBP10
–1V
V
0.5
Minimum controllable pulse width
100
150
ns
90
125
160
190
210
245
31.2
32.2
33.5
–10
–5
0
mV
25
µA
SS/SD SHUTDOWN
VSD
Shutdown threshold voltage
VEN
Device active threshold voltage
Outputs off
mV
BOOST REGULATOR
VBOOST Output voltage
VIN= 24 V
V
RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 ONLY)
VSW
Switch voltage
LDRV output OFF
SW NODE
Leakage current(1) (out of pin)
ILEAK
THERMAL SHUTDOWN
Shutdown temperature(1)
TSD
165
Hysteresis(1)
°C
20
UVLO
VUVLO
KFF programmable threshold voltage
VDD
UVLO, fixed
VDD
UVLO, hysteresis
(1)
(2)
6
RKFF = 28.7 kΩ
6.95
7.2
7.5
7.95
7.5
7.9
V
0.46
Specified by design. Not production tested.
IKFF increases with SYNC frequency, maximum duty cycle decreases with IKFF.
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6.5 Typical Characteristics
700
RKFF - Feed-Forward Impedance - kW
600
RT - Timing Resistance - kW
500
400
300
200
100
0
100
600
500
400
VIN = 9 V
300
VIN = 15 V
VIN = 25 V
200
100
300
200
400
500
600
700 800
0
100
900 1000
200
300 400
fSW - Switching Frequency - kHz
500
600
700
800
900 1000
fSW - Switching Frequency - kHz
Figure 6-1. Switching Frequency vs Timing
Resistance
Figure 6-2. Feed-Forward Impedance vs Switching
Frequency
6
1.2
110°C
1.0
VBP5 – BP5 Voltage – V
VUVLO – Hysteresis – V
5
0.8
0.6
0.4
25°C
4
– 55°C
3
2
0.2
0
1
10
15
20
25
30
35
40
2
4
VUVLO – Undervoltage Lockout Threshold – V
6
8
10
12
VIN – Input Voltage – V
Figure 6-3. Undervoltage Lockout Threshold vs
Hysteresis
Figure 6-4. Input Voltage vs BP5 Voltage
10
9
VBP10 – BP10 Voltage – V
8
110°C
7
6
5
25°C
4
3
2
– 55°C
1
0
2
4
6
8
10
12
VIN – Input Voltage – V
Figure 6-5. Input Voltage vs BP10 Voltage
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7 Detailed Description
7.1 Overview
The TPS4005x family of synchronous buck controllers are designed to operate over a wide range of input
voltages (8 V to 40 V). These devices offer a variety of user programmable functions such as the following:
•
•
•
•
•
Operating frequency
Soft start
Voltage feedforward
High-side current limit
External loop compensation
7.2 Functional Block Diagram
ILIM
16
BP10
VIN 15
11
BP10
14
BOOST
CLK
RT
2
SYNC
4
CLK
Oscillator
+
10V Regulator
7 1V5REF
Ramp Generator
07VREF
KFF
1
1V5REF
Reference
Voltages
3V5REF
BP5
3-bit up/down
Fault Counter
7
N-channel
Driver
7
Restart
Fault
7
12 SW
07VREF
VFB
+
7
7
Soft Start
SS/SD
13 HDRV
7
7
3
7 CL
7
7
BP5
BP5
7 CLK
7 BP10
+
7 Fault
6
7
S
Q
R
Q
CL
N-channel
Driver
10
LDRV
9
PGND
tSTART
7
Overtemperature
COMP
Restart
7
7
8
5
SW
S
CLK
Q
R Q
Zero Current Detector
(TPS40054 Only)
SGND
UDG-08118
7.3 Feature Description
7.3.1 Setting the Switching Frequency (Programming the Clock Oscillator)
The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the
controller clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by
a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by Equation 1 and the relationship is
charted in Figure 6-1.
RT +
ǒ
f SW
1
17.82
10 *6
Ǔ
* 17
kW
(1)
7.3.2 Programming The Ramp Generator Circuit
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feedforward control by varying the PWM ramp slope with line voltage, while maintaining a constant
ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations
because the PWM does not have to wait for loop delays before changing the duty cycle (see Figure 7-1).
8
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VIN
SW
VPEAK
COMP
RAMP
VVALLEY
t1
tON1
tON2
t2
tON
D=
t
tON1 > tON2 and D1 > D2
UDG-08119
Figure 7-1. Voltage Feedforward Effect on PWM Duty Cycle
The PWM ramp must be faster than the controller clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed through a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the
minimum input voltage, VIN(min), through the following:
(
)
RKFF = VIN(min) - VKFF ´ (58.14 ´ RT + 1340 ) W
(2)
where
•
•
•
VIN(min) is the ensured minimum start-up voltage (the actual start-up voltage is nominally about 10% lower at
25°C). VIN(min) must be programmed equal to or greater than 8 V to ensure start-up and shutdown through the
programmed UVLO through the KFF pin.
RT is the timing resistance in kΩ.
VKFF is the voltage at the KFF pin (typical value is 3.48 V).
The curve showing the RKFF required for a given switching frequency, fSW, and VUVLO is shown in Figure 6-2.
For low-input voltage and high duty-cycle applications, the voltage feedforward can limit the duty cycle
prematurely, but does not occur for most applications. The voltage control loop controls the duty cycle
and regulates the output voltage. For more information on large duty cycle operation, refer to the Effect of
Programmable UVLO on Maximum Duty Cycle application note.
7.3.3 UVLO Operation
The TPS4005x uses variable (user-programmable) UVLO protection. See the Programming the Ramp Generator
section for more information on setting the UVLO voltage. The UVLO circuit holds the soft start low until the input
voltage exceeds the user-programmable undervoltage threshold.
The TPS4005x uses the feedforward pin, KFF, as a user-programmable low-line UVLO detection. This variable
low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage
condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude.
The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The
KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor
can be referenced to the oscillator frequency as described in Equation 2.
The programmable UVLO function uses a 3-bit counter to prevent spurious shutdowns or turn-ons due to
spikes or fast line transients. When the counter reaches a total of seven counts in which the ramp duration is
shorter than the clock cycle, a power-good signal is asserted and a soft start initiated, and the upper and lower
MOSFETS are turned off.
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Once the soft start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared (see Figure 7-2).
UVLO Threshold
VIN
Clock
PWM RAMP
1 2 3 4 5 6 7
1 2
1 2 3 4 5 6 7
PowerGood
UDG-02132
Figure 7-2. Undervoltage Lockout Operation
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start-up voltage.
The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to
select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 6-3.
Some applications can require an additional circuit to prevent false restarts at the UVLO voltage level. This
applies to applications that have high impedance on the input voltage line or that have excessive ringing on the
VIN line. The input voltage impedance can cause the input voltage to sag enough at start-up to cause a UVLO
shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and cause a
UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to prevent the
nuisance UVLO shutdown.
Assuming a hysteresis current of 10% IKFF, and the peak detector charges to 8 V and VIN(min) = 10 V, the value
of RA is calculated by Equation 3 using a RKFF = 71.5 kΩ.
RA =
RKFF ´ (8 - 3.48 )
(
0.1´ VIN(min ) - 3.48
= 495kW = 499kW
)
(3)
CA is chosen to maintain the peak voltage between switching cycles to keep the capacitor charge from drooping
0.1 V (from 8 V to 7.9 V).
CA =
(8 - 3.48 )
(R A ´ 7.9 ´ fSW )
(4)
The value of CA can calculate to less than 10 pF, but some standard value up to 47 pF works adequately. The
diode can be a small-signal switching diode or Schottky rated for more then 20 V. Figure 7-3 shows a typical
implementation using a small switching diode.
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start-up voltage.
10
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RA
499 kΩ
TPS4005xPWP
RKFF
71.5 kΩ
CA
47 pF
1
KFF
2
RT
3
BP5
4
SYNC
5
SGND
6
SS
7
VFB
LDRV 10
8
COMP
PGND
ILIM 16
VIN 15
BOOST 14
HDRV 13
SW 12
BP10 11
9
PGND
DA
1N914, 1N4150
Type Signal Diode
Copyright © 2017, Texas Instruments Incorporated
Figure 7-3. Hysteresis for Programmable UVLO
7.3.4 BP5 and BP10 Internal Voltage Regulators
Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in Figure
6-4 and Figure 6-5. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the
BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs.
7.3.5 Programming Soft Start
The TPS4005x uses a closed-loop soft-start system to ensure a controlled ramp of the output during start-up.
The reference voltage used for the start-up is derived in the following manner. A capacitor (CSS/SD) is connected
to the SS/SD pin. There is a ramped voltage generated at this pin by charging CSS/SD with a current source.
A value of 0.85 V is subtracted from the voltage at the SS/SSD pin and is applied to a non-inverting input of
the error amplifier. This is the effective soft-start ramp voltage, VSSRMP. The error amplifier also has the 0.7-V
reference (VFB) voltage applied to a non-inverting input. The structure of the error amplifier input stage is such
that the lower of VFB or VSSRMP becomes the dominant voltage that the error amplifier uses to regulate the
FB pin. This provides a clean, closed-loop start-up while VSSRMP is lower than VFB and a precision reference
regulated supply as VSSRMP climbs above VFB. To ensure a controlled ramp-up of the output voltage, the
soft-start time must be greater than the L-CO time constant as described in Equation 5.
t START w 2p
ǸL
CO
(seconds)
(5)
where
•
tSTART is the start-up ramp time in s.
There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the
higher the input current required during start-up. This relationship is described in more detail in the Programming
the Current Limit section. The soft-start capacitance, CSS/SD, is described in Equation 6.
For applications in which the VIN supply ramps up slowly (typically between 50 ms and 100 ms), it can be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time must be longer than the time that the VIN supply transitions between 6 V and 7 V.
æI
C SS / SD = ç SS / SD
è VFB
ö
÷ ´ t START (F )
ø
(6)
where
•
•
ISS/SD is the soft-start charge current (typical value is 2.35 μA).
VFB is the feedback reference voltage (typical value is 0.7 V).
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7.3.6 Programming Current Limit
The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven, a restart is issued
and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period.
The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is
re-enabled. If the fault has been removed, the output starts up normally. If the output is still present, the counter
counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 7-4 for typical overcurrent
protection waveforms.
The minimum current limit setpoint (IILIM) is calculated in Equation 7.
æ C ´ VO ö
IILIM = ç O
÷ + ILOAD (A )
è tSTART ø
(7)
where
•
ILOAD is the load current at start-up.
HDRV
CLOCK
tBLANKING
VILIM
VVIN-VSW
SS
7 CURRENT LIMIT TRIPS
(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP)
7 SOFT-START CYCLES
UDG-02136
Figure 7-4. Typical Current Limit Protection Waveforms
The current limit programming resistor (RILIM) is calculated using Equation 8. Care must be taken in choosing the
values used for VOS and ISINK in the equation. To ensure the output current at the overcurrent level, the minimum
value of ISINK and the maximum value of VOS must be used. The main purpose is hard fault protection of the
power switches.
RILIM =
IOC ´ RDS(on )émax ù + VOS
ë
û
1.12 ´ ISINK
+
42.86 ´ 10-3
(W )
ISINK
(8)
where
•
•
•
12
ISINK is the current into the ILIM pin and is 8.5 μA, minimum.
IOC is the overcurrent setpoint, which is the DC output current plus one-half of the peak inductor current.
VOS is the overcurrent comparator offset and is –20 mV maximum.
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7.3.7 Synchronizing to an External Supply
The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on
the falling edge of the SYNC signal. The synchronization frequency must be in the range of 20% to 30%
higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the controller
clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the
frequency programmed by RT.
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically,
this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching
frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a dummy value
for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the
design.
æ
ö
1
RT(dummy ) = ç
- 17 ÷ (kW )
-6
çf
÷
è SYNC ´ 17.82 ´ 10
ø
(9)
where
•
fSYNC is the synchronizing frequency in kHz.
Use the value of RT(dummy) to calculate the value for RKFF.
)(
(
)
RKFF = VIN(min ) - VKFF ´ 58.14 ´ RT(dummy ) + 1340 W
(10)
where
•
RT(dummy) is in kΩ.
This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency.
7.3.8 Loop Compensation
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x
uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be
included. The generic modulator gain is described in Figure 7-5. Duty cycle, D, varies from 0 to 1 as the control
voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous
buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input
voltage and ramp voltage:
D+
VO
V
+ C
V IN
VS
or
VO
V
+ IN
VS
VC
(11)
With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore, the
moderator DC gain is independent to the change of input voltage.
For the TPS4005x, with VIN(min) being the minimum input voltage required to cause the ramp excursion to reach
the maximum ramp amplitude of VRAMP, the modulator DC gain is shown in Equation 12.
æ VIN(min ) ö
÷
AMOD = ç
ç VRAMP ÷
è
ø
or
æ VIN(min ) ö
÷
AMOD(dB ) = 20 ´ log ç
ç VRAMP ÷
è
ø
(12)
For a buck converter using voltage mode control, there is a double pole due to the output L-CO. The double pole
is located at the frequency calculated in Equation 13.
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f LC +
1
2p
ǸL
CO
(Hertz)
(13)
There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 14.
fZ +
1
ESR
2p
CO
(Hertz)
(14)
Calculate the value of RBIAS to set the output voltage, VO.
RBIAS =
0.7 ´ R1
W
VO - 0.7
(15)
The maximum crossover frequency (0 dB loop gain) is set by Equation 16.
fC +
f SW
4
(Hertz)
(16)
Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (–40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 7-6 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
Modulator Gain (dB)
ESR Zero, +1
VS
VC
D= VC/VS
AMOD = VIN(min)/VRAMP
Resultant, –1
L-C Filter, –2
100
Figure 7-5. PWM Modulator Relationships
1k
10 k
Switching Frequency (Hz)
100 k
Figure 7-6. Modulator Gain vs Switching
Frequency
A Type III topology, shown in Figure 7-7, has two zero-pole pairs in addition to a pole at the origin. The gain
and phase boost of a Type III topology is shown in Figure 7-8. The two zeros are used to compensate the L-CO
double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide
controlled gain roll-off. In many cases, the second pole can be eliminated and the gain roll-off of the amplifier is
used to roll-off the overall gain at higher frequencies.
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C2
(optional)
-1
+1
0 dB
C1
R3
-1
R2
GAIN
-90 °
C3
180 °
VFB
R1
PHASE
-270 °
7
VO
8
+
COMP
RBIAS
VREF
UDG-08103
Figure 7-7. Type III Compensation Configuration
Figure 7-8. Type III Compensation Gain and Phase
The poles and zeros for a Type III network are described in Equation 17 through Equation 20.
fZ1 =
1
(Hz )
2p ´ R2 ´ C1
(17)
fZ2 =
1
(Hz )
2p ´ R1´ C3
(18)
fP1 =
1
(Hz )
2p ´ R2 ´ C2
(19)
fP2 =
1
(Hz )
2p ´ R3 ´ C3
(20)
The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩ and
100 kΩ usually yields reasonable values.
The unity gain frequency is described in Equation 21.
fC +
1
2p
R1
C2
G
(Hertz)
(21)
where
•
G is the reciprocal of the modulator gain at fC.
The modulator gain as a function of frequency at fC is described in Equation 22.
æf ö
AMOD(f ) = AMOD ´ ç LC ÷
è fC ø
2
and G =
1
AMOD(f )
(22)
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current, which must be considered when sizing R2.
A value that is too small does not allow the output to swing over its full range.
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R2 (MIN) +
VC (max)
I SOURCE (min)
+ 3.5 V + 1750 W
2 mA
www.ti.com
(23)
7.4 Device Functional Modes
The TPS40057 is safe for prebiased outputs, not turning on the synchronous rectifier until the high-side FET has
already started switching. The TPS40054 operates in one quadrant and sources output current only, allowing
for paralleling of converters and ensures that one converter does not sink current from another converter.
This controller also emulates a non-synchronous buck converter at light loads where the inductor current goes
discontinuous. At continuous output inductor currents, the controller operates as a synchronous buck converter
to optimize efficiency. The TPS40055 operates in two quadrants, sourcing and sinking output current.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS4005x family of synchronous buck controllers are designed to operate over a wide range of input
voltages (8 V to 40 V). These devices are used to convert a higher DC input voltage to a lower DC output
voltage for a variety of applications. Use the following design procedure to select key component values for this
family of devices.
8.1.1 Selecting the Inductor Value
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is
physically larger for the same load current. An inductance that is too small results in larger ripple currents and
a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A
good compromise is to select the inductance value such that the converter does not enter discontinuous mode
until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is
described in Equation 24.
L+
ǒV IN * V OǓ
VIN
DI
VO
f SW
(Henries)
(24)
where
•
•
VO is the output voltage.
ΔI is the peak-to-peak inductor current.
8.1.2 Calculating the Output Capacitance
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.
The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst-case output
ripple is described in Equation 25.
æ
æ
1
D V = D I ´ ç ESR + ç
ç
è 8 ´ CO ´ fSW
è
öö
÷ ÷÷
øø
(25)
where
•
•
CO is the output capacitance.
ESR is the equivalent series resistance of the output capacitance.
The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During
a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop, and the size of the
inductor.
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Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in Equation
26.
EL + 1
2
I 2 (Joules)
L
(26)
where
I2 +
•
•
ƪǒI
Ǔ
2
OH
* ǒI OLǓ
ƫ
2
ǒ(Amperes)2Ǔ
(27)
IOH is the output current under heavy load conditions.
IOL is the output current under light load conditions.
Energy in the capacitor is described in Equation 28.
EC + 1
2
V2 (Joules)
C
(28)
where
V2 +
ƪǒV Ǔ * ǒV Ǔ ƫ
2
2
f
ǒVolts2Ǔ
i
(29)
where
•
•
Vf is the final peak capacitor voltage.
Vi is the initial capacitor voltage.
Substituting Equation 27 into Equation 26, then substituting Equation 29 into Equation 28, then setting Equation
28 equal to Equation 26, and then solving for CO yields the capacitance described in Equation 30.
L
CO +
ƪǒI Ǔ * ǒI Ǔ ƫ
ƪǒV Ǔ * ǒV Ǔ ƫ
2
2
OH
OL
2
(Farads)
2
f
i
(30)
8.1.3 Calculating the Boost and BP10 Bypass Capacitor
The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor
must be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate
charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is
described in Equation 31.
C BOOST +
Qg
DV
(Farads)
(31)
The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET
through the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in
Equation 32.
C BP10 +
18
ǒQgHS ) QgSRǓ
DV
(Farads)
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(32)
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8.1.4 DV-DT Induced Turn-On
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused
by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage on the
MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source
voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through
currents. Therefore, the SR MOSFET should be chosen so that the QGD charge is smaller than the QGS charge.
8.1.5 High-Side MOSFET Power Dissipation
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The
high-side MOSFET conduction losses are defined by Equation 33.
P COND + ǒI RMSǓ
2
ǒ1 ) TCR ƪT J * 25 CƫǓ
R DS(on)
O
(Watts)
(33)
where
•
TCR is the temperature coefficient of the MOSFET RDS(on).
The TCR varies depending on MOSFET technology and manufacturer, but typically ranges between 3500
ppm/°C and 7000 ppm/°C.
The IRMS current for the high-side MOSFET is described in Equation 34.
I RMS + I OUT
Ǹd
ǒARMSǓ
(34)
The switching losses for the high-side MOSFET are described in Equation 35.
P SW(fsw) + ǒVIN
I OUT
t SWǓ
f SW (Watts)
(35)
where
•
•
•
IO is the DC output current.
tSW is the switching rise time, typically < 20 ns.
fSW is the switching frequency.
Typical switching waveforms are shown in Figure 8-1.
ID2
IO
ID1
d
}
∆I
1-d
BODY DIODE
CONDUCTION
BODY DIODE
CONDUCTION
SW
0
ANTI-CROSS
CONDUCTION
SYNCHRONOUS
RECTIFIER ON
HIGH SIDE ON
UDG-02139
Figure 8-1. Inductor Current and SW Node Waveforms
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The maximum allowable power dissipation in the MOSFET is determined by Equation 36.
PT +
ǒTJ * TAǓ
q JA
(Watts)
(36)
where
•
•
PT = PCOND + PSW(fsw) (W).
θJA is the package thermal impedance.
8.1.6 Synchronous Rectifier MOSFET Power Dissipation
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on)
conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can
be defined using Equation 31 and the RMS current through the synchronous rectifier MOSFET is described in
Equation 37.
I RMS + I O
Ǹ1 * d
ǒAmperes RMSǓ
(37)
The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross
conduction delay time. The body diode conduction losses are described by Equation 38.
P DC + 2
IO
VF
t DELAY
f SW (Watts)
(38)
where
•
•
VF is the body diode forward voltage.
tDELAY is the delay time just before the SW node rises.
The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and
once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recover
from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 39.
P RR + 0.5
Q RR
V IN
f SW (Watts)
(39)
where
•
QRR is the reverse recovery charge of the body diode.
The QRR is not always described in a MOSFET data sheet, but can be obtained from the MOSFET vendor. The
total synchronous rectifier MOSFET power dissipation is described in Equation 40.
P SR + PDC ) PRR ) PCOND (Watts)
(40)
8.1.7 TPS4005x Power Dissipation
The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance (refer to the PowerPAD Thermally Enhanced Package application note) can
be calculated from Equation 41.
P D + Qg
VDR
f SW (Wattsńdriver)
(41)
And the total power dissipation in the TPS4005x, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier, is described in Equation 42.
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PT +
SLUS593J – DECEMBER 2003 – REVISED JUNE 2022
ǒ
2
PD
V DR
) IQ
Ǔ
V IN (Watts)
(42)
or
P T + ǒ2
Qg
f SW ) I QǓ
V IN (Watts)
(43)
where
•
IQ is the quiescent operating current (neglecting drivers).
The maximum power capability of the PowerPAD package is dependent on the layout as well as air flow. The
thermal impedance from junction to air, assuming 2-oz. copper trace and thermal pad with solder and no air flow:
q JA + 36.515 CńW
O
(44)
The maximum allowable package power dissipation is related to ambient temperature by Equation 45.
PT +
TJ * TA
(Watts)
q JA
(45)
Substituting Equation 38 into Equation 43 and solving for fSW yields the maximum operating frequency for the
TPS4005x. The result is described in Equation 46.
æ æ (T - TA ) ö
çç J
÷ - IQ
ç çè qJA ´ VIN ÷ø
fSW = ç
2 ´ Qg
ç
ç
è
ö
÷
÷
÷
÷
÷
ø
(Hz )
(46)
8.2 Typical Application
Figure 8-2 shows component selection for the 10-V to 24-V to 3.3-V at 8 A DC-to-DC converter specified in the
design example. For an 8-V input application, it can be necessary to add a Schottky diode from BP10 to BOOST
to get sufficient gate drive for the upper MOSFET. As seen in Figure 6-4, the BP10 output is about 6 V with the
input at 8 V, so the upper MOSFET gate drive can be less than 5 V.
A Schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that can
be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V.
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+
330 µF
330 µF
VIN
RKFF
71.5 kΩ
TPS4005xPWP
100 pF
18.7 kΩ
–
1
KFF
ILIM 16
2
RT
VIN 15
3
BP5
4
SYNC
RT
169 kΩ
1.0 µF
0.1 µF
BOOST 14
22 µF
50 V
22 µF
50 V
1.0 µF 1.0 kΩ
HDRV 13
Si7860
CSS/SD
3300 pF
5
SGND
SW 12
6
SS/SD
BP10 11
2.9 µH
+
R3
6.49 kΩ
C1
330 pF
R2
97.6 kΩ
C2
22 pF
7
VFB
LDRV 10
8
COMP
PGND
9
180 µF
180 µF
R1
100 kΩ
∗optional
Si7860
VO
C3
330 pF
1.0 µF
–
PWP
RBIAS
26.7 kΩ
Copyright © 2017, Texas Instruments Incorporated
Figure 8-2. 24-V to 3.3-V at 8-A DC-DC Converter Design Example
8.2.1 Design Requirements
•
•
•
•
•
•
•
Input voltage: 10 VDC to 24 VDC
Output voltage: 3.3 V ±2% (3.234 ≤ VO ≤ 3.366)
Output current: 8 A (maximum, steady state), 10 A (surge, 10-ms duration, 10% duty cycle maximum)
Output ripple: 33 mVPP at 8 A
Output load response: 0.3 V ≥ 10% to 90% step load change, from 1 A to 7 A
Operating temperature: –40°C to 85°C
fSW = 300 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Calculate Maximum and Minimum Duty Cycles
DMIN =
VO(min )
VIN(max )
=
3.234
= 0.135
24
DMAX =
VO(max )
VIN(min )
=
3.366
= 0.337
10
(47)
8.2.2.2 Select Switching Frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater
than 300 ns (see the Electrical Characteristics). Therefore:
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ææ V
öö
ç ç O(min ) ÷ ÷
ç ç VIN max ÷ ÷
æ V
ö æ
ö
( )ø÷
ç O(min ) ÷ = ç tON ÷ or 1 = fSW = ç è
ç
÷
ç VIN(max ) ÷ è tSW ø
tSW
tON
è
ø
ç
÷
ç
÷
è
ø
(48)
Using 400 ns to provide margin,
f SW + 0.135 + 337 kHz
400 ns
(49)
Since the oscillator can vary by 10%, decrease fSW, by 10%
fSW = 0.9 × 337 kHz = 303 kHz
(50)
and, therefore, choose a frequency of 300 kHz.
8.2.2.3 Select ΔI
In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load.
DI + I O
2
0.2 + 8
2
0.2 + 3.2 A
(51)
8.2.2.4 Calculate the High-Side MOSFET Power Losses
Power losses in the high-side MOSFET (Si7860DP) at 24-VIN where switching losses dominate can be
calculated from Equation 52.
I RMS + I O
Ǹd + 8
Ǹ0.135 + 2.93 A
(52)
Substituting Equation 34 into Equation 33 yields
P COND + 2.932
0.008
(1 ) 0.007
(150 * 25)) + 0.129 W
(53)
and from Equation 35, the switching losses can be determined.
P SW(fsw) + ǒVIN
IO
t SWǓ
f SW + 24 V
8A
20 ns
300 kHz + 1.152 W
(54)
The MOSFET junction temperature can be found by substituting Equation 53 and Equation 54 into Equation 36:
T J + ǒPCOND ) PSWǓ
q JA ) T A + (0.129 ) 1.152)
40 ) 85 + 136 C
O
(55)
8.2.2.5 Calculate Synchronous Rectifier Losses
The synchronous rectifier MOSFET has two loss components, conduction, and diode reverse recovery losses.
The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time
associated with the anti-cross conduction delay.
The IRMS current through the synchronous rectifier from Equation 37:
I RMS + I O
Ǹ1 * d + 8
Ǹ1 * 0.135 + 7.44 A
RMS
(56)
The synchronous MOSFET conduction loss from Equation 33 is:
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PCOND = 7.442 ´ 0.008 ´ 1 + 0.007 ´ (150 - 25 ) = 0.83 W
(
)
(57)
The body diode conduction loss from Equation 38 is:
P DC + 2
IO
V FD
t DELAY
f SW + 2
8.0 A
0.8 V
100 ns
300 kHz + 0.384
(58)
The body diode reverse recovery loss from Equation 39 is:
P RR + 0.5
Q RR
V IN
f SW + 0.5
30 nC
24 V
300 kHz + 0.108 W
(59)
The total power dissipated in the synchronous rectifier MOSFET from Equation 40 is:
P SR + PRR ) PCOND ) PDC + 0.108 ) 0.83 ) 0.384 + 1.322 W
(60)
The junction temperature of the synchronous rectifier at 85°C is:
40 ) 85 + 139 oC
q JA ) T A + (1.322)
T J + PSR
(61)
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.
8.2.2.6 Calculate the Inductor Value
The inductor value is calculated from Equation 24.
L+
(24 * 3.3 V) 3.3 V
+ 2.96 mH
24 V 3.2 A 300 kHz
(62)
A 2.9-µH Coev DXM1306-2R9 or 2.6-µH Panasonic ETQ-P6F2R9LFA can be used.
8.2.2.7 Set the Switching Frequency
The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from
Equation 1, with fSW in kHz.
RT +
ǒ
f SW
1
17.82
10 *6
Ǔ
* 17
kW + 170 kW N use 169 kW
(63)
8.2.2.8 Program the Ramp Generator Circuit
The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from Equation 2:
(
)
RKFF = VIN(min) - 3.48 ´ (58.14 ´ RT + 1340 ) = 72.8kW \ use 71.5kW
(64)
8.2.2.9 Calculate the Output Capacitance (CO)
In this example the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1-A
to 8-A step load. CO can be calculated using Equation 30:
ǒ(8 A)2 * (1 A)2Ǔ
+ 97 mF
ǒ(3.3)2 * (3.0)2Ǔ
2.9 m
CO +
24
Submit Document Feedback
(65)
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Using Equation 25 calculate the ESR required to meet the output ripple requirements.
æ
æ
öö
1
33mV = 3.2 A ç ESR + ç
÷ ÷÷
ç
è 8 ´ 97 mF ´ 300kHz ø ø
è
(66)
ESR = 10.3mW - 4.3mW = 6.0mW
(67)
For this design example two Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.
8.2.2.10 Calculate the Soft-Start Capacitor (CSS/SD)
This design requires a soft-start time (tSTART) of 1 ms. CSS/SD can be calculated using Equation 6:
CSS / SD =
2.35 mA
´ 1ms = 3.36nF @ 3300pF
0.7 V
(68)
8.2.2.11 Calculate the Current Limit Resistor (RILIM)
The current limit set point depends on tSTART, VO,CO and ILOAD at start-up as shown in Equation 7. For this
design,
IILIM >
360 mF ´ 3.3 V
+ 8.0 A = 9.2 A
1 ms
(69)
For this design, add IILIM (9.2 A) to one-half the ripple current (1.6 A) and increase this value by 30% to allow for
tolerances. This yields a overcurrent setpoint (IOC) of 14 A. RDS(on) is increased 30% (1.3 × 0.008) to allow for
MOSFET heating. Using Equation 8 to calculate RILIM.
RILIM =
14 ´ 0.0104 - 0.020
1.12 ´ 8.5 ´ 10-6
+
42.86 ´ 10-3
8.5 ´ 10-6
= 18.24kW @ 18.7kW
(70)
8.2.2.12 Calculate Loop Compensation Values
Calculate the DC modulator gain (AMOD) from Equation 12:
A MOD + 10 + 5.0
2
AMOD(dB) + 20
log (5) + 14 dB
(71)
Calculate the output filter L-CO poles and CO ESR zeros from Equation 13 and Equation 14:
f LC +
1
2p ǸL
CO
+
1
2p Ǹ2.9 mH
360 mF
+ 4.93 kHz
(72)
and
fZ +
2p
1
ESR
CO
+
1
0.006
2p
360 mF
+ 73.7 kHz
(73)
Select the close-loop 0 dB crossover frequency, fC. For this example fC = 20 kHz.
Select the double zero location for the Type III compensation network at the output filter double pole at 4.93 kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7
kHz.
The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 22:
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A MOD(f) + AMOD
ǒ Ǔ
f LC
fC
2
+5
kHzǓ
ǒ4.93
20 kHz
2
+ 0.304
(74)
And also from Equation 22:
G+
1
+ 1 + 3.29
0.304
A MOD(f)
(75)
Choose R1 = 100 kΩ
The poles and zeros for a type III network are described in Equation 17 through Equation 21.
f Z2 +
2p
1
R1
C3
f P2 +
2p
1
R3
C3
fC +
N C3 +
N R3 +
1
2p
R1
C2
f P1 +
2p
1
R2
C2
f Z1 +
2p
1
R2
C1
G
2p
1
100 kW
4.93 kHz
2p
1
330 pF
73.3 kHz
N C2 +
N R2 +
N C1 +
+ 323 pF, choose 330 pF
+ 6.55 kW, choose 6.49 kW
1
2p
100 kW
2p
1
22 pF
2p
1
97.6 kW
3.29
73.3 kHz
20 kHz
+ 24.2 pF, choose 22 pF
+ 98.2 kW, choose 97.6 kW
4.93 kHz
+ 331 pF, choose 330 pF
(76)
(77)
(78)
(79)
(80)
Calculate the value of RBIAS from Equation 15 with R1 = 100 kΩ.
R BIAS + 0.7 V R1 + 0.7 V 100kW + 26.9 kW, choose 26.7 kW
VO * 0.7 V
3.3 V * 0.7 V
(81)
8.2.2.13 Calculate the Boost and BP10V Bypass Capacitance
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass capacitor. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage
droop on the BOOST pin from Equation 31 is:
C BOOST +
Qg
+ 18 nC + 36 nF
DV
0.5 V
(82)
and the BP10V capacitance from Equation 32 is
C BP(10 V) +
Q gHS ) Q gSR
DV
2
+
Qg
+ 36 nC + 72 nF
DV
0.5 V
(83)
For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1-µF capacitor is used for
the BP10V bypass.
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8.2.3 Application Curves
The TPS40055EVM-001 application curves are shown in Figure 8-3 to Figure 8-7 for reference.
7
92
6
PDISS − Power Dissipation − W
94
Efficiency − %
90
88
86
84
82
5
4
3
2
1
80
0
78
0
4
6
8
10
12
IOUT − Output Current − A
2
14
0
16
2
4
6
8
10
12
IOUT − Output Current − A
14
16
Figure 8-4. Power Dissipation vs Load
Figure 8-3. Efficiency vs Load
160
50
Phase
140
40
Gain
20
100
10
80
0
60
−10
40
−20
20
−30
100
1k
Phase − º
120
30
Gain − dB
IOUT = 15 A
0
100 k
10 k
VRIPPLE
(10 mV/div)
t − Time − 1 µs/div
Figure 8-6. Output Voltage Ripple
f − Frequency − kHz
Figure 8-5. Overall Gain and Phase vs Frequency
VOUT = 50 mV/div
IOUT 5 A/div
t − Time − 200 µs/div
Figure 8-7. Transient Response
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 8 V and 40 V. This supply must be
well regulated. Proper bypassing of input supplies and internal regulators is critical for noise performance, as is
PCB layout and grounding scheme. See the recommendations in Section 10.
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10 Layout
10.1 Layout Guidelines
The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that
circuit grounds are properly separated. Each ground must consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (BP10), and the input capacitor must be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, RT, and ILIM must be connected to the SGND plane. The SGND
plane must only make a single point connection to the PGND plane.
Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible
to their respective power and ground pins. Also, sensitive circuits such as FB, RT, and ILIM should not be
located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
10.2 Layout Example
The TPS40055EVM-001 layout is shown in Figure 10-1 to Figure 10-5 for reference.
Figure 10-1. Top-Side Component Assembly
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Figure 10-2. Top-Side Copper
Figure 10-3. Internal Layer 1 Copper
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Figure 10-4. Internal Layer 2 Copper
Figure 10-5. Bottom Layer Copper
10.3 MOSFET Packaging
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions.
In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance
(θJA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends
on proper layout and thermal management. The θJA specified in the MOSFET data sheet refers to a given
copper area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of
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2-ounce copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board
area. Please refer to the selected MOSFET's data sheet for more information regarding proper mounting.
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11 Device and Documentation Support
11.1 Device Support
The following devices have characteristics similar to the TPS40054/5/7 and may be of interest.
Table 11-1. Related Devices
DEVICE
DESCRIPTION
TPS40055-EP
Enhanced performance TPS40055.
TPS40192
4.5-V to 18-V controller with synchronization power good
TPS40193
TPS40200
Wide-input non-synchronous DC-DC controller
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2.
Texas Instruments, PowerPAD Thermally Enhanced Package application note
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS40054PWP
NRND
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40054
TPS40054PWPG4
NRND
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40054
TPS40054PWPR
NRND
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40054
TPS40055PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40055
Samples
TPS40055PWPG4
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40055
Samples
TPS40055PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40055
Samples
TPS40055PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40055
Samples
TPS40057PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40057
Samples
TPS40057PWPG4
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40057
Samples
TPS40057PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40057
Samples
TPS40057PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40057
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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