TPS40075RHLT

TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD FEATURES 1 • Operation Over 4.5-V to 28-V Input Range • Fixed-Frequency Voltage-Mode Controller • Integrated Unity Gain Amplifier for Remote Output Sensing • Predictive Gate Drive™ Generation II for Improved Efficiency • 10 V Output voltage 7 8 4.0 4.3 TA = TJ = 25°C 0.698 0.700 0.704 0°C ≤ TA = TJ ≤ 85°C 0.690 0.700 0.707 -40°C ≤ TA = TJ ≤ 85°C 0.690 0.700 0.715 VVDD = 4.5 V, IOUT = 25 mA 9 V ERROR AMPLIFIER VFB Feedback regulation voltage total variation VSS(offset) Soft-start offset from VSS (1) Offset from VSS to error amplifier (1) 1 GBWP Gain bandwidth AVOL Open loop gain 50 5 ISRC Output source current 2.5 4.5 ISINK Output sink current 2.5 6 IBIAS Input bias current VFB = 0.7 V V 10 MHz dB –250 mA 0 nA SHORT CIRCUIT CURRENT PROTECTION IILIM Current sink into ILIM pin VILIM(ofst) Current limit offset voltage VILIM = 11.5 V, (VSW - VILIM) VVDD = 12 V tHSC Minimum HDRV pulse width During short circuit tBLANK (1) 4 115 135 150 µA –50 –30 –10 mV 135 225 ns Propagation delay to output (1) 50 ns (1) 50 ns Blanking time Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS tOFF Off time during a fault (SS cycle times) VSW Switching level to end precondition (1) tPC Precondition time VILIM(pre) Current limit precondition voltage threshold (2) MIN TYP MAX 7 (VVDD - VSW) 2 (2) UNIT cycles V 100 6.8 ns V OUTPUT DRIVERS tHFALL High-side driver fall time (2) tHRISE High-side driver rise time (2) tHFALL High-side driver fall time (2) (2) tHRISE High-side driver rise time tLFALL Low-side driver fall time (2) tLRISE Low-side driver rise time (2) tLFALL Low-side driver fall time (2) tLRISE Low-side driver rise time (2) VOH High-level output voltage, HDRV VOL Low-level output voltage, HDRV VOH High-level output voltage, LDRV VOL Low-level output voltage, LDRV 36 CHDRV = 2200 pF, (HDRV - SW) ns 48 72 CHDRV = 2200 pF, (HDRV - SW) VVDD= 4.5 V ns 96 24 CLDRV = 2200 pF ns 48 48 CLDRV = 2200 pF, VDD= 4.5 V ns 96 IHDRV= -0.01 A, (VBOOST- VHDRV) 0.7 1.0 IHDRV = -0.1 A, (VBOOST - VHDRV) 0.95 1.35 (VHDRV - VSW), IHDRV = 0.01A 0.06 0.10 (VHDRV - VSW), IHDRV = 0.1 A 0.65 1.00 (VDBP - VLDRV), ILDRV= -0.01A 0.65 1.00 (VDBP - VLDRV), ILDRV = -0.1 A 0.875 1.300 ILDRV = 0.01 A 0.03 0.05 ILDRV = 0.1 A 0.3 0.5 V V V V BOOST REGULATOR VBOOST Output voltage VVDD= 12 V 15.2 17.0 V Programmable UVLO threshold voltage RKFF = 90.9 kΩ, turn-on, VVDD rising 6.2 7.2 8.2 Programmable UVLO hysteresis RKFF = 90.9 kΩ 1.10 1.55 2.00 Fixed UVLO threshold voltage Turn-on, VVDD rising 4.15 4.30 4.45 275 365 UVLO VUVLO Fixed UVLO hysteresis V mV POWER GOOD VPGD Powergood voltage VFBH High-level output voltage, FB IPGD = 1 mA 370 770 VFBL Low-level output voltage, FB 630 550 mV SENSE AMPLIFIER VIO Input offset voltage VSA+ = VSA- = 1.25 V, Offset referenced to SA+ and SA- ADIFF Differential gain VSA+ - VSA- = 4.5 V VICM Input common mode range (3) RG Internal resistance for setting gain IOH Output source current IOL Output sink current GBWP Gain bandwidth (4) -9 0.995 9 mV 1.000 1.005 6 V 14 20 26 kΩ 2 10 15 15 25 35 0 2 mA MHz THERMAL SHUTDOWN (2) (3) (4) Ensured by design. Not production tested. 3 V at internal amplifier terminals, 6 V at SA+ and SA- pins. Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 5 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Shutdown temperature threshold (4) TYP MAX 165 Hysteresis (4) UNIT °C 15 TYPICAL CHARACTERISTICS LVBP VOLTAGE vs JUNCTION TEMPERATURE DBP VOLTAGE vs JUNCTION TEMPERATURE 8.15 4.30 8.10 VDD = 28 V VDD = 28 V VDBP − DBP Voltage − V VLVPP − LVBP Voltage − V 4.25 4.20 VDD = 12 V 4.15 4.10 4.05 8.05 8.00 VDD = 12 V 7.95 7.90 7.85 4.00 −50 −25 0 25 50 100 75 125 7.80 −50 TJ − Junction Temperature − °C Figure 1. 6 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 2. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) DBP VOLTAGE vs JUNCTION TEMPERATURE BOOTSTRAP DIODE VOLTAGE vs JUNCTION TEMPERATURE 4.50 2.0 VDD = 4.5 V ILOAD = 25 mA 1.9 VDROP − Bootstrap Diode Voltage Drop − V 4.49 VDBP − DBP Voltage − V 4.48 4.47 4.46 4.45 4.44 4.43 4.42 4.41 4.40 −50 −25 0 25 50 100 75 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 −50 125 −25 TJ − Junction Temperature − °C 25 50 75 100 125 TJ − Junction Temperature − °C Figure 3. Figure 4. CURRENT LIMIT OFFSET VOLTAGE vs JUNCTION TEMPERATURE CURRENT LIMIT SINK CURRENT vs JUNCTION TEMPERATURE 150 0 145 −10 IILIM − Current Limit Sink Current − µA VILIM(offst) – Current Limit Offset Voltage Drop – mV 0 +3 S −20 Average −30 −40 −3 S −50 −60 −50 −25 0 25 50 75 100 125 140 135 130 125 120 115 VDD 28 V 12 V 4.5 V 110 105 100 −50 TJ – Junction Temperature – °C Figure 5. −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 6. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 7 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) FEEDBACK REGULATION VOLTAGE vs JUNCTION TEMPERATURE SENSE AMPLIFIER OUTPUT CURRENT vs JUNCTION TEMPERATURE 704 30 VFB − Feedback Voltage − V 703 ISENSE − Sense Amplifier Output Current − mA VDD 28 V 4.5 V 12 V 702 701 700 699 698 697 −50 −25 0 25 50 75 100 25 20 15 Low Level Output Current 10 High Level Output Current 5 0 −5 −10 −15 −50 125 −25 TJ − Junction Temperature − °C 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 7. Figure 8. CURRENT SENSE AMPLIFIER GAIN vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs INPUT VOLTAGE 500 1.0005 RRT = 90.1kΩ 499 VDD = 2.5 V 0.9995 fSW − Switching Frequency − kHz ADIFF − Sense Amplifier Gain − V/V 1.000 VDD = 4.5 V 0.9990 0.9985 VDD = 1.25 V 0.9980 VDD = 0.5 V 0.9975 0.9970 0.9965 −50 498 497 496 495 494 493 492 491 490 −25 0 25 50 75 100 125 4 TJ − Junction Temperature − °C Figure 9. 8 8 12 16 20 VVDD − Input Voltage − V 24 28 Figure 10. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 93 VUVLO − Undervoltage Lockout Threshold − V 4.35 DMAX − Maximum Duty Cycle − % 92 91 fSW = 100 kHZ 90 89 88 fSW = 500 kHZ 87 86 85 fSW = 1 MHZ 84 83 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C VUVLO(on) 4.20 4.15 4.10 4.05 4.00 VUVLO(off) 3.95 −25 0 25 50 75 100 TJ − Junction Temperature − °C Figure 11. Figure 12. PROGRAMMABLE UVLO THRESHOLD vs JUNCTION TEMPERATURE SOFTSTART CHARGING CURRENT vs JUNCTION TEMPERATURE 125 14.0 1.08 VUVLO(off) ISS − Soft−Start Charging Current − µA VUVLO − Relative Programmable UVLO Threshold − % 4.25 3.90 −50 125 1.10 VUVLO(on) 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 −50 4.30 −25 0 25 50 75 100 125 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 −50 TJ − Junction Temperature − °C −25 0 25 50 75 100 125 TJ − Junction Temperature − °C Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 9 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) ERROR AMPLIFIER INPUT BIAS CURRENT vs JUNCTION TEMPERATURE MINIMUM OUTPUT VOLTAGE vs FREQUENCY 5.0 −10 VIN = 28 V 4.5 −20 VOUT − Output Voltage − V IBIAS − Error Amplifier Input Bias Current − nA 0 −30 −40 −50 −60 VIN = 8 V 2.5 50 75 100 VIN = 5 V 2.0 1.0 25 VIN = 10 V 3.0 −80 0 VIN = 15 V VIN = 12 V 3.5 1.5 −25 VIN = 18 V 4.0 −70 −90 −50 VIN = 24 V 0.5 100 125 200 300 400 500 600 700 800 900 1000 fOSC − Oscillator Frequency − kHz TJ − Junction Temperature − °C Figure 15. Figure 16. SWITCHING FREQUENCY vs TIMING RESISTANCE TYPICAL SWITCHING FREQUENCY vs INPUT VOLTAGE 520 600 515 fOSC − Frequency − kHz RT − Timing Resistance − kΩ 500 400 300 200 510 505 500 495 490 100 485 480 0 0 200 400 600 800 1000 2 fSW − Switching Frequency − kHz Figure 17. 10 6 10 14 18 22 VDD − Input Voltage − V 26 30 Figure 18. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE 20 20 fSW = 500 kHz UVLOVON 18 VUVLO − Programmable UVLO Threshold − V VUVLO − Programmable UVLO Threshold − V fSW = 300 kHz 16 14 12 UVLOVOFF 10 8 6 4 2 100 16 14 12 UVLOVOFF 10 8 6 4 2 150 200 250 300 350 400 60 450 90 RKFF − Feedforward Impedance − kΩ Figure 19. 120 150 180 210 240 RKFF − Feedforward Impedance − kΩ TYPICAL MAXIMUM DUTY CYCLE vs INPUT VOLTAGE 100 20 fSW = 750 kHz UVLOVON 18 270 Figure 20. UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE UVLO(on) = 15 V 90 16 80 UVLO(on) = 8 V 14 12 Duty Cycle − % VUVLO − Programmable UVLO Threshold − V UVLOVON 18 UVLOVOFF 10 8 60 UVLO(on) = 4.5 V 50 6 40 4 30 2 UVLO(on) = 12 V 70 20 40 60 80 100 120 140 160 RKFF − Feedforward Impedance − kΩ 180 4 Figure 21. 8 12 16 20 24 28 VIN − Input Voltage − V Figure 22. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 11 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) INPUT VOLTAGE vs DBP VOLTAGE INPUT VOLTAGE vs LOW VOLTAGE BYPASS VOLTAGE 4.50 VDBP − Low Voltage Bypass Voltage − V VDBP − Driver Bypass Voltage − V 10 9 8 7 6 5 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 4 0 5 10 15 VDD − Input Voltage − V Figure 23. 20 5 25 10 15 20 25 30 VDD − Input Voltage − V Figure 24. TERMINAL INFORMATION SYNC 1 2 SAO 3 GND LVBP 17 4 SS RT 16 5 FB KFF 15 6 COMP ILIM 14 7 PGND VDD 13 8 LDRV 9 DBP 12 11 10 SW 18 BOOST PGD HDRV 12 19 20 SA− SA+ RHL PACKAGE (BOTTOM VIEW) Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Table 1. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 11 I The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is the available drive voltage for the high-side FET. COMP 6 O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the FB pin to compensate the overall loop. This pin is internally clamped to a 3.4-V maximum output drive capability for quicker recovery from a saturated feedback loop situation. DBP 9 O 8-V regulator output used for the gate drive of the N-channel synchronous rectifier and as the supply for charging the bootstrap capacitor. This pin should be bypassed to ground with a 1.0-µF ceramic capacitor. FB 5 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. GND 3 - Ground reference for the device. HDRV 12 O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). NAME NO. BOOST ILIM 14 I Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage on this pin is compared to the voltage drop (VVDD -VSW) across the high side N-channel MOSFET during conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VVDD/2 and released when SW is within 2 V of VVDD or after a timeout (the precondition time) - whichever occurs first. Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time, effectively programming the ILIM blanking time. See Applications Information section. KFF 15 I A resistor is connected from this pin to VDD programs the amount of input voltage feed-forward. The current fed into this pin is used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at this pin is maintained at 400 mV. LDRV 8 O Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to PGND (MOSFET off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC. LVBP 17 O 4.2-V reference used for internal device logic and analog functions. This pin should be bypassed to GND with a 0.1-µF ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied. PGD 18 O This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10% band around the 700 mV reference voltage. PGND 7 RT 16 I A resistor is connected from this pin to GND to set the switching frequency. SA+ 20 I Noninverting input of the remote voltage sense amplifier. SA- 1 I Inverting input of the remote voltage sense amplifier. SAO 2 O Output of the remote voltage sense amplifier. Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). SS 4 I Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an internal current source of 12 µA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is below the internal offset voltage of 1 V (300 mV minimum ensured), the resulting output voltage is zero. Also provides timing for fault recovery attempts. Pulling this pin below 250 mV causes the controller to enter a shutdown state with HDRV and LDRV held in a low state. SW 10 I This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate drive timing. This pin is also the return path from the high-side FET for the floating high-side FET driver. A 1.5-Ω resistor in series with this pin is required for protection against substrate current issues. SYNC 19 I Logic input for pulse train to synchronize oscillator. VDD 13 I Supply voltage for the device. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 13 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 SIMPLIFIED BLOCK DIAGRAM TPS40075 9 VDD VDD 13 Reference Regulator UVLO Controller DBP 14 ILIM UVLO LVBP 17 RT 16 Oscillator Ramp Generator SW CLK Pulse Control SYNC 19 R R 20 SA+ KFF 15 + SAO 2 1 R PGD 18 Power Good Logic GND 3 770 mV FB 630 mV SS Active 10 SW RAMP ILIM CLK LVBP Soft Start and Fault Control CLK + + SS 4 COMP 6 OC DBP CLK 700 mV Overcurrent Comparator and Control OC OC FB 5 SA− R PWM Predictive Gate Drive Control Logic BOOST 12 HDRV 8 LDRV 7 PGND SW UVLO PGND FAULT 11 IZERO UDG−04076 14 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION The TPS40075 allows the user to construct synchronous voltage mode buck converters with inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease loop compensation for wide input range designs and provide better line transient response. An on-board unity gain differential amplifier is provided for remote sensing in applications that require the tightest load regulation. The TPS40075 incorporates circuitry to allow startup into a pre-existing output voltage without sinking current from the source of the pre-existing output voltage. This avoids damaging sensitive loads at startup. The controller can be synchronized to an external clock source or can free run at a user programmable frequency. An integrated power good indicator is available for logic (open drain) output of the condition of the output of the converter. MINIMUM PULSE WIDTH The TPS40075 has limitations on the minimum pulse width that can be used to design a converter. Reliable operation is guaranteed for nominal pulse widths of 150 ns and above. This places some restrictions on the conversion ratio that can be achieved at a given switching frequency. See Figure 16. SLEW RATE LIMIT ON VDD The regulator that supplies power for the drivers on the TPS40075 requires a limited rising slew rate on VDD for proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot and damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than 0.12 V/μs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in normal operation. This places some constraints on the R-C values that can be used. Figure 25 is a schematic fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R and C that limits the slew rate in the worst case condition. TPS40075 R ILIM 14 13 VDD VIN + _ HDRV 12 C SW 10 7 PGND LDRV 8 UDG−05058 Figure 25. Limiting the Slew Rate Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 15 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Rt f SW 0.2 V Q g(TOT) ) I IDD (1) V *8V C u VIN R SR (2) where • • • • • VVIN is the final value of the input voltage ramp fSW is the switching frequency Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet) IIDD is the TPS40075 input current (3.5 mA maximum) SR is the maximum allowed slew rate [12 ×104] (V/s) SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS40075 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching frequency of the clock oscillator. The clock frequency is related to RT by: RT + ǒ f SW(kHz) 1 17.82 10 *6 Ǔ * 23 kW (3) PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO FUNCTION The ramp generator circuit provides the actual ramp used by the PWM comparator and provides voltage feed-forward by varying the PWM ramp slope as the line voltage changes. As the input voltage to the converter increases, the slope of the PWM ramp increase by a proportionate amount. The programmable UVLO circuit works by monitoring the level reached by the PWM ramp during a clock cycle. The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the converter is not be allowed to start. This programmable UVLO point is set via a single resistor (RKFF) connected from KFF to VDD. RKFF , VSTART and RRT are related by (approximately) R KFF + 0.131 RT V UVLO(on) * 1.61 10*3 2 V UVLO(on) ) 1.886 V UVLO * 1.363 * 0.02 R T * 4.87 10*5 R 2T (4) where • • VUVLO(on) is in volts RKFF and RT are in kΩ This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up ±15% from this number. Figure 19 through Figure 21 show the typical relationship of VUVLO(on), VUVLO(off) and RKFF at three common frequencies. The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice the startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 22 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages If the programmable UVLO voltage is set below 6.5V nominal, a possibility exists that the part may enter factory test mode when powered down. This can cause an undesired output rise as power is removed from the converter. To prevent this from happening, connect a 330 kΩresistor from SS to GND. An example of this can be seen in Figure 37 16 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Figure 26 shows the effect of changing input voltage on the duty cycle, and how that change takes place. The pulse width modulator (PWM) ramp input is generated using a current that is proportional to the current into the KFF pin. The TPS40075 holds this pin at a constant 400 mV, so connecting a resistor from KFF to the input power supply causes a current to flow into the KFF pin that is proportional to the input voltage. The slope of the ramp signal to the PWM is therefore proportional to the input voltage. This allows the duty cycle to change with variations in Vin without requiring much response from the error amplifier, resulting in very good line transient response. Another benefit is essentially constant PWM gain over the entire input voltage operating range. This makes the output control loop easier to design for a wide input range converter. VIN VIN SW SW RAMP VPEAK COMP COMP RAMP VVALLEY tON1 t d + ON T T1 tON2 T2 tON1 > tON2 and d1 > d2 VDG−03172 Figure 26. Voltage Feed-Forward and PWM Duty Cycle Waveforms PROGRAMMING SOFT START TPS40075 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a fixed current, generating a ramp signal. The voltage on SS is level shifted down approximately 1 V and fed into a separate non-inverting input to the error amplifier. The loop is closed on the lower of the level shifted SS voltage or the 700-mV internal reference voltage. Once the level shifted SS voltage rises above the internal reference voltage, output voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-COUT time constant or: t START w 2p ǸL COUT (seconds) (5) where • L is the value of the filter inductor • COUT is the value of the output capacitance • tSTART is the output ramp up-time For a desired soft-start time, the soft-start capacitance, CSS, can be found from: I SS C SS + t SS VFB (6) Please note: There is a direct correlation between tSTART and the input current required during start-up. The lower tSTART is, the higher the input current required during start-up since the output capacitance must be charged faster. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 17 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 PROGRAMMING SHORT CIRCUIT PROTECTION The TPS40075 uses a two-tier approach to short circuit protection. The first tier is a pulse-by-pulse protection scheme. Short circuit protection is implemented by sensing the voltage drop across the high-side MOSFET while it is turned on. The MOSFET drain to source voltage is compared to the voltage dropped across a resistor (RILIM) connected from VDD to the ILIM pin. The voltage drop across this resistor is produced by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of VDD. The ILIM pin is allowed to return to its nominal value after one of two events occur: 1. The SW node rises to within approximately 2 V of VDD 2. An internal timeout occurs, approximately 125-ns after ILIM is initially pulled down If the SW node rises to within approximately 2-V of VDD, the device allows ILIM to go back to its nominal value. This is illustrated in Figure 27 A. T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes the driver delay of 50 ns typical, and the turn on time of the high-side MOSFET. The MOSFET used should have a turn on time less than 75 ns. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to its nominal value, typically 20ns. ILIM ILIM Threshold (A) Overcurrent VIN − 2V SW T2 ILIM T1 VIN − 2V ILIM Threshold (B) SW T1 T3 UDG−03173 Figure 27. Switching and Current Limit Waveforms and Timing Relationship The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire. This is illustrated in Figure 27 B as T3. Here SW never rises to VDD-2, for whatever reason, and the internal timer times out. This allows the ILIM pin to start its transition back to its nominal value. Prior to ILIM starting back to its nominal value, short circuit sensing is not enabled. In normal operation, this insures that the SW node is at a higher voltage than ILIM when short circuit sensing starts, avoiding false trips while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM sets an exponential approach to the normal voltage at the ILIM pin. This exponential “decay” of the short circuit threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate for slower turn-on MOSFETs. Choosing the proper capacitance requires care. If the capacitance is too large, the voltage at ILIM does not approach the desired short circuit level quickly enough, resulting in an apparent shift in short circuit threshold as pulse width changes. 18 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 The comparator that looks at ILIM and SW to determine if a short circuit condition exists has a clamp on its SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as 2 V at – 40°C) below VDD. While ILIM is more than 1.4 V below VDD short circuit sensing is effectively disabled, giving a programmable absolute blanking time. As a general rule, it is best to make the time constant of the R-C at the ILIM pin 20% or less of the nominal pulse width of the converter (See Equation 11) The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a fault condition is declared by the controller. When this happens, the output drivers turn both MOSFETs off. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removed the output starts up normally. If the output fault is still present the counter counts seven overcurrent pulses and re-enters the second tier fault mode. Refer to Figure 28 for typical fault protection waveforms. HDRV Clock tBLANKING VILIM VVIN−VSW SS 7 Current Limit Trips (HDRV Cycle Terminated by Current Limit Trip) 7 Soft-Start Cycles VDG−03174 Figure 28. Typical Fault Protection Waveforms Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 19 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 The minimum short circuit limit threshold (ISCP) depends on tSTART, COUT, VOUT, and the load current at turn-on (ILOAD). C VOUT I SCP u OUT ) I LOAD (A) t START (7) The short circuit limit programming resistor (RILIM) is calculated from: I SCP RDS(onMAX) ) VILIM (ofst) R ILIM + W I ILIM (8) where • • • • IILIM is the current into the ILIM pin (135 μA typical) VILIM(ofst) is the offset voltage of the ILIM comparator (-30 mV typical) ISCP is the short-circuit protection current RDS(on)MAX is the drain-to-source resistance of the high-side MOSFET To find the range of the short circuit threshold values use the following equations. I ILIM(max) RILIM ) 50 mV I SCP(max) + A R DS(onMIN) I SCP(min) + I ILIM(min) RILIM ) 10 mV R DS(onMAX) (9) A (10) The TPS40075 provides short-circuit protection only. As such, it is recommended that the minimum short circuit protection level be placed at least 20% above the maximum output current required from the converter. The maximum output of the converter should be the steady state maximum output plus any transient specification that may exist. The ILIM capacitor maximum value can be found from: V OUT 0.2 C ILIM(max) + (Farads) VIN RILIM f SW (11) Note that this is a recommended maximum value. If a smaller value can be used, it should be to improve protection. For most applications, consider using half the maximum value shown in Equation 11. BOOST AND DBP BYPASS CAPACITANCE The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST capacitor should be a good quality, high-frequency ceramic capacitor. A minimum value of 100-nF is suggested. The DBP capacitor has to provide energy storage for switching both the synchronous MOSFET and the high-side MOSFET (via the BOOST capacitor). The suggested value for this capacitor is 1-μF ceramic, minimum. INTERNAL REGULATORS The internal regulators are linear regulators that provide controlled voltages for the drivers and the internal circuitry to operate from. The low-side driver operates directly from the 8-V regulator supply while the high-side driver bootstrap capacitor is charged from this supply. The actual voltage delivered to the high-side driver is the voltage on the DBP pin less any drop from the bootstrap diode. If the internal bootstrap diode is used, the drop across that diode is nominally 1.4 V at room temperature. This regulator has two modes of operation. At voltages below 8.5 V on VDD, the regulator is in a low dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP. When VDD is above 10 V, the regulator regulates DBP to 8 V. Between these two voltages, the regulator is in whatever state it was in when VDD entered this region. The LVBP pin is connected to a 4.2-V regulator that supplies power for the internal control circuitry. Small amounts of current can be drawn from these pins for other external circuit functions, as long as power dissipation in the controller chip remains at acceptable levels and junction temperature does not exceed 125°C. Any external load connected to LVBP should be electrically quiet to avoid degrading performance of the TPS40075. Typical output voltages for these two regulators are shown in Figure 23 and Figure 24. 20 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 DIFFERENTIAL SENSE AMPLIFIER The TPS40075 has an on board differential amplifier intended for use as a remote sensing amplifier for the output voltage. Use of this amplifier for remote sensing eliminates load regulation issues due to voltage drops that occur between the converter and the actual point of load. The amplifier is powered from the DBP pin and can be used to monitor output voltages up to 6 V with a DBP voltage of 8 V. For lower DBP voltages, the sense amplifier can be used to monitor output voltages up to 2-V below the DBP voltage. The internal resistors used to configure the amplifier for unity gain match each other closely, but their absolute values can vary as much as 30%, so adding external resistance to alter the gain is not accurate in a production environment. SYNCHRONIZATION The SYNC pin accepts logic level signals and is used to synchronize the TPS40075 to an external clock source. Synchronization occurs on the rising edge of the signal at the SYNC pin. There is a fixed delay of approximately 300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high-side FET. The pin may be left floating in this function is not used, or it may be connected to GND. The frequency of the external clock must be greater than the free running frequency of the device as set by the resistor on the RT pin (RRT). This pin requires a totem pole drive, or open collector/drain if pull up resistor to either LVBP or a separate supply between 2.5 V and 5 V is used. Synchronization does not affect the modulator gain due to the voltage feed forward circuitry. The programmable UVLO thresholds are affected by synchronization. The thresholds are shifted by the ratio of the sync frequency to the free running frequency of the converter. For example, synchronizing to a frequency 20% higher than the free running frequency results in the programmable UVLO thresholds shifting up 20% from their calculated free run values. The synchronization frequency should be kept less than 1.5 times the free run frequency for best performance, although higher multiples can be used. POWERGOOD OPERATION The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met (assuming that the input voltage is above 4.5 V) • Soft-start is active (VVSS < 3.5 V) • VFB < 0.63 V • VFB > 0.77 V • Programmable UVLO condition not satisfied (VIN below programmed level) • Overcurrent condition exists • Die temperature is greater than 165°C PRE-BIASED OUTPUTS Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the output. Since synchronous buck converters inherently sink current some method of overcoming this characteristic must be employed. Applications that require this operation are typically power rails for a multi supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn on until there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage. This is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage is commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current only during the startup sequence. If the pre-existing voltage is higher that the intended regulation point for the output of the converter, the converter starts and sinks current when the soft-start time has completed SHUTDOWN AND SEQUENCING The TPS40075 can be shut down by pulling the SS pin to a level below 250 mV. Pulling the pin low resets the internal pre-bias circuitry to ensure that the converter does not damage sensitive loads. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 21 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Automatic startup sequencing can be accomplished by connecting the PGD pin of a master supply based on the TPS40075 to the SS pin of a slave supply. The master comes up first and release the salve SS pin to allow the slave to come up. Controlled shutdown of sequenced supplies can be accomplished by either pulling the SS pin of the master below the shutdown threshold and letting the PGD pin pull the slave SS pin down, or by pulling down the SS pins of all supplies simultaneously. TPS40075 POWER DISSIPATION The power dissipation in the TPS40075 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance) can be calculated from: P D + Q g VDR f SW (Wattsńdriver) (12) where • VDR is the driver output voltage The total power dissipation in the TPS40075, assuming the same MOSFET is selected for both the high-side and synchronous rectifier is described in Equation 13. 2 PD PT + ) IQ V IN (Watts) V DR ǒ Ǔ (13) or P T + ǒ2 f SW ) I QǓ Qg V IN (Watts) (14) where • IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the TPS40075 PowerPAD package is dependent on the layout as well as air flow. The thermal impedance from junction to air ambient assuming 2-oz. copper trace and thermal pad with solder and no air flow is θJA = 60 °C/W The maximum allowable package power dissipation is related to ambient temperature by Equation 15. T * TA PT + J (Watts) q JA (15) Substituting Equation 15 into Equation 14 and solving for fSW yields the maximum operating frequency for the TPS4007x. The result is described in Equation 16. ǒƪ ǒT J*T AǓ ƫ ǒq JA V INǓ f SW + ǒ2 * IQ Ǔ Q gǓ (Hz) (16) BOOST DIODE The TPS40075 has internal diodes to charge the boost capacitor connected from SW to BOOST. The drop across this diode is rather large at 1.4-V nominal at room temperature resulting in the drive voltage to the high-side MOSFET being reduced by this amount from the DBP voltage. If this drop is too large for a particular application, an external diode may be connected from DBP (anode) to BOOST (cathode). This provides significantly improved gate drive for the high-side MOSFET, especially at lower input voltages. 22 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 GROUNDING AND BOARD LAYOUT The TPS40075 provides separate signal ground (GND) and power ground (PGND) pins. Care should be given to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane. Sensitive nodes such as the FB resistor divider and RT should be connected to the GND plane. The GND plane should only make a single point connection to the PGND plane. It is suggested that the GND pin be tied to the copper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as well and make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the GND pin. Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout practices results in sub-optimal operation. SYNCHRONOUS RECTIFIER CONTROL Table 2 describes the state of the rectifier MOSFET control under various operating conditions. Table 2. Synchronous Rectifier MOSFET States SYNCHRONOUS RECTIFIER OPERATION DURING SOFT-START NORMAL FAULT (FAULT RECOVERY IS SAME AS SOFT-START) OVERVOLTAGE Off until first high-side pulse is detected, then on when high-side MOSFET is off Turns off at the start of a new cycle. Turns on when the high-side MOSFET is turned off OFF Turns OFF only at start of next cycle ON if duty cycle is > 0 For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 23 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 DESIGN EXAMPLE 1. SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10.8 12.0 13.2 INPUT CURRENT VIN Input voltage VO Output voltage IOUT = 10 A 1.5 Regulation 1.47 5 V 1.53 VRIPPLE Output ripple voltage IO(max) = 15 A 30 VOVER Output overshoot ISTEP = 8 A 50 VUNDER Output undershoot ISTEP = 8 A 50 ILOAD Output current ISCP Short circuit current trip point η Efficiency fSW Switching frequency mV 0 15 16 30 VIN = 12 V, ILOAD = 15 A A 85% 400 kHz 2. SCHEMATIC VIN −SENSE SYNC CIN ELCO CPZ1 RP1 +SENSE 1 20 SA− SA+ TPS40075 RKFF RLIM RZ1 2 SAO SYNC 19 3 GND PGD 18 RPGD CZ2 CP2 SS LVBP 17 5 FB RT 16 4 RPZ2 6 COMP KFF 15 7 PGND ILIM 14 8 LDRV VDD 13 CLIM QSW 9 DBP HDRV 12 L SW BOOST 10 11 RT CVLVBP VO CVDD 1.5 Ω RSET2 QSR RSET1 DBOOST CSS CO ELCO CBOOST CO MLCC CDBP 0V UDG−04125 Figure 29. TPS40075 Reference Design Schematic 24 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 3. COMPONENT SELECTION 3. 1 Power Train Components Designers familiar with the buck converter can skip to section 3.2 Component Selection for TPS40075. 3.1.1 Output Inductor, LO The output inductor is one of the most important components to select. It stores the energy necessary to keep the output regulated when the switch MOSFET is turned off. The value of the output inductor dictates the peak and RMS currents in the converter. These currents are important when selecting other components. Equation 17 can be used to calculate a value for L. L+ ǒV IN(max) * V OǓ VO V IN(max) f SW DI (17) Δ I is the allowable ripple in the inductor. Selecting ΔI also sets the output current when the converter goes into discontinuous mode (DCM) operation. Since this converter utilizes MOSFETs for the rectifier, DCM is not a major concern. Select ΔI to be between 20% and 30% of maximum ILOAD. For this design, ΔI of 3 A was selected. The calculated L is 1.1 μH. A standard inductor with value of 1.0 μH was chosen. This increases ΔI by about 10% to 3.3 A. With this ΔI value, calculate the RMS and peak current flowing in LO. Note this peak current is also seen by the switching MOSFET and synchronous rectifier. I LOAD_RMS + ǸI 2 LOAD 2 ) DI + 15.03 A 12 (18) 2 I PK + I LOAD ) DI + 16.65 A 2 (19) 3.1.2 Output Capacitor, CO, ELCO and MLCC Several parameters must be considered when selecting the output capacitor. The capacitance value should be selected based on the output overshoot, VOVER, and undershoot, VUNDER, during a transient load, ISTEP, on the converter. The equivalent series resistance (ESR) is chosen to allow the converter meet the output ripple specification, VRIPPLE. The voltage rating must be greater than the maximum output voltage. Other parameters to consider are: equivalent series inductance which is important in fast transient load situations. Also size and technology can be factors when choosing the output capacitor. In this design a large capacitance electrolytic type capacitor, CO ELCO, is used to meet the overshoot and under shoot specifications. Its ESR is chosen to meet the output ripple specification. While a smaller multiple layer ceramic capacitor, CO MLCC, is used to filter high frequency noise. The minimum required capacitance and maximum ESR can be calculated using the equations below. CO u L 2 V UNDER I STEP D MAX 2 ǒV IN * V OǓ (20) 2 CO u L I STEP 2 V OVER V O ESR t (21) V RIPPLE DI (22) Using Equation 20 through Equation 22, the capacitance for CO should be greater than 495 μF and its ESR should be less than 9.1mΩ. The 1000 μF/25 V capacitor from Rubycon's MBZ or Panasonic's series EEU-FL was chosen. Its ESR is 19 mΩ, so two in parallel are used. The slightly higher ESR is offset by the four times increase in capacitance. A 2.2 μF/16 V MLCC is also added in parallel to reduce high frequency noise. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 25 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 3.1.3. Input Capacitor, CIN, ELCO and MLCC The input capacitor is selected to handle the ripple current of the buck stage. Also a relative large capacitance is used to keep the ripple voltage on the supply line low. This is especially important where the supply line is high impedance. It is recommended that the supply line be kept low impedance. The input capacitor ripple current can be calculated using Equation 23. I CAP(RMS) + Ǹƪǒ I LOAD(max) * I IN(avg) Ǔ ) DI122ƫ 2 D ) I IN(avg) 2 (1 * D) (23) where • IIN(avg) is the average input current This is calculated simply by multiplying the output DC current by the duty cycle. The ripple current in the input capacitor is 5.05 A. A 1206 MLCC using X7R material has a typical dissipation factor of 5%. For a 2.2 μF capacitor at 400 kHz the ESR is approximately 7.2 mΩ. If two capacitors are used in parallel the power dissipation in each capacitor is less than 46 mW. A 470 μF/16 V electrolytic capacitor is added to maintain the voltage on the input rail. 3.1.4 Switching MOSFET, QSW The following key parameters must be met by the selected MOSFET. • Drain source voltage, VDS, must be able to withstand the input voltage plus spikes that may be on the switching node. For this design a VDS rating of 25 V to 30 V is recommended. • Drain current, ID, at 25°C, must be greater than that calculated using Equation 24. For this design, ID should be greater than 5 A. ID + • Ǹ VO VIN(min) ǒI 2 LOAD(max) 2 ) DI 12 Ǔ (24) Gate source voltage, VGS must be able to withstand the gate voltage from the control device . For the TPS40075 this is 9 V. Once the above boundary parameters are defined the next step in selecting the switching MOSFET is to select the key performance parameters. Efficiency is the performance characteristic which drives the other selection criteria. Target efficiency for this design is 90%. Based on 1.5-V output and 15 A this equates to a power loss in the converter of 2.5 W. Using this figure a target of 0.5 W dissipated in the switching MOSFET was chosen. 26 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Equation 25 through Equation 28 can be used to calculate the power loss, PQSW, in the switching MOSFET P QSW + PQSW(CON) ) PQSW(SW) ) PQSW(GATE) P QSW(CON) + RDS(on) P QSW(SW) + VIN f SW P QSW(GATE) + Q g(TOT) 2 I D + R DS(on) VO V IN ǒI 2 LOAD ) 12 Ǔ (26) ȱǒILOAD ) DI2Ǔ ǒQ gs1 ) QgdǓ QOSS(SW) ) QOSS(SR)ȳ ) ȧ ȧ 2 Ig Ȳ ȴ Vg (25) DI 2 F SW (27) (28) where • • • • • • • • • • PQSW(CON) = conduction losses PQSW(SW) = switching losses PQSW(GATE) = gate drive losses Qgd = drain source charge or miller charge Qgs1 = gate source post threshold charge Ig = gate drive current QOSS(SW) = switching MOSFET output charge QOSS(SR) = synchronous MOSFET output charge Qg(TOT) = total gate charge from zero volts to the gate voltage Vg = gate voltage If the total estimated loss is split evenly between conduction and switching losses, Equation 25 and Equation 26 yields preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been ignored here. Once a MOSFET is selected these parameters can be added. The switching MOSFET for this design should have an RDS(on) of less than 9 mΩ. The sum of Qgd and Qgs should be approximately 4 nC. It is not always possible to get a MOSFET which meets both these criteria so a comprise may have to be made. Also by selecting different MOSFETs close to this criteria and calculating power loss the final selection can be made. It was found that the PH6325L MOSFET from Philips semiconductor gave reasonable results. This device has an RDS(on) of 6.3 mΩ and a (Qgs1+Qgd) of 5.9 nC. The estimated conduction losses are 0.178 W and the switching losses are 0.270 W. This gives a total estimated power loss of 0.448 W versus 0.5 W for our initial boundary condition. Note this does not include gate losses of approximately 10 mW and output losses of less than 1 mW. 3.1.5 Rectifier MOSFET, QSR Similar criteria can be used for the rectifier MOSFET. There is one significant difference. Due to the body diode conducting, the rectifier MOSFET switches with near zero voltage across its drain and source so effectively with near zero switching losses. However, there are some losses in the body diode. These are minimized by reducing the delay time between the transition from the switching MOSFET turn off to rectifier MOSFET turn on and vice versa. The TPS40075 incorporates TI's proprietary predictive gate drive which helps reduce this delay to between 10 ns and 20 ns. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 27 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 The calculations for the losses in the rectifier MOSFET are show in Equation 29 through Equation 32. P QSR + PQSR(CON) ) PDIODE ) PQSR(GATE) 2 P QSW(CON) + RDS(on) I D + R DS(on) P DIODE + Vf ǒt1 ) t 2Ǔ I LOAD VO V IN ǒI 2 LOAD ) (29) DI 2 12 Ǔ (30) f SW (31) V K PWM ^ UVLO 1V (32) where • • • • PDIODE = body diode losses t1 = body diode conduction prior to turn on of channel = 10 ns for predictive gate drive t2 = body diode conduction after turn off of channel = 10 ns for predictive gate drive Vf = body diode forward voltage Estimating the body diode losses based on a forward voltage of 1.2 V gives 0.142 W. The gate losses are unknown at this time so assume 0.1 W gate losses. This leaves 0.258 W for conduction losses. Using this figure a target RDS(on) of 1.1 mΩ was calculated. This is an extremely low value. It is not possible to meet this without paralleling multiple MOSFETs. Paralleling MOSFETs increases the gate capacitance and slows down switching speeds. This increases body diode and gate losses. The PH2625L from Philips was chosen. Using the parameters from its data sheet the actual expected power losses were calculated. Conduction loss is 0.527 W, body diode loss is 0.142 W and the gate loss was 0.174 W. This totals 0.843 W associated with the rectifier MOSFET. This is somewhat greater than the initial allowance. Because of this the converter may not hit its efficiency figure at the maximum load. Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensure that predictive gate drive functions correctly. The maximum turn off delay of the PH2625L is 67 ns. The minimum turn on delay of the PH6325L is 25 ns. These devices easily meet the 100 ns difference requirement. Secondly the ratio between Cgs and Cgd should be greater than 1. The Cgs of the PH2625L is 2133 pF and the Cgd is 1622 pF, so the Cgs:Cgd ratio is 1.3:1. This helps reduce the risk of dv/dt induced turn on of the rectifier MOSFET. If this is likely to be a problem a small resistor may be added in series with the boost capacitor, CBOOST. 3.2 Component Selection for TPS40075 3.2.1 Timing Resistor, RT The timing resistor is calculated using the following equation. 1 RT + * 23 f SW 17.82 10 *6 (33) This gives a resistor value of 89.2 kΩ. Using the E24 range of resistor values a 118-kΩ resistor was selected. The nominal frequency using this resistor is 398 kHz. 3.2.2 Feed Forward and UVLO Resistor, RKFF A resistor connected to the KFF pin of the device feeds into the ramp generator. This resistor provides current into the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different input voltages. Is provides the voltage feed forward feature of the TPS40075. The same resistor also sets the under voltage lock out point. The input start voltage should be used to calculate a value for RKFF. For this converter the minimum input voltage is 10.8 V however due to tolerances in the device, a start voltage of 15% less than the minimum input voltage is selected. The start voltage for RKFF calculation is 9.18 V. Using Equation 34 RKFF can be selected. 28 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com R KFF + SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ǒVUVLO(on) * 0.5Ǔ ǒ 0.018 ) ǒ ǓǓ 5 RT (34) This equation gives a RKFF value of 136 kΩ. The closest lower standard value should be selected. For this design and using E24 resistor range 133 kΩ was chosen. This yields a typical start voltage of 8.52 V. 3.2.3 Soft Start Capacitor It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible damage to the load. The selection of the soft start time is arbitrary, but it must meet one condition; it should be greater than the time constant of the output filter, L and CO. This time is given by Equation 35 t START w 2p ǸL CO (35) The soft-start time must be greater than 0.281 ms. A time of 1 ms was chosen, this time also helps keep the initial input current during start up low. The value of CSS can be calculated using Equation 36. *6 C SS w 12 10 t START 0.7 (36) CSS should be greater than 17 nF, a 22 nF MLCC was chosen. The calculated start time using this capacitor is 1.28 ms. 3.2.4 Short Circuit Protection, RILIM and CILIM Short circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of the switching MOSFET selected and the required short circuit current trip point, ISCP. The minimum ISCP is limited by the inductor peak current, the output voltage, the output capacitor and the soft start time. Their relationship is given by Equation 37. A short circuit current trip point greater than that calculated by this equation should be used. C VOUT I SCP w O ) I LOAD DI t START 2 (37) The minimum short circuit current trip point for this design is 16.35 A. This value is used in Equation 38 to calculate the minimum RILIM value. I SCP RDS(on)MAX ) VILIM(min) R ILIM w I SINK(max) (38) RILIM is calculated to be 1.14 kΩ . The closest standard value greater than 1.14 kΩ is chose, this is 1.15 kΩ. To verify that the short circuit current requirements are met the minimum and maximum short circuit current can be calculated using Equation 39 and Equation 40. I SINK(min) RILIM(min) * VILIM(max) I SCP(min) + R DS(on)MIN (39) I SCP(max) + I SINK(max) RILIM(max) * VILIM(min) RDS(on)MAX (40) The minimum ISCP is 17.09 A and the maximum is 29.45 A. It is recommended to add a small capacitor, CILIM, across RILIM. The value of this capacitor should be less than that calculated in Equation 41. V O 0.2 C ILIM(max) + VIN RILIM f SW (41) This equation yields a maximum CILIM of 44 pF. A value half this is chosen, 22 pF. Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 29 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 3.2.5 Voltage Decoupling Capacitors, CDBP, CLVBP and CVDD Several pins on the TPS40075 have DC voltages. It is recommended to add small decoupling capacitors to these pins. Below is a list of the recommended values. • CDBP = 1.0 μF • CLVBP = 0.1 μF • CVDD = 4.7 μF 3.2.6 Boost Voltage, CBOOST and DBOOST (optional) A capacitor charge pump or boost circuit is required to drive an N-channel MOSFET in the switch location of a buck converter . The TPS40075 contains the elements for this boost circuit. The designer just has to add a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the device. Selection of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the boost voltage, ΔVBOOST. A ripple of 0.15 V is assumed for this design. Using these two parameters and Equation 42 the minimum value for CBOOST can be calculated. Q g(TOTAL) C BOOST u DVBOOST (42) The total gate charge of the switching MOSFET is 13.3 nC. A minimum CBOOST of 0.089 μF is required. A 0.1 μF capacitor was chosen. This capacitor must be able to withstand the maximum voltage on DBP (10 V in this instance ). A 50 V capacitor is used for expediancy. To reduce losses in the TPS40075 and to increase the available gate voltage for the switching MOSFET an external diode can be added between the DBP pin and the BOOST pin of the device. A small signal schottky should be used here, such as the BAT54. 3.3 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 and CPZ1 A graphical method is used to select the compensation components. This is a standard feedforward buck converter. Its PWM gain is shown in Equation 43. V K PWM ^ UVLO 1V (43) The gain of the output L-C filter is given by Equation 44 ǒ1 ) s K LC + 1)s ǒ C OǓ ESR Ǔ L ) s2 RLOAD L CO (44) The PWM and LC gain is, shown in Equation 45. G e(s) + KPWM KLC + ǒ1 ) s V UVLO 1V 1)s ǒ ESR Ǔ L ) s2 R LOAD C OǓ L CO (45) To describe this in a Bode plot, the DC gain must be expressed in dB. The DC gain is equal to KPWM. To express this in dB we take its LOG and multiple by 20. For this converter the DC gain is shown in Equation 46. V DCGAIN + 20 LOG UVLO + 20 LOG(8.752) + 18.8 dB 1V ǒ Ǔ (46) The pole and zero frequencies should be calculated, also. A double pole is associated with the L-C and a zero is associated with the ESR of the output capacitor. The frequency at where these occur can be calculated using the following two equations. 30 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com f LC_Pole + SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 1 ǸL 2p f ESR_Zero + 2p CO 1 ESR + 3559 Hz (47) CO + 8377 Hz (48) The resulting bode plot is shown in Figure 30. 30 Double Pole 20 10 ESR Zero Gain − dB 0 −10 ESR = 0.0095 Ω Slope = −20 dB / decade −20 −40 ESR = 0 Ω Slope = −40 dB / decade −50 −60 100 1k 10 k 100 k 1M Frequency − Hz Figure 30. PWM and LC Filter Gain The next step is to establish the required compensation gain to achieve the desired overall system response. The target response is to have the crossover frequency between 1/10 to 1/4 times the switching frequency. To have a phase margin greater than 45° and a gain margin greater than 6 dB. A Type III compensation network, as shown in Figure 31, was used for this design. This network gives the best overall flexibility for compensating the converter. CPZ1 RP1 TPS40075 RZ1 CP2 2 SAO 5 FB 6 COMP CZ2 RPZ2 RSET2 RSET1 UDG−04126 Figure 31. Type III Conpensation with TPS40075 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 31 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 A typical bode plot to this type of compensation network is shown in Figure 32. 40 Gain − dB 30 High Frequency Gain 20 10 0 −10 −20 100 1k fZ1 10 k fP1 fZ2 Frequency − Hz 100 k 1M fP2 Figure 32. Type III Compensation Bode Plot The high frequency gain and the break (pole and zero) frequencies are calculated using the following equations. RZ1 ) RSET V O + VFB RSET (49) R SET + RSET1 RSET2 RSET1 ) RSET2 GAIN + f P1 + f P2 + f Z1 + f Z2 + (50) RPZ2 ǒ Ǔ R Z1 RP1 R Z1)RP1 (51) 1 2p R P1 C PZ1 2p C P2 ) CZ2 R PZ2 C P2 (52) C Z2 ^ 1 R PZ2 2p CP2 (53) 1 2p R Z1 C PZ1 2p 1 ǒR PZ2 ) R P1Ǔ (54) C Z2 ^ 1 2p R PZ2 CZ2 (55) Using this PWM and L-C bode plot the following actions ensure stability. 1. Place two zero’s close to the double pole, i.e. fZ1 = fZ2 = 3559 Hz 2. Place a pole at one octave below the desired crossover frequency. The crossover frequency was selected as one quarter the switching frequency, fCO = 100 kHz, fP1 = 50 kHz 3. Place the second pole about an octave above fco. This ensures that the overall system gain falls off quickly to give good gain margin, fP2 = 200 kHz 4. The high-frequency gain is sufficient to ensure 0 dB at the required crossover frequency, GAIN = -1 GAIN of PWM and LC at the crossover frequency, GAIN = 17.6 dB, or 7.586 32 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Desired frequency response and resultant overall system response can be seen in Figure 33. 40 Overall System Response ESR = 0 Ω 30 20 GBWP Overall System Response ESR = 0.0095 Ω Gain − dB 10 0 −10 −20 −30 −40 −50 Compensation Response PWM and LC Response ESR = 0 Ω PWM and LC Response ESR = 0.0095 Ω fCO2 −60 100 1k fCO1 10 k 100 k 1M Frequency − Hz Figure 33. Overall System Bode Plot Using these values and the equations above the resistors and capacitors around the compensation network can be calculated. 1. Set RZ1 = 10 kΩ. 2. Calculate RSET using Equation 49; RSET = 8750 Ω. Two resistors in parallel, RSET1 and RSET2, are used to make up RSET. RSET1 = 9.53 kΩ, RSET2 = 105 kΩ. 3. Using Equation 54 and fZ1 = 3559 Hz, CPZ1 can be calculated to be 4.47 nF; CPZ1= 4.7 nF. 4. FP1 and Equation 52 yields RP1 to be 677 Ω, RP1 = 680 Ω. 5. The required gain of 17.6 dB (7.586) and Equation 52 sets the value for RPZ1. Note actual gain used for this calculation was 20 dB (10), this ensures that the gain of the transfer function is high enough, RPZ1 = 6.2 kΩ. 6. CZ2 is calculated using Equation 55 and the desired frequency for the second zero, CZ2 = 6.8 nF. 7. CP2 is calculated using the second pole frequency and Equation 53, CP2 = 150 pF. Using MathCAD the above values were used to draw the actual Bode plot for gain and phase. From these plots the crossover frequency, phase margin and gain margin can be recorded. Table 3. Equivalent Series Resistance ESR (Ω) CROSSOVER FREQUENCY (kHz) PHASE MARGIN (°) GAIN MARGIN (dB) 0 0.0095 23.1 72 > 46 98.6 78.8 > 33 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 33 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 GAIN vs FREQUENCY PHASE vs FREQUENCY 200 60 180 40 System Gain ESR = 0.95 mΩ 140 Phase − ° 20 Gain − dB System Phase ESR = 0 Ω 160 0 120 100 80 −20 60 40 −40 System Gain ESR = 0 Ω −60 100 1k 10 k Frequency − Hz 20 100 k 1M 0 100 System Phase ESR = 0.95 mΩ 1k Figure 34. 10 k 100 k Frequency − Hz 1M Figure 35. ALTERNATE APPLICATIONS Some alternative applicaiton diagrams are shown in Figure 36 through Figure 38. 34 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 1 20 External Logic Supply SA− SA+ TPS40075 402 Ω 10 nF 10 kΩ 2 SAO SYNC 19 3 GND PGD 18 4 SS 5 FB 6 COMP 14 kΩ Power Good 1 µF LVBP 17 2 nF 2 nF 10 kΩ VDD 12 V 118 kΩ RT 16 10 kΩ 118 kΩ KFF 15 75 pF 1.27 kΩ 120 µF 120 µF ILIM 14 7 PGND 8 LDRV 22 pF VDD 13  1 µF Si7390DP 9 DBP 22 µF HDRV 12 SW BOOST 10 11 22 µF 100 nF 1.3 µH
1.5 Ω  100 nF Si7868DP
COEV DXM1306 100 µF, TDK, C3225X5R0J107M (× 3)  TDK C4532X5R1C226M (× 2) 1.2 V 10 A UDG−04109 Figure 36. 400 kHz, 12 V to 1.2 V Converter with Powergood Indication Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 35 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 1 20 SA− SA+ TPS40075 294 Ω 2 SAO SYNC 19 3 GND PGD 18 1 µF 10 nF 10 kΩ LVBP 17 330 kΩ 4 SS 5 FB VDD 5 V to 12 V 165 kΩ 3.9 nF 3.3 nF From 3.3 V Logic Clock Source RT 16 88.7 kΩ 11.3 kΩ 6 KFF 15 COMP 120 µF 120 µF 1.74 kΩ 100 pF ILIM 14 2.67 kΩ 7 PGND 8 LDRV 39 pF VDD 13  1 µF Si7344DP 9 DBP 22 µF HDRV 12 SW BOOST 10 11 22 µF 100 nF 2.2 µH
BAT54 1.5 Ω 100 nF 3.3 V  180 µF 180 µF 15 A Si7868DP UDG−04110
Coiltronics HC2LP−2R2 or Vishay IHLP5050FDRZ2R2M01  Panasonic EEF−SE0J181R (× 2)  TDK C4532X5R1C226M (×2) Figure 37. 300 kHz Intermediate Bus (5 V to 12 V) to 3.3 V Converter 36 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 14 kΩ 10 kΩ Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 1 µF 75 pF 10 kΩ 10 nF Si7868DP 2 nF 2 nF 402 Ω HDRV 12 VDD 13 ILIM 14 KFF 15 RT 16 LVBP 17 PGD 18 SYNC 19 10 100 n 1.5 Ω 11 SW BOOST 9 DBP 8 LDRV 7 PGND 6 COMP FB 4 SS 3 GND 5 20 SA− SA+ TPS40075 1 2 SAO SYNC Clock Input 300 kHz 10 kΩ 100 nF Si7390DP 22 µF 120 µF 100 µF × 3 22 µF 120 µF 13 µH VDD, 12 V 22 pF 1.27 kΩ 205 kΩ 215 kΩ 1 µF SN74LVC1G04 1.2 V 10 A 2.67 kΩ 1 µF 120 pF 2 SAO 3 GND HDRV 12 VDD 13 ILIM 14 KFF 15 RT 16 LVBP 17 PGD 18 SYNC 19 100 nF 1.5 Ω Si7806DN 10 11 SW BOOST 9 DBP 8 LDRV 7 PGND 6 COMP 5 FB 4 SS 10 nF 8.06 kΩ 3.3 nF 267 Ω 3.9 nF 10 kΩ 20 SA− SA+ TPS40075 1 100 nF 47 pF 787 Ω 2.2 µH Si7804DN 205 kΩ 215 kΩ 1 µF 180 µF 180 µF 3.3 V 5A UDG−04111 22 µF Power Good VDD 12 V 10 kΩ 3.3 V or Other Logic Supply www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TPS40075 Figure 38. Sequenced Supplies, Synchronized 180° Out of Phase Submit Documentation Feedback 37 TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ADDITIONAL REFERENCES The following parts are similar to the TPS40075 and may be of interest: 1. TPS40071 Mid Range Input (4.5 V to 28 V) up to 1-MHz Frequency Synchronous Buck Controller 2. TPS40100 Wide Input Range Synchronous Buck Controller for Sequencing 3. TPS40057 Wide Input (8 V to 40 V) up to 1MHz Frequency Synchronous Buck Controller, source/sink with prebias 4. TPS40190 Low Pin Count Synchronous Buck DC/DC Controller 38 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40075RHLR VQFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 TPS40075RHLT VQFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40075RHLR VQFN RHL 20 3000 356.0 356.0 35.0 TPS40075RHLT VQFN RHL 20 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE VQFN - 1 mm max height RHL0020A PLASTIC QUAD FLATPACK- NO LEAD A 3.6 3.4 B PIN 1 INDEX AREA 4.6 4.4 C 1 MAX SEATING PLANE 0.08 C 2.05±0.1 2X 1.5 20X 0.5 0.3 SYMM 10 14X 0.5 2X 3.5 9 12 SYMM 21 3.05±0.1 19 2 PIN 1 ID (OPTIONAL) (0.2) TYP 11 1 20 4X (0.2) 2X (0.55) 20X 0.29 0.19 0.1 0.05 C A B C 4219071 / A 05/2017 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RHL0020A PLASTIC QUAD FLATPACK- NO LEAD (3.3) (2.05) 2X (1.5) SYMM 1 20 2X (0.4) 20X (0.6) 19 2 20X (0.24) 14X (0.5) SYMM 21 (3.05) (4.3) 6X (0.525) 2X (0.75) SOLDER MASK OPENING METAL UNDER SOLDER MASK 9 12 (R0.05) TYP (Ø0.2) VIA TYP) 11 10 4X (0.2) 4X (0.775) 2X (0.55) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X 0.07 MAX ALL AROUND EXPOSED METAL SOLDER MASK OPENING 0.07 MIN ALL AROUND SOLDER MASK OPENING EXPOSED METAL METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4219071 / A 05/2017 NOTES: (continued) 4. 5. 6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . Solder mask tolerances between and around signal pads can vary based on board fabrication site. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RHL0020A PLASTIC QUAD FLATPACK- NO LEAD (3.3) 2X (1.5) (0.55) TYP 1 20 (0.56) TYP SOLDER MASK EDGE TYP 20X (0.6) 2 19 20X (0.24) 14X (0.5) (1.05) TYP SYMM (4.3) 21 6X (0.85) (R0.05) TYP METAL TYP 12 9 2X (0.775) 2X (0.25) 11 10 4X (0.2) 6X (0.92) SYMM SOLDER PASTE EXAMPLE BASED ON 0.1mm THICK STENCIL EXPOSED PAD 75% PRINTED COVERAGE BY AREA SCALE: 20X 4219071 / A 05/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. 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