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TPS40077
SLUS714E – JANUARY 2007 – REVISED JUNE 2019
TPS40077 4.5-V to 28-V Input, Voltage Mode, Synchronous Buck Controller
With Voltage Feed Forward
1 Features
3 Description
•
•
The TPS40077 is a mid-voltage, wide-input (4.5-V to
28-V), synchronous, step-down controller, offering
design flexibility for a variety of user-programmable
functions, including soft start, undervoltage lockout
(UVLO), operating frequency, voltage feed-forward,
and high-side, FET-sensed, short-circuit protection.
1
•
•
•
•
•
•
•
•
Operation Over 4.5-V to 28-V Input Range
Programmable, Fixed-Frequency, up to 1-MHz,
Voltage-Mode Controller
Predictive Gate-Drive Anti-Cross-Conduction
Circuitry
tON2 and d1 > d2
VDG−03172
Figure 25. Voltage Feed-Forward and PWM Duty Cycle Waveforms
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Programming (continued)
7.4.2 Programming Soft Start
TPS40077 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft start is
programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a
fixed current, generating a ramp signal. The voltage on SS is level-shifted down approximately 1 V and fed into a
separate noninverting input to the error amplifier. The loop is closed on the lower of the level-shifted SS voltage
or the 700-mV internal reference voltage. Once the level-shifted SS voltage rises above the internal reference
voltage, output-voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the
output voltage, the soft-start time should be greater than the L-COUT time constant or Equation 11.
t START w 2p
ǸL
COUT
(11)
Note that there is a direct correlation between tSTART and the input current required during start-up. The lower
tSTART is, the higher the input current required during start-up, because the output capacitance must be charged
faster. For a desired soft-start time, the soft-start capacitance, CSS, can be found from Equation 12.
I SS
C SS + t SS
VFB
(12)
7.4.3 Programming Short-Circuit Protection
The TPS40077 uses a two-tier approach for short-circuit protection. The first tier is a pulse-by-pulse protection
scheme. Short-circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across
the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor (RILIM) connected from VVDD to the ILIM pin when driven by a constant-current sink. If the voltage drop
across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately
terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 26.
ILIM
ILIM Threshold
(A)
Overcurrent
VIN − 2V
SW
T2
ILIM
T1
VIN − 2V
ILIM Threshold
(B)
SW
T1
T3
UDG−03173
Figure 26. Switching and Current-Limit Waveforms and Timing Relationship
18
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Programming (continued)
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of
VVDD. The ILIM pin is allowed to return to its nominal value after one of two events occurs. If the SW node rises
to within approximately 2 V of VVDD, the device allows ILIM to go back to its nominal value. This is illustrated in
Figure 26(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes
a driver delay of 50 ns, typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to
its nominal value, typically 20 ns. The second event that can cause ILIM to return to its nominal value is for an
internal timeout to expire. This is illustrated in Figure 26(B) as T3. Here SW never rises to VVDD – 2 V, for
whatever reason, and the internal timer times out, releasing the ILIM pin.
Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this
ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips
while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM
sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent
threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate
for slower-turnon FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the
voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in
overcurrent threshold as pulse duration changes. As a general rule, it is best to make the time constant of the RC at the ILIM pin 0.2 times or less of the nominal pulse duration of the converter as shown in Equation 17.
Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its
SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as
much as 2 V at –40°C) below VVDD. When ILIM is more than 1.4 V below VVDD, the overcurrent circuit is
effectively disabled.
The second-tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an
overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches
seven (7), a fault condition is declared by the controller. When this happens, the outputs are placed in a state
defined in Table 2. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the
PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is
decremented to zero, the PWM is re-enabled and the controller attempts to restart. If the fault has been
removed, the output starts up normally. If the output is still present, the counter counts seven overcurrent pulses
and re-enters the second-tier fault mode. Refer to Figure 27 for typical fault-protection waveforms.
In Equation 13, the minimum short-circuit limit setpoint (ISCP(min)) depends on tSTART, COUT, VOUT, ripple current in
the inductor (IRIPPLE), and the load current at turnon (ILOAD).
COUT VOUT
I
) I LOAD ) RIPPLE
I SCP(min) u
t START
2
ǒ
Ǔ
ǒ
Ǔ
(13)
The short-circuit limit programming resistor (RILIM) is calculated from Equation 14.
I SCP RDS(onMAX) ) VILIM (offset)
R ILIM +
W
I ILIM
where
•
•
•
IILIM is the current into the ILIM pin (110 μA, typical)
VILIM(offset) is the offset voltage of the ILIM comparator (–50 mV, typical)
ISCP is the short-circuit protection current
(14)
To find the range of the overcurrent values, use Equation 15 and Equation 16.
1.09 I ILIM(max) R ILIM * 0.09 RVDD I R
* 0.045 V ) 75 mV
VDD
I SCP(max) +
(A)
R DS(ON)min
1.09
I SCP(min) +
I ILIM(min)
R ILIM * 0.09
RVDD
IR
VDD
* 0.045 V ) 30 mV
R DS(ON)max
(A)
(16)
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Programming (continued)
The TPS40077 provides short-circuit protection only. Therefore, it is recommended that the minimum short-circuit
protection level be placed at least 20% above the maximum output current required from the converter. The
maximum output of the converter should be the steady state maximum output plus any transient specification
that may exist.
The ILIM capacitor maximum value can be found from Equation 17.
V OUT 0.2
C ILIM(max) +
(Farads)
VIN RILIM f SW
(17)
Note that this is a recommended maximum value. If a smaller value can be used, it should be. For most
applications, consider using half the maximum value above.
HDRV
Clock
tBLANKING
VILIM
VVIN − VSW
SS
7 Current-Limit Trips
(HDRV Cycle Terminated by Current-Limit Trip)
7
Soft-Start
Cycles
VDG−03174
Figure 27. Typical Fault Protection Waveforms
20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from
4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays for
increased efficiency and improved converter output-power capability. Voltage feed-forward is employed to ease
loop compensation for wide-input-range designs and provide better line transient response.
The TPS40077 incorporates circuitry to allow startup into a preexisting output voltage without sinking current
from the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. An integrated
power-good indicator is available for logic (open-drain) output of the condition of the output of the converter.
8.2 Typical Applications
8.2.1 Buck Regulator 8-V to 16-V Input, 1.8-V Output at 10 A
VIN
CIN +
ELCO
RKFF
RT
CDELAY
RLIM
U1
TPS40077PWP
CBP5
1
KFF
ILIM
2
RT
VDD
3
BP5
BOOST
4
PGD
HDRV
5
SGND
SW
6
SS
DBP
7
FB
LDRV
8
PGND
COMP
PWP
RPGD
CSS
R10
330 kW
QSW
16
15
14
13
LOUT
CBOOST
VOUT
CVDD
12
C_IN
MLCC
11
R4
0W
10
9
QSR
CDBP
RPZ2
VOUT = 1.8 V
IOUT up to 10 A
+
COUT
ELCO
C_OUT
MLCC
C13
2.2nF
CZ2
CP2
0V
RZ1
RSET
CPZ1
RP1
C11
0.1 mF
S0239-01
Figure 28. Schematic Diagram
8.2.1.1 Design Requirements
Table 3 lists the design specifications and Table 4 lists the bill of materials for this buck regulator application
example.
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Typical Applications (continued)
Table 3. Characteristics
PARAMETER
NOTES AND CONDITIONS
MIN
NOM
MAX
UNITS
INPUT CHARACTERSTICS
VIN
Input voltage
8
IIN
Input current
VIN = NOM, IOUT = MAX
No-load input current
VIN = NOM, IOUT = 0 A
VIN_UVLO
Input UVLO
IOUT = MIN to MAX
VIN_ONV
Input ONV
IOUT = MIN to MAX
12
16
V
1.8
2
62.6
3.6
mA
A
5.4
6
6.6
V
6.3
7
7.7
V
1.75
1.8
1.85
V
OUTPUT CHARACTERSTICS
VOUT
Output voltage
VIN = NOM, IOUT = NOM
Line regulation (1)
VIN = MIN to MAX, IOUT = NOM
0.5%
Load regulation (1)
VIN = NOM, IOUT = MIN to MAX
0.5%
VOUT_ripple
Output voltage ripple
VIN = NOM, IOUT = MAX
IOUT
Output current
VIN = MIN to MAX
IOCP
Output overcurrent
inception point
VIN = NOM, VOUT = VOUT – 5%
VOVP
Output OVP
IOUT = MIN to MAX
100
mVpp
0
5
10
A
12.25
19.4
34
A
NA
NA
NA
Transient response
Load step
ΔI
IOUT_Max to 0.2 × IOUT _Max
Load slew rate
Overshoot
Settling time
8
A
10
A/μs
200
mV
1
ms
SYSTEM CHARACTERSTICS
fSW
Switching frequency
240
300
ηpk
Peak efficiency
VIN = NOM, IOUT = MIN to MAX
90%
η
Full-load efficiency
VIN = NOM, IOUT = MAX
90%
Top
Operating temperature
range
VIN = MIN to MAX, IOUT = MIN to MAX
–40
360
kHz
85
°C
25
MECHANICAL CHARACTERSTICS
L
Width
W
Length
h
2
5.08
3
Component height
(1)
Inches
cm
Inches
7.62
cm
0.41
Inch
1.04
cm
Voltage accuracy is dependent on resistor tolerance and reference accuracy. Line and load regulation are calculated with respect to the
actual set point voltage.
Table 4. Bill of Materials
REFDES
COUNT
VALUE
DESCRIPTION
SIZE
PART NUMBER
MFR
C1
1
470 μF
Capacitor, aluminum, 470-μF, 25-V,
20%
0.457 x 0.406
EEVFK1E471P
Panasonic
C2, C10
2
0.1 μF
Capacitor, ceramic, 25-V, X7R, 20%
0603
Std
Vishay
C3
1
15 nF
Capacitor, ceramic, 25-V, X7R 20%
0603
Std
Vishay
C4
1
47 pF
Capacitor, ceramic, 25-V, X7R, 20%
0603
Std
Vishay
C5
1
1.8 nF
Capacitor, ceramic, 25-V, X7R 20%
0603
Std
Vishay
C6
1
680 pF
Capacitor, ceramic, 25-V, X7R 20%
0603
Std
Vishay
C7
1
51 pF
Capacitor, ceramic, 25-V, COG 20%
0603
Std
Vishay
C8, C11
2
0.1 μF
Capacitor, ceramic, 25-V, X7R, 20%
0603
Std
Vishay
22
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Table 4. Bill of Materials (continued)
REFDES
COUNT
VALUE
DESCRIPTION
SIZE
PART NUMBER
MFR
C9
1
1 μF
Capacitor, ceramic, 25-V, X7R, 20%
0805
Std
Vishay
C12, C14,
C15
3
22 μF
Capacitor, ceramic, 22-μF, 16-V,
X5R, 20%
1812
C4532X5R1C226MT
TDK
C13
1
2.2 nF
Capacitor, ceramic, 25-V, X7R, 20%
0603
Std
Vishay
C16
1
470 μF
Capacitor, aluminum, SM, 6.3-V,
300-mΩ (FC series)
8 × 10
Std
Panasonic
C17
1
47 μF
Capacitor, ceramic, 47-uF, 6.3-V,
X5R, 20%
1812
C4532X5R0J476MT
TDK
D1
1
BAT54
Diode, Schottky, 200-mA, 30-V
SOT23
BAT54
Vishay
J1, J2
2
ED1609-ND
Terminal block, 2-pin, 15-A, 5,1-mm
0.40 × 0.35
ED1609
OST
J3
1
PTC36SAAN
Header, 2-pin, 100-mil spacing, (36pin strip)
0.100 × 2
PTC36SAAN
Sullins
L1
1
2.5 μH
Inductor, SMT, 2.5 μH, 16.5-A, 3.4mΩ
0.515 × 0.516
MLC1550-252ML
Coilcraft
Q1
1
Si7860DP
MOSFET, N-channel, 30-V, 18-A,
8.0-mΩ
PWRPAK S0-8
Si7860DP
Vishay
Q2
1
Si7336ADP
MOSFET, N-channel, 30-V, 18-A, 40- PWRPAK S0-8
mΩ
Si7886ADP
Vishay
Q3
1
FDV301N
MOSFET, N-channel, 25-V, 220-mA,
5-Ω
SOT23
FDV301N
Fairchild
R1
1
10 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R2, R6
2
165 kΩ
Resistor, Chip, 1/16-W, 20%
0603
Std
Std
R3
1
32.4 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R4, R11
2
0Ω
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R5
1
21.5 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R7
1
51 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R8
1
3.3 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R9
1
1.8 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R10
1
330 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R12
1
51 Ω
Resistor, chip, 1/16-W, 20%
0603
Std
Std
R13
1
1 kΩ
Resistor, chip, 1/16-W, 20%
0603
Std
Std
U1
1
TPS40077PWP
IC, Texas Instruments
PWP16
TPS40077PWP
TI
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Power Train Components
8.2.1.2.1.1 Output Inductor, LOUT
The output inductor is one of the most important components to select. It stores the energy necessary to keep
the output regulated when the switch FET is turned off. The value of the output inductor dictates the peak and
RMS currents in the converter. These currents are important when selecting other components. Equation 18 can
be used to calculate a value for LOUT for this module which operates at a switching frequency (f) of 300 kHz.
V IN(max) * V OUT
VOUT
LOUT +
f s I RIPPLE
V IN(max)
(18)
IRIPPLE is the allowable ripple in the inductor. Select IRIPPLE to be between 20% and 30% of maximum IOUT. For
this design, IRIPPLE of 2.5 A was selected. Calculated LOUT is 2.13 μH. A standard inductor with value of 2.5 μH
was chosen. This will reduce IRIPPLE by about 17% to 2.07 A.
This IRIPPLE value can be used calculate the rms and peak current flowing in LOUT with Equation 19. Note that
this peak current is also seen by the switching FET and synchronous rectifier.
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I LOUT_RMS +
Ǹ
www.ti.com
2
I OUT
2
I
) RIPPLE + 10.02 A
12
(19)
The power loss from the selected inductor DCR is 357 mW. The ac core loss for this Coilcraft inductor may be
found from the Coilcraft Web site, where there is a loss calculator. The loss is 179 mW calculated with
Equation 20.
I
I PK + I OUT ) RIPPLE + 11.03 A
2
(20)
The inductor is selected with a saturation current higher than this current plus the current that is developed
charging the output capacitance during the soft-start interval.
8.2.1.2.1.2 Output Capacitor, COUT, ELCO and MLCC
Several parameters must be considered when selecting the output capacitor. The capacitance value should be
selected based on the output overshoot, VOVER, and undershoot, VUNDER, during a transient load, ISTEP, on the
converter. The equivalent series resistance (ESR) is chosen to allow the converter to meet the output ripple
specification, VRIPPLE. The voltage rating must be greater than the maximum output voltage. Another parameter
to consider is equivalent series inductance, which is important in fast-transient load situations. Also, size and
technology can be factors when choosing the output capacitor. In this design, a large-capacitance electrolytic
type capacitor, COUT ELCO, is used to meet the overshoot and undershoot specifications. Its ESR is chosen to
meet the output ripple specification. Smaller multiple-layer ceramic capacitors, COUT MLCC, are used to filter
high-frequency noise.
The minimum required capacitance and maximum ESR can be calculated using Equation 21, Equation 22, and
Equation 23.
2
COUT +
2
LOUT I STEP
VUNDER Dmax (VIN * VOUT)
(21)
2
COUT +
LOUT I STEP
2 VOVER VOUT
(22)
V
ESR + RIPPLE
I RIPPLE
(23)
The capacitance for COUT should be greater than 444 μF, and its ESR should be less than 12 mΩ. The 470μF/6.3-V capacitor from Panasonic's FC series was chosen. Its ESR is 160 mΩ. MLCCs of 47 μF and 22 μF/16 V
are also added in parallel to achieve the required ESR and to reduce high-frequency noise.
8.2.1.2.1.3 Input Capacitor, CIN ELCO and MLCC
The input capacitor is selected to handle the ripple current of the buck stage. Also, a relatively large capacitance
is used to keep the ripple voltage on the supply line low. This is especially important where the supply line has
high impedance. It is recommended however, that the supply-line impedance be kept as low as possible.
The input-capacitor ripple current can be calculated using Equation 24.
I CAP(RMS) +
Ǹƪ
ǒIOUT * IIN(AVG)Ǔ
2
I
) RIPPLE
12
ƫ
2
D ) I IN(AVG)
2
(1 * D)
(24)
IIN(AVG) is the average input current. This is calculated simply by multiplying the output dc current by the duty
cycle. The ripple current in the input capacitor is 3.3 A. An 1812 MLCC using X5R material has a typical
dissipation factor of 5%. For a 22-μF capacitor at 300 kHz, the ESR is approximately 4 mΩ. Two capacitors are
used in parallel, so the power dissipation in each capacitor is less than 11 mW.
A 470-μF/16-V electrolytic is added to maintain the voltage on the input rail.
24
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8.2.1.2.1.4 Switching MOSFET, QSW
The following key parameters must be met by the selected MOSFET.
• Drain source voltage, Vds, must be able to withstand the input voltage plus spikes that may be on the
switching node. For this design a Vds rating of 30 volts is recommended.
• Drain current, ID, at 25°C, must be greater than that calculated using Equation 25.
I QSW(RMS) +
•
•
Ǹ
V OUT
VIN(MIN)
ƪ
2
I OUT(MAX) )
I RIPPLE
12
ƫ
2
(25)
With the parameters specified, the calculation of IQSW(RMS) should be greater than 5 A.
Gate source voltage, Vgs, must be able to withstand the gate voltage from the control IC. For the TPS40077,
this is 11 V.
Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to select
the key performance parameters. Efficiency is the performance characteristic which drives the other selection
criteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss in
the converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen.
Equation 26 through Equation 29 can be used to calculate the power loss, PQSW, in the switching MOSFET.
P QSW + PCON ) PSW ) PGATE
P CON + RDS(on)
P SW + VIN
fS
P GATE + Q g(TOT)
2
I QSW(RMS) + R DS(on)
V OUT
VIN
ƪ
2
I out )
I RIPPLE
12
ƫ
2
(27)
ȱǒI ) IRIPPLEǓ ǒQ ) Q Ǔ
ȳ
gs1
OUT
gd
2
Q OSS(SW) ) Q OSS(SR)ȧ
ȧ
)
ȧ
ȧ
12
Ig
ȧ
ȧ
Ȳ
ȴ
Vg
(26)
f SW
(28)
(29)
where
PCON = conduction losses
PSW = switching losses
PGATE = gate-drive losses
Qgd = drain-source charge or Miller charge
Qgs1 = gate-source post-threshold charge
Ig = gate-drive current
QOSS(SW) = switching MOSFET output charge
QOSS(SR) = synchronous MOSFET output charge
Qg(TOT) = total gate charge from zero volts to the gate voltage
Vg = gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28
yield preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been
ignored here. Once a MOSFET is selected, these parameters can be added.
The switching MOSFET for this design should have an RDS(on) of less than 8 mΩ. The sum of Qgd and Qgs should
be approximately 4 nC.
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It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may be
necessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the final
selection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonable
results. This device has an RDS(on) of 8 mΩ and a (Qgs1 + Qgd) of 5 nC. The estimated conduction losses are
0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 W
for our initial boundary condition. Note this does not include gate losses of approximately 71 mW and output
losses of 20 mW.
8.2.1.2.1.5 Rectifier MOSFET, QSR
Similar criteria to the foregoing can be used for the rectifier MOSFET. There is one significant difference: due to
the body diode conducting, the rectifier MOSFET switches with zero voltage across its drain and source, so
effectively with zero switching losses. However, there are some losses in the body diode. These are minimized
by reducing the delay time between the transition from the switching MOSFET turnoff to rectifier MOSFET turnon
and vice-versa. The TPS40077 incorporates TI's proprietary Predictive Gate Drive circuitry (PGD), which helps
reduce these delays to around 10 ns.
To calculate the losses in the rectifier MOSFET, use Equation 30 through Equation 33.
P QSR + PCON ) PBD ) PGATE
P CON + RDS(on)
P BD + Vf
ƪ
I OUT
P GATE + Q g(TOTAL)
1*
V OUT
* ǒt 1 ) t 2Ǔ
VIN
ǒt1 ) t 2Ǔ
fS
Vg
fS
ƫ
fS
ƪ
2
I out )
I RIPPLE
12
ƫ
(30)
2
(31)
(32)
where
•
•
•
•
PBD = body diode losses
t1 = body diode conduction prior to turnon of channel = 12 ns for PGD
t2 = body diode conduction after turnoff of channel = 12 ns for PGD
Vf = body diode forward voltage
(33)
Estimating the body diode losses based on a forward voltage of 1 V gives 0.072 W. The gate losses are
unknown at this time, so assume 0.1-W gate losses. This leaves 0.428 W for conduction losses. Using this
figure, a target RDS(on) of 5 mΩ was calculated.
The Si7336ADP from Vishay was chosen. Using the parameters from its data sheet, the actual expected power
losses are calculated. Conduction loss is 0.317 W, body diode loss is 0.072 W, and the gate loss is 0.136W. This
totals 0.525 W associated with the rectifier MOSFET.
Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensure
that predictive gate drive functions correctly. The turnoff delay of the Si7336ADP is 97 ns. The minimum turnoff
delay of the Si7860DP is 25 ns. Together these devices meet the 130-ns requirement.
Secondly, the ratio between Cgs and Cgd should be greater than 1. The Si7336ADP easily meets this criterion.
This helps reduce the risk of dv/dt-induced turnon of the rectifier MOSFET. If this is likely to be a problem, a
small resistor may be added in series with the boost capacitor, CBOOST.
8.2.1.2.1.6 Timing Resistor, RT
The timing resistor is calculated using Equation 34.
1
RT +
* 23
f S 17.82 10 *6
(34)
This gives a resistor value of 165 kΩ. The nominal frequency using this resistor is 300 kHz.
8.2.1.2.1.7 Feed-Forward and UVLO Resistor, RKFF
A resistor connected to the KFF pin of the IC feeds into the ramp generator. This resistor provides current into
the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different input
voltages. This provides the voltage feed-forward feature of the TPS40077.
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The same resistor also sets the undervoltage lockout point. The input start voltage should be used to calculate a
value for RKFF. For this module, the minimum input voltage is 8 V; however, due to tolerances in the IC, a start
voltage of 10% less than the minimum input voltage is selected. The start voltage for RKFF calculation is 7.2 V.
Using Equation 35, RKFF can be selected.
R KFF + 0.131
* 4.87
10*5
RT
RT
V UVLO(on) * 1.61
10*3
2
V UVLO(on) ) 1.886
V UVLO * 1.363 * 0.02
RT
2
where
•
RKFF and RT are in kΩ
(35)
Equation 35 gives an RKFF value of 156 kΩ. The closest lower standard value of 154 kΩ should be selected. This
gives a minimum start voltage of 7.1 V.
8.2.1.2.1.8 Soft-Start Capacitor, CSS
It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible
damage to the load. The selection of the soft-start time is arbitrary. It must meet one condition: it should be
greater than the time constant of the output filter, LOUT and COUT. This time is given by Equation 36.
t
w 2p ǸLOUT COUT
START
(36)
The soft-start time must be greater than 0.23 ms. A time of 0.75 ms was chosen. This time also helps limit the
initial input current during start-up so that the peak current plus the capacitor start-up current is less than the
minimum short-circuit current. The value of CSS can be calculated using Equation 37.
I
C SS + SS
t START
VFB
(37)
A standard 15-nF MLCC capacitor was chosen. The calculated start time using this capacitor is 0.875 ms.
8.2.1.2.1.9 Short-Circuit Protection, RILIM and CILIM
Short-circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of
the switching MOSFET selected and the required short-circuit current trip point, ISCP. The minimum ISCP is limited
by the inductor peak current, the output voltage, the output capacitor, and the soft-start time. Their relationship is
given by Equation 38. A short-circuit current trip point greater than that calculated by Equation 38 should be
used.
COUT V OUT
I SCP w
) I PK
t START
(38)
The minimum short-circuit current trip point for this design is 12.25 A. This value is used in Equation 39 to
calculate the minimum RILIM value.
I SCP RDS(on)MAX ) VILIM(Max)
R ILIM +
I LIM(Min)
(39)
RILIM is calculated to be 1.17 kΩ, and a 1.2-kΩ resistor is used to verify that the short-circuit current requirements
are met. The minimum and maximum short-circuit current can be calculated using Equation 40 and Equation 41.
I ILIM(MIN) RILIM(MIN) * VILIM(MAX)
I SCP(MIN) +
R DS(on)MAX
(40)
I SCP(MAX) +
I ILIM(MAX)
RILIM(MAX) * VILIM(MIN)
R DS(on)MIN
(41)
where: VILIM(MAX) and VILIM(MIN) are maximum and minimum voltages across the high side FET when it is turned
on, taking into account temperature variations.
The minimum ISCP is 12.25 A, and the maximum is 34 A.
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It is also recommended to add a small capacitor, CILIM, across RILIM. The value of this capacitor should be about
half the value calculated in Equation 42.
VOUT 0.2
C ILIM(Max) +
VIN RILIM f S
(42)
This equation yields a maximum CILIM as 55 pF. A smaller value of 27 pF is chosen is chosen.
8.2.1.2.1.10 Boost Voltage, CBOOST and DBOOST (Optional)
To be able to drive an N-channel MOSFET in the switch location of a buck converter, a capacitor charge pump
or boost circuit is required. The TPS40077 contains the elements for this boost circuit. The designer must only
add a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the IC. Selection
of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the
boost voltage, ΔVBOOST. A ripple of 0.2 V is assumed for this design. Using these two parameters and
Equation 43, the minimum value for CBOOST can be calculated.
Q g(TOTAL)
CBOOST u
DV BOOST
(43)
The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092 μF is required. A 0.1 μF
capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximum
voltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used.
To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, an
external diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diode
should be used here, such as the BAT54.
8.2.1.2.1.11 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
A graphical method is used to select the compensation components. This is a standard feed-forward buck
converter. Its PWM gain is given by Equation 44.
V
K PWM ^ UVLO
1V
(44)
The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmed
UVLO voltage is the voltage that sets the PWM gain.
The gain of the output LC filter is given by Equation 45.
1 ) s ESR COUT
K LC +
LOUT ) s 2 LOUT COUT
1)s
ROUT
The PWM and LC gain is Equation 46.
VUVLO
G c(s) + KPWM KLC
1V
1)s
1 ) s ESR
LOUT ) s 2
ROUT
(45)
COUT
LOUT
COUT
(46)
To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express this
in dB, take its logarithm and multiply by 20. For this converter, the dc gain is Equation 47.
DCGAIN + 20
ƪ
log
ƫ
V UVLO
+ 20
VRAMP
log(7) + 16.9 dB
(47)
Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is
associated with the ESR of the output capacitor. The frequencies where these occur can be calculated using
Equation 48 and Equation 49.
1
f LC_Pole +
+ 4.3 kHz
Ǹ
2p
LOUT COUT
(48)
1
f ESR_Zero +
+ 2.1 kHz
2p ESR COUT
(49)
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These are shown in the Bode plot of Figure 29.
30
20
Double Pole
10
ESR Zero
Gain − dB
0
−10
ESR = 0.16 Ω
Slope = –20 dB/Decade
−20
−30
−40
−50
−60
0.1
1
10
100
1k
f − Frequency − kHz
G028
Figure 29. PWM and LC Filter Gain
The next step is to establish the required compensation gain to achieve the desired overall system response.
The target response is to have the crossover frequency between 1/9 and 1/5 times the switching frequency, in
order to have a phase margin greater than 45° and a gain margin greater than 6 dB.
A type-III compensation network, shown in Figure 30, was used for this design. This network gives the best
overall flexibility for compensating the converter.
RP1
CPZ1
TPS40077
VOUT
6
SS
7
FB
8
COMP
RZ1
CZ2
CP2
RPZ2
RSET
S0240-01
Figure 30. Type-III Compensation With the TPS40077
A typical Bode plot for this type of compensation network is shown in Figure 31.
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40
30
High-Frequency Gain
Gain − dB
20
10
0
−10
fZ1
fZ2
fP1
fP2
−20
0.1
1
10
100
1k
f − Frequency − kHz
G029
Figure 31. Type-III Compensation Typical Bode Plot
The high-frequency gain and the break (pole and zero) frequencies are calculated using Equation 50 through
Equation 55.
RZ1 ) RSET
VOUT + VREF
RSET
(50)
R Z1 ) R P1
R Z1 R P1
GAIN + R PZ2
f P1 +
f P2 +
f Z1 +
f Z2 +
(51)
1
2p
R P1
C PZ1
2p
C P2 ) CZ2
R PZ2 C P2
(52)
C Z2
[
1
R PZ2
2p
CP2
(53)
1
2p
R Z1
C PZ1
2p
ǒR PZ2 ) R P1Ǔ
(54)
1
C Z2
[
2p
1
R PZ2
CZ2
(55)
Looking at the PWM and LC bode plot, there are a few things which must be done to achieve stability.
1. Place two zeros close to the double pole, e.g., fZ1 = fZ2 = 4.3 kHz
2. Place both poles well above the crossover frequency. The crossover frequency was selected as one sixth the
switching frequency, fco1 = 50 kHz, fP1 = 66 kHz
3. Place the second pole at three times fco1. This ensures that the overall system gain falls off quickly to give
good gain margin, fp2 = 150 kHz
4. The high-frequency gain should be sufficient to ensure 0 dB at the required crossover frequency, GAIN = –1
× gain of PWM and LC at the crossover frequency, GAIN = 16.9 dB
Using these values and Equation 50 through Equation 55, the Rs and Cs around the compensation network can
be calculated.
1. Set RZ1 = 51 kΩ
2. Calculate RSET using Equation 50, RSET = 32.4 kΩ
3. Using Equation 54 and fz1 = 4.3 kHz, CPZ1 can be calculated to be 726 pF, CPZ1= 680 pF
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4. fP1 and Equation 52 yields RP1 to be a standard value of 3.3 kΩ.
5. The required gain of 16.9 dB and Equation 51 sets the value for RPZ2. RPZ2 = 21.5 kΩ.
6. CZ2 is calculated using Equation 55 and the desired frequency for the second zero, CZ2 = 1.7 nF, or using
standard values, 1.8 nF.
7. Finally, CP2 is calculated using the second pole frequency and Equation 53; CP2 = 47 pF.
Using these values, the simulated results are 57° of phase margin at 54 kHz.
8.2.1.3 Application Curves
50
90
45
80
12 V
16 V
60
Gain − dB
η − Efficiency − %
180
Phase
40
8V
70
200
50
40
160
35
140
30
120
25
100
20
80
Phase − °
100
30
15
60
Gain
20
10
40
5
20
10
0
0
1
2
3
4
5
6
7
8
9
IOUT − Load Current − A
10
G026
Figure 32. Module Efficiency,
8 V, 12 V, and 16 V In, 0 to 10 A Out
0
100
1k
10k
100k
0
1M
f − Frequency − Hz
G027
Figure 33. Bode Plot Showing 57° Phase Margin
at Crossover Frequency of 54 kHz
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8.3 Additional System Examples
+
VDD
12 V
–
R6
165 kW
R9
2 kW
TPS40077PWP
R2
165 kW
1
KFF
ILIM 16
2
RT
VDD 15
3
LVBP BOOST
14
4
PGD
HDRV
13
5
SGND
SW
12
6
SS
DBP
11
C3 22 nF
C5
5.6 nF
C12
22 mF
C10 0.1 mF
C2 0.1 mF
R5
10 kW
C7
10 pF
FB
8
COMP
C4 470 pF
LDRV
10
PGND
9
C8
0.1 mF
L1
Pulse
Q1
PG0077.202
Si7840BDP
2 mH
D1
BAT54
C9 1 mF
7
C14
22 mF
+
Q2
Si7856ADP
+
C13
4.7 nF
C15
47 mF
+
C16
470 mF
C17
470 mF
C18
0.1 mF
VOUT
1.8 V
10 A
–
PWP
R7 8.66 kW
R3
5.49 kW
C6
4.7 nF
R8
226 W
S0209-01
Figure 34. 300 kHz, 12 V to 1.8 V
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Additional System Examples (continued)
+
VDD
12 V
–
R6
165 kW
R9
2 kW
TPS40077PWP
R2
165 kW
1
KFF
ILIM 16
2
RT
VDD 15
3
LVBP BOOST
14
4
PGD
HDRV
13
5
SGND
SW
12
6
SS
DBP
11
C3 22 nF
C5
5.6 nF
C12
22 mF
C10 0.1 mF
C2 0.1 mF
R5
10 kW
C7
10 pF
FB
8
COMP
C4 470 pF
LDRV
10
PGND
9
C8
0.1 mF
L1
Pulse
Q1
PG0077.202
Si7840BDP
2 mH
D1
BAT54
C9 1 mF
7
C14
22 mF
+
Q2
Si7856ADP
+
C13
4.7 nF
C15
47 mF
+
C16
470 mF
C17
470 mF
C18
0.1 mF
VOUT
1.8 V
10 A
–
PWP
R7 8.66 kW
C6
4.7 nF
R3
5.49 kW
R8
226 W
S0210-01
See Boost Diode.
Figure 35. 300 kHz, 12 V to 1.8 V With Improved High-Side Gate Drive
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Additional System Examples (continued)
+
VDD
5V
–
R6
47 kW
R9
2 kW
TPS40077PWP
R2
90.1 kW
1
KFF
ILIM 16
2
RT
VDD 15
3
LVBP BOOST
C12
22 mF
C10 0.1 mF
C2 0.1 mF
C3 22 nF
C7
10 pF
4
PGD
5
SGND
6
SS
13
SW
12
DBP
11
Q1
Si7860DP
R5
10 kW
C5
5.6 nF
7
FB
8
COMP
C4 470 pF
LDRV
10
PGND
9
L1
Pulse
PG0077.202
2 mH
D1
BAT54
C9 1 mF
R4 330 kW
C8
0.1 mF
14
HDRV
C14
22 mF
+
Q2
Si7860DP
+
C13
4.7 nF
C15
47 mF
+
C16
470 mF
C17
470 mF
C18
0.1 mF
VOUT
1.2 V
10 A
–
PWP
R7 8.66 kW
C6
4.7 nF
R3
12.1 kW
R8
226 W
Note: Resistor across soft start capacitor.
S0211-01
See Boost Diode.
Figure 36. 500 kHz, 5 V to 1.2 V With Improved High-Side Gate Drive
9 Layout
9.1 Layout Guidelines
The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Take care to properly
separation of the circuit grounds. Each ground must consist of a plane to minimize its impedance, if possible.
The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor
(DBP), and the input capacitor should be connected to PGND plane.
Connect sensitive nodes such as the FB resistor divider and RT to the SGND plane. The SGND plane must only
make a single-point connection to the PGND plane. TI recommends that the SGND pin be tied to the copper
area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area as well, and make
the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND
pin.
Component placement must ensure that bypass capacitors (LVPB and DBP) are located as close as possible to
their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout
practices results in suboptimal operation. More detailed information can be found in the TPS40077EVM user's
guide (SLVU192).
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package, SLMA002
• TPS40190 Low Pin Count Synchronous Buck Controller, SLUS658
• TPS40100 Midrange Input Synchronous Buck Controller With Advanced Sequencing and Output Margining,
SLUS601
• TPS40075 Midrange Input Synchronous Buck Controller With Voltage Feed-Forward, SLUS676
• TPS40057 Wide-Input Synchronous Buck Controller, SLUS593
• Using the TPS40077EVM 12-V Input, 1.8-V Output, 10-A Synchronous Buck Converter, SLVU192
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40077PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40077
TPS40077PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40077
TPS40077PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40077
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
