TPS40140RHHR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 TPS40140 Dual or 2-Phase, Stackable Controller 1 Features 2 Applications • • • • • • • • 1 • • • • • • • • • • • • VDD from 4.5 to 15 V, With Internal 5-V Regulator VOUT from 0.7 V to 5.8 V Converts from 15-V Input to 0.7-V Output at 1 MHz Dual-Output or 2-Phase Interleaved Operation, Stackable to 16 Phases Supports Prebiased Outputs Programmable Switching Frequency up to 1 MHz/Phase 0.5% Internally Trimmed 0.7-V Reference 10-μA Shutdown Current Current Mode Control With Forced Current Sharing (1) 1- to 40-V Power Stage Operation Range Power Sharing From Different Input Voltage Rails, (for Example, Master From 5 V, Slave From 12 V) True Remote Sensing Differential Amplifier Programmable Input Undervoltage Lockout (UVLO) Resistive or Inductor DCR Current Sensing Provide a 6-Bit Digitally Controlled Output When Used With TPS40120 36-Pin VQFN Package Graphic Cards Internet Servers Networking Equipment Telecommunications Equipment DC Power Distributed Systems 3 Description The TPS40140 is a multifunctional synchronous buck controller that can be configured to provide either a single-output 2-phase power supply or a power supply that supports two independent outputs. Several TPS40140 controllers can be stacked up to a 16-phase single output power supply. Alternatively, several controllers providing multiple independent outputs can be synchronized in an interleaving pattern for improved input ripple current. The TPS40140 can convert from a 15-V input to a 0.7-V output at 1 MHz. Each phase operates at a switching frequency of up to 1 MHz. The two phases in one device operate 180° out-of-phase. In a multiple-device stackable configuration, the phase shift of the slaves, relative to a master, is programmable. Device Information(1) PART NUMBER TPS40140 (1) PACKAGE VQFN (36) BODY SIZE (NOM) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Patents Pending Simplified Schematic VIN CSRT1 TPS40140 CS1 HDRV1 VOUT1 SW1 LDRV1 L1 VIN CSRT2 CS2 HDRV2 SW2 VOUT2 LDRV2 L2 UDG−06016 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 6 6 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application ................................................. 40 9.3 System Example ..................................................... 55 10 Power Supply Recommendations ..................... 60 11 Layout................................................................... 60 11.1 Layout Guidelines ................................................. 60 11.2 Layout Example .................................................... 61 12 Device and Documentation Support ................. 62 12.1 12.2 12.3 12.4 12.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 62 63 63 63 63 13 Mechanical, Packaging, and Orderable Information ........................................................... 63 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (June 2013) to Revision I Page • Added ESD Ratings table, ESD Ratings table Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1 • Added R1 to resistor in Figure 33 ........................................................................................................................................ 33 Changes from Revision G (July 2013) to Revision H Page • Changed max Operating junction temperature from 125 to 150 in Absolute Maximum Ratings ........................................... 5 • Changed switching frequency equation in Setting the Switching Frequency to match updated measurement................... 34 • Changed Phase Frequency vs Timing Resistor curve in Setting the Switching Frequency to match updated measurement........................................................................................................................................................................ 34 Changes from Revision F (September 2009) to Revision G Page • Updated Thermal Information table ........................................................................................................................................ 6 • Added clarity to Functional Block Diagram........................................................................................................................... 13 • Added clarity to Figure 24..................................................................................................................................................... 26 • Added clarity to Figure 25..................................................................................................................................................... 27 2 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 5 Device Comparison Table DEVICE DESCRIPTION TPS40130 2-phase synchronous buck controller with integrated MOSFET drivers TPS40090 4-channel multi-phase DC-DC controller with tri-state TPS40120 Feedback divider, digitally controlled 6 Pin Configuration and Functions TRK1 CSRT1 CS1 PGOOD1 UVLO_CE1 CLKIO 31 30 29 28 ILIM1 34 32 COMP1 35 33 FB1 36 RHH PACKAGE VQFN 36-PINS (TOP VIEW) PGND VSHARE 6 22 LDRV2 GND 7 21 VREG BP5 8 20 SW2 FB2 9 19 HDRV2 18 23 BOOT2 5 17 LDRV1 VDD 24 16 4 RT UVLO−CE2 PHSEL 14 SW1 15 25 PGOOD2 3 13 GSNS CS2 HDRV1 CSRT2 26 12 2 TRK2 VOUT 11 BOOT1 ILIM2 27 10 1 COMP2 DIFFO The thermal pad is an electrical ground connection. Pin Functions PIN (1) I/O DESCRIPTION 27 I BOOT1 provides a bootstrapped supply for the high side FET driver for PWM1, enabling the gate of the high side FET to be driven above the input supply rail. Connect a capacitor from BOOT1 to SW1 pin and a Schottky diode from this pin to VREG. BOOT2 18 I BOOT2 provides a bootstrapped supply for the high side FET driver for PWM2, enabling the gate of the high side FET to be driven above the input supply rail. Connect a capacitor from BOOT2 to SW2 pin and a Schottky diode from this pin to VREG. BP5 8 I Filtered input from the VREG pin. A 10-Ω resistor should be connected between VREG and BP5 and a 1.0-μF ceramic capacitor should be connected from BP5 to ground. CLKIO 28 O Digital clock signal for synchronizing slave controllers to the master CLKIO frequency and is either 6 or 8 times the PWM switching frequency. COMP1 35 O Output of the error amplifier, CH1. The voltage at this pin determines the duty cycle for the PWM1. NAME NO. BOOT1 (1) It is often necessary to refer to a pin or pins that are used in CH1 and/or CH2. The shortcut nomenclature used is the pin name with a lower case 'x' to mean either or both channels. For example, TRKx refers to TRK1 and/or TRK2. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 3 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Pin Functions (continued) PIN (1) NAME NO. I/O DESCRIPTION COMP2 10 O Output of the error amplifier, CH2. The voltage at this pin determines the duty cycle for the PWM2. CS1 31 I These pins are used to sense the CH1 phase current. Inductor current can be sensed with an external current sense resistor or by using an external R-C circuit and the inductor’s DC resistance. The traces for these signals must be connected directly at the current sense element. CS2 14 I These pins are used to sense the CH2 phase current. Inductor current can be sensed with an external current sense resistor or by using an external R-C circuit and the inductor’s DC resistance. The traces for these signals must be connected directly at the current sense element. DIFFO 1 O Output of the differential amplifier. The output voltage of the differential amplifier is limited to 5.8 V. For remote sensing, the voltage at this pin represents the true output voltage without I × R drops that result from high current in the PCB traces. The VOUT and GSNS pins must be connected directly at the point of load where regulation is required. See Layout Guidelines for more information. CSRT1 32 I Return point of CH1 current sense voltage. The trace for this signal must be connected directly at the current sense element. CSRT2 13 I Return point of CH1 current sense voltage. The trace for this signal must be connected directly at the current sense element. FB1 36 I Inverting input of the error amplifier for CH1. In closed loop operation, the voltage at this pin is nominally 700 mV. This pin is also monitored for PGOOD1 and undervoltage on CH1. FB2 9 I Inverting input of the error amplifier for CH2. In closed loop operation, the voltage at this pin is nominally 700 mV. This pin is also monitored for PGOOD2 and undervoltage on CH2. GND 7 — GSNS 3 I Inverting input of the differential amplifier. This pin should be connected to ground at the load. If the differential amplifier is not used, tie this pin to GND or leave open. HDRV1 26 O Gate drive output for the high-side N-channel MOSFET switch for CH1. Output is referenced to SW1 and is bootstrapped for enhancement of the high side switch. HRDV2 19 O Gate drive output for the high-side N-channel MOSFET switch for CH2. Output is referenced to SW2 and is bootstrapped for enhancement of the high side switch. ILIM1 34 I Used to set the cycle-by-cycle current limit threshold for CH1. If the ILIM1 threshold is reached, the PWM pulse is terminated and the converter delivers limited current to the output. ILIM2 11 I Used to set the cycle-by-cycle current limit threshold for CH2. If the ILIM2 threshold is reached, the PWM pulse is terminated and the converter delivers limited current to the output. LRDV1 24 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH1. LRDV2 22 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH2. PGOOD1 30 O Power good indicators for CH1 output voltage. This open-drain output connects to a voltage via an external resistor PGOOD2 15 O Power good indicators for CH2 output voltage. This open-drain output connects to a voltage via an external resistor PGND 23 — Power ground reference for the controller lower gate drivers. There should be a high current return path from the sources of the lower MOSFETs to this pin. PHSEL 4 O A 20μA current flows from this pin. In a single controller design, this pin should be grounded. In a multi controller configuration, a 39- kΩ resistor string sets the voltage on this pin determines the proper phasing for the slaves. See the section on Clock Master, PHSEL, and CLKIO Configurations. RT 5 I Connecting a resistor from this pin to ground sets the oscillator frequency. SW1 25 I Connect to the switched node on converter CH1. It is the return for the CH 1 upper gate driver. There should be a high current return path from the source of the upper MOSFET to this pin. This pin is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. SW2 20 I Connect to the switched node on converter CH2. It is the return for the CH 2 upper gate driver. There should be a high current return path from the source of the upper MOSFET to this pin. This pin is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. TRK1 33 I This is an input to the non-inverting input of the error amplifier CH1. This pin is normally connected to the softstart capacitor or to another voltage that is tracked. TRK2 12 I This is an input to the non-inverting input of the error amplifier CH2. This pin is normally connected to the softstart capacitor or to another voltage that is tracked. UVLO_CE1 29 I A voltage divider from VIN to this pin determines the input voltage that CH1 starts. When the voltage is between 0.5 and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH1 soft start is allowed to begin. 4 Low noise ground connection to the device. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Pin Functions (continued) PIN (1) NAME NO. I/O DESCRIPTION UVLO_CE2 16 I A voltage divider from VIN to this pin determines the input voltage that CH2 starts. When the voltage is between 0.5 and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH2 soft start is allowed to begin. VDD 17 I Power input for the controller 5V regulator and differential amplifier. A 1.0-μF ceramic capacitor should be connected from this pin to ground. VOUT 2 I Non-inverting input of the differential amplifier. This pin should be connected to the output of the converter close to the load point. If the differential amplifier is not used, leave this pin open. VREG 21 O The output of the internal 5-V regulator. A 4.7-μF ceramic capacitor should be connected from this pin to PGND. VSHARE 6 O The 1.8-V reference output 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VDD, UVLO ≤ VDD, RT, SS SW1, SW2 Input voltage MIN MAX –0.3 16 –1 44 SW1, SW2, transient < 50 ns UNIT –5 BOOT1, BOOT2, HDRV1, HDRV2 V VSW + 6.0 All other pins –0.3 6.0 Output current RT 200 µA TJ Operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C VALUE UNIT 7.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 3000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD, UVLO ≤ VDD Input voltage SW1, SW2 MAX UNIT 15 –1 BOOT1, BOOT2, HDRV1, HDRV2 All other pins Maximum output current NOM –0.3 40 VSW + 5.5 –0.3 RT 5.5 25 Operating free-air temperature –40 µA 85 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 V °C 5 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 7.4 Thermal Information TPS40140 THERMAL METRIC RHH (VQFN) (1) UNIT 36 PINS RθJA Junction-to-ambient thermal resistance 30.8 RθJC(top) Junction-to-case (top) thermal resistance 18.4 RθJB Junction-to-board thermal resistance 5.9 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 5.9 RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics –40°C ≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, ƒSW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.5 12 15 V 1 10 µA 5.0 5.5 V VDD INPUT SUPPLY Operating voltage range Shutdown current UVLO_CE1 = UVLO_CE2 = GND BP5 INPUT SUPPLY Operating voltage range 4.5 BP5 operating current 2 3 5 Rising BP5 turnon 4.0 4.25 4.45 V BP5 turnoff hysteresis 100 220 400 mV Standby mode current (1) UVLO_CEx = 1.7 V 2.8 mA mA VREG 7 V < VDD < 15 V Output current 4.5 5.1 0 5.5 V 100 mA OSCILLATOR, RT Phase frequency accuracy RRT= 110 kΩ Phase frequency set range RT (1) 300 150 25 kΩ ≤ RRT ≤ 500 kΩ kHz 1000 0.7 kHz V UNDERVOLTAGE LOCKOUT (UVLO_CE1, UVLO_CE2) Enable threshold, standby mode Internal 5VREG regulator enabled 0.5 1.0 1.5 V UVLO threshold PWM Switching enabled 1.9 2 2.1 V UVLO hysteresis At the UVLO_CEx pin 40 UVLO_CE1, UVLO_CE2 bias current (1) mV 1 μA 70 ns 3 mV PWM DMAX Maximum duty cycle per channel (1) tON(min) Minimum controllable pulse width 2-phase, 4-phase, 8-phase, or 16-phase 87.5% 3-phase, 6-phase, or 12-phase 83.3% PWM COMPARATOR Input offset voltage –3 VSHARE See (1) (1) 6 IVSHR = 0 1.785 1.8 1.815 V –30 μA < iVSHR < 50 μA 1.785 1.8 1.815 V Specified by design. Not production tested. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Electrical Characteristics (continued) –40°C ≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, ƒSW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX 0 0.7 2.0 UNIT ERROR AMPLIFIER CH1, ERROR AMPLIFIER CH2 Input common mode range (1) Input bias current (1) VFB = 0.7 V FBx voltage (1) 10 0.6965 0.700 V nA 0.7035 V Output source current VCOMP = 1.1 V, VFB = 0.6 V 1 2 Output sink current VCOMP = 1.1 V, VFB = BP5 1 2 mA 8 12 MHz 60 90 dB BW (1) Open loop gain (1) mA VOLTAGE TRACKING (TRK1, TRK2) SS source current After EN, before PWM and during hiccup mode After first PWM pulse 5 6.0 7.3 10 12.5 15 Fault enable threshold (1) 1.4 Internal clamp voltage (1) 2.4 SS sink resistance (1) Pulldown resistance µA V V 1 kΩ 60 mV CURRENT SENSE AMPLIFIERS (CS1, CS2) Differential input voltage Ac –60 Input offset voltage CS1, CS2, trimmed Gain transfer to PWM COMP 5 mV < VCS < 60 mV, VCSRT = 1.5 V Input common mode (1) CSA –2.0 0 2.0 mV 12 13 14 V/V 0 Input bias current 5.8 100 V nA DIFFERENTIAL AMPLIFIER (DIFFO) Gain 1.0 V < VOUT < 5.8 V Input common mode range (1) 0.997 1 0 1.003 5.8 Output source current (1) VOUT – VVGSNS = 2 V, VDIFFO > 1.98 V, VDD-VOUT > 2 V 2 Output source current (1) VOUT – VVGSNS = 2 V, VDIFFO > 2.02 V VDD – VOUT = 1 V 1 Output sink current (1) VOUT – VVGSNS = 2 V, VDIFFO > 2.02 V 2 Unity gain bandwidth (1) 5 8 Input Impedance, non inverting (1) VOUT to GND 60 Input Impedance, inverting (1) GSNS to DIFFO 60 V/V V mA MHz kΩ GATE DRIVERS tRISE HDRV1, HDRV2 source onresistance VBOOT1, VBOOT2 = 5 V, VSW1 = VSW2 = 0 V, Sourcing 100 mA HDRV1, HDRV2 sink onresistance 1 2 3 VVREG = 5 V, VSW1 = VSW2 = 0 V, Sinking 100 mA 0.5 1.2 2 LDRV1, LDRV2 source onresistance VVREG = 5 V, VSW1 = VSW2 = 0 V, Sourcing 100 mA 1 2 3 LDRV1, LDRV2 sink onresistance VVREG = 5 V, VSW1 = VSW2 = 0 V, Sinking 100 mA 0.3 0.65 1 HDRVx rise time (1) Ω CLOAD= 3.3 nF 25 75 tFALL HDRVx fall time (1) CLOAD= 3.3 nF 25 75 tRISE LDRVx rise time (1) CLOAD= 3.3 nF 25 75 tFALL LDRVx fall time (1) CLOAD= 3.3 nF 20 60 Minimum controllable on-time CLOAD= 3.3 nF 50 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 ns 7 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Electrical Characteristics (continued) –40°C ≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, ƒSW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX –19% –16.5% –14% UNIT OUTPUT UNDERVOLTAGE FAULT VFB relative to VREF Undervoltage delay (1) 3 µs CURRENT LIMIT IILIM Output current 18.8 20 21.2 µA POWER GOOD PGOOD transition low threshold VFB rising relative to VREF 10% 12.5% 15% PGOOD transition low threshold VFB falling relative to VREF –15% –12.5% –10% PGOOD trip hysteresis 2% PGOOD delay (1) 5% 10 Low level output voltage, VOL IPGOOD = 4 mA PGOOD bias current VPGOOD= 5.0 V µs 0.35 0.4 V –2 1 2 µA 0.421 0.5 0.526 V 0.23 0.25 0.27 V/V RAMP Ramp amplitude (1) VIN BALANCE VIN balance gain, AVB THERMAL SHUTDOWN Shutdown temperature (1) Hysteresis 155 (1) °C 30 DIGITAL CLOCK SIGNAL (CLKIO) Pullup resistance (1) Pulldown resistance (1) Output leakage (1) 8 IOH = 5 mA 27 IOL = 10 mA 27 Tri-state Submit Documentation Feedback Ω Ω 1 µA Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 7.6 Typical Characteristics 4.2660 VBP5 − BP5 Turnon Threshold Voltage − V VBP5 − BP5 Turnoff Hysteresis Voltage − mV 230.4 230.2 230.0 229.8 229.6 229.4 229.2 4.2655 4.2650 4.2645 4.2640 4.2635 4.2630 4.2625 4.2620 4.2615 229.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 4.2610 −40 −25 −10 TJ − Junction Temperature − °C 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 1. BP5 Turnoff Hysteresis Voltage vs Temperature Figure 2. BP5 Turnon Threshold Voltage vs Temperature 310 13.00 RT = 110 kΩ ∆CS = 30 mV 308 12.90 ∆CS = 60 mV 12.85 12.80 ∆CS = 5 mV 12.75 12.70 12.65 fOSC − Oscillator Frequency − kHz AC − Current Sense Gain − V/V 12.95 12.60 306 304 302 300 298 296 294 12.55 −40 −25 −10 5 20 35 50 65 80 292 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 3. Current Sense Gain vs Temperature Figure 4. Oscillator Frequency vs Temperature 1.0055 3.1 1.0050 3.0 1.0045 IBP5 − BP5 Current − mA Voltage Gain 1.0040 1.0035 1.0030 VIN = 0.7 V 1.0025 1.0020 1.0015 VIN = 4.0 V 1.0010 2.9 2.8 2.7 2.6 2.5 1.0005 1.0000 −40 −25 −10 5 20 35 50 65 80 95 110 125 2.4 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 5. Differential Amplifier Voltage Gain vs Temperature Figure 6. BP5 Current vs Temperature Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 9 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 4.0 14 3.5 12 ISS − Soft Start Current − µA IDDQ − Shutdown Quiescent Current − mA Typical Characteristics (continued) 3.0 2.5 2.0 1.5 1.0 After First PWM 10 8 6 Prior to PWM 4 2 0.5 0 −40 −25 −10 5 20 35 50 65 80 0 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 8. TRKX Soft Start Current vs Temperature Figure 7. Shutdown Quiescent Current vs Temperature 3.5 4.0 3.0 RHDRV − Drive Resistance − Ω DIFFAMP Input Offset Voltage − mV 3.5 3.0 2.5 2.0 1.5 1.0 Source 2.5 2.0 Sink 1.5 0.5 0 −40 −25 −10 5 20 35 50 65 80 1.0 −40 −25 −10 5 95 110 125 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 9. Differential Amplifier Input Offset Voltage vs Temperature Figure 10. HDRV Source and Sink Resistance vs Temperature 1.2 701.0 700.8 VFB − Feedback Voltage − mV RLDRV − Sink Resistance − Ω 1.1 1.0 0.9 0.8 700.6 700.4 700.2 700.0 699.8 0.7 699.6 0.6 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction T emperature − °C Figure 11. LDRV Sink Resistance vs Temperature 10 699.4 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 12. Feedback Voltage vs Temperature Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 5.30 2.0 5.28 1.8 5.26 VVSHARE − VSHARE Voltage − V VVREG − Output Regulation Voltage − V Typical Characteristics (continued) ILOAD = 66 mA 5.24 5.22 5.20 5.18 5.16 No Load 5.14 1.6 ILOAD = 189 µA 1.4 1.2 No Load 1.0 0.8 0.6 0.4 0.2 5.12 5.10 −40 −25 −10 5 20 35 50 65 80 0.0 −40 −25 −10 95 110 125 TJ − Junction Temperature − °C 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 14. VSHARE Voltage vs Temperature Figure 13. VREG Output Voltage vs Temperature VUVLO_CEx − UVLO Threshold Voltage − V 2.3 2.1 1.9 1.7 PWM Enabled 1.5 1.3 1.1 VREG Enabled 0.9 0.7 0.5 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 15. UVLO_CEX Threshold Voltage vs Temperature Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 11 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The TPS40140 operates with a programmable fixed switching frequency. It is a current feedback controller with forced phase current balancing. When compared to voltage mode control, the current feedback controller results in a simplified feedback network and reduced input line sensitivity. Phase current is sensed by using either the direct current resistance (DCR) of the filter inductors or current sense resistors installed in series with the output. See the section Inductor DCR Current Sense. The current signal is then amplified and superimposed on the amplified voltage error signal to provide current mode PWM control. Other features include programmable input undervoltage lockout (UVLO), differential input amplifier for precise output regulation, user programmable operation frequency, programmable pulse-by-pulse overcurrent protection, output undervoltage shutdown and restart, capacitor to set soft-start time and power good indicators. The TPS40140 is a versatile controller that can operate as a single controller or 'stacked' in a multi-controller configuration. A TPS40140 has two channels that may be configured as a multi-phase (single output) or as a dual, with two independent output voltages. The two channels of a single controller always switch 180° out-ofphase. See the Feature Description for further discussion on the clock and voltage master and clock and voltage slave. Some pins are used to set the operating mode, and other pins' definition change based on the mode selected. 12 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 8.2 Functional Block Diagram BP5 TPS40140 U1 V5REG VDD 17 21 VREG U4 RAMP1 8 CS1 31 + + U5 27 BOOT1 PWM1 U8 U3 ICTLR1 CSRT1 32 2 GSNS 3 DIFFO 1 FB1 36 + U12 + + + U11 U10 OC1 6 mA to 12 mA OC2 FB1 U23 UV/OV/OC Control 18 BOOT2 FB2 0.7 V VREF + U20 6 mA to 12 mA + TRK2 12 U6 PWM Logic – COMP1 35 U14 + U15 – + U17 U19 PWM2 U16 RAMP2 COMP2 10 CS2 14 + CSRT2 13 U18 Anti Cross Conduction U21 U22 ICTLR2 OC2 VREG U24 TRK1 TRK2 U27 PGOOD Control 30 PGOOD1 15 PGOOD2 1.8 V UVLO_CE2 16 PHSEL 4 22 LDRV2 FB2 UVLO_CE1 29 5 19 HDRV2 20 SW2 FB1 ILIM2 11 RT 24 LDRV1 23 PGND 0.7 V VREF U13 9 VREG U9 TRK1 33 FB2 25 SW1 U7 Anti Cross Conduction OC1 ILIM1 34 VOUT 26 HDRV1 U2 MCLK U25 CLOCK U26 RAMP GEN RAMP1 RAMP2 6 VSHARE 7 GND 28 CLKIO UDG-08198 8.3 Feature Description 8.3.1 Clock Master and Clock Slave A controller may function as a 'clock master' or a 'clock slave'. The term 'clock master' designates the controller, in a multi-controller configuration, that generates the CLKIO signal for clock synchronization between the clock master and the clock slaves. The CLKIO signal is generated when the 'RT' pin of the clock master is terminated with a resistor to ground and the PHSEL pin of the clock master is terminated with a resistor, or resistor string, to ground. The 'Clock slave' is configured by connecting the RT pin to BP5. Then the Clock slave receives the CLKIO signal from the clock master. The phasing of the slave is accomplished with a resistor string tied to the PHSEL pin. More information is covered in the Clock Master, PHSEL, and CLKIO Configurations section. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 13 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Feature Description (continued) 8.3.2 Voltage Master and Voltage Slave A voltage master has the channel that monitors the output voltage and generates the 'COMP' signal for voltage regulation. A Voltage slave channel is configured by connecting the TRKx pin to BP5. Then the COMP signal from the master is connected to the COMPx pin on the Voltage slave. When the TRKx pin is connected to BP5 the COMPx output for that channel is put in a high impedance state, allowing the regulation for that channel to be controlled by the voltage master COMP signal. 8.3.3 Power Good The PGOOD1, PGOOD2 pins indicate when the inputs and output are within their specified ranges of operation. Also monitored are the UVLO_CE1, UVLO_CE2 and TRK1 and TRK2 pins. The PGOOD has a high impedance when indicating inputs and outputs are within specified limits and is pulled low to indicate an out of limits condition. The PGOOD signal is held low until the respective TRK1 or TRK2 pin voltages exceed 1.4 V, then the undervoltage, overcurrent or overtemperature controls the state of PGOOD. 8.3.4 Power-On Reset (POR) The internal POR function ensures the VREG and BP5 voltages are within their regulation windows before the controller is allowed to start. 8.3.5 Overcurrent The operation during an overcurrent condition is described in the ‘Overcurrent Detection and Hiccup Mode’ section. In summary, when the controller detects 7 clock cycles of an overcurrent condition, the upper and lower MOSFETs are turned off and the controller enters a 'hiccup' mode'. After seven soft start cycles, normal switching is attempted. If the overcurrent has cleared, normal operation resumes, otherwise the sequence repeats. 8.3.6 Output Undervoltage Protection If the output voltage, as sensed by U23 of the functional block diagram on the FB pin becomes less than 0.588 V, the undervoltage protection threshold (84% of VREF), the controller enters the hiccup mode as described in the Overcurrent Detection and Hiccup Mode section. 8.3.7 Output Overvoltage Protection The TPS40140 includes an output overvoltage protection mechanism. This mechanism is designed to turn on the low-side FET when the FB pin voltages exceeds the overvoltage protection threshold of 810-mV (typical). The high-side FET turns off and the low-side FET turns on and stays on until the voltage on the FB drops below the undervoltage threshold. The controller then enters a hiccup recovery cycle as in the undervoltage case. The output overvoltage protection scheme is active at all times. If at any time when the controller is enabled, the FB pin voltage exceeds the overvoltage threshold, the low-side FET turns on until the FB pin voltage falls below the undervoltage threshold. Output overvoltage is defined as any voltage greater than the regulation level that appears on the output. Overvoltage protection is accomplished by the feedback loop monitoring the output voltage via the FB pin. If, during operation the output voltage experiences an overvoltage condition the FB pin voltage rises and the control loop turns the upper FET off and the lower FET is turned on until the output returns to set level. This puts the overvoltage channel in a boost mode configuration and tends to cause the input voltage to be boosted up. If the output overvoltage condition exists prior to the controller PWM switching starting, that is, no switching has commenced, the overvoltaged channel does not start PWM switching. This controller allows for operating with a prebiased output. Because the output is greater than the regulation voltage, no PWM switching occurs. DESIGN HINT Ensure there is sufficient load on the input voltage to prevent excessive boosting. 14 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 8.4 Device Functional Modes 8.4.1 Protection and Fault Modes There are modes of normal operation during start-up and shutdown as well various fault modes that may be detected. It is often necessary to know the state of the upper and lower MOSFETs in these modes. Table 1 shows a summary of these modes and the state of the MOSFETs. A description of each mode follows. Table 1. Fault Mode Summary UPPER MOSFET LOWER MOSFET Programmable UVLO_CEx = LOW MODE OFF OFF Power-on reset: fixed UVLO, BP5 < 4.25 V OFF OFF Overcurrent OFF, hiccup mode OFF, hiccup mode Output undervoltage OFF, hiccup mode OFF, hiccup mode Output overvoltage OFF ON CLKFLT, missing CLKIO at slave OFF OFF PHSEL voltage > 4 V, or open to ground OFF OFF Overtemperature OFF OFF Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 15 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The following sections are partitioned to facilitate applying the TPS40140 in various modes and configurations. The first sections describe functions that are used in all configurations. The following sections are specific to the configuration (that is, single controller, multiple controllers, master and slave). 9.1.1 Synchronizing a Single Controller to an External Clock The TPS40140 has the ability to synchronize a single controller to an external clock. The clock must be a pulse stream at 6 or 8 times the master PWM frequency. See Figure 16. EXT CLK−A 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 1 2 3 PWM −A EXT CLK−S PWM −S UDG−06032 Figure 16. Synchronizing a Single Controller to an External Clock Synchronizing the single controller to an external clock is similar to synchronizing a clock slave to a clock master. The single controller is put in clock slave mode by connecting the RT pin to BP5, disabling the internal clock generator. If the external CLKIO signal is a clock stream without any missing pulses, the master synchronize to an arbitrary pulse so there is no determinant phase synchronization. Without a missing pulse, the PWM frequency is 1/8 of the external clock. If the external CLKIO signal has a missing pulse every 6 cycles or 8 cycles, the controller synchronizes based on the missing pulse which would be in the 6th or 8th position. With the missing pulse, the phase synchronization of the master, to the missing pulse, can be controlled by the voltage on the PHSEL pin. See the section on DIGITAL CLOCK SYNCHRONIZATION. Phase shifting would also be desirable if more than one controller were to be synchronized to the same external clock. The high-level threshold for the external clock is 3.2 V, and the low-level threshold is 0.5 V. The typical duty ratio is approximately 0.5. Figure 16 shows a time slice of the two external clock possibilities and the resulting PWM signal. EXT CLK-A is the continuous clock with no missing pulse and the PWM-A signal could be frequency synchronized anywhere in the clock stream. The PWM signal is at 1/8 of the EXT CLK-A frequency. EXT CLK-S is the external clock stream with a missing pulse every 8 cycles. The phasing of the PWM-S is based on the voltage on the PHSEL pin. For PHSEL grounded, the PWM-S signal is shifted 90 degrees from what would be the falling edge of the missing pulse as shown in Figure 16. 16 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Application Information (continued) If the controller has free running operation (in clock master mode) before receiving the external clock, the switching frequency is set by connecting a resistor from the RT pin to GND. In order to receive the external clock, the PHSEL pin should be connected to GND to disable the output of CLKIO pin. A 500-Ω resistor is recommended to be placed between the external clock and the CLKIO pin. When dynamically shorting the RT pin to BP5 through a switch, the controller switches to clock slave mode and starts to synchronize to the external clock. 9.1.2 Split Input Voltage Operation It may be advantageous to operate a master controller’s power stages from VIN 1, different from the slave controller(s) power stages, VIN 2 where VIN1 > VIN 2. This enables the system designer to optimize the current taken from the system input voltages. In order to balance the output currents, a programmed offset is applied to ILIM2 of the slave controller(s). The voltage on this pin sets the offset current for channel 2. The ramp offset is determined by a resistor, RSET, connected to the ILIM2 pin of the slave, and is given by: ǒ R SET + VOUT Ǔ 1 * 1 100 kW V IN2 V IN1 (1) 9.1.3 Configuring Single and Multiple ICs The controller may be configured for a single output, 2-phase mode or a dual output voltage mode. In the dual output mode the input voltages and the output voltages are independent of each other. In 2-phase mode the input voltages and output voltages are tied together, respectively and certain other pins must be configured. The two phases of a single controller are always 180° out-of-phase. The entry in Table 3 that refer to "TO NETWORK" means the normal resistor-capacitor network used for control loop compensation. The other entries refer to components that are typically connected to the device pin. Table 2. Configuring Clock Mode TIMING RESISTANCE VOLTAGE (V) CLOCK MODE < 0.7 V (resistor to GND) Master (or single device) > 1 V (tied to VREG or VDD) Slave 9.1.3.1 Single Device Operation A single controller may be configured as a 2-phase or dual output. A summary of the modes and device pin connections for a single controller is given in Table 3. The basic schematic of a single controller operating in a 2phase mode is shown in Figure 17. The dual output schematic is shown in Figure 18. Table 3. TPS40140 Single Device Mode Selection and Pin Configuration DEVICE PIN FOR 2 PHASE MODE FOR DUAL OUTPUT MODE COMP1 TO NETWORK TO NETWORK COMP2 COMP1 TO NETWORK TRK1 TO SS CAPACITOR TO SS CAPACITOR TRK2 TO BP5 TO SS CAPACITOR ILIM1 TO SET RESISTORS TO SET RESISTORS ILIM2 GND TO SET RESISTORS FB1 TO NETWORK TO NETWORK TO NETWORK FB2 GND PHSEL GND GND PGOOD1 TO PULLUP RESISTOR TO PULL-UP RESISTOR PGOOD1 TO PULLUP RESISTOR TO PULL-UP RESISTOR CLKIO OPEN OPEN Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 17 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com VIN VIN CS1 CSRT1 CRST2 CS2 HDRV1 HDRV2 SW1 SW2 VOUT LDRV1 VREG LDRV2 L1 L2 PGND PGND VREG BP5 36 35 34 33 32 31 30 29 28 COMP1 ILIM1 TRK1 CSRT1 CS1 PGOOD1 UVLO_CE1 CLKIO EN CLKIO FB1 CSRT1CS1 1 DIFFO BOOT1 27 VLOAD 2 VOUT HDRV1 26 GNDLD 3 GSNS SW1 25 4 PHSEL 5 RT 6 VSHARE 7 GND 8 BP5 9 FB2 LDRV1 24 HDRV1 SW1 LDRV1 PGND 23 TPS40140 LDRV2 22 LDRV2 VREG 21 VLOAD ILIM2 TRK2 CSRT2 CS2 PGOOD2 UVLO_CE2 VDD BOOT2 GNDLD COMP2 L O A D SW2 20 10 11 12 13 14 15 16 17 18 HDRV2 19 SW2 HDRV2 COMP1 VIN CRST2 CS2 EN UDG-07130 Figure 17. Typical Applications Circuit, 2-Phase Mode 18 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 CS1 VIN CSRT1 CS2 CSRT2 VIN HDRV1 HDRV2 Vout1 SW1 LDRV1 VREG Vout2 SW2 LDRV2 L2 L1 PGND PGND BOOT1 VREG BOOT2 CLKIO CLKIO 28 UVLO−CE1 29 PGOOD1 30 EN CS1 CS1 31 CSRT1 32 2 VOUT 3 GSNS BOOT1 27 BOOT1 HDRV1 HDRV1 26 SW1 SW1 25 PHSEL LDRV1 24 LDRV1 5 RT 6 VSHARE 7 GND VREG 21 8 BP5 SW2 20 9 FB2 18 BOOT2 17 VDD 16 UVLO−CE2 15 PGOOD2 14 CS2 13 CSRT2 Vout2 LDRV2 VREG SW2 HDRV2 19 HDRV2 CS2 CSRT2 L O A D LDRV2 22 12 TRK2 VLOAD PGND 23 11 ILIM2 BP5 TRK1 33 DIFFO 4 V R E G ILIM1 34 1 10 COMP2 VLOAD GNDLD COMP1 35 FB1 36 CSRT1 BP5 Vout2 VIN BOOT2 EN BP5 GNDLD ‘ Figure 18. Typical Applications Circuit, Dual Mode 9.1.3.2 Multiple Devices In a multiple device system, it is often desirable to synchronize the clocks each device to minimize input ripple current as well as radiated and conducted emissions. This is accomplished by designating one of the controllers as the master and the other devices as 'slaves. The master generates the system clock, CLKIO, and it is distributed to the slaves. This is the most useful configuration of multiple devices and the one that is demonstrated in this data sheet. It is described in more detail in the Clock Master, PHSEL, and CLKIO Configurations section. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 19 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com To increase the total current capability, or number of outputs, a single slave controller can be added to a master controller as shown in Figure 21. The configuration of the 2-phase master and a 2-phase slave controller is also shown in Table 4 It is possible to have the master controller operate on one switching frequency and the slave controllers on another, independent frequency. In a multi-phase system the slave controllers would continue to share load current with the master. This is not a preferred configuration and is mentioned here only for completeness. The 10-kΩ resistor connected from the CLKIO line to GND is required to ensure that the CLKIO line falls to GND quickly when the master device is shutdown or powers off. The master CLKIO pin goes to a high impedance state at these times and if the CLKIO line was high, there is no other active discharge part. The slave controllers look at the CLKIO line to determine if the system is supposed to be running or not. A level below 0.5 V on CLKIO is required for this purpose. NOTE In any system configured to have a CLK master and CLK slaves, a 10-kΩ resistor connected from CLKIO to GND is required. Table 4. TPS40140 Two-Device, 4-Phase Mode Selection and Pin Configuration DEVICE PIN, MASTER MASTER, 2-PHASE DEVICE PIN, SLAVE SLAVE, 2-PHASE COMP1 TO NETWORK COMP1 TO MASTER, COMP1 COMP2 COMP1 COMP2 TO MASTER, COMP1 TRK1 TO SS CAPACITOR TRK1 TO BP5 TRK2 TO BP5 TRK2 TO BP5 ILIM1 TO SET RESISTORS ILIM1 GND ILIM2 GND ILIM2 GND FB1 TO NETWORK FB1 GND FB2 GND FB2 GND GND PHSEL 39-kΩ TO GND PHSEL PGOOD1 TO PULLUP RESISTOR PGOOD1 TO PULL-UP RESISTOR PGOOD1 TO PULLUP RESISTOR PGOOD1 TO PULL-UP RESISTOR CLKIO TO SLAVE, CLKIO CLKIO VSHARE TO SLAVE, VSHARE VSHARE BP5 TO SLAVE, BP5 BP5 TO MASTER, CLKIO TO MASTER, VSHARE TO MASTER, BP5 DESIGN HINT TI recommends adding a 220-pF ceramic capacitor in parallel with the PHSEL resistor string. This capacitor is connected from the PHSEL pin of the master control to GND. 20 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Figure 19. Typical Applications Circuit, 4-Phase Mode In this configuration, the master senses that there is one slave controller, by the 39-kΩ resistor on the PHSRL pin, and distributes the CLKIO signal. The slave controller senses the 0-V level on its PHSEL pin and delays the proper number of CLKIO pulses to be 90° out-of-phase with the master. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 21 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Two ICs could also be configured as a 2-phase, single output master and a slave which has two independent outputs, but is synchronized with the master controller clock. Table 5 shows the configuration. Table 5. TPS40140 Two-Device, 2-Phase Master and a Dual-Output Slave Configuration DEVICE PIN, MASTER MASTER, 2 PHASE DEVICE PIN, SLAVE SLAVE, DUAL OUTPUT COMP1 To network COMP1 To network COMP2 COMP1 COMP2 To network TRK1 To SS capacitor TRK1 To SS capacitor TRK2 To BP5 TRK2 To SS capacitor ILIM1 To set resistors ILIM1 To set resistors ILIM2 GND ILIM2 To set resistors FB1 To network FB1 To network FB2 GND FB2 To network PHSEL 39-kΩ to GND PHSEL GND PGOOD1 To pullup resistor PGOOD1 To pullup resistor PGOOD1 To pullup resistor PGOOD1 To pullup resistor CLKIO To slave, CLKIO CLKIO To master, CLKIO 9.1.3.3 Clock Master, PHSEL, and CLKIO Configurations The clock synchronization between the master and the slave controller(s) is implemented in a simple configuration of series 39-kΩ resistors. There is a 20-μA current source from the PHSEL pin of the master controller. Depending on the number of slave controllers connected, the slave controllers selects the proper delay from the master CLKIO signal to accomplish phase interleaving. On a given master or slave controller, the two phases are always 180° out-of-phase. The CLKIO signal has either six or eight clocks for each cycle of the switching period. For maximum flexibility the master and slave controllers can be either in a 2-phase configuration or a Dual output configuration 9.1.3.3.1 One Device Operation The basic configuration of a single device is shown in Figure 20. TPS40140 MASTER 20 µA PHSEL CLKIO Figure 20. Single Controller Only, Two Phases 22 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.1.3.3.2 Two ICs Operation To increase the total current capability, or number of outputs, a single slave controller can be added as shown in Figure 21. TPS40140!MASTER 20 μA PHSEL CLKIO TPS40140 R1 CLKIO PHSEL SLAVE1 10 kΩ Figure 21. Master Controller and One Slave Controller, Four Phases In this configuration, the master senses that there is one slave controller, and distributes the CLKIO signal. The slave controller senses the zero-volt level on its PHSEL pin and delays the proper number of CLKIO pulses to be 90° out-of-phase with the master. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 23 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.1.3.3.3 Three ICs Operation To increase the total current capability to six phases, or to increase the number of outputs, two slave controllers can be added as shown in Figure 22. In this configuration for perfect interleaving, the master and slaves are 120° out-of-phase. The CLKIO signal has six clocks for each cycle of the switching period; therefore, the switching period is reduced. In this six-phase mode, the switching frequency is increased 33%. TPS40140!MASTER 20 μA PHSEL CLKIO TPS40140 R2 CLKIO PHSEL SLAVE2 TPS40140 R1 CLKIO PHSEL SLAVE1 10 k" Figure 22. Master Controller and Two Slave Controllers, Six Phases In this configuration, the master senses that there are two slave controllers, and distributes a six-phase CLKIO signal. The slave controllers sense the voltage on their PHSEL pins, and delay the proper number of CLKIO pulses to be 60° or 120° out-of-phase with the master. 9.1.3.3.4 Four ICs Operation To further increase the total current capability to eight phases, or to increase the number of outputs, three slave controllers can be added as shown in Figure 23. 24 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 TPS40140!MASTER 20 μA PHSEL CLKIO TPS40140 R3 CLKIO PHSEL SLAVE3 TPS40140 R2 CLKIO PHSEL SLAVE2 TPS40140 R1 CLKIO PHSEL SLAVE1 10 kΩ Figure 23. Master Controller and Three Slave Controllers, Eight Phases In this configuration, the master senses that there are three slave controllers, and distributes a eight-phase CLKIO signal. The slave controllers sense the voltage on their PHSEL pins and delay the proper number of CLKIO pulses to be 45°, 90°, and 135° out-of-phase with the master. 9.1.3.3.5 Six ICs Operation To further increase the total current capability to twelve phases, or to increase the number of outputs, five slave controllers can be added as shown in Figure 24. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 25 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com TPS40140!MASTER 20 μA BP5 TPS40140 ILIM2 PHSEL CLKIO CLKIO SLAVE5 PHSEL TPS40140 ILIM2 TPS40140 R2 CLKIO CLKIO PHSEL PHSEL SLAVE4 TPS40140 ILIM2 SLAVE3 SLAVE2 TPS40140 R1 CLKIO CLKIO PHSEL PHSEL SLAVE1 10 kΩ Figure 24. Master Controller and Five Slave Controllers, 12-Phases In this configuration, the master senses that there are two slave controllers (due to the 2 resistors) and distributes a six-phase CLKIO signal. Slave1 and slave2 are turned on at 60° and 120° respectively, as before with two slaves. However, to get twelve phases with a six-phase clock, both edges of the CLKIO signal are used to control the slaves. With the ILIM2 tied high on slave3,slave4, and slave5, they turn on at the rising edge of CLKIO while the master and slave1 and slave2 turn on at the falling edge of CLKIO. If four slaves are desired, just delete one of the slaves from Figure 24. The interleaving is not perfect because there is be 30° between the master and three slaves. The deleted slave causes 60° between the two adjacent slaves. See Figure 26 for phasing details. 26 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.1.3.3.6 Eight ICs Operation To further increase the total current capability to sixteen phases, or to increase the number of outputs, seven slave controllers can be added as shown in Figure 25. TPS40140!MASTER 20 μA PHSEL CLKIO BP5 TPS40140 PHSEL TPS40140 R3 ILIM2 CLKIO CLKIO SLAVE7 PHSEL SLAVE3 TPS40140 PHSEL ILIM2 CLKIO TPS40140 R2 CLKIO SLAVE6 PHSEL SLAVE2 TPS40140 PHSEL ILIM2 TPS40140 R1 CLKIO CLKIO SLAVE5 PHSEL SLAVE1 TPS40140 PHSEL ILIM2 10 kΩ CLKIO SLAVE4 Figure 25. Master Controller and Seven Slave Controllers, 16 Phases In this configuration, the master senses that there are three slave controllers (due to the three resistors) and distributes an eight-phase CLKIO signal. Slave1, slave2, and slave3 are turned on at 90°, 45°, and 135° respectively as before with three slaves. However, to get sixteen phases with an eight-phase clock, both edges of the CLKIO signal are used to control the slaves. With the ILIM2 tied high on slave4, slave5, slave6, and slave7 they turn on at the rising edge of CLKIO, while the master and slave1, slave2, and slave3 turn on at the falling edge of CLKIO. If six slaves are desired, just delete one of the slaves from Figure 25. The interleaving is not be perfect because there is 22.5° between the master and three slaves. The deleted slave causes 45° between the two adjacent slaves. See Figure 26 for a phasing details. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 27 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.1.4 Digital Clock Synchronization Figure 26 is a summary of the master and slave clock phasing. The master and the slaves can be selected to be a multi-phase, single output configuration and/or several independent output voltage rails, independent of the clocking. Phase PHSEL connection Clock scheme M M_CH2 M_CH1 (A) Two Phase Master 1 2 3 4 5 6 1 2 3 4 5 6 7 8 S_CH1 (E) ‘Missing’ Pulse with six and eight CLKIO pulses M R M_CH2 M_CH1 S PHSEL connection S_CH2 (B) Four Phase, Master and one Slave S1_CH1 ILIM2= h i M S2_CH1 M Phase S5 S1_CH1 R R M_CH1 S2_CH1 S5_CH1 S2 M_CH2 S2 S3_CH1 S4 S4_CH1 M_CH2 M_CH1 R S4_CH2 R S1 S1 S2_CH2 S5_CH2 S3 S2_CH2 S1_CH2 S3_CH2 S1_CH2 (F) Twelve Phase , Master and five Slaves (C) SixPhase, Master and two Slaves S1_CH1 S4_CH1 S6_CH1 S1_CH1 M S3_CH1 M S2_CH1 R R S3 M_CH2 M_CH1 S2 S6 S2_CH2 S5_CH2 S7_CH1 S5 S2_CH2 R S3_CH2 S4_CH2 S1 (D) Eight Phase, Master and three Slaves M_CH1 M_CH2 S1_CH2 S1 S5_CH1 R S2 R S2_CH1 S7_CH2 S3 R S3_CH1 S7 S4 S3_CH2 S1_CH2 S6_CH2 (G) Sixteen Phase, Master and seven Slaves Figure 26. Clock Phasing Summary 28 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.1.4.1 Basic Configurations for 2, 4, 6, 8, 12, or 16 Phases The solid square boxes in Figure 26 represent the PHSEL pin of the master (M) controller or a numbered slave controller (S1-S7). The labels on the spokes of the wheels indicate a master Channel 1 and master Channel 2 (M_CH1 and M_CH2) and numbered slaves Channel 1 and slave Channel 2 (Sn_CH1 and Sn_CH2). The Channel 1 and Channel 2 of a given master or slave is always 180° out-of-phase. The master and slaves are automatically configured for proper phasing based on the resistor string from the master to the slaves. All the resistors are 39 kΩ to 41.2 kΩ. Part (A) above shows a single controller operating two phases 180° out-of-phase. Part (B) above shows four phase operation. This is configured by connecting a single resistor from the master PHSEL to GND and grounding the slave PHSEL pin. The individual channels are 90° out-of-phase. Part (C) above shows six phase operation. This is configured by connecting two resistors from the master PHSEL to GND. The first resistor tap is connected to slave2 PHSEL pin and then grounding the slave1 PHSEL pin. The individual channels are 60°out-of-phase. Part (D) above shows eight phase operation. This is configured by connecting three resistors from the master PHSEL to GND. The first resistor tap is connected to slave3 PHSEL pin. The second resistor tap is connected to slave2 PHSEL pin and then grounding the slave1 PHSEL pin. The individual channels are 45° out-of-phase. Part (F) above shows twelve phase operation. This is configured by connecting two resistors from the master PHSEL to GND. The master PHSEL pin is also connected to slave5 PHSEL pin. The first resistor tap is connected to slave2 and slave4 PHSEL pins and then grounding the slave1 and slave3 PHSEL pins. The individual channels are 30° out-of-phase. Additionally, the ILIM2 pins of slave5, slave4 and slave3 are left open (internal pullup) or externally connected to BP5. Part (G) above shows sixteen phase operation. This is configured by connecting three resistors from the master PHSEL to GND. The master PHSEL pin is also connected to slave7 PHSEL pin. The first resistor tap is connected to slave3 and slave6 PHSEL pins. The second resistor tap is connected to slave2 and slave5 PHSEL pins and then grounding the slave1 and slave4 PHSEL pins. The individual channels are 22.5° out-of-phase. Additionally, the ILIM2 pins of slave7, slave6, slave5, and slave4 are left open (internal pullup) or externally connected to BP5. 9.1.4.2 Configuring for Other Number of Phases Configuring for other than 2, 4, 6, 8, 12 or 16 phases is simply a matter of not attaching one or more slave controllers. The phasing between master and populated slaves is as shown above. For example a 3-phase system could be configured with a master CH1 and master CH2 and 1 phase of a slave. Referring to Part (B) above, the 3 phases could be master CH1, master CH2 and slave CH1 or slave CH2 as shown in Figure 27. S_CH1 M R S M_CH2 M_CH1 S_CH2− NOT USED IN3PH Figure 27. Phase System: 2 Channels of the Master and 1 Channel of the Slave The 3-phase system could also be configured with 1 channel of the master and 2 channels of the slave. Referring to Part (B) above, the 3 phases could be master CH1 or master CH2 and slave CH1 and slave CH2. In either of these configurations there is 90° between two of the channels and 180° between the other channel. The unused channel could be another independent output voltage whose clocking would occupy the phase not used in the 3-phase system. This philosophy can be used for any number of phases not shown in Figure 26, Clock Phasing Summary. For example, a 10-phase system could be configured as shown in Figure 28. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 29 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com PHSEL connection Phase ILIM 2 = hi M S1_CH1 S4 R S1 S2_CH1 S5_CH1 NOT USED R S2 S3_CH1 S4_CH1 M_CH2 M_CH1 S5_CH2 NOT USED S4_CH2 S3 S2_CH2 S3_CH2 S1_CH2 Figure 28. Ten-Phase System With Slaves Not Attached Clocking between the attached slave channels is as shown. 9.1.5 Typical Start-Up Sequence Figure 29 shows a typical start-up with the VDD applied to the controller and then the UVLO-CEx being enabled. Shutdown occurs when the VDD is removed. VDD VREG BP5 2.0 V 1.0 V UVLO_CEx 2.4 V 1.4 V 0.7 V 0 TRKx SSWAIT VOUT PGOOD t - TIME Figure 29. Typical Start-Up and Shut-Down Sequence 30 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.1.6 Track (Soft-Start Without PreBiased Output) A capacitor connected to the TRKx pins sets the power-up time. When UVLO_CEx is high and the internal power-on reset (POR) is cleared, the calibrated current source, starts charging the external soft start capacitor with 12-μA. The PGOOD pin is held low during the start-up. The rising voltage across the capacitor serves as a reference for the error amplifier, U10 and U14. When the soft start voltage reaches the level of the reference voltage, VREF = 0.7 V, the converter’s output reaches the regulation point and further voltage rise of the soft-start voltage has no effect on the output. When the soft start voltage reaches 1.4 V, the powergood (PGOOD) function is cleared to be reported on the PGOOD pin. Normally the PGOOD pin goes high at this time. Equation 2 is used to calculate the value of the soft-start capacitor. CSS is in Farads and tSS is given in seconds. tSS = CSS ´ 58 ´ 103 (2) 9.1.7 Soft-Start With PreBiased Outputs For prebiased outputs the TPS40140 uses two levels of soft-start current that charge the soft-start capacitor connected to the TRKx pin(s). PWM switching begins when the TRKx voltage rises to the voltage present on the FBx pin. When the first PWM pulse occurs, the charging current is increased to 12 μA. Figure 30 shows the typical waveforms present on the TRKx pin and the output voltage, VOUT when VOUT is prebiased. TRKx rises due to the 6 μA current, until at 1 the voltage on TRKx equals the prebiased voltage on the FBx pin, at time t1. At this time, the soft-start current is increased to 12 μA and TRKx rises with an increase in the slope. When TRKx reaches 0.7 V, at time t2, the output should be in regulation. The voltage on the TRKx pin continues to rise. When the TRKx voltage is 1.4 V, at time t3, the PGOODx signal is enabled. The TRKx voltage continues to rise to 2.4 V where it is clamped internally. This approach provides for an accurate detection of the threshold where FBx = TRKx. Figure 31 is a block diagram of the implementation. The calculation for the soft start time, due to prebias, includes the time from t0 to t1, plus the time from t1 to t2, as shown in Equation 3 through Equation 5. t1 + t2 + C SS 6 mA CSS 12 mA ǒ Ǔ VOUT RBIAS R1 ) R BIAS ǒ 0.7 V * ǒ (3) ǓǓ V OUT R BIAS R1 ) RBIAS where • • CSS is in Farads tSS is in seconds (4) tSS = t1 + t2 (5) If there is no prebias (VOUT = 0 V), the equation reduces to case without prebias. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 31 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 2.4 1.4 12 µA FBx 0.7 FBx TRKx 6 µA 0 VOUT VPRE-BIAS VOUT PGOOD 0 t0 t1 t2 t3 UDG-12121 Figure 30. Soft-Start With PreBiased Output Waveforms From CSx Amplifier VOUT VREF 0.7 V R1 FBx TRKx RBIAS Error Amplifier Ramp1 + COMPx + U3 + + 12 µA CEXT PWM Logic + 6 µA U7 Comparator + UDG−06031 Figure 31. Implementation of PreBiased Output DESIGN HINT If the prebiased is greater than the regulation voltage, the controller does not start. This is a condition of an overvoltage being applied before the controller starts PWM switching. 9.1.8 Track Function in Configuring a Slave Channel The TRKx pin is internally clamped to 2.4 V. To configure a channel as a slave, the TRKx pin is pulled up externally to 5 V. This configures the output of the error amplifier, COMPx, for that channel to be a high impedance, allowing the master COMP signal to control the slave channel. 32 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.1.9 Differential Amplifier, U9 The unity gain differential amplifier has high bandwidth to achieve improved regulation at user defined point of load and ease layout constrains. The output voltage is sensed between the VOUT and GSNS pins. The output voltage programming divider is connected to the output of the amplifier, the DIFFO pin. 30 kW VOUT + DIFFO − 30 kW 30 kW GSNS 30 kW Figure 32. Differential Amplifier Configuration DESIGN HINT Because of the resistor configuration of the differential amplifier, the input impedance must be kept very low or errors result in setting the output voltage. 9.1.10 Setting the Output Voltage Two resistors, R1 and RBIAS sets the output voltage as shown in Figure 33. VOUT R1 VFB RBIAS COMP + 0.7 V UDG-05100 Figure 33. Setting the Output Voltage With RBIAS RBIAS is calculated in Equation 6. R BIAS + 0.7 ǒ R1 Ǔ ǒV OUT * 0.7Ǔ (6) 9.1.11 Programmable Input UVLO Protection A voltage divider that sets 2 V on the UVLO_CEx pins determines when the controller begins to operate. The internal regulators are enabled when the voltage on the UVLO_CEx pins exceeds 1 V, but switching commences when the voltage is 2 V. 9.1.12 CLKFLT, CLKIO Pin Fault If the CLKIO signal is to be distributed from the master to the slave controllers, and is not there, the slave controller enters a ‘Standby’ mode. The upper and lower MOSFETs are turned off but the internal 5-V regulator is still active and VREG is present. The CLKIO signal could be turned off at the master controller or the connection to the slave CLKIO input could be opened. If the CLKIO signal is restored, normal operation continues. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 33 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.1.13 www.ti.com PHSEL Pin Fault The PHSEL pin is normally terminated with a resistor string, or tied directly to ground. If this string becomes open, the PHSEL pin voltage is pulled up internally to greater than 4 V. The controller enters a ‘Standby’ mode. The upper and lower MOSFETs are turned off but the internal 5-V regulator is still active and VREG is present. If the PHSEL connection is restored, normal operation continues after 64 PWM clock cycles. 9.1.14 Overtemperature If the temperature of the controller die is detected to be above 155°C, the upper and lower MOSFETs are turned off and the 5-V regulator, VREG, is turned off. When the die temperature decreases 30°C the controller performs a normal start-up. 9.1.15 Fault Masking Operation If the TRKx pin voltage is externally limited below the 1.4-V threshold, the controller does not respond to an Undervoltage fault and the PGOOD output remains low. Other fault modes remain operational. The overcurrent protection continues to terminate PWM cycle every time the threshold is exceeded, but the hiccup mode is not entered. 9.1.16 Setting the Switching Frequency The clock frequency is programmed by the value of the timing resistor connected from the RT pin to ground. See Equation 7. This equation gives the frequency for an 8-phase system. For a 6-phase system the frequency is 1 1/3 times higher. ( -1.058 R = 1.33 ´ 39.2 ´ 103 ´ ƒ PH ) -7 , where • • ƒPH is a single-phase frequency, kHz The Rt resistor value is expressed in kΩ (7) See Figure 34. 450 400 RT- Timing Resistor (k  350 300 250 200 150 100 50 0 100 200 300 400 500 600 700 800 900 1000 Phase Switching Frequency (kHz) C001 Figure 34. Phase Switching Frequency vs Timing Resistance 34 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com 9.1.17 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Current Sense Figure 35 shows the current sensing and overcurrent detection architecture. R SNS VOUT IOUT CSn + CSRTn VC – + + COMP U1 CS gain = 12. 5 + U2 Error Amplifier – U3 Ve + VSHARE Ramp 1.8 V 0.5 V R1 ILIM R2 U4 PWM + U5 + 0V U6 20 µA + U7 Overcurrent UDG-12122 VOUT Figure 35. Output Current Sensing and Overcurrent Detection The output current, IOUT, flows through RSNS and develops a voltage, VC across it, representative of the output current. The voltage, VC, could also be derived from an R-C network in parallel with the output inductor. This voltage is amplified with a gain of 12.5 and then subtracted from the Error Amp output, COMP, to generate the Ve voltage. The Ve signal is compared to the slope-compensation RAMP signal to generate the PWM for the modulator. As the output current is increased, the amplified VC causes the Ve signal to decrease. In order to maintain the proper duty cycle (PWM), the COMP signal must increase. Therefore the magnitude of the COMP signal contains the output current information: COMP = Ve + (IPEAK ´ R SNS ) ´ 12.5 (8) This is integral in the overcurrent detection as can be seen at comparator U7, comparing the ILIM voltage with COMP. In order to have the proper duty cycle at PWM, Ve is shown in Equation 9. V RAMP Ve = RAMP ´ OUT + VSHR + VIN 2Nph where • Nph is 6 if PHSEL voltage = 1.6 ± 0.2 V, otherwise Nph is 8 (9) Combining equations: COMP = RAMP ´ VOUT RAMP + VSHR + + (IPEAK ´ RSNS ) ´ 12.5 VIN 2Nph (10) Equation 10 shows the reason for resistors R1 and R2 being tied to VSHR and VOUT, respectively. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 35 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.1.18 Current Sensing and Balancing The controller employs peak current mode control scheme, thus naturally provides certain degree of current balancing. With current mode, the level of current feedback should comply with certain guidelines depending on duty factor known as “slope compensation” to avoid the sub-harmonic instability. This requirement can prohibit achieving a higher degree of phase current balance. To avoid the controversy, a separate current loop that forces phase currents to match is added to the proprietary control scheme. This effectively provides high degree of current sharing independent of the controller’s small signal response and is implemented in U3 and U22 in the Functional Block Diagram section. High bandwidth current amplifiers, U2 and U21 can accept as an input voltage either the voltage drop across dedicated precise current sense resistors, or inductor’s DCR voltage derived by an RC network, or thermally compensated voltage derived from the inductor’s DCR. The wide range of current sense arrangements ease the cost/complexity constrains and provides superior performance compared to controllers utilizing the low-side MOSFET current sensing. See the Inductor DCR Current Sense section for selecting the values of the RC network. 9.1.19 Overcurrent Detection and Hiccup Mode To reduce the input current and component dissipation during on overcurrent event, a hiccup mode is implemented. Hiccup mode refers to a sequence of 7 soft-start cycles where no MOSFET switching occurs and then a restart is attempted. If the fault has cleared, the restart results in returning to normal operation and regulation. This is shown in Figure 36. 2.4 V TRCKn 1.5 V 0.5 V (A) GND VIN SW NODE GND (B) VOUT, REG VOUT GND (C) ILIM COMP (D) t0 t1 t2 t3 Figure 36. Hiccup Mode and Recovery 36 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 In Figure 36, normal operation is occurring between t0 and t1 as shown by VOUT being at the regulated voltage, (C) and normal switching on the SW NODE (B) and COMP at its nominal level, (D). At t1, an overcurrent load is experienced. The increased current forces COMP to increase to the ILIM level as shown in (D). If the COMP voltage is above the ILIM voltage for 7 switching cycles, the controller enters a hiccup mode. During this time the controller is not switching and the switching MOSFETs are turned off. The TRKx voltage goes through 7 cycles of charging and discharging the soft-start capacitor. At the end of the 7 cycles the controller attempts another normal restart. If the fault has been cleared, the output voltage comes up to the regulation level as shown at time t3. If the fault has not cleared, the COMP voltage again rises above the ILIM voltage and the hiccup mode repeats. If the overcurrent condition exists for seven (7) PWM clock cycles the converter turns off the upper and lower MOSFETs and initiates a hiccup mode restart. In hiccup mode, the TRKx pin is periodically charged and discharged. After seven hiccup cycles, the controller attempts another soft-start cycle to restore normal operation. If the overload condition persists, the controller returns to the hiccup mode. This condition may continue indefinitely. 9.1.20 Calculating Overcurrent Protection Level In order to set the desired overcurrent (IOC), a few variables must be known. The input and output voltage, the output inductor value and it's DC resistance (DCR), as well as the switching frequency. Also known are the ramp voltage which is 0.5 V and the VSHARE voltage, VSH which is 1.8 V. See the list of variables and their values at the end of this section. The overcurrent set point is in terms of the DC output current, but the current sense circuit monitors the peak of the current. Therefore, the current ripple is needed and is calculated from the values of: • input voltage (VIN) • output voltage (VOUT) • switching frequency (fSW) • output inductance (L) The ripple current is given by Equation 11. IRIPPLE = (VIN - VOUT ) ´ VOUT ´ L VIN 1 fSW (11) Equation 12 calculates the detected peak current and is used in Equation 14. æI IPEAK = ç RIPPLE 2 è ö ÷ + IOC ø (12) It is this IPEAK current that is detected by the current sense circuit. The two resistors needed to set the peak overcurrent protection threshold and their connection for each channel is shown in Figure 37. DESIGN HINT Resistor R2 may be connected to the output voltage, VOUT, or to the output of the differential amplifier, DIFFO, if used. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 37 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com VOUT TPS40140 R2 ILIMx R1 VSHARE UDG-12123 Figure 37. Selecting Overcurrent Threshold Resistors, R2 and R1 The two factors, alpha and beta help simplify the final equations and are given by Equation 13 and Equation 14. V a = RAMP VIN (13) æ V ö b = DCR ´ A C ´ I PEAK + ç RAMP ÷ è 2 ´ Nph ø (14) R1 is shown in Equation 15. b + a ´ VSH R1 = (1 - a ) ´ I LIM (15) R2 is shown in Equation 16. b + a ´ VSH R2 = a ´ I LIM where • • • • • • • • • • VRAMP is the ramp amplitude (0.5 V typ) VIN is the input voltage DCR is the inductor equivalent DC resistance AC is the gain transfer to comparator IOC is the single-phase DC overcurrent trip point IPEAK is the peak single-phase inductor current Nph is 6 if PHSEL voltage = 1.6 V ±0.2 V, otherwise Nph = 8 VSH is the VSHARE reference voltage (typ 1.8 V) ILIM is the current limit, output current (typ 20 μA) Variable range is specified in the Electrical Characteristics table (16) 9.1.21 Design Examples Information 9.1.21.1 Inductor DCR Current Sense The preferred method for sampling the output current for the TPS40140 is known as the inductor DCR method. This is a lossless approach, as opposed to using a discrete current sense resistor which occupies board area and impacts efficiency as well. The inductor DCR implementation is shown in Figure 38. 38 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 VIN L1 DCR VOUT C1 R1 + VC − To CSRTx To CSx Figure 38. Inductor DCR Current Sense Approach The inductor L1 consists of inductance, L, and resistance, DCR. The time constant of the inductor: L / DCR should equal the R1 × C1 time constant. Then choosing a value for C1 (0.1 μF is a good choice) solving for R1 is shown in Equation 17. L1 R1 = DCR ´ C1 (17) The voltage into the current sense amplifier of the controller , VC, is calculated in Equation 18. VOUT 1 VC = ´ (VIN - VOUT )´ + IOC ´ DCR 2 R1´ C1´ fSW ´ VIN (18) As the DC load increases the majority of the voltage, VC, is determined by (IOC ×DCR), where IOC is the per phase DC output current. It is important that at the overcurrent set point that the peak voltage of VC does not exceed 60 mV, the maximum differential input voltage. If the voltage VC exceeds 60 mV, a resistor, R2,can be added in parallel with C1 as shown in Figure 39. Adding R2 reduces the equivalent inductor DCR by the ratio shown in Equation 20 VIN L1 DCR VOUT C1 R1 R2 + VC − To CSRTx To CSx Figure 39. Using Resistor R2 to Reduce the Current Sense Amplifier Voltage The parallel combination of R1 and R2 is shown in Equation 19. L1 R1 R2 = DCR ´ C1 (19) The ratio shown in Equation 20 provides the required voltage attenuation. R2 R1 + R2 (20) Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 39 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.2 Typical Application 9.2.1 Application 1: Dual-Output Configuration from 12 to 3.3 V and 1.5 V DC-DC Converter Using a TPS40140 Figure 40 shows the schematic of the dual output converter design. J1 1 2 3 4 12Vin +/- 10% GND 12VIN C3 22uF C2 22uF C1 22uF C4 22uF GNDTP1 5 R1 10K 5 TRK1 C5 0.022uF TRK1 Q1 RJK0305DPB 4 3 2 1 R2 10k C6 1uF CSRT1 C8 0.1uF R3 open C7 330pF 5 R7 10K CMP1 5 Q3 RJK0301DPB 4 3 2 1 UVLO1 C10 3.3n 3 2 1 R32 10K BP5 R4 1 SW1 Q4 RJK0301DPB 4 12VIN COMP1 L1 1uH 3 2 1 1 R33 10K CS1 C9 open R5 50 CS1 Q2 Open 4 R6 10K 1 2 1 R8 8.66K C11 2.2 n D1 BAT54HT1 UVLO1 J2 Remote Sense+ Remote Sense- GSNS VOUT1 VREG RT R16 33K C20 1uF C21 1uF ILIM2 R18 698k COMP2 VSHR BP5 1 BP5 COMP2 VOUT2 C26 470pF R22 10K BODE21 BODE21 R24 open VOUT2 PG2 PGOOD2 C15 + 220u + C17 220u 1.5V @ 20A 1 2 3 4 C18 22uF J9 R17 4.7 BP5 C22 0.1uF R21 4.7 D2 BAT54HT1 C24 0.1uF C25 4.7uF 1 2 3 1 2 3 C28 3.3n R27 10K 12VIN Q5 RJK0301DPB Q6 RJK0301DPB 4 1 R25 1 5 VOUT2 VOUT2 3.3V @ 20A 5 UVLO2 1 2 3 1 2 3 R31 10K L2 1.5uH SW2 4 Q8 RJK0305DPB 4 AGND2 Q7 Open + C31 + 220u C32 220u + C33 + 220u C34 220u C35 22uF CS2 R30 10K 5 4 3 2 1 J10 5 1 1 TRK2 C16 + 220u VREG 4 AGND1 TRK2 C14 220u R11 51.1 VOUT1 VREG R28 10k C36 1uF C37 0.022uF R10 51.1 CSRT1 C30 0.1uF C27 open 1 C13 0.1uF + C29 0.1uF R26 2.7k BP5 R29 10K 10 C23 2.2n ILIM2 R20 50 CMP2 R19 50 U1 TPS40140RHH C12 0.1uF GNDTP2 GSNS R14 62K 2 VOUT 3 GSNS 4 PHSEL 5 RT 6 VSHARE 7 GND 8 BP5 9 FB2 TRK2 12 CSRT2 13 CS2 14 PGOOD2 15 UVLO-CE2 16 VDD 17 BOOT2 18 PHSELIN VSHR R15 22.6K BOOT1 27 26 HDRV1 SW1 25 LDRV1 24 23 PGND 22 LDRV2 VREG 21 20 SW2 19 HDRV2 DIFFO CS2 R23 39K R12 4.7 PGOOD2 1 PwPd 37 FB1 36 COMP1 35 ILIM1 34 TRK1 33 CSRT1 32 CS1 31 PGOOD1 30 UVLO-CE1 29 CLKIO 28 BODE12 BODE11 ILIM2 PHSELOUT R13 510k CLKIO 11 1 TRK2 R9 50 VOUT1 GNDTP3 12VIN 1 C38 22uF C39 22uF C40 22uF C41 22uF Figure 40. Dual-Output Converter Schematic 9.2.1.1 Design Requirements The following example shows the design process and component selection for a dual output synchronous buck converter using TPS40140. Table 6 provides the design goal parameters. Only the calculated numbers for the 1.5-V output are shown, however, the equations are suitable for both channel design. A list of symbol definitions is found at the end of this section. Table 6. Design Goal Parameters PARAMETER VIN Input voltage VIN(ripple) Input ripple voltage VOUT Output voltage TEST CONDITION MIN TYP MAX UNIT 10.8 12 13.2 V IOUT = 20 A 0.15 V 1.5 V Line regulation 10.8 V ≤ VIN ≤ 13.2 V 0.5% Load regulation 0 V ≤ IOUT ≤ 20 A 0.5% VP-P Output ripple voltage IOUT = 20 A 30 mV ΔVOUT Output voltage deviation during load transient ΔIOUT = 10 A, VIN = 12 V 80 mV IOUT Output current 10.8 V ≤ VIN ≤ 13.2 V η Efficiency IOUT = 20 A VIN = 12 V fSW Switching frequency 40 0 20 500 Submit Documentation Feedback A 87% kHz Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Step 1: Inductor Selection The inductor is determined by the desired ripple current. The required inductor is calculated by: VIN(max) - VOUT VOUT 1 L= × × IRIPPLE VIN(max) fSW (21) Typically the peak-to-peak inductor current, IRIPPLE is selected to be around 20% of the rated output current. In this design, IRIPPLE is targeted at 15% of IOUT1. The calculated inductor is 0.89 μH and in practical a 1-μH, 32-A, 1.7 mΩ inductor IHLP-5050FD from Vishay is selected. So, the inductor ripple current is 2.66 A. 9.2.1.2.2 Step 2: Output Capacitor Selection The output capacitor is typically selected by the output load transient response requirement. Equation 22 estimates the minimum capacitor to reach the undervoltage requirement with load step up. Equation 23 estimates the minimum capacitor for overvoltage requirement with load step down. When VIN(min) < 2 ×VOUT, the minimum output capacitance can be calculated using Equation 22. Otherwise, Equation 23 is used. COUT (MIN) = I2TRAN(MAX) ´ L ( ) 2 ´ VIN(min) - VOUT ´ VUNDER (22) when VIN(min) < 2 × VOUT COUT (MIN) = I2TRAN(MAX) ´ L 2 ´ VOUT ´ VOVER (23) when VIN(min) > 2×VOUT In this design, VIN(min) is much larger than 2 × VOUT, so Equation 23 is used to determine the minimum capacitance. Based on a 10-A load transient with a maximum of 80-mV deviation, a minimum 417-μF output capacitor is required. In the design, four 220-μF, 4-V, SP capacitor are selected to meet this requirement. Each capacitor has an ESR of 5 mΩ. Another criterion for capacitor selection is the output ripple voltage. The output ripple is determined mainly by the capacitance and the ESR. ESRCo = VRIPPLE(TotOUT) - VRIPPLE(COUT) IRIPPLE æ ö IRIPPLE VRIPPLE(TotOUT) - ç ÷ 8×COUT × fSW ø è = IRIPPLE (24) With 880-μF output capacitance, the ripple voltage at the capacitor is calculated to be 0.76 mV. In the specification, the output ripple voltage should be less than 30 mV, so based on Equation 24, the required maximum ESR is 11 mΩ. The selected capacitors can meet this requirement. 9.2.1.2.3 Step 3: Input Capacitor Selection The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the maximum ESR can be estimated by: ´ (VIN - VOUT )´ VOUT I CIN(min) = OUT 2 VRIPPLE(CIN) ´ fsw ´ VIN (25) VRIPPLE(CinESR ) ´ VIN ESRCIN = IOUT + 1 IRIPPLE ´ (VIN - VOUT ) 2 (26) ( ) For this design, assume VRIPPLE(CIN) is 100 mV and VRIPPLE(CinESR) is 50 mV, so the calculated minimum capacitance is 43.6 μF and the maximum ESR is 2.7 mΩ. Choosing four 22-μF, 16-V, 2-mΩ ESR ceramic capacitors meets this requirement. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 41 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com Another important consideration for the input capacitor is the RMS ripple current rating. The RMS current in the input capacitor is estimated by: IRMS_CIN = D × (1 - D) × IOUT (27) D is the duty cycle. The calculated RMS current is 6.6 A. Each selected ceramic capacitor has a RMS current rating of 4.3 A, so it is sufficient to reach this requirement. 9.2.1.2.4 Step 4: MOSFET Selection The MOSFET selection determines the converter efficiency. In this design, the duty cycle is very small so that the high-side MOSFET is dominated with switching losses and the low-side MOSFET is dominated with conduction loss. To optimize the efficiency, choose smaller gate charge for the high-side MOSFET and smaller RDS(on) for the low-side MOSFET. The RENESAS RJK0305 and RJK0301 are selected as the high-side and low-side MOSFETs respectively. To reduce the conduction loss, two RJK0301 components are used. The power losses in the high-side MOSFET is calculated with the following equations: The RMS current in the high side MOSFET is show in Equation 28. I SWrms + Ǹ D ǒ I OUT I ) RIPPLE 12 2 Ǔ 2 + 7.07 A (28) The RDS(on) is 13 mΩ when the MOSFET gate voltage is 4.5 V. The conduction loss is: P SWcond + ǒI SWrmsǓ 2 R DS(on) (sw) + 0.65 W (29) The switching loss is: Psw sw = Ipk × Vin × fsw × R drv × (Qgd sw + Qgssw ) Vgtdrv = 0.26 W (30) The calculated total loss in the high-side MOSFET is: P SWtot + PSWcond ) PSWsw + 0.91 W (31) The power losses in the low-side SR MOSFET is calculated in the following equations: The RMS current in the low-side MOSFET is shown in Equation 32. I SRrms + Ǹ (1 * D) ǒ 2 I OUT ) I RIPPLE 12 Ǔ 2 + 18.7 A (32) The RDS(on) is 4 mΩ when the MOSFET gate voltage is 4.5 V. The total conduction loss in the two low-side MOSFETs is shown in Equation 33. R DS(on) (sr) 2 P SRcond + ǒI SRrmsǓ + 0.7 W N where • N is the number of MOSFETs. Here, it is equal to 2. (33) The total power loss in the body diode is: Pdiode = 2 × IOUT × t d × Vf × fsw = 0.77 W (34) So the calculated total loss in the SR MOSFET is: 42 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 P SRtot + PSRcond ) PDIODE + 1.47 W (35) 9.2.1.2.5 Step 5: Peripheral Component Design 9.2.1.2.5.1 Switching Frequency Setting (RT Pin 5) ( -1.058 R = 1.33 ´ 39.2 ´ 103 ´ ƒ PH ) -7 , (36) In the design, a 62-kΩ resistor is selected. The actual switching frequency is 510 kHz. 9.2.1.2.5.2 Output Voltage Setting (FB1 Pin 36) Substitute R1 with 10 kΩ and then calculate RBIAS. RBIAS = 0.7 × R1 = 8.75 kΩ VOUT - 0.7 (37) 9.2.1.2.5.3 Current Sensing Network Design (CS1 Pin 31 and CSRT1 Pin 32) For small pulse width, to avoid the sub-harmonics brought by the loop delay, a resistor divider is usually used to attenuate the current feedback information as described in the Inductor DCR Current Sense section. Choosing C1 a value for 0.1-μF, and let R1 and R2 be equal, calculating R1 and R2 with Equation 38 and Equation 39. In this design, R1 and R2 are 10 kΩ. L R1//R2 = = 5.8 kΩ DCR ´ C1 (38) R1 = R2 = 11.6 kΩ (39) A simplified equation to determine if the design produces sub-harmonics is shown in Equation 40. VIN × Ac L > DCR(eqv) 2 × Vramp × fsw DCR (eqv) (40) R2 DCR = × DCR = R1+ R2 2 (41) In this design, a 1-μF capacitor is placed at the CSRT1 pin for the purpose of eliminating noise. It can be removed without degrading performance. 9.2.1.2.5.4 Overcurrent Protection (ILIM1 Pin 34) The resistor selection equations in the CALCULATING OVERCURRENT PROTECTION LEVEL section are simplified to calculate the over current setting resistors. Set the DC over current rating at 30 A. VRAMP VRAMP DCRe qv ´ Ac ´ IPK + + ´ VSH 2 ´ NPH VIN R1 = = 22.5kW VRAMP (1 ) ´ ILIM VIN (42) VRAMP VRAMP DCRe qv ´ Ac ´ IPK + + ´ VSH 2 ´ NPH VIN R2 = = 510kW VRAMP ´ ILIM VIN where • • • • • AC is the gain transfer to comparator (typ 12.5) VRAMP is the ramp amplitude (typ 0.5 V) VSH is the VSHARE reference voltage (typ 1.8 V) ILIM is the current limit output current (typ 20 µA) NPH is 6 if VPHSEL = 1.6 V ±0.2 V, otherwise NPH = 8 (43) Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 43 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.2.1.2.5.5 VREG (Pin 21) A 4.7-μF capacitor is connected to VREG pin to filter noise. 9.2.1.2.5.6 BP5 (Pin 8) A 4.7-Ω and 1-μF capacitor is placed between VREG and BP5. 9.2.1.2.5.7 PHSEL (Pin 4) For this dual output configuration, the PHSEL pin is directly tied to GND. The channel 1 and channel 2 has a 180° phase shift. 9.2.1.2.5.8 VSHARE (Pin 6) A 1-μF capacitor is tied from VSHARE pin to GND. 9.2.1.2.5.9 PGOOD1 (Pin 30) The PGOOD1 pin is tied to BP5 with a 10-kΩ resistor. 9.2.1.2.5.10 UVLO_CE1 (Pin 29) It is connected to the input voltage with a resistor divider. The two resistors have the same value of 10-kΩ. When the input voltage is higher than 2 V, the chip is enabled. 9.2.1.2.5.11 Clkio (Pin 28) CLKIO is floating as no clock synchronization required for dual output configuration. 9.2.1.2.5.12 BOOT1 and SW1 (Pin 27 and 25) A bootstrap capacitor is connected between the BOOT1 and SW1 pin. The bootstrap capacitor depends on the total gate charge of the high side MOSFET and the amount of droop allowed on the bootstrap capacitor. Cboot = Qg 8nc = = 16 nF ΔV 0.5V (44) For this application, a 0.1-μF capacitor is selected. 9.2.1.2.5.13 TRK1 (Pin 33) A 22-nF capacitor is tied to TRK1 pin to provide 1.28-ms of soft-start time. ( ) tSS = CSS ´ 58 ´ 103 = 22 ´ 10-9 ´ 58 ´ 103 = 1.28ms (45) 9.2.1.2.5.14 DIFFO, VOUT, and GSNS (Pin 1, Pin 2, and Pin 3) VOUT and GSNS are connected to the remote sensing output connector. DIFFO is connected to the feedback resistor divider. If the differential amplifier is not used, VOUT and GSNS are suggested to be grounded, and DIFFO is left open. 9.2.1.2.6 Feedback Compensator Design (COMP1 Pin 35) Peak current mode control method is employed in the controller. A small signal model is developed from the COMP signal to the output. Gvc(s) = (s × COUT × ESR + 1) × ROUT 1 1 × × DCR × Ac s × τs + 1 s × COUT × (ESR +ROUT ) + 1 (46) The time constant is defined by: 44 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com tS = SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 t æ ç ç ln ç æV ç ç RAMP çè t è ö æ æ VRAMP ö æ VOUT ö ö -ç ´ DCR ´ Ac ÷ ÷ çç ÷ ÷ t ø è L ø ÷ èè ø ÷ V V 2 V ´ ö æ IN OUT ö ´ DCR ´ Ac OUT ´ DCR ´ Ac ÷ ÷ ÷-ç ÷ L L ø è ø ø (47) The low-frequency pole is calculated by: fVCP1 = 2 × π × COUT 1 = 2.36 kHz × (ESR +ROUT ) (48) The ESR zero is calculated by: fESR = 1 = 144.7 kHz 2 × π × COUT × ESR (49) In this design, a Type II compensator is employed to compensate the loop. VREF R2 C1 R1 + C2 Figure 41. Type II Compensator The compensator transfer function is: Gc(s) = 1 s × (R1+ R2) × C1+ 1 × R1× C2 s × (s × R2 × C1+ 1) (50) The loop gain transfer function is: Tv(s) = Gc(s) × Gvc(s) (51) Assume the desired crossover frequency is 60 kHz, then set the compensator zero about 1/10 of the crossover frequency and the compensator pole equal to the ESR zero. The compensator gain is then calculated to achieve the desired bandwidth. In this design, the compensator gain, pole and zero are selected as following: 1 = 174.9 kHz 2 × π × R2 × C1 1 fz = = 5.91kHz 2 × π × (R1+ R2) × C1 fp = (52) (53) T v (j × 2 × π × fc) = 1 (54) The compensator gain is solved as 400. 1 A CM = = 400 R1´ C2 where • • • • C1 = 2.6 nF C2 = 250 pF R2 = 350 Ω Set R1 equal to 10-kΩ, and then calculate all the other components (55) Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 45 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com In the real laboratory practice, the final components are selected as following to increase the phase margin and reduce PWM jitter. • R1 = 10 kΩ • C2 = 330 pF • R2 = 50 Ω • C1 = 2.2 nF 1 1.5122 0.9 1.512 0.8 1.5118 0.7 1.5116 Output Voltage Efficiency 9.2.1.3 Application Curves 0.6 0.5 0.4 Vin = 10.8 V Vin = 12 V Vin = 13.2 V 1.5114 1.5112 1.511 1.5108 0.3 0.2 1.5106 Vin = 10.8 V Vin = 12 V Vin = 13.2 0.1 0 0 5 10 15 Output Current 20 1.5104 1.5102 25 0 5 D001 Figure 42. Efficiency vs Output Current VIN = 12 V VOUT = 1.5 V IOUT = 20A 20 25 D001 Figure 43. Load Regulation VIN = 12 V Figure 44. Output Voltage Ripple 46 10 15 Output Current Submit Documentation Feedback VOUT = 1.5 V IOUT = 20A Figure 45. Input Voltage Ripple Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 VIN = 12 V VOUT = 1.5 V IOUT = 0A VIN = 12 V Figure 46. Start-up from UVLO_CE VIN = 12 V IOUT = 1A Figure 47. Shutdown from UVLO_CE VOUT = 1.5 V VIN = 12 V Figure 48. Load Step 0 A to 10 A, 5 A/us VIN = 12 V VOUT = 1.5 V VOUT = 1.5 V Figure 49. Load Step 10 A to 0 A, 5 A/us VOUT = 1.5 V Figure 50. Prebias Sequence Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 47 TPS40140 www.ti.com 60 240 40 160 20 80 0 0 -20 Phase [B-A] (deg) Mag [B/A] (dB) SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 -80 Mag [B/A] Phase [B-A] -40 100 200 300 500 700 1000 VIN = 12 V 2000 3000 5000 10000 20000 Frequency (Hz) 50000 100000 200000 -160 500000 1000000 D004 VOUT = 1.5 V IOUT = 20A Figure 51. Bode Plot 48 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.2.2 Application 2: Two-Phase Single Output Configuration from 12 to 1.5 V DC-DC Converter Using a TPS40140 The following example illustrates the design process and component selection for a two-phase single output synchronous buck converter using TPS40140. The design goal parameters are given in Table 7. The inductor and MOSFET selection equations are quite similar to the dual output converter design, so they are not repeated here. Figure 52 shows the schematic of the two phase single output converter design. TP1 J1 12ViN +/- 10% GND 1 12VIN 2 C1 22uF 16V TP2 C5 0.022uF Q1 RJK0305DPB C2 22uF 16V C3 22uF 16V C4 22uF 16V R1 3.01K CS1 Q2 Open L1 0.53uH R2 Open C6 CSRT 1uF C8 0.1uF R3 open C7 220pF Q3 RJK0301DPB CS1 TP3 Q4 RJK0301DPB C9 open R9 51.1 PHSEL U1 TPS40140RHH RT VSHARE LDRV1 PGND LDRV2 VREG GND BP5 FB2 SW2 HDRV2 COMP CSRT R11 51.1 TP7 1 2 27 26 25 24 23 22 21 20 19 + C15 + C16 + C17 + C18 330uF 330uF 330uF 330uF 2V 2V 2V 2V C19 10uF 6.3V 1 2 J3 1.5v @ 32A J4 GND VREG R16 4.7 BP5 C23 0.1uF R17 4.7 VREG CS2 BP5 R10 51.1 TP8 PwPd 37 FB1 36 COMP1 35 ILIM1 34 TRK1 33 CSRT1 32 CS1 31 PGOOD1 30 UVLO-CE1 29 CLKIO 28 SW1 C14 0.1uF Remote Sense+ Remote Sense- GSNS VOUT VREG C13 0.1uF R12 4.7 BOOT2 1uF HDRV1 UVLO-CE2 VDD C22 VOUT GSNS 10 11 12 13 14 15 16 17 18 C21 1uF 64.9K BOOT1 PGOOD2 R15 41.2K DIFFO COMP2 GSNS 1 2 3 4 5 6 7 8 9 ILIM2 TRK2 CSRT2 CS2 C20 1000pF 1 2 D1 BAT54HT1 UVLO VOUT R14 J2 TP4 C12 2.2n TP5 R13 1M R6 10K R8 8.66K TP6 R7 10K C10 Open C11 47pF COMP R5 50 R4 Open CSRT C27 0.1uF D2 BAT54HT1 C28 0.1uF R20 Open R19 10K C24 0.1uF C26 Open C25 4.7uF Q6 RJK0301DPB Q5 RJK0301DPB 12VIN UVLO C29 1uF C30 47pF Enable On/Off R22 10K J5 L2 0.53uH TP9 Q8 RJK0305DPB R18 Open Q7 Open CS2 R21 3.01K 12VIN C31 22uF 16V C32 22uF 16V C33 22uF 16V C34 22uF 16V Figure 52. Two-Phase Single Output Converter Schematic Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 49 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.2.2.1 Design Requirements Table 7. Design Goal Parameters PARAMETER VIN Input voltage VIN(ripple) Input ripple voltage VOUT Output voltage TEST CONDITION MIN TYP MAX UNIT 12 13.2 V 10.8 IOUT = 32 A 0.15 V 1.5 V Line regulation 10.8 V ≤ VIN ≤ 13.2 V Load regulation 0 V ≤ IOUT ≤ 32 A VP-P Output ripple voltage IOUT = 32 A 30 mV ΔVOUT Output voltage deviation during load transient ΔIOUT = 15 A, VIN = 12 V 50 mV IOUT Output current 10.8 V ≤ VIN ≤ 13.2 V η Efficiency IOUT = 32 A VIN = 12 V fSW Switching frequency 0.5% 0.5% 0 32 A 87% 500 kHz 9.2.2.2 Detailed Design Procedure 9.2.2.2.1 Step 1: Output Capacitor Selection The output capacitor is typically selected by the output load transient response requirement. Equation 23 in the dual output design example is used. The inductor L in the equation is equal to the phase inductance divided by number of phases. Based on a 15-A load transient with a maximum of 50 mV deviation, a minimum 795-μF output capacitor is required. In the design, four 330-μF, 2 V, SP capacitor are selected to meet this requirement. Each capacitor has an ESR of 6 mΩ. Another criterion for capacitor selection is the output ripple voltage that is determined mainly by the capacitance and the ESR. Due to the interleaving of channels, the total output ripple current is smaller than the ripple current from a single phase. The ripple cancellation factor is expressed in Equation 56. m m +1 NPH ´ (D )´( - D) PH N NPH IRIP _ NORN = D ´ (1 - D) where • • • D is the duty cycle for a single phase NPH is the number of active phases, here it is equal to 2 m = floor (NPH × D) is the maximum integer that does not exceed the (NPH × D), here m is 0 (56) The output ripple current is then calculated in Equation 57. The maximum output ripple current is 4.3 A with maximum input voltage. VOUT ´ (1 - D) ´ IRIP _ NORM IRIPPLE = L ´ fSW (57) With 1.32 mF output capacitance, the ripple voltage at the capacitor is calculated to be 0.82 mV. In the specification, the output ripple voltage should be less than 30 mV, so based on Equation 24, the required maximum ESR is 6.7 mΩ. The selected capacitors can meet this requirement. 9.2.2.2.2 Step 2: Input Capacitor Selection The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the maximum ESR can be estimated by Equation 25 and Equation 26 in the dual output design example. The phase current should be used in the calculation. For this design, VRIPPLE(CIN) assume is 100mV and VRIPPLE(CinESR) is 50 mV, so the calculated minimum capacitance is 40 μF and the maximum ESR is 2.7 mΩ. Choosing four 22-μF, 16-V, 2-mΩ ESR ceramic capacitors meet this requirement. 50 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 Another important consideration for the input capacitor is the RMS ripple current rating. Due to the interleaving of multi-phase, the input RMS current is reduced. The input ripple current RMS value over load current is calculated in Equation 58. 2 3 3 m ö æm +1 NPH é VOUT ´ (1 - D )ù m ö æ ö ö 2 æ 2 æm +1 ´ + ´ + ´ + ´ IIN _ NORM = ç D D m 1 D m D ( ) ê ú ÷ ç ç ÷ NPH ø÷ èç NPH NPH ø÷ è ø 12 ´ D2 ë L ´ fSW ´ IOUT û è è NPH ø where • • • D is the duty cycle for a single phase NPH is the number of active phases, here it is equal to 2 m = floor (NPH × D) is the maximum integer that does not exceed the (NPH × D), here m is 0 (58) The input ripple RMS current is calculated in Equation 59. In this design, the maximum IIN_NORM is calculated to be 0.225 with the minimum input voltage, and the maximum input ripple RMS current is 7.2 A. Each selected ceramic capacitor has a RMS current rating of 4.3 A, therefore, sufficient to reach this requirement. IRMS_CIN = IIN_NORM × IOUT (59) 9.2.2.2.3 Step 3: Peripheral Component Design 9.2.2.2.3.1 Switching Frequency Setting (Rt Pin 5) RRT = 1.33 ´ (39.2 ´ 103 ´ (fSW )-1.058 - 7) = 71.5 kW where • ƒsw represents the phase switching frequency (60) In the design, a 64.9-kΩ resistor is selected. The actual switching frequency is 490 kHz. 9.2.2.2.3.2 COMP1 and COMP2 (Pin 35 and Pin 10) COMP1 is connected to the compensator network. The selection of compensation components is similar to the dual output design example. COMP2 is directly tied to COMP1. 9.2.2.2.3.3 TRK1 and TRK2 (Pin 33 and Pin 12) A soft start capacitor is connected between TRK1 and GND. TRK2 is directly tied to BP5 to set this channel as a slave 9.2.2.2.3.4 ILIM1 and ILIM2 (Pin 34 and Pin 11) ILIM1 is connected to the resistor network that has the same design as the dual output example. The peak current in Equation 42 and Equation 43 is the peak current of each phase. ILIM2 is connected to GND. 9.2.2.2.3.5 FB1 and FB2 (Pin 36 and Pin 9) FB1 is tied to the feedback network. FB2 is connected to GND. 9.2.2.2.3.6 PHSEL (Pin 4) For this two phase configuration, the PHSEL pin is directly tied to GND. 9.2.2.2.3.7 PGOOD1 and PGOOD2 (Pin 30 and Pin 15) Both of PGOOD1 and PGOOD2 are tied to BP5 with a 10-kΩ resistor. 9.2.2.2.3.8 CLKIO (Pin 28) CLKIO is open as no clock synchronization required for two phase configuration. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 51 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 9.2.2.2.3.9 DIFFO, VOUT, and GSNS (Pin 1, Pin 2, and Pin 3) VOUT and GSNS should be connected to the remote sensing output connector. DIFFO is connected to the feedback resistor divider. If the differential amplifier is not used, VOUT and GSNS are suggested to be grounded, and DIFFO is left open. 9.2.3 Application Curves 1 1.5145 Vin = 10.8 V Vin = 12 V Vin = 13.2 V 0.9 1.5135 0.8 1.5125 Output Voltage Efficiency 0.7 0.6 0.5 0.4 1.5115 1.5105 1.5095 0.3 1.5085 0.2 Vin = 10.8 V Vin = 12 V Vin = 13.2 V 0.1 0 0 4 8 12 16 20 24 Output Current 28 32 36 1.5075 1.5065 40 0 5 10 D001 VOUT = 1.5 V IOUT = 32A VIN = 12 V Figure 55. Output Voltage Ripple 52 25 30 35 D002 Figure 54. Load Regulation Figure 53. Efficiency vs Output Current VIN = 12 V 15 20 Output Current Submit Documentation Feedback VOUT = 1.5 V IOUT = 32A Figure 56. Input Voltage Ripple Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 VIN = 12 V VOUT = 1.5 V IOUT = 0A VIN = 12 V Figure 57. Start-up from UVLO_CE VIN = 12 V IOUT = 1A Figure 58. Shutdown from UVLO_CE VOUT = 1.5 V VIN = 12 V Figure 59. Load Step 0 A to 15 A, 5 A/us VIN = 12 V VOUT = 1.5 V VOUT = 1.5 V Figure 60. Load Step 15 A to 0 A, 5 A/us VOUT = 1.5 V Figure 61. Prebias Sequence Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 53 TPS40140 www.ti.com Mag [B/A] (dB) 60 50 250 Mag [B/A] Phase [B-A] 200 40 150 30 100 20 50 10 0 0 -50 -10 -100 -20 -150 -30 100 200 300 500 700 1000 VIN = 12 V 2000 3000 5000 10000 20000 Frequency (Hz) 50000 100000 200000 Phase [B-A] (deg) SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 -200 500000 1000000 D003 VOUT = 1.5 V IOUT = 32A Figure 62. Bode Plot 54 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.3 System Example 9.3.1 Four-Phase Single Output Configuration from 12 to 1.8 V DC-DC Converter Using Two TPS40140 The following example illustrates the design process and component selection for a 4-phase single output synchronous buck converter using two TPS40140. Here, two modules are designed. One is a master module. The other one is a slave module. Each module contains two phases and each phase handle 5 A. The two modules are stacked together to form a 4-phase converter. More slave modules can be stacked to this converter to get the desired phases. The modules are plugged into a mother board. Figure 63, Figure 64, and Figure 65 shows the schematics of the four phase converter design. Figure 63. Master Module Schematic Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 55 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com System Example (continued) VIN VIN 2.2K CS1 VOUT C7 C8 22u,6.3v 22u,6.3v C16 22u,6.3v C15 22u,6.3v C10 4.7u,6.3V COMP1 PwPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 UVLOCE SW2 HDRV2 VREG PGND LDRV2 SW1 LDRV1 C21 1000p,25v BOOT2 R13 0.0 CS2 R11 2.21k VOUT BP5 ILIM2 C17 1.0u,6.3V 1 2 3 4 5 6 7 8 9 J1 VIN 18 17 C13 16 0.1u,6.3v 15 14 C14 13 0.1u,16v 12 11 10 COMP1 FB2 1 1 GND C6 1.0u,6.3V BP5 BP5 30 PGOOD1 UVLO-CE2 31 CS1 PGOOD2 32 CSRT1 CS2 U1 33 TRK1 CSRT2 34 ILIM1 TPS40140RHH-REV2 TRK2 35 COMP1 ILIM2 36 COMP2 FB1 37 VSHARE VOUT R3 10K VDD RT UVLOCE C9 0.1u,16V BP5 BOOT2 UVLO-CE1 GSNS CS1 28 CLKIO 29 PHSEL R2 10K CLKIO R6 2.21K HDRV1 BP5 VIN VOUT BOOT2 BOOT1 R7 10k C1 0.1u,6.3V C18 0.1u,16v 27 26 25 24 23 22 21 20 19 R5 0.0 DIFFO C5 0.1u,16v Q4 Si7112DN S VREG D1 BAT54A VREG R14 2.0 D G S C20 22u,16V 4 SW2 R12 2.2k C2 1000p,25V G 3 CS2 D Q2 Si7112DN C19 1.0u,16V 2 2 1 R4 R1 2.0 L2 0.8uH,12A 4 SW1 Q3 1 SI5480DU 1 3 C4 22u,16v 2 C3 1.0u,25V 2 L1 0.8uH,12A Q1 1 SI5480DU CLKIO VREG 1 VIN 1 PHSELIN COMP1 1 BP5 1 VSHR 1 R8 4.7 ILIM2 C11 1.0u,6.3V VOUT BP5 1 PHSELIN 1 C12 1.0u,6.3V VSHR 1 Figure 64. Slave Module Schematic 56 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 S1 VIN J1 VOUTTP1 1 VOUT PHSELIN VOUT VINTP1 NC 2 3 4 R3 39 kW C2 180 mF C1 47 mF GND GND GNDTP5 GNDTP3 CLKIO VIN CLKIO VIN 10 kW PHSELIN COMP1 VSHR GND COMP1 VSHR GND Master GND Slave VOUT VOUT UDG-08085 Figure 65. Motherboard Schematic The design goal parameters are given in Table 8. Table 8. Design Goal Parameters PARAMETER VIN Input Voltage VOUT Output voltage VRIPPLE Output ripple IPH Phase current fsw Switching frequency NPH Phase number TEST CONDITIONS IO = 20 A MIN TYP MAX UNIT 10.8 12 13.2 V 1.8 V 20 mV 5 650 A kHz 4 9.3.1.1 Step 1: Output Capacitor Selection The output capacitor is typically selected by the output load transient response requirement. Equation 23 in the dual output design example is used. Also, as mentioned in the two phase design example, the inductor is L equivalent to NPH . Based on a 10-A load transient with a maximum of 30 mV deviation, a minimum 370-μF output capacitor is required. In the design, one 180 μF, 6.3 V, SP capacitor is placed on the mother board. Four 22-μF, 6,3-V ceramic capacitors are placed on each module. The total output capacitance is 356 μF. The output ripple current cancellation factor is calculated to be 0.526 with maximum input voltage based on Equation 56. So the maximum output ripple current is calculated by: Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 57 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 IRIPPLE = www.ti.com VOUT ´ (1 - D) ´ 0.526 = 1.573 A L ´ fSW (61) With 356-μF output capacitance, the ripple voltage at the capacitor is calculated to be 0.85 mV. In the specification, the output ripple voltage should be less than 20 mV, so based on Equation 24, the required maximum ESR is 12 mΩ. The selected capacitors can reach this requirement. 9.3.1.2 Step 2: Input Capacitor Selection The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the maximum ESR can be estimated by Equation 25 and Equation 26 in the dual output design example. For this design, assume VRIPPLE(CIN) is 50 mV and VRIPPLE(CinEST) is 30 mV, also each phase inductor ripple current is 50%, so the calculated minimum capacitance is 23-μF and the maximum ESR is 4.6 mΩ. In this case, one 33-μF 6.3-V SP-capacitor is placed on the mother board and each module has two 22-μF, 6.3-V ceramic capacitors. The maximum input ripple RMS current is calculated to be 2.57 A with the maximum input voltage based on Equation 58. The selected capacitors are sufficient to meet this requirement. 9.3.1.3 Step 3: Peripheral Component Design 9.3.1.3.1 Master Module 9.3.1.3.1.1 Rt (Pin 5) It is connected to GND with a resistor that sets the switching frequency. R = 1.33 ´ (39.2 ´ 103 ´ (fSW )-1.058 - 7) = 45.8 kW (62) Here, ƒsw represents the phase switching frequency. In the design, a 47-kΩ resistor is selected. The actual switching frequency is 650 kHz. 9.3.1.3.1.2 COMP1 and COMP2 (Pin 35 and Pin 10) COMP1 is connected to the compensator network. COMP2 is directly tied to COMP1. 9.3.1.3.1.3 TRK1 and TRK2 (Pin 33 and Pin 12) A soft start capacitor is connected between TRK1 and GND. TRK2 is directly tied to BP5 to set this channel as a salve. 9.3.1.3.1.4 ILIM1 and ILIM2 (Pin 34 and Pin 11) ILIM1 is connected to the resistor network that has the same design as the dual output example. The peak current in Equation 42 and Equation 43 is the peak current of each phase. ILIM2 is grounded. 9.3.1.3.1.5 FB1 and FB2 (Pin 36 and Pin 9) FB1 is tied to the feedback network. FB2 is connected to GND. 9.3.1.3.1.6 PHSEL (Pin 4) For this four phase configuration, the PHSEL pin is tied to GND with a 39-kΩ resistor. 9.3.1.3.1.7 PGOOD1 and PGOOD2 (Pin 30 and Pin 15) Both of PGOOD1 and PGOOD2 are tied to BP5 with a 10-kΩ resistor. 9.3.1.3.1.8 CLKIO (Pin 28) CLKIO is connected to the same pin in the salve module. 58 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 9.3.1.3.2 Slave Module: 9.3.1.3.2.1 RT (Pin 5) It is connected to BP5. The slave module receives the clock from the master module. 9.3.1.3.2.2 COMP1 and COMP2 (Pin 35 and Pin 10) Both of COMP1 and COMP2 are directly tied together to COMP1 or COMP2 in the master module. 9.3.1.3.2.3 TRK1 and TRK2 (Pin 33 and Pin 12) Both TRK1 and TRK2 are directly tied to BP5. 9.3.1.3.2.4 ILIM1 and ILIM2 ( Pin 34 and Pin 11) Both ILIM1 and ILIM2 are grounded. 9.3.1.3.2.5 FB1 and FB2 (Pin 36 and Pin 9) Both FB1 and FB2 are connected to GND. 9.3.1.3.2.6 PHSEL (Pin 4) The PHSEL pin is directly tied to GND. 9.3.1.3.2.7 PGOOD1 and PGOOD2 (Pin 30 and Pin 15) Both of PGOOD1 and PGOOD2 are tied to BP5 with a 10-kΩ resistor. 9.3.1.3.2.8 CLKIO (Pin 28) CLKIO is connected to the master module CLKIO. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 59 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 10 Power Supply Recommendations This device is designed to operate from an input voltage supply between 4.5 V and 15 V. The proper bypassing of input supplies is critical for noise performance. 11 Layout 11.1 Layout Guidelines 11.1.1 Power Stage A synchronous BUCK power stage has two primary current loops – The input current loop which carries high AC discontinuous current while the output current loop carries high DC continuous current. The input current loop includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground path back to the input capacitors. To keep this loop as small as possible, it is generally good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the output capacitor ground and the source of the SR MOSFET should be routed under the inductor and SR MOSFET to minimize the power loop area. The SW node area should be as small as possible to reduce the parasitic capacitance and minimize the radiated emissions. The gate drive loop impedance (HDRV-gate-sourceSW and LDRV-gate-source-GND) should be kept to as low as possible. The HDRV and LDRV connections should widen to 20mils as soon as possible out from the device pin. 11.1.2 Device Peripheral The TPS40140 provides separate signal ground (GND) and power ground (PGND) pins. It is required to separate properly the circuit grounds. The return path for the pins associated with the power stage should be through PGND. The other pins especially for those sensitive pins such as FB, RT and ILIM should be through the low noise GND. The GND and PGND plane are suggested to be connected at the output capacitor with single 20 mil trace. A minimum 0.1-μF ceramic capacitor must be placed as close to the VDD pin and GND as possible with at least 15-mil wide trace from the bypass capacitor to the GND. A 4.7-μF ceramic capacitor should be placed as close to VREG pin and GND as possible. BP5 is the filtered input from the VREG pin. A 4.7-Ω resistor should be connected between VREG and BP5 and a 1-μF ceramic capacitor should be connected from BP5 to GND. Both components should be as close to BP5 pin as possible. When DCR sensing method is applied, the sensing resistor is placed close to the SW node. It is connected to the inductor with Kelvin connection. The sensing traces from the power stage to the chip should be away from the switching components. The sensing capacitor should be placed very close to the CS and CSRT pins. The frequency setting resistor should be placed as close to RT pin and GND as possible. The VOUT and GSNS pins should be directly connected to the point of load where the voltage regulation is required. A parallel pair of 10-mil traces connects the regulated voltage back to the chip. They should be away from the switching components. The PowerPAD™ should be electrically connected to GND. 11.1.3 PowerPAD Layout The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0,33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™ Thermally Enhanced Package (SLMA002) for more information on the PowerPAD package. 60 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 11.2 Layout Example (place capacitor close to controller) (Route as differential pair) R R (place resistor close to inductor) C C C R Vout1 (Route as differential pair) CLKIO BOOT1 VOUT HDRV1 R C UVLO_CE1 CS1 PGOOD1 TRK1 L DIFFO GSNS PHSEL R RT SW1 Thermal Pad PGND R GND C BP5 SW2 R FB2 HDRV2 (Minimize the switching node copper area) VREG VDD L R C R C C VOUT2 Q C R Q C VIN BOOT2 CS2 TRK2 CSRT2 C ILIM2 COMP2 R R LDRV2 (GND) PGOOD2 Vout2 (Route as differential pair) PGND C LDRV1 C R UVLO_CE2 VREG PGND VOUT1 Q C R VSHARE GND Q C R CSRT1 R ILIM1 FB1 R COMP1 C VIN C R GND PGND C (place capacitor close to controller) (Route as differential pair) R (place resistor close to inductor) Figure 66. TPS40140 Layout Example Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 61 TPS40140 SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support Table 9. Definition of Symbols PARAMETER DESCRIPTION VIN(min) Minimum operating input voltage VIN(max) Maximum operating input voltage VOUT Output voltage IRIPPLE Inductor peak-peak ripple current ITRAN(MAX) Maximum load transient VUNDER Output voltage undershot VOVER Output voltage overshot VRIPPLE(TotOUT) Total output ripple VRIPPLE(COUT) Output voltage ripple due to output capacitance VRIPPLE(CIN) Input voltage ripple due to input capacitance VRIPPLE(CinESR) Input voltage ripple due to the ESR of input capacitance Pswcond High-side MOSFET conduction loss Iswrms RMS current in the high-side MOSFET Rdson(sw) ON drain-source resistance of the high-side MOSFET Pswsw High-side MOSFET switching loss Ipk Peak current through the high-side MOSFET Rdrv Driver resistance of the high-side MOSFET Qgdsw Gate to drain charge of the high-side MOSFET Qgssw Gate to source charge of the high-side MOSFET Vgsw Gate drive voltage of the high-side MOSFET Pswgate Gate drive loss of the high-side MOSFET Qgsw Gate charge of the high-side MOSFET Pswtot Total losses of the high-side MOSFET Psrcond Low-side MOSFET conduction loss Isrrms RMS current in the low-side MOSFET Rdson(sr) ON drain-source resistance of the low-side MOSFET Psrgate Gate drive loss of the low-side MOSFET Qgsr Gate charge of the low-side MOSFET Vgsr Gate drive voltage of the low-side MOSFET Pdiode Power loss in the diode td Dead time between the conduction of high- and low-side MOSFET Vf Forward voltage drop of the body diode of the low-side MOSFET Psrtot Total losses of the low-side MOSFET DCR Inductor DC resistance Ac The gain of the current sensing amplifier, typically 13 ROUT Output load resistance Vramp Ramp amplitude, typically 0.5 V T Switching period Gvc(s) Control to output transfer function Gc(s) Compensator transfer function Tv(s) Loop gain transfer function Acm Gain of the compensator fp The pole frequency of the compensator fz The zero frequency of the compensator 62 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 TPS40140 www.ti.com SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015 12.2 Documentation Support 12.2.1 Related Documentation These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, including design software, may also be found at www.power.ti.com 1. Under The Hood of Low Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series 2. Understanding Buck Power Stages in Switchmode Power Supplies (SLVA057) March 1999 3. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series 4. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series 5. Additional PowerPAD information may be found in Applications Briefs (SLMA002) and (SLMA004) 6. QFN/SON PCB Attachment, Texas Instruments (SLUA271), June 2002 12.3 Trademarks PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS40140 63 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS40140RHHR NRND VQFN RHH 36 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40140 TPS40140RHHRG4 NRND VQFN RHH 36 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40140 TPS40140RHHT NRND VQFN RHH 36 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40140 TPS40140RHHTG4 NRND VQFN RHH 36 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40140 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of