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TPS40190
SLUS658D – JULY 2005 – REVISED JUNE 2019
TPS40190 4.5-V to 15-V Input, Voltage-Mode, Synchronous Buck Controller
1 Features
3 Description
•
•
•
•
The TPS40190 is a cost-optimized synchronous buck
controller that operates from 4.5 V to 15 V nominally,
and implements a fixed frequency voltage mode
power supply. The controller uses an adaptive anticross conduction scheme to prevent both the highside and the rectifier MOSFET to be turned on at the
same time, preventing shoot through current in the
two MOSFETs.
1
•
•
•
•
•
•
•
•
•
Input Operating Voltage Range: 4.5 V to 15 V
Reference 0.591 V ±1%
Voltage Mode Control
Internal 5-V Regulator For Internal Housekeeping,
Driver Power and Light External Loads
Selectable Short-Circuit Protection Thresholds
Pre-Bias Ouput Safe
Fixed Switching Frequency of 300 kHz
Internal Soft Start
Small 3 mm × 3 mm, 10-Pin SON Package
Bootstrapped Drivers for N-Channel MOSFET
Adaptive Anti-Cross Conduction
Internal Bootstrap Diode
1.2-A Drivers for Decreased Switching Loss
2 Applications
•
•
•
•
The controller also provides a short circuit protection
threshold that is user selectable between one of three
values. The protection level is set with a single
external resistor connected from COMP to GND.
During start-up, the impedance connected to COMP
is sensed, and the information is decoded to select
one of the three thresholds. When the controller
senses an output short circuit, both MOSFETs are
turned off and a timeout period is observed before
attempting to restart. This provides limited power
dissipation in the event of a sustained fault.
The TPS40190 provides strong drivers to minimize
switching losses in the power stage, reducing heat
build up in the MOSFETs and allowing larger
MOSFETs to be used without undue switching time
penalty.
Cable modem CPE
Digital Set Top Box
Graphics/Audio Cards
Entry-level and Mid-Range Servers
Device Information(1)
PART NUMBER
TPS40190
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
VDD
TPS40190
1 ENABLE HDRV 10
SHUTDOWN
2 FB
SW 9
3 COMP
BOOT 8
4 VDD
LDRV 7
5 GND
BP5 6
VOUT
UDG−05059
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40190
SLUS658D – JULY 2005 – REVISED JUNE 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
5
7
Absolute Maximum Ratings ......................................
Dissipation Ratings ...................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
8
Application and Implementation ........................ 17
9
Device and Documentation Support.................. 20
8.1 Typical Applications ............................................... 17
9.1
9.2
9.3
9.4
9.5
9.6
Documentation Support .......................................... 20
Receiving Notification of Documentation Updates.. 20
Community Resources............................................ 20
Trademarks ............................................................. 20
Electrostatic Discharge Caution .............................. 20
Glossary .................................................................. 20
10 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2012) to Revision D
Page
•
Editorial changes only, no technical revisions........................................................................................................................ 1
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Deleted Ordering Information table ........................................................................................................................................ 3
Changes from Revision B (August 2007) to Revision C
•
2
Page
Added a new paragraph to the end of the Enable Functionality section.............................................................................. 14
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SLUS658D – JULY 2005 – REVISED JUNE 2019
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
DRC PACKAGE
(TOP VIEW)
GND
5
VDD COMP
4
3
FB ENABLE
2
1
TPS40190DRC
6
BP5
7
8
LDRV BOOT
9
10
SW
HDRV
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
ENABLE
I
Logic level input that starts or stops the controller from an external user command. A high level turns
the controller on. This pin has a high-impedance internal pull-up integrated into the device. Because
this pin is high impedance, a 10-nF capacitor to ground or an external pull-up resistor (100 kΩ) to VDD
is recommended to avoid noise coupling to this pin.
2
FB
I
Inverting input to the error amplifier
3
COMP
O
Output of the error amplifier. Connecting a resistance from COMP to GND sets the output short circuit
detection threshold. See applications information for details.
Power input to the controller
4
VDD
I
5
GND
—
Common connection for the controller
6
BP5
O
Output bypass for the internal regulator. Connect 4.7-μF capacitor from this pin to GND. Low power,
low noise loads may be connected here if desired. The sum of the external load and the gate drive
requirements must not exceed 40 mA. The regulator is turned off when the ENABLE pin is pulled low.
7
LDRV
O
Output to the rectifier FET gate
8
BOOT
I
Power supply for the flying high-side driver
9
SW
I
Sense line for the adaptive anti cross conduction circuitry. Serves as common connection for the flying
high side FET driver
10
HDRV
O
Bootstrapped output for driving the gate of the high side N channel FET.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD
–0.3
16.5
SW
UNIT
–5
22
BOOT-SW, HDRV-SW
(differential from BOOT or HDRV to SW)
–0.3
6
COMP
–0.3
3
FB, BP5, LDRV, ENABLE
–0.3
6
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–55
150
°C
Input voltage range
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Dissipation Ratings
(1)
(2)
PACKAGE
RθJA High-K Board (1)
(°C/W)
RθJC (2)
(°C/W)
DRC
47.9
14.1
The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), multilayer board with oneounce internal power and ground planes and two-ounce copper traces on top and bottom of the board.
The junction-to-case impedance is measured from the die to the thermal pad on the device package.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VDD
Input voltage
4.5
15
V
TA
Operating free-air temperature
–40
85
°C
4
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6.4 Electrical Characteristics
TA = –40°C to 85°C, VVDD= 12 Vdc, TA =TJ, and all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
VFB
TEST CONDITIONS
Feedback voltage range
MIN
TYP
MAX
0°C ≤ TJ ≤ 85°C
585
591
597
-40°C ≤ TJ ≤ 85°C
582
591
597
UNIT
mV
INPUT SUPPLY
VVDD
Input voltage range
IVDD
Operating current
4.5
15.0
V
VENABLE = 2.5 V, Outputs switching
2.5
mA
VENABLE = 0.6 V
20
μA
ON BOARD REGULATOR
V5VBP
Output voltage
VVDD > 6 V, I5VBP ≤ 10 mA
VDO
Regulator dropout voltage
VVDD - VBP5 , VVDD = 5 V, IBP5 ≤ 25 mA
ISC
Regulator current limit threshold
IBP5
Average current
5.1
5.3
5.5
V
270
400
mV
40
mA
(1)
40
OSCILLATOR
fSW
Switching frequency
VRMP
Ramp amplitude (2)
VVALLEY
Valley voltage
240
(2)
300
360
kHz
0.75
V
0.5
V
PWM
DMAX
tON(min)
tDEAD
Maximum duty cycle (2)
Minimum controlled pulse
85%
(2)
130
Output driver dead time
HDRV off to LDRV on
50
LDRV off to HDRV on
25
ns
ns
SOFT-START
tSS
Soft-start time
tSSDLY
Soft-start delay time (3)
tREG
Time to regulation
3.0
4.7
7.0
ms
6
ms
10.5
ms
ERROR AMPLIFIER
GBWP
Gain bandwidth product (2)
AOL
DC gain (2)
IIB
Input bias current (current out of FB pin)
IEAOP
Output source current
VFB = 0 V
1
mA
IEAOM
Output sink current
VFB = 2 V
1
mA
5
MHz
60
dB
100
0
nA
SHORT CIRCUIT PROTECTION
tPSS(min)
Minimum pulse during short circuit (2)
tBLNK
Blanking time (2)
tOFF
Off-time between restart attempts
VILIM
Short circuit comparator threshold voltage
(1)
(2)
(3)
250
100
140
180
25
95
RCOMP(GND) = OPEN, TJ = 25°C
256
320
384
RCOMP(GND) = 4 kΩ, TJ = 25°C
128
160
192
RCOMP(GND) = 12 kΩ, TJ = 25°C
368
460
552
ns
ns
ms
mV
40 mA is the current available for MOSFET gate drive, the device itself and any external loads. The sum of these must not exceed
40 mA.
Specified by design. Not production tested.
The delay time is the time delay from application of power to the device or from assertion of ENABLE until the output begins to rise.
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Electrical Characteristics (continued)
TA = –40°C to 85°C, VVDD= 12 Vdc, TA =TJ, and all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVERS
RHDHI
High-side driver pull-up resistance
VBOOT - VSW = 4.5 V, IHDRV = -100 mA
3
6
Ω
RHDLO
High-side driver pull-down resistance
VBOOT - VSW = 4.5 V, IHDRV = 100 mA
1.5
3
Ω
RLDHI
Low-side driver pull-up resistance
ILDRV = -100 mA
2.5
5
Ω
RLDLO
Low-side driver pull-down resistance
ILDRV = 100 mA
0.8
1.5
Ω
tHRISE
High-side driver rise time (2)
CLOAD = 1 nF
15
35
ns
tHFALL
High-side driver fall time (2)
CLOAD = 1 nF
10
25
ns
tLRISE
Low-side driver rise time
(2)
CLOAD = 1 nF
15
35
ns
tLFALL
Low-side driver fall time (2)
CLOAD = 1 nF
10
25
ns
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO
Turn-on voltage
UVLOHYST Hysteresis
4.1
4.25
4.4
V
270
320
370
mV
2.8
V
SHUTDOWN
VIH
High-level input voltage
ENABLE
VIL
Low-level input votlage
ENABLE
0.6
IBOOT = 5 mA
0.6
V
BOOT DIODE
VDFWD
6
Bootstrap diode forward voltage
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0.8
1.2
V
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6.5 Typical Characteristics
591.02
592.0
VVDD = 12 V
TJ = 25°C
591.00
VVREF − Voltage Reference − V
VVREF − Voltage Reference − V
591.5
591.0
590.5
590.0
589.5
590.98
590.96
590.94
590.92
590.90
590.88
4.5
589.0
−50
−25
0
25
50
75
100
6.0
7.5
125
9.0
10.5
12.0
13.5
15.0
VVDD − Input Voltage − V
TJ − Junction Temperature − °C
Figure 2. Reference Voltage vs Input Voltage
Figure 1. Reference Voltage vs Temperature
293
306
TJ = 25°C
304
292
fOSC − Oscillator Frequency − kHz
fOSC − Oscillator Frequency − kHz
VVDD = 12 V
302
300
298
296
294
292
290
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
288
287
6.0
7.5
9.0 10.5 12.0
VVDD − Input Voltage − V
13.5
15.0
16
VVDD = 12 V
VENABLE < 0.6 V
14
IVDD − Operating Current − µA
IVDD − Operating Current − µA
289
Figure 4. Oscillator Frequency vs Input Voltage
18
16
290
286
4.5
125
Figure 3. Oscillator Frequency vs Temperature
291
14
12
10
8
6
12
10
8
6
4
2
4
2
−50
VENABLE < 0.6 V
TJ = 25°C
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
VVDD − Input Voltage − V
Figure 5. Operating Current vs Temperature
Figure 6. Operating Current vs Input Voltage
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Typical Characteristics (continued)
1.840
VVDD = 12 V
TJ = 25°C
2.0
1.5
1.0
0.5
0
−50
1.836
VIH − Enable Threshold On − V
VIH − Enable Threshold On − V
2.5
−25
0
25
50
75
100
1.832
1.828
1.824
1.820
4.5
125
TJ − Junction Temperature − °C
Figure 7. Enable Threshold On vs Temperature
6.0
7.5
9.0 10.5 12.0
VVDD − Input Voltage − V
13.5
15.0
Figure 8. Enable Threshold On vs Input Voltage
1.4
1.20
VVDD = 12 V
TJ = 25°C
1.2
VIL − Enable Threshold Off − V
VIL − Enable Threshold Off − V
1.18
1.0
0.8
0.6
0.4
0.2
0
−50
−25
0
25
50
75
100
1.16
1.14
1.12
1.10
4.5
125
6.0
TJ − Junction Temperature − °C
7.5
9.0
10.5
12.0
13.5
15.0
VVDD − Input Voltage − V
Figure 9. Enable Threshold Off vs Temperature
Figure 10. Enable Threshold Off vs Input Voltage
11.6
7.0
VVDD = 12 V
VVDD = 12 V
11.4
6.5
Soft−Start Delay TIme
11.2
t − Time − ms
t − Time − ms
6.0
5.5
5.0
4.5
10.8
10.6
10.4
Soft−Start TIme
4.0
−50
11.0
−25
0
10.2
25
50
75
100
125
−50
Figure 11. Soft Start Timing vs Temperature
8
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 12. Total Startup Time vs Temperature
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Typical Characteristics (continued)
4.705
VILIM − Current Limit Threshold Voltage − mV
250
TJ = 25°C
4.700
tSS − Soft−Start Time − ms
4.695
4.690
4.685
4.680
4.675
4.670
4.665
4.660
4.655
4.5
6.0
7.5
9.0 10.5 12.0
VVDD − Input Voltage − V
13.5
TJ = 25°C
RCOMP = 4 kΩ
160.8
160.6
160.4
160.2
160.0
159.8
159.6
6.0
7.5
9.0
10.5
12.0
13.5
150
100
50
0
−50
−25
75
100
125
VVDD = 12 V
RCOMP = 12 kΩ
500
400
300
200
100
0
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
Figure 16. Current Limit Threshold vs Temperature
450
VILIM − Current Limit Threshold Voltage − mV
ViLIM − Current Limit Threshold Voltage − mV
50
600
15.0
470
TJ = 25°C
RCOMP = 12 kΩ
469
468
467
466
465
464
463
4.5
25
Figure 14. Current Limit Threshold vs Temperature
VVDD − Input Voltage − V
Figure 15. Current Limit Threshold vs Input Voltage
0
TJ − Junction Temperature − °C
VILIM − Current Limit Threshold Voltage − mV
VILIM − Current Limit Threshold Voltage − mV
161.2
159.4
4.5
200
15.0
Figure 13. Soft Start Timing vs Input Voltage
161.0
VVDD = 12 V
RCOMP = 4 kΩ
6.0
7.5
9.0 10.5 12.0
VVDD − Input Voltage − V
13.5
400
VVDD = 12 V
RCOMP = OPEN
350
300
250
200
150
100
50
0
−50
15.0
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
Figure 17. Current Limit Threshold vs Input Voltage
Figure 18. Current Limit Threshold vs Temperature
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Typical Characteristics (continued)
4.238
320.5
TJ = 25°C
RCOMP = OPEN
4.236
320.0
VUVLO − Turn−On Voltage − V
VILIM − Current Limit Threshold Voltage − mV
321.0
319.5
319.0
318.5
318.0
4.232
4.230
4.228
4.226
317.5
317.0
4.5
4.234
6.0
7.5
9.0
10.5
12.0
13.5
15.0
4.224
−50
VVDD − Input Voltage − V
Figure 19. Current Limit Threshold vs Input Voltage
10
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
Figure 20. Undervoltage Lockout Turn On Voltage
vs Temperature
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7 Detailed Description
7.1 Overview
The TPS40190 is a cost optimized controller providing all the necessary features to construct a high-performance
DC-DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about
damaging sensitive loads during start-up. Strong gate drivers for the high side and rectifier N-channel MOSFETs
decrease switching losses for increased efficiency. Adaptive gate drive timing minimizes body diode conduction
in the rectifier MOSFET, also increasing efficiency. Selectable short circuit protection thresholds and hiccup
recovery from a short-circuit increase design flexibility and minimize power dissipation in the event of a prolonged
output fault. A dedicated enable pin (ENABLE) allows the converter to be placed in a very low quiescent current
shutdown mode.
Internally fixed switching frequency and soft-start time reduce external component count, simplifying design and
layout, as well as reducing footprint and cost. The 3-mm × 3-mm package size also contributes to a reduced
overall converter footprint.
7.2 Functional Block Diagram
VDD
SC
1.5 MΩ
OC
+
CLK
ENABLE 1
FAULT
Fault
Controller
Soft−Start
Ramp
Generator
SD
UVLO
SC
SS
Threshold Latch
4.25 V
+
5−V
Regulator
VDD 4
BP5 6
CLK
FAULT
UVLO
Oscillator
+
Error Amplifier
FB 2
10 HDRV
5V
GND 5
SS
+
+
8 BOOT
5V
UVLO
PWM Logic
and
Anti−Cross
Conduction
9 SW
5V
PWM
Comparator
7 LDRV
SC Threshold Latch
591 mV
Short Circuit
Threshold
Selector
SC: 160 mV, 320 mV
or 460 mV below VDD
COMP 3
TPS40190
UDG−05060
7.3 Feature Description
7.3.1 Internally Fixed Parameters
The TPS40190 has a fixed internal switching frequency of 300 kHz. Soft-start time is fixed at 4.7 ms typical and
the UVLO level is set between 4.1 V and 4.4 V.
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Feature Description (continued)
7.3.2 Output Short Circuit Protection
The short circuit detection in the TPS40190 is done by sensing the voltage drop across the high side FET when
it is on. If the voltage drop across this FET exceeds the selected threshold in any given switching cycle, a
counter counts up one count and the FET is turned off early. If the voltage drop across that FET does not exceed
this threshold, the counter is decremented for that cycle and the FET is allowed to remain on for the normal
pulse width commanded by the internal pulse width modulator. If the counter fills up (a count of 7) a fault
condition is declared and the drivers turn both FETs off. After a timeout of approximately 95 ms, the controller
attempts to restart. If a short circuit is still present at the output, the current ramps quickly up to the short-circuit
threshold and another fault condition is declared. The device then waits 95 ms to attempt to restart again.
Typical waveforms during a short circuit event are shown in Figure 21 and Figure 22.
VSW (10 V/ div)
VOUT
(100 mV/ div)
VOUT
(1 V/ div)
T − Time − 10 µs / div
IOUT
(10 A/ div)
IOUT (10 A/ div)
T − Time − 10 µs / div
T − Time − 20 ms / div
Figure 21. Output Short Circuit Detected
(Nominal Threshold 25 A)
Figure 22. Output Fault Hiccup Restart Timing
The TPS40190 provides three selectable short circuit protection thresholds: 160 mV, 320 mV and 460 mV. The
particular threshold is selected by connecting a resistor from COMP to GND. Table 1 gives the short circuit
thresholds for corresponding resistors from COMP to GND. Note that since the TPS40190 measures the
resistance from COMP to GND during a 2-ms window, the compensation network from COMP to FB should have
a time constant significantly less than 1 ms or there can be issues detecting the resistance and setting the
correct short circuit threshold. This network should have no DC path from COMP to FB.
The short circuit detection threshold in the TPS40190 has some temperature compensation built in to help offset
the high-side FET rise in resistance as its temperature rises. A typical FET has a resistance temperature
coefficient of about 4500 ppm/°C. The temperature coefficient of the short circuit threshold is approximately
4200 ppm/°C. Figure 23 shows how the short circuit threshold increases with temperature to help compensate for
the FET resistance increase. The relative FET resistance change is based on an estimate of a linear
4500 ppm/°C temperature coefficient. The effectiveness of this compensation depends on how tight the thermal
coupling between the TPS40190 and the high-side FET is. Better thermal coupling between the TPS40190 and
the high-side FET gives better compensation effectiveness.
12
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Feature Description (continued)
1.3
FET
Resistance
Relative Change
1.2
1.1
1.0
Short Circuit
Threshold
Voltage
0.9
0.8
0.7
−50
−25
0
25
50
75
TJ − Junction Temperature − °C
100
Figure 23. Relative Short Circuit Threshold Change vs Temperature
Table 1. Short Circuit Threshold Voltage Selection
SHORT CIRCUIT PROTECTION
RESISTANCE, RCOMP (kΩ)
NOMINAL CURRENT LIMIT
VOLTAGE, VILIM (mV)
10.8 to 13.2
460
OPEN
320
3.6 to 4.4
160
The range of short circuit current thresholds that can be expected is given by Equation 1 and Equation 2.
V ILIM(max)
I SCP(max) +
RDS(onMIN)
I SCP(min) +
(1)
VILIM(min)
RDS(onMAX)
where
•
•
•
ISCP is the short circuit current
VILIM is the short circuit threshold
RDS(on) is the channel resistance of the high-side MOSFET
(2)
7.3.3 Enable Functionality
The TPS40190 has a dedicated ENABLE pin. This simplifies user level interface design since no multiplexed
functions exist. Another benefit is a true low power shutdown mode of operation. In this state, the BP5 regulator
is turned off. When the ENABLE pin is pulled to GND, the TPS40190 consumes a typical 20-μA of current. A
functionally equivalent circuit to the enable circuitry on the TPS40190 is shown in Figure 24.
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VDD
4
200 kΩ
1.5 MΩ
1 kΩ
ENABLE
1
To
Enable
Chip
200 Ω
1 kΩ
300 kΩ
GND
5
UDG−05061
Figure 24. TPS40190 ENABLE Pin Internal Circuitry
If the ENABLE pin is left floating, the chip starts automatically. The pin must be pulled to less than 600 mV to
ensure that the TPS40190 is in shutdown mode. Note that the ENABLE pin is relatively high impedance. In some
situations, there could be enough noise nearby to cause the ENABLE pin to swing below the 600 mV threshold
and give erroneous shutdown commands to the rest of the device. There are two solutions to this problem should
it arise.
1. Place a capacitor from ENABLE to GND. A side effect of this is to delay the start of the converter while the
capacitor charges past the enable threshold
2. Place a resistor from VDD to ENABLE. This causes more current to flow in the shutdown mode, but does not
delay converter startup. If a resistor is used, the total current into the ENABLE pin should be limited to no
more than 500 μA.
The ENABLE pin is self-clamping. The clamp voltage can be as low as 1 V with a 1-kΩ ground impedance. Due
to this self-clamping feature, the pull-up impedance on the ENABLE pin should be selected to limit the sink
current to less than 500 μA. Driving the ENABLE pin with a low-impedance source voltage can result in damage
to the device. Because of the self-clamping feature, it requires care when connecting multiple ENABLE pins
together. For enabling multiple TPS4019x devices (TPS40190, TPS40192, TPS40193, TPS40195, TPS40197),
see the Application Report SLVA509.
Typical waveforms for startup and shutdown using the ENABLE pin are shown in Figure 25 and Figure 26.
14
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VENABLE (10 V/ div)
VENABLE
(5 V/ div)
VLDRV (10 V/ div)
VCOMP
(500 mV/ div)
VSW (10 V/ div)
VOUT
(500 mV/ div)
VOUT
(500 mV/ div)
T − Time − 2 ms / div
T − Time − 20 µs / div
Figure 25. Startup Using ENABLE Pin
Figure 26. Shutdown Using ENABLE Pin
7.3.4 5-V Regulator
The TPS40190 has an on board 5-V regulator that allows the part to operate from a single voltage feed. No
separate 5-V feed to the part is required. This regulator needs to have 4.7-μF of capacitance on the BP5 pin for
stability. A ceramic capacitor is suggested for this purpose.
This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in
some cases. If this pin is used for external loads, keep in mind that this is the power supply for the internals of
the TPS40190. While efforts have been made to reduce sensitivity, any noise induced on this line has an
adverse effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or
skewed reference voltage. This regulator is turned off when the ENABLE pin is pulled low.
The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must
operate. Larger MOSFETs require more gate drive current and reduces the amount of power available on this pin
for other tasks.
The total amount of current required by the gate drive and the external circuitry should not exceed 40 mA. The
current required to drive the FET gates can be found from Equation 3.
I G + f SW
ǒQG (high) ) QG (low)Ǔ
Where
•
•
•
•
IG is the required gate drive current
f SW is the switching frequency (300 kHz)
QG(high) is the gate charge requirement for the high-side FET at 5 V VGS
QG(low) is the gate charge requirement for the low-side FET at 5 V VGS
(3)
7.3.5 Startup Sequence and Timing
The TPS40190 startup sequence is as follows. After input power is applied, the 5-V onboard regulator comes up.
Once this regulator comes up, the TPS40190 goes through a period where it samples the impedance at the
COMP pin and decides the short circuit protection threshold voltage. This is accomplished by placing 400 mV on
the COMP pin for approximately 2 ms. During this time, the current is measured and compared against internal
thresholds to select the short circuit protection threshold. After this, the COMP pin is brought low for 4 ms. This
ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the
converter when the converter is allowed to start switching. After these initial 6 milliseconds, the internal soft-start
circuitry is engaged and the converter is allowed to start. See Figure 27.
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7.3.6 Prebias Outputs
Some applications require that the converter not sink current during start-up if a pre-existing voltage is higher
than the output. Because synchronous buck converters inherently sink current some method of overcoming this
characteristic must be employed. Applications that require this operation are typically power rails for a multi
supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn
on until there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage.
This is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Because this
controller uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage
is commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current
only during the startup sequence.
If the pre-existing voltage is higher than the intended regulation point for the output of the converter, the
converter starts and sinks current when the soft-start time has completed. A typical pre-biased start-up is shown
in Figure 28.
VIN
(10 V/ div)
VOUT
1 V/div
VOUT
(500 mV/ div)
VLDRV
(5 V/div)
VCOMP
(500 mV/ div)
T − Time − 2 ms / div
t − TIme − 1 ms/div
Figure 27. TPS40190 Start-up Timing
16
Figure 28. Prebiased Start-up Timing
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Typical Applications
110 Ω
12 V
120 µF
10 kΩ
4.7 nF
TPS40190
Si4874BDY
On/Off
82 nF
634 Ω
1
ENABLE HDRV 10
2
FB
SW
3
COMP
BOOT 8
4
VDD
LDRV 7
5 V, 10 A
47 µF TDK C3225X5R0J476M
2
22 µF TDK C3225X5R1C226M
1
1
1
4.7 µF
1 µF
1
VOUT
100 nF
Si4874BDY
1.33 kΩ
2
2 µH,
COEV DXM1306 2R0
9
10 nF
820 pF
2
5
GND
BP5 6
UDG−05072
Figure 29. 12-V to 5-V at 10 A
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Typical Applications (continued)
12 V
137 Ω
120 µF
10 kΩ
3.3 nF
TPS40190
2
Si7344DP
1
ENABLE
2
FB
1.4 µH,
Pulse PG0077.142
Off
12 nF
2.49 kΩ
SW
9
VOUT
100 nF
10 nF
3
COMP
BOOT 8
4
VDD
LDRV 7
1.2 V, 20 A
Si7868ADP
180 pF
2
HDRV 10
1
1
1
4.7 µF
9.76 kΩ
12.1 kΩ 1 µF
1
100 µF TDK C3225X5R0J107M
2
22 µF TDK C3225X5R1C226M
5
GND
BP5 6
UDG−05073
Figure 30. 12-V to 1.2-V at 20 A
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+
Typical Applications (continued)
Figure 31. PMP1285, 12-V to 1.5-V, at 3.7 A
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
• TI Application Report, Enabling Multiple TPS4019x Devices, SLVA509
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40190DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
0190
TPS40190DRCRG4
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
0190
TPS40190DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
0190
TPS40190DRCTG4
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
0190
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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