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TPS40200
SLUS659G – FEBRUARY 2006 – REVISED NOVEMBER 2014
TPS40200 Wide Input Range Non-Synchronous Voltage Mode Controller
1 Features
3 Description
•
•
•
•
•
•
The TPS40200 is a flexible, non-synchronous
controller with a built-in 200-mA driver for P-channel
FETs. The circuit operates with inputs up to 52 V with
a power-saving feature that turns off driver current
once the external FET has been fully turned on. This
feature extends the flexibility of the device, allowing it
to operate with an input voltage up to 52 V without
dissipating excessive power. The circuit operates with
voltage-mode feedback and has feed-forward input
voltage compensation that responds instantly to input
voltage change. The integral 700-mV reference is
trimmed to 2%, providing the means to accurately
control low voltages. The TPS40200 is available in an
8-pin SOIC and an 8-pin VSON package and
supports many of the features of more complex
controllers.
Clock
frequency,
soft-start,
and
overcurrent limits are each easily programmed by a
single, external component. The part has
undervoltage lockout, and can be easily synchronized
to other controllers or a system clock to satisfy
sequencing and/or noise-reduction requirements.
1
•
•
•
•
•
•
Input Voltage Range 4.5 V to 52 V
Output Voltage (700 mV to 90% VIN)
200-mA Internal P-channel FET Driver
Voltage Feed-Forward Compensation
Undervoltage Lockout
Programmable Fixed-Frequency (between 35 kHz
and 500 kHz) Operation
Programmable Short-Circuit Protection
Hiccup Overcurrent Fault Recovery
Programmable Closed-Loop Soft-Start
700 mV 1% Reference Voltage
External Synchronization
Small 8-Pin SOIC (D) and VSON (DRB) Packages
2 Applications
•
•
•
•
•
Industrial Control
Distributed Power Systems
DSL/Cable Modems
Scanners
Telecom
Device Information(1)
PART NUMBER
TPS40200
PACKAGE
BODY SIZE (NOM)
VSON (8)
3.00 mm x 3.00 mm
SOIC (8)
4.90 mm x 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Efficiency vs Output Current
VIN
100
VOUT = 5 V
90
2 SS
ISNS 7
3 COMP GDRV 6
4 FB
Efficiency (%)
TPS40200
VDD 8
1 RC
VOUT
GND 5
80
70
VIN (V)
16
12
8
60
50
0
0.5
1.0
1.5
2.0
2.5
Load Current (A)
UDG-11201
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40200
SLUS659G – FEBRUARY 2006 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 19
9 Power Supply Recommendations...................... 37
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 38
11 Device and Documentation Support ................. 39
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
Changes from Revision F (September 2014) to Revision G
•
2
Page
Changed Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
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5 Pin Configuration and Functions
8 PINS
VSON (DRB) PACKAGE
(BOTTOM VIEW)
RC
1
8
8 PINS
SOIC (D) PACKAGE
(TOP VIEW)
SS COMP FB
2
7
3
6
RC
1
8
VDD
SS
2
7
ISNS
COMP
3
6
GDRV
FB
4
5
GND
4
5
VDD ISNS GDRV GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COMP
3
O
Error amplifier output. Connect control loop compensation network from COMP to FB.
FB
4
I
Error amplifier inverting input. Connect feedback resistor network center tap to this pin.
GND
5
GDRV
6
O
Driver output for external P-channel MOSFET
ISNS
7
I
Current-sense comparator input. Connect a current sense resistor between ISNS and VDD in order to set
desired overcurrent threshold.
RC
1
I
Switching frequency setting RC network. Connect a capacitor from the RC pin to the GND pin and connect a
resistor from the VDD pin to the RC pin. The device may be synchronized to an external clock by connecting
an open drain output to this pin and pulling it to GND. For mor info on pulse width for synchronization,
please refer to the Synchronizing the Oscillator section.
SS
2
I
Soft-start programming pin. Connect capacitor from SS to GND to program soft start time. Pulling this pin
below 150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also
functions as a restart timer for overcurrent events.
VDD
8
I
System input voltage. Connect local bypass capacitor from VDD to GND.
Device ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage range
Output voltage range
TJ
(1)
MIN
MAX
VDD , ISNS
–0.3
52
RC, FB
–0.3
5.5
SS
–0.3
9.0
COMP
–0.3
9.0
GDRV
VIN –10
VIN
–40
125
Operating Junction Temperature
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
UNIT
V
V
°C
260
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
MAX
UNIT
–55
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–1500
1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–1500
1500
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Input voltage
4.5
52
V
TJ
Operating temperature range
–40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
D
DRB
SOIC
VSON
(8 PINS)
(8 PINS)
RθJA
Junction-to-ambient thermal resistance
109.6
44.2
RθJC(top)
Junction-to-case (top) thermal resistance
54.0
53.6
RθJB
Junction-to-board thermal resistance
49.6
19.8
ψJT
Junction-to-top characterization parameter
11.2
1.1
ψJB
Junction-to-board characterization parameter
49.1
19.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
7.9
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
–40°C < TA = TJ < 85°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE
COMP = FB, TA = 25°C
VFB
Feedback voltage
4.5 < VDD < 52
689
696
702
TA = 25°C
686
696
703
–40°C < TA < 85°C
679
696
708
–40°C < TA < 125°C
679
696
710
125
300
200
300
6
8
10
V
1.5
3.0
mA
4.25
4.5
mV
GATE DRIVER
Isrc
Gate driver pull-up current
Isnk
Gate driver pull-down current
VGATE
Gate driver output voltage
VGATE = (VDD – VGDRV), for 12 < VDD < 52
mA
mA
QUIESCENT CURRENT
Iqq
Device quiescent current
f OSC = 300 kHz, Driver not switching, 4.5 < VDD < 52
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO(on)
Turn-on threshold
VUVLO(off)
Turn-off threshold
VUVLO(HYST)
Hysteresis
–40°C < TA < 125°C
3.8
4.05
110
200
275
65
105
170
V
mV
SOFT-START
RSS(chg)
Internal soft-start pull-up
resistance
RSS(dchg)
Internal soft-start pull-down
resistance
190
305
485
VSSRST
Soft-start reset threshold
100
150
200
0°C < TA < 125°C
65
100
140
–40°C < TA < 125°C
55
100
140
100
150
200
kΩ
mV
OVERCURRENT PROTECTION
VILIM
Overcurrent threshold
OCDF
Overcurrent duty cycle (1)
VILIM(rst)
Overcurrent reset threshold
4.5 < VDD < 52
mV
2%
mV
OSCILLATOR
Oscillator frequency range (1)
fOSC
Oscillator frequency
Frequency line regulation
VRMP
(1)
Ramp amplitude
35
500
RRC = 200 kΩ, CRC = 470 pF
85
100
115
RRC = 68.1 kΩ, CRC = 470 pF
255
300
345
12 V < VDD < 52 V
-9%
4.5 V < VDD < 12 V
–20%
4.5 V < VDD < 52 V
kHz
0%
0%
VDD÷10
V
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
–40°C < TA = TJ < 85°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD = 12 V
200
400
VDD = 30 V
100
200
UNIT
PULSE WIDTH MODULATOR
tMIN
Minimum controllable pulse
width (2)
DMAX
Maximum duty cycle
KPWM
Modulator and power stage
DC gain
fosc = 100 kHz, CL = 470 pF
93%
95%
fosc = 300 kHz, CL = 470 pF
90%
93%
8
10
12
100
250
ns
V/V
ERROR AMPLIFIER
IIB
Input bias current
AOL
Open loop gain (1)
60
(1)
nA
80
dB
MHz
GBWP
Unity gain bandwidth
1.5
3
ICOMP(src)
Output source current
VFB = 0.6 V, COMP = 1 V
100
250
μA
ICOMP(snk)
Output sink current
VFB = 1.2 V, COMP = 1 V
1.0
2.5
mA
(2)
6
See Figure 21 for for tMIN vs fOSC at various input voltages.
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6.6 Typical Characteristics
3
1.66
1.65
2.5
1.64
2
1.62
IDD - mA
IDD - mA
1.63
1.61
1.6
1.5
1
1.59
1.58
VDD = 12 V
0.5
1.57
0
1.56
-50
-25
0
25
50
75
100
5
125
10
15
20
Temp - °C
4.3
156
4.25
155.5
155
154.5
154
VDD = 12 V
153.5
-50
-25
30 35
VDD - V
40
45
50
55
Figure 2. Quiescent Current vs Input Voltage
156.5
UVLO Turn On - V
Reset Threshold - mV
Figure 1. Quiescent Current vs Temperature
25
Turn On
4.2
4.15
4.1
Turn Off
4.05
4
0
25
50
75
100
-50
125
-25
0
Temp - °C
25
50
Temp - °C
75
100
125
Figure 4. UVLO Turn-On and Turn-Off vs Temperature
Figure 3. Soft-Start Threshold vs Temperature
103
98
96
102.5
VDD = 4.5 V
102
R = 202 kW
C = 470 pF
92
ILIM threshold - mV
Frequency (kHz)
94
90
88
VDD = 12 V
86
84
80
-50
-25
0
25
50
75
100
101
VDD = 12 V
100.5
100
VDD = 52 V
82
101.5
125
99.5
-50
Temp (°C)
-25
0
25
50
75
100
125
Temp - °C
Figure 5. Oscillator Frequency vs Temperature
Figure 6. Current Limit Threshold vs Temperature
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Typical Characteristics (continued)
275
21.00
R = 68.1 kW
C = 470 pF
TJ = 25°C
270
Oscillator Frequency (kHz)
265
TJ = 25°C
20.50
260
Gain - dB
255
250
245
20.00
240
235
19.50
230
225
220
19.00
5
10
15
20
25
30 35
VDD (V)
40
45
50
55
5
10
Figure 7. Oscillator Frequency vs VDD
15
20
25
30 35
VDD - V
40
45
50
55
Figure 8. Power Stage Gain vs VDD
20.50
20.50
20.30
20.45
VDD = 24 V
VDD = 4.5 V
20.40
VDD = 12 V
19.90
Gain - dB
Gain - dB
20.10
19.70
20.35
VDD = 52 V
20.30
19.50
20.25
-50
-25
0
25
50
75
100
125
-50
-25
0
Temp - °C
Figure 9. Power Stage Gain vs Temperature
2.6
VDD = 24 V
Vramp - V
Vramp - V
2.2
2
1.8
1.6
VDD = 12 V
1.2
1
-50
-25
0
25
50
75
100
125
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
100
125
VDD = 52 V
VDD = 36 V
-50
Temp - °C
-25
0
25
50
75
100
125
Temp - °C
Figure 11. Modulator Ramp Amplitude vs Temperature
8
75
Figure 10. Power Stage Gain vs Temperature
2.8
1.4
50
Temp °C
3
2.4
25
Figure 12. Modulator Ramp Amplitude vs Temperature
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Typical Characteristics (continued)
160
6
TJ = 25°C
140
5
120
4
IIB - nA
VRAMP - V
100
3
80
60
2
40
1
20
0
0
5
10
15
20
25
30
35
VDD - V
40
45
50
55
-50
0
25
75
100
125
Figure 14. Feedback Amplifier Input Bias Current vs
Temperature
3.5
300
3
250
2.5
Output Current - mA
200
150
100
2
1.5
1
50
0.5
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temp - °C
50
75
100
125
Temp - °C
Figure 15. Comp Source Current vs Temperature
Figure 16. Comp Sink Current vs Temperature
8.4
8
VDD = 12 V
7.8
VJ = 25°C
8.2
7.6
VGATE - V
50
Temp - °C
Figure 13. Modulator Ramp Amplitude vs VDD
Output Current - mA
-25
8
7.4
7.8
7.2
7.6
7
7.4
6.8
7.2
6.6
7
6.4
Temp - °C
30 35
VDD - V
Figure 17. Gate Drive Voltage vs Temperature
Figure 18. Gate Drive Voltage vs VIN
-50
-25
0
25
50
75
100
125
5
10
15
20
25
40
45
50
55
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720
720
718
718
716
716
714
714
712
VFB - mV
VFB - mV
Typical Characteristics (continued)
VDD = 24 V
710
708
706
712
710
VDD = 4.5 V
708
706
VDD = 50 V
704
704
702
702
700
VDD = 12 V
700
-50
-25
0
25
50
75
100
125
-50
-25
Temp - °C
Figure 19. Reference Voltage vs Temperature
50
75
100
125
Figure 20. Reference Voltage vs Temperature
100
600
95
Maximum Duty Cycle (%)
VDD = 4.5 V
500
Pulse Width - ns
25
Temp - °C
700
400
300
VDD = 24 V
VDD = 12 V
200
100 VDD = 36 V
100
85
80
75
fOSC (kHz)
500
200
100
50
70
60
0
0
90
65
VDD = 52 V
200
300
400
500
0
10
20
30
40
50
Input Voltage (V)
Frequency - kHz
Figure 21. Minimum Controllable Pulse Width vs Frequency
10
0
Figure 22. Maximum Duty Cycle vs Input Voltage
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7 Detailed Description
7.1 Overview
The TPS40200 is a non-synchronous controller with a built in 200-mA driver designed to drive high speed Pchannel FETs up to 500 kHz. Small size combined with complete functionality makes the part both versatile and
easy to use.
The controller uses a low-value current-sensing resistor in series with the input voltage and the power FETs
source connection to detect switching current. When the voltage drop across this resistor exceeds 100 mV, the
part enters an hiccup fault mode at about 2% of the operating frequency.
The device uses voltage feedback to an error amplifier that is biased by a precision 700-mV reference. Feedforward compensation from the input keeps the PWM gain constant over the full input voltage range, eliminating
the need to change frequency compensation for different input voltages.
The TPS40200 also incorporates a soft-start feature where the output follows a slowly rising soft-start voltage,
preventing output-voltage overshoot.
7.2 Functional Block Diagram
TPS40200
COMP
3
FB
4
SS
E/A and SS
Reference
2
+ 700 mV
Soft-Start
and
Overcurrent
ISNS
Enable E/A
7
+
PWM
Logic
1
VDD
6
GDRV
5
GND
GDRV voltage swing
limited to (VIN–8V)
Driver
RC
8
OSC
UVLO
UDG-05069
7.3 Feature Description
7.3.1 MOSFET Gate Drive
The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When
the driver pulls the gate charge of the FET it is controlling to 8 V, the drive current folds back to a low level so
that high-power dissipation only occurs during the turn-on period of the FET. This feature is particularly valuable
when turning on a FET at high input voltages where leaving the gate drive current on would otherwise cause
unacceptable power dissipation.
7.3.2 Undervoltage Lockout Protection
Undervoltage lockout (UVLO) protection ensures proper startup of the device only when the input voltage has
exceeded minimum operating voltage. Undervoltage protection incorporates hysteresis which eliminates hiccup
starting in cases where input supply impedance is high.
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Feature Description (continued)
TPS40200
545 kW
VDD
8
Run
+
+
200 kW
1.3 V
36 kW
GND
5
UDG-05082
Figure 23. Undervoltage Lockout
Undervoltage protection ensures proper startup of the device only when the input voltage has exceeded
minimum operating voltage. The UVLO level is measured at the VDD pin with respect to GND. Startup voltage is
typically 4.3 V with approximately 200 mV of hysteresis. The device shuts off at a nominal 4.1 V. As shown in
Figure 23, when the input VDD voltage rises to 4.3 V , the 1.3-V comparator’s threshold voltage is exceeded and
a RUN signal occurs. Feedback from the output closes the switch, and shunts the 200-kΩ resistor so that an
approximately 200 mV lower voltage, or 4.1 V, is required before the part shuts down.
7.3.3 Selecting the Operating Frequency
The operating frequency of the controller is determined by an external resistor RRC that is connected from the RC
pin to VDD and a capacitor attached from the RC pin to ground. This connection and the two oscillator
comparators inside the device, are shown in Figure 24. The oscillator frequency can be calculated in Equation 1.
1
f SW =
R RC ´ C RC ´ 0.105
(1)
where
fSW is the clock frequency
RRC is the timing resistor value in Ω
CRC is the timing capacitor value in F
RRC must be kept large enough that the current through it does not exceed 750 μA when the internal switch
(shown in Figure 24) is discharging the timing capacitor. This condition may be expressed by Equation 2.
VIN
£ 750 mA
R RC
(2)
7.3.4 Synchronizing the Oscillator
Figure 24 shows the functional diagram of the oscillator. When synchronizing the oscillator to an external clock,
the RC pin must be pulled below 150 mV for 20 ns or more. The external clock frequency must be higher than
the free running frequency of the converter as well. When synchronizing the controller, if the RC pin is held low
for an excessive amount of time, erratic operation may occur. The maximum amount of time that the RC pin
should be held low is 50% of a nominal output pulse, or 10% of the period of the synchronization frequency
whichever is less.
12
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Feature Description (continued)
Under circumstances where the input voltage is high and the duty cycle is less than 50%, a Schottky diode
connected from the RC pin to an external clock may be used to synchronize the oscillator. The cathode of the
diode is connected to the RC pin. The trip point of the oscillator is set by an internal voltage divider to be 1/10 of
the input voltage. The clock signal must have an amplitude higher than this trip point. When the clock goes low, it
allows the reset current to restart the RC ramp, synchronizing the oscillator to the external clock. This provides a
simple, single-component method for clock synchronization.
TPS40200
VDD
8
VIN
+
S
Q
R
Q
CLK
RRC
External Frequency
Synchronization
(optional)
RC
+
1
+
CRC
150 mV
GND
5
UDG-05070
Figure 24. Oscillator Functional Diagram
TPS40200
VDD
8
VIN
+
Amplitude >
VIN
10
Q
R
Q
CLK
RC
RRC
RC
+
1
Frequency > Controller Frequency
S
+
CRC
150 mV
GND
5
UDG-10076
Figure 25. Diode-Connected Synchronization
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Feature Description (continued)
7.3.5 Current Limit Resistor Selection
As shown in Figure 28, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a
low-inductance resistor to avoid ringing signals and nuisance tripping. When the FET is on and the controller
senses 100 mV or more drop from the VDD pin to the ISNS pin, an overcurrent condition is declared. When this
happens, the FET is turned off, and as shown in Figure 26, the soft-start capacitor is discharged. When the softstart capacitor reaches a level below 150 mV, the converter clears the overcurrent condition flag and attempts to
restart. If the condition that caused the overcurrent event to occur is still present on the output of the converter
(see Figure 27), another overcurrent condition is declared and the process repeats indefinitely. Figure 27 shows
the soft-start capacitor voltage during an extended output fault condition. The overall duty cycle of current
conduction during a persistent fault is approximately 2%.
VSS
TPS40200
100 mV
SS
+
Fault
S
7
R
2
+
Reset Fault
Q
Q
Latched
Fault
100 kW
300 mV
+
ISNS
8
+
VDD
300 kW
SS Reference
Error Amplifier
Enable
Error Amplifier
+
150 mV
GND
5
UDG-10077
Figure 26. Current Limit Reset
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Feature Description (continued)
Figure 27. Typical Soft-Start Capacitor and VOUT During Overcurrent
If necessary, a small RC filter can be added to the current sensing network to reduce nuisance tripping due to
noise pickup. This filter can also be used to trim the overcurrent trip point to a higher level with the addition of a
single resistor. See Figure 28. The nominal overcurrent trip point using the circuit of Figure 28 is described in
Equation 3.
V
R + R F2
IOC = ILIM ´ F1
R ILIM
R F2
(3)
Where
IOC is the overcurrent trip point, peak current in the inductor
VILIM is the overcurrent threshold voltage for the TPS40200, typically 100 mV
RILIM is the value of the current sense resistor in Ω
RF1 and RF2 are the values of the scaling resistors in Ω
The value of the capacitor is determined by the nominal pulse width of the converter and the values of the
scaling resistors RF1 and RF2. It is best not to have the time constant of the filter longer than the nominal pulse
width of the converter, otherwise a substantial increase in the overcurrent trip point occurs. Using this constraint,
the capacitor value may be bounded by Equation 4.
æ VOUT ö
ç
÷
VIN ´ fSW ø
è
CF £
(RF1 ´ RF2 )
(RF1 + RF2 )
(4)
Where
CF is the value of the current limit filter capacitor in F
VOUT is the output voltage of the converter
VIN is the input voltage to the converter
fSW is the converter switching frequency
RF1 and RF2 are the values of the scaling resistors in Ω
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Feature Description (continued)
VIN
VDD
8
CF
RF2
RILIM
RF1
ISNS
7
GDRV
6
TPS40200
UDG-05071
Figure 28. Current Limit Adjustment
NOTE
The current limit resistor and its associated circuitry can be eliminated and the ISNS pin
(pin 7) and the VDD pin (pin 8) are shorted. The result of this however, may result in
damage to the device or PC board during an overcurrent event.
16
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Feature Description (continued)
7.3.6 Calculating the Soft-Start Time
An external capacitor CSS, connected from the SS pin to ground, controls the soft-start interval. An internal
charging resistor connected to VDD produces a rising reference voltage which is connected though a 700-mV
offset to the reference input of the TPS40200 error amplifier. When the soft-start capacitor voltage (VCSS) is
below 150 mV, there is no switching activity. When VCSS rises above the 700 mV offset, the error amplifier starts
to follow VSST– 700 mV, and uses this rising voltage as a reference. When VCSS reaches 1.4 V, the internal
reference takes over, and further increases have no effect. An advantage of initiating a slow start in this fashion
is that the controller cannot overshoot because its output follows a scaled version of the controller reference
voltage. A conceptual drawing of the circuit that produces these results is shown in Figure 29. A consequence of
the 700 mV offset is that the controller does not start switching until VCSS has risen to 700 mV. The output
remains at 0 V during the resulting delay. When VCSS exceeds the 700 mV offset, the TPS40200 output follows
the soft-start time constant. Once above 1.4 V, the 700-mV internal reference takes over, and normal operation
begins.
TPS40200
VSST
2
700 mV
VSST(offset)
Ideal
Diodes
+
105 kW
SS
Error Amplifier
+
CSS
FB
+
700 mV
4
COMP
3
UDG-05083
Figure 29. Soft-Start Circuit
The slow-start time should be longer (slower) than the time constant of the output LC filter. This time constraint
may be expressed as described in Equation 5.
tS ³ 2p ´ LOUT ´ COUT
(5)
The calculation of the soft-start interval is simply the time it takes the RC network to exponentially charge from 0
V to 1.4 V. An internal 105 kΩ charging resistor is connected from the SS pin to VSST. For applications where the
voltage is above 8 V, an internal regulator clamps the maximum charging voltage to 8 V.
The result of this is a formula for the start-up time, as shown in Equation 6.
æ VSST ö
tSS = RC ´ CSS ´ ln ´ ç
÷
è VSST - 1.4 ø
(6)
Where
tSS is the required soft-start time in seconds
CSS is the soft-start capacitor value in F
Rc is the internal soft-start charging resistor (105 kΩ nominal)
VSST is the input voltage up to a maximum of 8 V
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Feature Description (continued)
7.3.7 Voltage Setting and Modulator Gain
Since the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide
range. Knowing that the reference voltage is 696 mV, choose a convenient value for R1 and then calculate the
value of R2 from Equation 7.
æ R2 ö
VOUT = 0.696 ´ ç 1 +
R1 ÷ø
è
(7)
Vg
L
VOUT
d
KPWM
COUT
RLOAD
VC
R2
+
VREF
R1
UDG-10220
Figure 30. System Gain Elements
The error amplifier has a DC open loop gain of at least 60 dB with a minimum of a 1.5-MHz gain bandwidth
product which gives the user flexibility with respect to the type of feedback compensation he uses for his
particular application. The gain selected by the user at the crossover frequency is set to provide an over all unity
gain for the system. The crossover frequency should be selected so that the error amplifier open-loop gain is
high with respect to the required closed-loop gain, ensuring that the amplifier response is determined by the
passive feedback elements.
7.4 Device Functional Modes
7.4.1 Operation Near Minimum Input Voltage
The TPS40200 is designed to operate with input voltages above 4.5 V. The typical VDD UVLO threshold is 4.25
V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. When VVDD passes the UVLO threshold the device will become active.
Switching is enabled and the soft start sequence is initiated. The TPS40200 will ramp up the output voltage at
the rate determined by the external capacitor at the soft-start pin.
7.4.2 Operation With SS Pin
The SS pin has a 150 mV threshold which can be used to disable the TPS40200. With SS forced below this
threshold voltage the device is disabled and switching is inhibited even if VVDD is above its UVLO threshold. If the
SS voltage is allowed to increase above the threshold while VVDD is above its UVLO threshold, the device
becomes active. Switching is enabled and the soft start sequence is initiated. The TPS40200 will ramp up the
output voltage at the rate determined by the external capacitor at the soft-start pin.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS40200 is a 4.5-V to 52-V buck controller with an integrated gate driver for a high-side p-channel
MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum
output current set by an external current sense resistor. In higher current applications, the maximum output
current can also be limited by the thermal performance of the external MOSFET and rectifying diode switch. Use
the following design procedure to select external components for the TPS40200. The design procedure illustrates
the design of a typical buck regulator with the TPS40200.
8.2 Typical Application
8.2.1 Buck Regulator, 8 V to 12 V Input, 3.3 V to 5.0 V at 2.5-A Output
The buck regulator design shown in Figure 31 shows the use of the TPS40200. It delivers 2.5 A at either 3.3 V or
5.0 V as selected by a single feedback resistor. It achieves approximately 90% efficiency at 3.3 V and 94% at 5.0
V. A discussion of design tradeoffs and methodology is included to serve as a guide to the successful design of
buck converters using the TPS40200.
The Bill of Materials for this application is given in Table 2. The efficiency and load regulation from boards built
from this design are shown in Figure 42 and Figure 43.
+
+
Notes
D3 : Do not populate. SOT 23 Common Cathode Dual Schottky
R6 =26.7k for 3.3 Vout, R6 = 16.2k for 5.0 Vout
Figure 31. 8 V to 16 VIN Step-Down Buck Converter
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Typical Application (continued)
8.2.1.1 Design Requirements
Table 1. Design Parameters
PARAMETER
VIN
TEST CONDITION
Input Voltage
VOUT
VOUT
MIN
NOM
MAX
8
12
16
V
(1)
V
3.4
UNIT
Output Voltage
IOUT = 2.5 A
3.2
3.3
Line Regulation
± 0.2 % VOUT
3.293
3.300
3.307
V
Load Regulation
± 0.2% VOUT
3.293
3.300
3.307
V
(1)
V
Output Voltage
IOUT at 2.5 A
4.85
5.0
Line Regulation
± 0.2% × VOUT
4.99
5.00
5.01
V
Load Regulation
± 0.2% × VOUT
4.99
5.00
5.01
V
VRIPPLE
Output ripple voltage
At maximum output current
60
mV
VOVER
Output overshoot
For 2.5 A load transient from 2.5 A to 0.25 A
100
mV
VUNDER
Output undershoot
For 2.5 A load transient from 0.25 A to 2.5 A
60
IOUT
Output Current
ISCP
Short circuit current trip point
0.125
3.75
Efficiency
FS
(1)
At nominal input voltage and maximum output
current
Switching frequency
5.150
mV
2.500
A
5.00
A
90%
300
kHz
Set point accuracy is dependent on external resistor tolerance and the device reference voltage. Line and Load regulation values are
referenced to the nominal design output voltage.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 FET Selection Criteria
•
•
•
The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that
can equal the input voltage. Since the RDS(on) of the FET rises with breakdown voltage, select a FET with as
low a breakdown voltage as possible. In this case, a 30-V FET was selected.
The selection of a power FET size requires knowing both the switching losses and DC losses in the
application. AC losses are all frequency dependent and directly related to device capacitances and device
size. On the other hand, DC losses are inversely related to device size. The result is an optimum where the
two types of losses are equal. Since device size is proportional to RDS(on), begin by selecting a device with an
RDS(on) that results in a small loss of power relative to package thermal capability and overall efficiency
objectives.
In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss
budget of 0.916 W. Total FET losses must be small relative to this number.
The DC conduction loss in the FET is given by: PDC = Irms2 × RDS(on)
The RMS current is given by:
1
IRMS
æ
æ
(DIP-P )2
= ç D ´ ç IOUT 2 +
çç
ç
12
è
è
öö2
÷÷
÷ ÷÷
øø
(8)
Where
t
DIP-P = DV ´ D ´ S
LI
ΔV = VIN – VOUT –(DCR + RDS(on)) × IOUT
RDS(on) is the FET on-state resistance
DCR is the inductor DC resistance
D is the duty cycle
tS = the reciprocal of the switching frequency
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Using the values in this example, the DC power loss is 129 mW. The remaining FET losses are as follows:
• PSW is the power dissipated while switching the FET on and off
• PGATE is the power dissipated driving the FET gate capacitance
• PCOSS is the power switching the FET output capacitance
The total power dissipated by the FET is the sum of these contributions.
PFET = PSW + PGATE + PCOSS + PRDS(on)
(9)
The P-channel FET used in this application is a FDC654P with the following characteristics:
tRISE = 13 × 10–9
COSS = 83 × 10–12
tFALL = 6 × 10–9
QG = 9 nC
RDS(on) = 0.1 Ω
VGATE= 1.9 V
–9
QGS = 1.0 × 10–9
QGD = 1.2 × 10
Using these device characteristics and Equation 10:
æ
ö f
f
PSW = S ´ çç VIN ´ Ipk ´ t CHON ÷÷ + S VIN ´ Ipk ´ t CHOFF
2 è
ø 2
(
where tCH(on ) =
)
= 10 mW
(10)
QGD ´ RG
QGD ´ RG
and tCH(off ) =
are the switching times for the power FET.
VIN - VTH
VIN
spacer
PGATE = QG × VGATE × fS = 22 mW
(11)
2
PCROSS =
COSS ´ VIN _ MAX ´ fS
2
= 2 mW
(12)
The gate current, IG = QG × fS = 2.7 mA
The sum of the switching losses is 34 mW, and is comparable to the 129-mW DC losses. At added expense, a
slightly larger FET is better because the DC loss drops and the AC losses increase, with both moving toward the
optimum point of equal losses.
8.2.1.2.2 Rectifier Selection Criteria
1. Rectifier Breakdown Voltage
The rectifier has to withstand the maximum input voltage which in this case is 16 V. To allow for switching
transients which can approach the switching voltage a 30-V rectifier was selected.
2. Diode Size
The importance of power losses from the Schottky rectifier D2 is determined by the duty cycle. For a low
duty cycle application, the rectifier is conducting most of the time, and the current that flows through it times
its forward drop can be the largest component of loss in the entire controller. In this application, the duty
cycle ranges from 20% to 40%, which in the worst case means that the diode is conducting 80% of the time.
Where efficiency is of paramount importance, choose a diode with a minimum of forward drop. In more cost
sensitive applications, size may be reduced to the point of the thermal limitations of the diode package.
The device in this application is large relative to the current required by the application. In a more cost
sensitive application, a smaller diode in a less-expensive package will provide a less-efficient but appropriate
solution
The device used has the following characteristics:
• Vf = 0.3 V at 3 A
• Ct = 300 pF (Ct = the effective reverse voltage capacitance of the synchronous rectifier, D2).
The two components of the losses from the diode D2 are:
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I
æ
PCON = Vf ´ ç IOUT + RIPPLE
4
è
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ö
÷ ´ (1 - D) = 653 mW
ø
(13)
Where
D = the duty cycle
IRIPPLE is the ripple current
IOUT is the output current
VF is the forward voltage
PCOND is the conduction power loss
The switching capacitance of this diode adds an AC loss, given by:
1
2
PSW = éC ´ (VIN + Vf ) ´ f ù = 6.8 mW
ê
ë
ûú
2
(14)
This additional loss raises the total loss to: 660 mW.
At an output voltage of 3.3 V, the application runs at a nominal duty cycle of 27%, and the diode is conducting
72.5% of the time. As the output voltage is moved up to 5 V, the on-time increases to 46% and the diode is
conducting only 54% of the time during each clock cycle. This change in duty cycle proportionately reduces the
conduction power losses in the diode. This reduction may be expressed as
æ 0.54 ö
660 ç
÷ = 491 mW
è0.725ø
for a savings in power of 660 – 491 = 169 mW.
To illustrate the relevance of this power savings we measured the full load module Efficiency for this application
at 3.3 V and 5 V. The 5-V output efficiency is 92% vs. 89% for the 3.3 V design. This difference in efficiency
represents a 456 mW reduction in losses between the two conditions. This 169 mW power-loss reduction in the
rectifier represents 37% of the difference.
8.2.1.2.3
Inductor Selection Criteria
The P-channel FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use
of smaller, less-expensive inductors as illustrated in this 300 kHz application. Ferrite, with its good high frequency
properties, is the material of choice. Several manufacturers provide catalogs with inductor saturation currents,
inductance values, and LSRs (internal resistance) for their various-sized ferrites.
In this application, the device must deliver a maximum current of 2.5 A. This requires that the output inductor’s
saturation current be above 2.5 A plus ½ the ripple current caused during inductor switching. The value of the
inductor determines this ripple current. A low value of inductance has a higher ripple current that contributes to
ripple voltage across the resistance of the output capacitors. The advantages of a low inductance are a higher
transient response, lower DCR, a higher saturation current, and a smaller, less expensive part. Too low an
inductor however, leads to higher peak currents which ultimately are bounded by the overcurrent limit set to
protect the output FET or by output ripple voltage. Fortunately, with low ESR Ceramic capacitors on the output,
the resulting ripple voltage for relatively high ripple currents can be small.
For example, a single 1-μF, 1206 size, 6.3-V, ceramic capacitor has an internal resistance of 2 Ω at 1 MHz. For
this 2.5-A application, a 10% ripple current of 0.25 A produces a 50-mV ripple voltage. This ripple voltage may be
further reduced by additional parallel capacitors.
The other bound on inductance is the minimum current at which the controller enters discontinuous conduction.
At this point, Inductor current is zero. The minimum output current for this application is specified at 0.125 A. This
average current is 1/2 the peak current that must develop during a minimum on time. The conditions for minimum
on time are high line and low load.
Using:
LMIN =
VIN - VOUT
´ t on = 32 mH
IPEAK
(15)
Where
VIN = 16 V
VOUT = 3.3 V
IPEAK = 0.25 A
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tON = 0.686 μs
tON is given by
3. 3 V
1
´
300 kHz 16 V
spacer
The inductor used in the circuit is the closest standard value of 33 μH. This is the minimum inductance that can
be used in the converter to deliver the minimum current while maintaining continuous conduction.
8.2.1.2.4 Output Capacitance
In order to satisfy the output voltage over and under shoot specifications there must be enough output
capacitance to keep the output voltage within the specified voltage limits during load current steps.
In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output
capacitor must absorb energy stored in the output inductor. This condition may be described by realizing that the
energy in the stored in the inductor must be suddenly absorbed by the output capacitance. This energy
relationship is written as:
1
1
2
2
2
´ L OIO £ ´ C O VOS - VO
2
2
(16)
[ (
)]
Where
VOS is the allowed over-shoot voltage above the output voltage
LO is the inductance
IO is the output current
CO is the output capacitance
VO is the output voltage
In this application, the worst case load step is 2.25 A and the allowed overshoot is 100 mV. With a 33 μH output
inductor, this implies an output capacitance of 249 μF for a 3.3 V output and 165 μF for a 5 V output..
When the load increases from minimum to full load the output capacitor must deliver current to the load. The
worst case is for a minimum on time that occurs at 16 V in and 3.3 VOUT and minimum load. This corresponds to
an off time of (1 – 0.2 ) times the period 3.3 μs and is the worst case time before the inductor can start supplying
current. This situation may be represented by:
t
DVO < DIO ´ OFFMAX
CO
(17)
Where
ΔVO is the undershoot specification of 60 mV
ΔIO is the load current step
tOFF(max) is the maximum off time
This condition produces a requirement of 100 μF for the output capacitance. The larger of these two
requirements becomes the minimum value of output capacitance.
The ripple current develops a voltage across the ESR of the output capacitance, so another requirement on this
component is it ESR be small relative to the ripple voltage specification.
8.2.1.2.5 Switching Frequency
The TPS40200 has a built-in, 8-V, 200-mA, P-channel FET driver output that facilitates using P-channel
switching FETs A clock frequency of 300 kHz is chosen as a switching frequency that represents a compromise
between a high-frequency that allows the use of smaller capacitors and inductors but one that is not so high as
to cause excessive transistor switching losses. As previously discussed, an optimum frequency can be selected
by picking a value where the DC and switching losses are equal.
The frequency is set by using the design formula given in the FET Selection Criteria section.
1
RRC ´ CRC =
0.105 ´ fSW
(18)
Where
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RRC is the timing resistor value in Ω
RRC = 68.1 kΩ
CRC is the timing capacitor value in F
C5 = 470 pF
fSW is the desired switching frequency in Hz
fSW = 297 kHz.
At a worst case of 16 V, the timing resistor draws about 250 μA which is well below the 750 μA maximum which
the circuit can pull down.
8.2.1.2.6
Calculating the Overcurrent Threshold Level
The current limit in the TSP40200 is triggered by a comparator with a 100-mV offset whose inputs are connected
across a current-sense resistor between VIN and the source of the high-side switching FET. When current in this
resistor develops more than 100 mV, the comparator trips and terminates the output gate drive.
In this application, the current-limit resistor is set by the peak output stage current which consists of the
maximum load current plus ½ the ripple current. In this case, we have 2.5 + 0.125 = 2.625 A. To accommodate
tolerances a 25% margin is added giving a 3.25 A peak current. Using the equation below then yields a value for
RILIM of 0.03 Ω.
Current sensing in a switching environment requires attention to both circuit board traces and noise pick up. In
the design shown a small RC filter has been added to the circuit to prevent switching noise from tripping the
current sense comparator. The requirements of this filter are board-dependent, but with the layout used in this
application, no unreasonable overcurrent is observed.
VIN
TPS40200
VDD
8
CF
RF2
RF1
ISNS
7
GDRV
6
RILIM
IILIM =
0.1
RILIM
UDG-11200
Figure 32. Overcurrent Trip Circuit for RF2 Open
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8.2.1.2.7 Soft-Start Capacitor
The soft-start interval is given (in pF) by the following equation:
t SS
C SS =
´ 10 3
æ VSST ö
÷
R ´ ln çç
÷
è VSST - 1.4 ø
(19)
Where
R is an internal 105-kΩ charging resistor
VIN is the input voltage up to 8 V where the charging voltage is internally clamped to 8 V maximum
VOS = 700 mV, and because the input voltage is 12 V, VSST = 8 V.
The oscilloscope picture below shows the expected delay at the output (middle trace) until the soft-start node
(bottom trace) reaches 700 mV. At this point, the output rises following the exponential rise of the soft-start
capacitor voltage until the soft-start capacitor reaches 1.4 V and the internal 700-mV reference takes over. This
total time is approximately 1 ms, which agrees with the calculated value of 0.95 ms where the soft-start
capacitance is 0.047 μF.
A.
Channel 1 is the output voltage (VOUT) rising to 3.3 V
B.
Channel 2 is the soft start pin (SS)
Figure 33. Soft-Start Showing Output Delay and Controlled Rise to Programmed Output Voltage
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8.2.1.2.8 Frequency Compensation
The four elements that determine the system overall response are discussed below The gain of the error
amplifier (KEA) is the first of there elements. Its output develops a control voltage which is the input to the PWM.
The TPS40200 has a unique modulator that scales the peak to peak amplitude of the PWM ramp to be 0.1 times
the value of the input voltage. Since modulator gain is given by VIN divided by VRAMP, the modulator gain is 10
and is constant at 10 (20 dB) over the entire specified input voltage range.
The last two elements that affect system gain are the transfer characteristic of the output LC filter and the
feedback network from the output to the input to the error amplifier.
These four elements maybe expressed by the following expression that represents the system transfer function
as shown in Figure 34.
TV (S ) = K FB ´ K EA (S)´ K PWM ´ X LC (S)
(20)
Where
KFB is the output voltage setting divider
KEA is the error amplifier feedback
KPWM is the modulator gain
XLC is the filter transfer function
vg
Vref
+
KEA
-
vc
KPWM
d
XLC
vo
Tv(s)
KFB
Figure 34. Control Loop
26
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Figure 35 shows the feedback network used in this application. This is a Type II compensation network which
gives a combination of good transient response and phase boost for good stability. This type of compensation
has a pole at the origin causing a –20dB/decade (–1) slope followed by a zero that causes a region of flat gain
followed by a final pole that returns the gain slope to –1. The bode plot in Figure 36 shows the effect of these
poles and zeros.
The procedure for setting up the compensation network is as follows:
1. Determine the break frequency of the output capacitor.
2. Select a zero frequency well below this break frequency.
3. From the gain bandwidth of the error amplifier select a crossover frequency where the amplifier gain is large
relative to expected closed loop gain
4. Select a second zero well above the crossover frequency, that returns the gain slope to a –1 slope.
5. Calculate the required gain for the amplifier at crossover.
Be prepared to iterate this procedure to optimize the pole and zero locations as needed.
The frequency response of this converter is largely determined by two poles that arise from the LC output filter
and a higher frequency zero caused by the ESR of the output capacitance. The poles from the output filter cause
a –40 dB/decade roll off with a phase shift approaching 180 degrees followed by the output capacitor zero that
reduced the roll off to –20 dB and gives a phase boost back toward 90 degrees. In other nomenclature, this is a
–2 slope followed by a –1 slope. The two zeros in the compensation network act to cancel the double pole from
the output filter The compensation network’s two poles produce a region where the error amplifier is flat and can
be set to a gain such that the overall gain of the system is zero dB. This region is set so that it brackets the
system crossover frequency.
C7
P1
Slope = –1
R10
Gain (dB)
C8
R8
Z1
P2
+
R6
VREF
f1
f2
Frequency
Figure 35. Error Amplifier Feedback Elements
Figure 36. Error Amplifier Bode Plot
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In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros.
8.2.1.2.8.1 Step 1
The break frequency of the output capacitor is given by:
1
fESR =
2p ´ RESR ´ COUT
(21)
Where
COUT = the output capacitor, 220 μF
RESR = the ESR of the capacitors
Because of the ESR of the output capacitor, the output LC filter has a single-pole response above the 1.8-kHz
break frequency of the output capacitor and its ESR. This simplifies compensation since the system becomes
essentially a single pole system.
8.2.1.2.8.2 Step 2
The first zero is place well below the 1.8-kHz break frequency of the output capacitor and its ESR. The phase
boost from this zero is shown in Figure 38.
1
fZ1 =
2p ´ R8 ´ C8
(22)
Where
R8 = 300 kΩ
C8 = 1500 pF
fZ1 = 354 Hz
8.2.1.2.8.3 Step 3
From its minimum gain bandwidth product of 1.5 MHz, and knowing it has a 20 dB/decade roll off, the open-loop
gain of the error amplifier is 33 dB at 35 kHz. This approximate frequency is chosen for a crossover frequency to
keep the amplifier gain contribution to the overall system gain small, as well as following the convention of
placing the crossover frequency between 1/6 to 1/10 the 300 kHz switching frequency.
8.2.1.2.8.4 Step 4
The second pole is placed well above the 35 kHz crossover frequency.
1
fP2 =
´ (C7 + C8 )
2p ´ C 7 ´ C 8 ´ R 8
(23)
Where
R8 = 300 kΩ
C7 = 10 pF
C8 = 1500 pF
fP2 = 53 kHz
28
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8.2.1.2.8.5 Step 5
Calculate the gain elements in the system to determine the gain required by the error amplifier to make the over
all gain 0 dB at 35 kHz.
The total gain around the voltage feedback loop is:
TV (S ) = K FB ´ K EA (S)´ K PWM ´ X LC (S)
(24)
Where
KFB is the output voltage setting divider
KEA is the error amplifier feedback
KPWM is the modulator gain
XLC is the filter transfer function
With reference to the graphic below, the output filter's transfer characteristic XLC (S) can be estimated by the
following:
RSW
VIN
L
D
Vsw
VOUT
1-D
RSR
COUT
RLOAD
Figure 37. Output Filter Analysis
X LC (S) =
Z OUT (S)
Z OUT (S) + Z L (S) + R SW ´ D + R SR ´ (1 - D)
(25)
Where
ZOUT is the parallel combination of output capacitor(s) and the load
RSW is the RDS(on) of the switching FET plus the current-sense resistor
RSR is the resistance of the synchronous rectifier
D is the duty cycle estimated as 3.3 / 12 = 0.27
To
•
•
•
•
evaluate XLC(S) at 35 kHz use the following:
ZOUT(s) at 35 kHz, which is dominated by the output capacitor's ESR; estimated to be 400 mΩ
ZL(s) at 35 kHz is 7.25 Ω
RSW = 0.95 mΩ, including the RLIM resistance
RSR = 100 mΩ
Using these numbers, XLC(S) = 0.04 or –27.9 dB.
The feedback network has a gain to the error amplifier given by:
R
K fb = 10
R6
(26)
Where
for 3.3 VOUT, R6 = 26.7 kΩ
Using the values in this application, Kfb = 11.4 dB.
The modulator has a gain of 10 that is flat to well beyond 35 kHz, so KPWM = 20 dB.
To achieve 0 db overall gain, the amplifier and feedback gain must be set to –7.9 dB (20 dB – 27.9dB).
The amplifier gain, including the feedback gain, Kfb, can be approximated by this expression:
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VOUT
(S ) =
VIN
www.ti.com
A VOL
R10 R10
1+
+
´ (1 + A VOL )
R 8 ZFS
(27)
Where
Zfs is the parallel combination of C7 in parallel with the sum of R8 and the impedance of C8.
AVOLis the open-loop gain of the error amplifier at 35 kHz, which is 44.6 dB or 33 dB.
Figure 38 shows the result of the compensation. The crossover frequency is 35 kHz and the phase margin is 45°.
The response of the system is dominated by the ESR of the output capacitor and is exploited to produce an
essentially single-pole system with simple compensation.
50
180
40
Gain
160
Phase
140
30
120
10
100
0
80
–10
60
–20
–30
40
–40
20
–50
0.1
Phase (°)
Gain (dB)
20
1
10
100
Crossover Frequency (kHz)
0
1000
Figure 38. Overall System Gain and Phase Response
Figure 38 also shows the phase boost that gives the system a crossover phase margin of 47°.
The bill of materials for this application is shown below. The efficiency and load regulation from boards built from
this design are shown in the following two figures. Gerber PCB layout files and additional application information
are available from the factory.
30
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Table 2. Bill of Materials, Buck Regulator, 12 V to 3.3 V and 5.0 V
REF. DES.
VALUE
DESCRIPTION
SIZE
MFR.
PART NUMBER
C1
100 μF
Capacitor, Aluminum, SM, 25V, 0.3 Ω
8 x 10 mm
Sanyo
20SVP100M
C12
220 μF
Capacitor, Aluminum, SM, 6.3V, 0.4 Ω
8 x 6.2 mm
Panasonic
EEVFC0J221P
C13
100 pF
Capacitor, Ceramic, 50V, [COG], [20%]
603
muRata
Std.
C3
0.1 pF
Capacitor, Ceramic, 50V, [X7R], [20%]
603
muRata
Std.
C2, C11
1 μF
Capacitor, Ceramic, 50V, [X7R], [20%]
603
muRata
Std.
C4, C5
470 pF
Capacitor, Ceramic, 50V, [X7R], [20%]
603
muRata
Std.
C6
0.047 μF
Capacitor, Ceramic, 50V, [X7R], [20%]
603
muRata
Std.
C7
10 pF
Capacitor, Ceramic, 50V, [COG], [20%]
603
muRata
Std.
C8
1500 pF
Capacitor, Ceramic, 50V, [X7R], [20%]
603
muRata
Std.
D1
12 V
Diode, Zener, 12-V, 350mW
SOT23
Diodes, Inc.
BZX84C12T
Diode, Schottky, 30A, 30V
SMC
On Semi
MBRS330T3
Diode Zener 12V 5mA
VMD2
Rohm
VDZT2R12B
J1,J3
Terminal Block 4-Pin 15A 5.1 mm
0.8 x 0.35
OST
ED2227
J2
Header, 2-pin, 100 mil spacing, (36-pin strip)
0.100 x 2
Sullins
PTC36SAAN
Inductor, SMT, 3.2A, .039 Ω
12.5 x 12.5 mm
TDK
SLF12575T330M3R2PF
PCB
2 Layer PCB 2 Ounce Cu
1.4 x 2.12 x 0.062
Q1
Trans, N-Chan Enhancement Switching, 50mA
SOT-143B
Phillips
BSS83
Q2
MOSFET, P-ch, 30V, 3.6A, 75mΩ
SuperSOT-6
Fairchild
FDC654P
U1
IC, Low Cost Non-Sync Buck Controller
SO-8
TI
TPS40200D
D2
D3
L1
12 V
33 μH
HPA164
R1
10 Ω
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R10
100 kΩ
Resistor, Chip, , 1/16W, 1%
603
Std.
Std.
R11
10 kΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R12
1 MΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R13
49.9 Ω
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R2
0.02 Ω
Resistor, Chip, ½ W, 5%
2010
Std.
Std.
R3
68.1 kΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R4
2.0 kΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R5
0Ω
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R6
26.7 kΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R7
1.0 kΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
R8
300 kΩ
Resistor, Chip, 1/16W, 1%
603
Std.
Std.
8.2.1.2.9 Printed Circuit Board Plots
The following figures Figure 39 through Figure 41 show the design of the TPS40200EVM-001 printed circuit
board. The design uses 2-layer, 2-oz copper and is 1.4” x 2.3” in size. All components are mounted on the top
side to allow the user to easily view, probe, and evaluate the TPS40200 control IC in a practical application.
Moving components to both sides of the printed circuit board (PCB) or using additional internal layers can offer
additional size reduction for space constrained applications.
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Figure 39. TPS40200EVM-001 Component Placement (Viewed from Top)
Figure 40. TPS40200EVM-001 Top Copper (Viewed from Top)
Figure 41. TPS40200EVM-001 Bottom Copper (X-Ray View from Top)
32
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8.2.1.3 Application Curves
100
100
VOUT = 5 V
VOUT = 3.3 V
90
Efficiency (%)
Efficiency (%)
90
80
70
80
70
VIN (V)
VIN (V)
16
12
8
60
16
12
8
60
50
50
0
0.5
1.0
1.5
2.0
2.5
0.5
0
1.5
1.0
2.0
2.5
Load Current (A)
Load Current (A)
Figure 42. Full-Load Efficiency at 5.0 VOUT
Figure 43. Full-Load Efficiency at 3.3 VOUT
8.2.2 18 V - 50 V Input, 16 V at 1-A Output
This is an example of using the TPS40200 in a higher voltage application. The output voltage is 16 V at 1 A with
an 18 V to 50 V input. Some of the test results are shown below.
+
+
Figure 44. Buck Converter. VIN = 18 V to 50 V; VOUT = 16 V @ 1 A
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8.2.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER
VIN
Input Voltage
VOUT
Output Voltage
IOUT
Output Current
ISCP
Short circuit current trip point
FS
Switching Frequency
MIN
NOM
MAX
18
50
16
1
2
200
UNIT
V
A
kHz
8.2.2.2 Detailed Design Procedures
Using the design parameters stated in Table 3, follow the detailed design procedures listed under Detailed
Design Procedure.
8.2.2.3 Application Curves
16.50
100
16.45
95
Output Voltage (V)
Efficiency (%)
16.40
90
85
80
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
16.25
1.0
16.10
0.0
34
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Load Current (A)
Load Current (A)
Figure 45. Efficiency vs. Load
VIN (V)
24
48
16.15
70
0.1
16.30
16.20
VIN (V)
24
48
75
16.35
Figure 46. 17604 Load Regulation, Two Input Voltage
Extremes
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8.2.3 Wide Input Voltage Led Constant Current Driver
This application uses the TPS40200 as a buck controller that drives a string of LED diodes. The feedback point
for this circuit is a sense resistor in series with this string. The low 0.7 V reference minimizes power wasted in
this resistor, and maintains the LED current at a value given by 0.7/RSENSE. As the input voltage is varied, the
duty cycle changes to maintain the LED current at a constant value so that the light intensity does not change
with large input voltage variations.
+
+
Figure 47. Wide-Input Voltage Range LED Driver
8.2.3.1 Design Requirements
Table 4. Design Parameters
PARAMETER
MIN
NOM
12
MAX
30
UNIT
VIN
Input Voltage
ILED
Output Voltage
ISCP
Short circuit current trip point
3.3
A
FS
Switching Frequency
300
kHz
0.25
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A
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8.2.3.2 Detailed Design Procedures
Using the design parameters stated in Table 4, follow the detailed design procedures listed under Detailed
Design Procedure.
8.2.3.3 Application Curve
100
Efficiency (%)
90
80
70
60
50
10
15
20
Input Voltage (V)
25
30
Figure 48. Efficiency vs Input Voltage
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9 Power Supply Recommendations
The TPS40200 is designed to operate from an input voltage supply range between 4.5 V and 52 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the buck power stage
controlled by the TPS40200, additional bulk capacitance may be required in addition to the ceramic-bypass
capacitors. An electrolytic capacitor with a value of 100 uF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Keep the AC current loops as short as possible. For the maximum effectiveness from C3, place it near the
VDD pin of the controller and design the input AC loop consisting of C1-RSENSE-Q1-D1 to be as short as
possible. Excessive high frequency noise on VDD during switching degrades overall regulation as the load
increases.
Keep the output loop A (D1-L1-C2) as small as possible. A larger loop can degrade the application output
noise performance.
Traces carrying large AC currents should NOT be connected through a ground plane. Instead, use PCB
traces on the top layer to conduct the AC current and use the ground plane as a noise shield. Split the ground
plane as necessary to keep noise away from the TPS40200 and noise sensitive areas such as feedback
resistors R6, and R10.
Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated
emissions.
For good output voltage regulation, Kelvin connections should be brought from the load to R6 and R10.
The trace from the R6-R10 junction to the TPS40200 should be short and kept away from any noise source
(such as the SW node).
The gate drive trace should be as close as possible to the power FET gate.
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10.2 Layout Example
R3
R1
Input
C5
C3
TPS40200
C6
1 RC
RSENSE
VDD 8
C4
Q1
R5
C1
L1
Output
ISNS 7
2 SS
R4
3 COMP
GDRV 6
C2
D1
C7
C8
Ground
4 FB
GND 5
R8
R9
C9
R6
R10
UDG-07045
R3
C5
TPS40200
C3
R1
VDD
C4
R5
SS
ISEN
COMP
GDRV
FB
GND
R4
RSENSE
High current
Power stage components
Switch node
R8
R6
Low current Control
Components
R9
R10
C1
Q1
L1
D1
C9
C7
RC
C8
C6
Input
Output
C2
Ground
Kelvin Ground
Kelvin Voltage Sense
Figure 49. PC Board Layout Recommendations
38
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Related Products
DEVICE NUMBER
TPS4007
TPS4009
TL5001
DESCRIPTION
Low Input Synchronous Buck Controller
Wide Input Range Controller
TPS40057
Wide input (8V to 40V) Synchronous Buck Controller
TPS40190
Low Pin Count Synchronous Buck Controller
TPS40192
TPS40193
– 4.5 V to 18 V Low Pin Count Synchronous Buck Controller
11.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
• Under the Hood of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series
• Understanding Buck Power Stages in Switchmode Power Supplies – SLVA057
• Design and Application Guide for High Speed MOSFET Gate Drive Circuits- SEM 1400 – 2001 Seminar
Series
• Designing Stable Control Loops - SEM 1400 – 2001 Seminar Series
• http://power.ti.com
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40200D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40200
TPS40200DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40200
TPS40200DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40200
TPS40200DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4200
TPS40200DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4200
TPS40200DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40200
TPS40200GDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40200
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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