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TPS40210, TPS40211
SLUS772G – MARCH 2008 – REVISED JUNE 2020
TPS4021x 4.5-V to 52-V Input Current Mode Boost Controller
1 Features
3 Description
•
The TPS40210 and TPS40211 are wide-input voltage
(4.5 V to 52 V), nonsynchronous boost controllers.
They are suitable for topologies which require a
grounded source N-channel FET including boost,
flyback, SEPIC, and various LED Driver applications.
The device features include programmable soft start,
overcurrent protection with automatic retry, and
programmable oscillator frequency. Current mode
control provides improved transient response and
simplified loop compensation. The main difference
between the two parts is the reference voltage to
which the error amplifier regulates the FB pin.
1
•
•
•
•
•
•
•
•
•
•
•
•
Functional Safety-Capable
– Documentation available to aid functional
safety system design
For boost, flyback, SEPIC, LED drive apps
Wide input operating voltage: 4.5 V to 52 V
Adjustable oscillator frequency
Fixed frequency current mode control
Internal slope compensation
Integrated low-side driver
Programmable closed-loop soft start
Overcurrent protection
External synchronization capable
Reference 700 mV (TPS40210), 260 mV
(TPS40211)
Low current disable function
Create a custom design using the TPS4021x with
the WEBENCH Power Designer
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS40210
HVSSOP (10)
3.05 mm x 4.98 mm
TPS40211
VSON (10)
3.10 mm x 3.10 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
LED lighting
Industrial control systems
Battery-powered systems
Simplified Schematic
VIN
TPS40210
1
RC
2
SS
3
VOUT
VDD 10
BP
9
DIS/EN
GDRV
8
4
COMP
ISNS
7
5
FB
GND
6
RSENSE
UDG-07110
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40210, TPS40211
SLUS772G – MARCH 2008 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
25
8
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 37
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 37
11 Device and Documentation Support ................. 40
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
41
41
41
41
12 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2015) to Revision G
•
Page
Added functional safety bullet to the Features ...................................................................................................................... 1
Changes from Revision E (October 2011) to Revision F
Page
•
Added Updated Land Pattern ................................................................................................................................................. 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision D (April 2010) to Revision E
Page
•
Changed the Revision date from D, April 2010 to E, October 2011 ...................................................................................... 1
•
Added Q1 and Q3 to Figure 36 by illustrator........................................................................................................................ 35
Changes from Revision C (October 2008) to Revision D
Page
•
Changed CISNS to CIFLT ......................................................................................................................................................... 21
•
Changed CISNS to CIFLT ......................................................................................................................................................... 21
•
Changed equations 22 and 23 ............................................................................................................................................. 22
•
Changed corrected equation 25 ........................................................................................................................................... 23
•
Added "R1 is the high side feedback resistor in Ω" and " fL is the desired loop crossover frequency, in Hz" ..................... 23
•
Changed paragraph with new input...................................................................................................................................... 23
•
Changed capacitor value from µF to F ................................................................................................................................. 23
•
Changed 0.2 with 0.1 in MIN col in Design Example Specifications table ........................................................................... 27
•
Deleted text from Peak efficiency row .................................................................................................................................. 27
•
Changed 10 V with 8 V in TOP conditions column ................................................................................................................ 27
•
Changed 42.8% to 42.9% in eq 32....................................................................................................................................... 28
2
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SLUS772G – MARCH 2008 – REVISED JUNE 2020
•
Added (VFD) and changed approximate duty cycle from 42.8% to 42.9% ........................................................................... 28
•
Changed equations 32, 34, 35, 36, 37, 38 and 39 ............................................................................................................... 28
•
Changed equations 47, 48, 49, 50, 51 and 53 ..................................................................................................................... 30
•
Changed equations 58, 60, 61, 62 ....................................................................................................................................... 31
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5 Pin Configuration and Functions
DGQ
10-Pin
Top View
DRC
10-Pin
Top View
RC
1
10
VDD
SS
2
9
BP
1
10
RC
1
SS
2
9
VDD
BP
DIS/EN
3
8
GDRV
DIS/EN
3
8
GDRV
COMP
4
7
ISNS
COMP
4
7
ISNS
FB
5
6
GND
FB
5
6
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BP
9
O
Regulator output pin. Connect a 1.0-μF bypass capacitor from this pin to GND.
COMP
4
O
Error amplifier output. Connect control loop compensation network between COMP pin and FB pin.
DIS/EN
3
I
Disable pin. Pulling this pin high places the part into a shutdown mode. Shutdown mode is characterized by
a very low quiescent current. While in shutdown mode, the functionality of all blocks is disabled and the BP
regulator is shut down. This pin has an internal 1 MΩ pulldown resistor to GND. Leaving this pin
unconnected enables the device.
FB
5
I
Error amplifier inverting input. Connect a voltage divider from the output to this pin to set output voltage.
Compensation network is connected between this pin and COMP.
GDRV
8
O
Connect the gate of the power N channel MOSFET to this pin.
GND
6
-
Device ground.
ISNS
7
I
Current sense pin. Connect an external current sensing resistor between this pin and GND. The voltage on
this pin is used to provide current feedback in the control loop and detect an overcurrent condition. An
overcurrent condition is declared when ISNS pin voltage exceeds the overcurrent threshold voltage, 150 mV
typical.
RC
1
I
Switching frequency setting pin. Connect a resistor from RC pin to VDD of the IC power supply and a
capacitor from RC to GND.
SS
2
I
Soft-start time programming pin. Connect capacitor from SS pin to GND to program converter soft-start time.
This pin also functions as a timeout timer when the power supply is in an overcurrent condition.
VDD
10
I
System input voltage. Connect a local bypass capacitor from this pin to GND. Depending on the amount of
required slope compensation, this pin can be connected to the converter output. See Application Information
section for additional details.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
Input voltage
Output voltage
MIN
MAX
VDD
–0.3
52
RC, SS, FB, DIS/EN
–0.3
10
ISNS
–0.3
8
COMP, BP, GDRV
–0.3
9
UNIT
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
VDD
Input voltage
4.5
52
UNIT
V
TJ
Operating Junction temperature
-40
125
°C
6.4 Thermal Information
TPS40210
THERMAL METRIC
(1)
TPS40211
HVSSOP
VSON
10 PINS
10 PINS
RθJA
Junction-to-ambient thermal resistance
67.2
47.2
RθJC(top)
Junction-to-case (top) thermal resistance
50.5
74.6
RθJB
Junction-to-board thermal resistance
41.0
22.2
ψJT
Junction-to-top characterization parameter
2.4
2.9
ψJB
Junction-to-board characterization parameter
40.7
22.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
15.6
8.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VDD= 12Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TPS40210 COMP = FB, 4.5 ≤ VDD ≤ 52 V, TJ = 25°C
693
700
707
TPS40211 COMP=FB, 4.5 ≤ VDD ≤ 52 V, TJ = 25°C
254
260
266
COMP = FB, 4.5 ≤ VDD ≤ 52 V, -40°C ≤ TJ ≤
TPS40210
125°C
686
700
714
COMP = FB, 4.5 ≤ VDD ≤ 52 V, -40°C ≤ TJ ≤
125°C
250
260
270
UNIT
VOLTAGE REFERENCE
Feedback voltage range
VFB
TPS40211
mV
INPUT SUPPLY
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VDD= 12Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
VDD
TEST CONDITIONS
MIN
TYP
MAX
52
V
4.5 ≤ VDD ≤ 52 V, no switching, VDIS < 0.8
1.5
2.5
mA
2.5 ≤ VDIS ≤ 7 V
10
20
μA
530
μA
Input voltage range
IDD
Operating current
4.5
VDD < VUVLO(on), VDIS < 0.8
UNIT
UNDERVOLTAGE LOCKOUT
VUVLO(on)
Turn on threshold voltage
4.00
4.25
4.50
V
VUVLO(hyst)
UVLO hysteresis
140
195
240
mV
OSCILLATOR
fOSC
VSLP
(1)
6
Oscillator frequency range (1)
35
Oscillator frequency
RRC = 182 kΩ, CRC = 330 pF
Frequency line regulation
4.5 ≤ VDD ≤ 52 V
260
1000
300
340
620
720
-20%
Slope compensation ramp
520
kHz
7%
mV
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VDD= 12Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
275
400
90
200
200
UNIT
PWM
VDD = 12 V (1)
tON(min)
Minimum pulse width
tOFF(min)
Minimum off time
170
VVLY
Valley voltage
1.2
V
700
mV
VDD = 30 V
ns
SOFT-START
VSS(ofst)
Offset voltage from SS pin to error
amplifier input
RSS(chg)
Soft-start charge resistance
320
430
600
RSS(dchg)
Soft-start discharge resistance
840
1200
1600
kΩ
ERROR AMPLIFIER
GBWP
Unity gain bandwidth product (1)
1.5
3.0
MHz
AOL
Open loop gain (1)
60
80
dB
IIB(FB)
Input bias current (current out of FB
pin)
ICOMP(src)
Output source current
VFB = 0.6 V, VCOMP = 1 V
100
250
μA
ICOMP(snk)
Output sink current
VFB = 1.2 V, VCOMP = 1 V
1.2
2.5
mA
4.5 ≤ VDD < 52 V, -40°C ≤ TJ ≤ 125°C
120
150
100
300
nA
OVERCURRENT PROTECTION
VISNS(oc)
Overcurrent detection threshold (at
ISNS pin)
DOC
Overcurrent duty cycle (1)
VSS(rst)
Overcurrent reset threshold voltage (at
SS pin)
TBLNK
Leading edge blanking (1)
180
mV
2%
100
150
350
75
mV
ns
CURRENT SENSE AMPLIFIER
ACS
Current sense amplifier gain
IB(ISNS)
Input bias current
4..2
5.6
7.2
V/V
1
3
μA
DRIVER
IGDRV(src)
Gate driver source current
VGDRV = 4 V, TJ = 25°C
375
400
IGDRV(snk)
Gate driver sink current
VGDRV = 4 V, TJ = 25°C
330
400
7
8
mA
LINEAR REGULATOR
VBP
Bypass voltage output
0 mA < IBP < 15 mA
9
V
1.3
V
DISABLE/ENABLE
VDIS(en)
Turn-on voltage
0.7
VDIS(hys)
Hysteresis voltage
25
130
220
mV
RDIS
DIS pin pulldown resistance
0.7
1.1
1.5
MΩ
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6.6 Typical Characteristics
68 pF
CT(pF)
33pF
470
220
100
68
33
fSW - Frequency - kHz
1000
800
100pF
600
220 pF
400
1200
1000
fSW - Frequency - kHz
1200
800
600
400
200
200
470 pF
0
100
0
0
200
300 400 500 600 700 800
RT - Timing Resistance - kW
0.2
900 1000
Figure 1. Frequency vs Timing Resistance
0.4
0.6
0.8
D - Duty Cycle
1.0
1.2
Figure 2. Switching Frequency vs Duty Cycle
1.4
6
52 V
4.5 V
5
1.0
12 V
0.8
0.6
0.4
VVDD
12 V
4.5 V
52 V
0.2
IVDD – Shutdown Current – mA
IVDD – Quiescent Current – mA
1.2
Figure 4. Shutdown Current vs Junction Temperature
0.5
0.4
0.2
0.0
-0.2
-0.4
4.5 V
12 V
VVDD
12 V
4.5 V
52 V
-0.8
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 5. Reference Voltage Change vs Junction
Temperature
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VFB – Reference Voltage Change – %
VFB – Reference Voltage Change – %
52 V
8
2
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
0.4
-0.6
3
1
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 3. Quiescent Current vs Junction Temperature
4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
0
10
20
30
40
VVDD – Input Voltage – V
50
60
Figure 6. Reference Voltage Change vs Input Voltage
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Typical Characteristics (continued)
155
4.30
VUVLO – Undervoltage Lockout Threshold – V
UVLO
4.20
VISNS(OC) – Overcurrent Threshold – mV
4.25
UVLO On
4.15
4.10
4.05
Figure 7. Undervoltage Lockout Threshold vs Junction
Temperature
153
4.5 V
7.5 V
12 V & 20 V
30 V
7.5 V
152
30 V
151
150
12 V & 20 V
149
148
147
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 8. Overcurrent Threshold vs Junction Temperature
5
155
154
fOSC – Switching Frequency Change – %
VISNS(OC) – Overcurrent Threshold – mV
154
UVLO Off
4.00
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
153
152
151
150
149
148
147
146
145
5
10
15
20
25
30 35
VVDD – Input Voltage – V
40
Figure 9. Overcurrent Threshold vs Input Voltage
4.5 V
4.5 V
1
12 V
0
-1
30 V
-2
VVDD (V)
4.5 V
12 V
30 V
-3
-4
Figure 10. Switching Frequency Change vs Junction
Temperature
RSS(DSCH) Discharge
1200
25
1000
23
24 V
12 V
21
19
VVDD (V)
36 V
17
2
1400
29
27
4
3
-5
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
45
RSS – Soft Start Charge/Discharge Resistance - kW
0
Slope Compensation Ratio (VVDD/VSLP)
4.5 V
VVDD
Off
On
12 V
24 V
36 V
4.5 V
15
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 11. Oscillator Amplitude vs Junction Temperature
800
600
400
200
RSS(CHG) Charge
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 12. Soft Start Charge/Discharge Resistance vs
Junction Temperature
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Typical Characteristics (continued)
180
ICOMP(SRC) – Compensation Source Current – mA
300
IIB(FB) – Feedback Bias Current – nA
160
140
120
100
80
60
40
20
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 13. FB Bias Current vs Junction Temperature
200
150
100
50
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 14. Compensation Source Current vs Junction
Temperature
5
300
4
250
VVLY – Valley Voltage Change – %
ICOMP(SNK) – Compensation Sink Current – mA
250
200
150
100
50
3
2
1
0
-1
-2
-3
-4
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 15. Compensation Sink Current vs Junction
Temperature
-5
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 16. Valley Voltage Change vs Junction Temperature
1.10
8.8
VDIS(EN) – DIS/EN Turn-On Threshold – mV
1.09
VBP – Regulator Voltage – V
8.6
1.08
ILOAD = 0 mA
8.4
1.07
1.06
8.2
1.05
8.0
7.8
1.06
1.03
ILOAD = 5 mA
1.02
7.6
1.01
7.4
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 17. Regulator Voltage vs Junction Temperature
10
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1.00
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 18. DIS/EN Turnon Threshold vs Junction
Temperature
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Typical Characteristics (continued)
ACS – Current Sense Amplifier Gain – V/V
7
6
5
4
3
2
1
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – ° C
Figure 19. Current Sense Amplifier Gain vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS4021x is a peak current-mode control low-side controller with a built in 400-mA gate driver designed to
drive n- channel MOSFETs at a fixed frequency. The frequency is adjustable from 35 kHz to 1000 kHz. Small
size combined with complete functionality makes the part both versatile and easy to use.
The controller uses a low-value current-sensing resistor in series with the power MOSFET's source connection to
detect switching current. When the voltage drop across this resistor exceeds 150 mV, the part enters an hiccup
fault mode with a time period set by the external soft-start capacitor.
The TPS40210 uses voltage feedback to an error amplifier that is biased by a precision 700-mV reference. The
TPS40211 has a lower 260-mV reference for higher efficiency in LED drive applications. Internal slope
compensation eliminates the characteristic sub-harmonic instability of peak current mode control with duty cycles
of 50% or greater.
The TPS4021x also incorporates a soft-start feature where the output follows a slowly rising soft-start voltage,
preventing output-voltage overshoot. The DIS/EN disables the TPS40210 putting it in a low quiescent current
shutdown mode.
7.2 Functional Block Diagram
DIS/EN
3
COMP
4
FB
5
10 VDD
+
+
SS
2
OC Fault
Soft Start
and
Overcurrent
E/A
SS Ref
700 mV
PWM
Logic
+
Oscillator
and
Slope
Compensation
1
9
BP
8
GDRV
6
GND
7
ISNS
Driver
Enable E/A
RC
LDO
Gain = 6
OC Fault
150 mV
UVLO
+
LEB
UDG-07107
12
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7.3 Feature Description
7.3.1 Soft Start
The soft-start feature of the TPS40210 and TPS40211 is a closed-loop soft start, meaning that the output voltage
follows a linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an
internal resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to
GND. The SS pin voltage (VSS) is level shifted down by approximately VSS(ofst) (approximately 700 mV) and sent
to one of the “+” (the “+” input with the lowest voltage dominates) inputs of the error amplifier. When this level
shifted voltage (VSSE) starts to rise at time t1 (see Figure 20), the output voltage the controller expects, rises as
well. Since VSSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of
zero volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage
less the drop across the diode (VIN - VD) and rises from there. The point at which the output voltage starts to rise
(t2) is the point where the VSSE ramp passes the point where it is commanding more output voltage than (VIN VD). This voltage level is labeled VSSE(1). The time required for the output voltage to ramp from a theoretical zero
to the final regulated value (from t1 to t3) is determined by the time it takes for the capacitor connected to the SS
pin (CSS) to rise through a 700-mV range, beginning at VSS(ofst) above GND.
TPS40210/11
VSS
RSS(chg)
700 mV REF
SS
VSS(ofst)+700 mV
RSS(dchg)
VSSE(1)
t0
+
+
2
VSSE
VSS(ofst)
Error Amplifier
t1
VIN - VD
VOUT
t2
t3
DIS
UVLO
OC Fault
FB
5
COMP
4
UDG-07121
Figure 20. SS Pin Voltage and Output Voltage
Figure 21. SS Pin Functional Circuit
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Feature Description (continued)
The required capacitance for a given soft-start time t3 – t1 in Figure 20 is calculated in Equation 1.
CSS =
tSS
æ
VBP - VSS(ofst)
RSS ´ ln ç
çV - V
SS(ofst) + VFB
è BP
(
ö
÷
÷
ø
)
where
•
•
•
•
•
•
tSS is the soft-start time, in seconds
RSS(chg) is the SS charging resistance in Ω, typically 500 kΩ
CSS is the value of the capacitor on the SS pin, in F
VBP is the value of the voltage on the BP pin, in V
VSS(ofst) is the approximate level shift from the SS pin to the error amplifier (~700 mV)
VFB is the error amplifier reference voltage, 700 mV typical
(1)
Note that tSS is the time it takes for the output voltage to rise from 0 V to the final output voltage. Also note the
tolerance on RSS(chg) given in the Electrical Characteristics. This contributes to some variability in the output
voltage rise time and margin must be applied to account for it in design.
Also take note of VBP. Its value varies depending on input conditions. For example, a converter operating from a
slowly rising input initializes VBP at a fairly low value and increases during the entire startup sequence. If the
controller has a voltage above 8 V at the input and the DIS pin is used to stop and then restart the converter, VBP
is approximately 8 V for the entire start-up sequence. The higher the voltage on BP, the shorter the start-up time
is and conversely, the lower the voltage on BP, the longer the start-up time is.
The soft-start time (tSS) must be chosen long enough so that the converter can start up without going into an
overcurrent state. Since the over current state is triggered by sensing the peak voltage on the ISNS pin, that
voltage must be kept below the overcurrent threshold voltage VISNS(oc). The voltage on the ISNS pin is a function
of the load current of the converter, the rate of rise of the output voltage and the output capacitance, and the
current sensing resistor. The total output current that must be supported by the converter is the sum of the
charging current required by the output capacitor and any external load that must be supplied during start-up.
This current must be less than the IOUT(oc) value used in Equation 15 or Equation 16 (depending on the operating
mode of the converter) to determine the current sense resistor value. In these equations, the actual input voltage
at the time that the controller reaches the final output voltage is the important input voltage to use in the
calculations. If the input voltage is slowly rising and is at less than the nominal input voltage when the start-up
time ends, the output current limit is less than IOUT(oc) at the nominal input voltage. The output capacitor charging
current must be reduced (decrease COUT or increase the tSS) or IOUT(oc) must be increased and a new value for
RISNS calculated.
IC(chg) =
COUT ´ VOUT
tSS
(2)
COUT ´ VOUT
(IOUT(oc) - IEXT)
tSS >
where
•
•
•
•
•
•
14
IC(chg) is the output capacitor charging current in A
COUT is the total output capacitance in F
VOUT is the output voltage in V
tSS is the soft-start time from Equation 1
IOUT(oc) is the desired over current trip point in A
IEXT is any external load current in A
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Feature Description (continued)
The capacitor on the SS pin (CSS) also plays a role in overcurrent functionality. It is used as the timer between
restart attempts. The SS pin is connected to GND through a resistor, RSS(dchg), whenever the controller senses an
overcurrent condition. Switching stops and nothing else happens until the SS pin discharges to the soft-start
reset threshold, VSS(rst). At this point, the SS pin capacitor is allowed to charge again through the charging
resistor RSS(chg), and the controller restarts from that point. The shortest time between restart attempts occurs
when the SS pin discharges from VSS(ofst) (approximately 700 mV) to VSS(rst) (150 mV) and then back to VSS(ofst)
and switching resumes. In actuality, this is a conservative estimate since switching does not resume until the
VSSE ramp rises to a point where it is commanding more output voltage than exists at the output of the controller.
This occurs at some SS pin voltage greater than VSS(ofst) and depends on the voltage that remains on the output
overvoltage the converter while switching has been halted. The fastest restart time can be calculated by using
Equation 4, Equation 5, and Equation 6.
æ VSS(ofst)
tDCHG = RSS(dchg) ´ CSS ´ ln ç
ç VSS(rst)
è
(
(
ö
÷
÷
ø
(4)
) ö÷
)÷ø
æ V -V
BP
SS(rst)
tCHG = RSS(chg) ´ CSS ´ ln ç
ç V -V
SS(ofst)
è BP
(5)
tRSTRT(min ) = tCHG + tDCHG
(6)
VBP
VSS
tRSTR(min)
VSS(ofst)
VSS(rst)
T - Time
Figure 22. Soft Start during Overcurrent
7.3.2 BP Regulator
The TPS40210 and TPS40211 have an on-board linear regulator that supplies power to the internal circuitry of
the controller, including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed
with a 1-μF capacitor. If the voltage at the VDD pin is less than 8 V, the voltage on the BP pin will also be less
and the gate drive voltage to the external FET is reduced from the nominal 8 V. This should be considered when
choosing a FET for the converter.
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Feature Description (continued)
Connecting external loads to this regulator can be done, but care must be taken to ensure that the thermal rating
of the device is observed since there is no thermal shutdown feature in this controller. Exceeding the thermal
ratings causes out of specification behavior and can lead to reduced reliability. The controller dissipates more
power when there is an external load on the BP pin and is tested for dropout voltage for up to 5-mA load. When
the controller is in the disabled state, the BP pin regulator also shuts off so loads connected there power down
as well. When the controller is disabled with the DIS/EN pin, this regulator is turned off.
The total power dissipation in the controller can be calculated as follows. The total power is the sum of PQ, PG,
and PE.
PQ = VVDD ´ IVDD(en)
(7)
PG = VVDD ´ Qg ´ fSW
(8)
PE = VVDD ´ IEXT
where
•
•
•
•
•
•
•
•
PQ is the quiescent power of the device in W
VDD is the VDD pin voltage in V
IDD(en) is the quiescent current of the controller when enabled but not switching in A
PG is the power dissipated by driving the gate of the FET in W
Qg is the total gate charge of the FET at the voltage on the BP pin in C
f SW is the switching frequency in Hz
PE is the dissipation caused be external loading of the BP pin in W
IEXT is the external load current in A
(9)
7.3.3 Shutdown (DIS/EN Pin)
The DIS/EN pin is an active high shutdown command for the controller. Pulling this pin above 1.2 V causes the
controller to completely shut down and enter a low current consumption state. In this state, the regulator
connected to the BP pin is turned off. There is an internal 1.1-MΩ pulldown resistor connected to this pin that
keeps the pin at GND level when left floating. If this function is not used in an application, it is best to connect
this pin to GND.
7.3.4 Minimum On-Time and Off-Time Considerations
The TPS40210 has a minimum off-time of approximately 200 ns and a minimum on-time of 300 ns. These two
constraints place limitations on the operating frequency that can be used for a given input-to-output conversion
ratio. See Figure 2 for the maximum frequency that can be used for a given duty cycle.
The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If the
converter is running in discontinuous conduction mode, the duty cycle varies with changes to the load much
more than it does when running in continuous conduction mode.
In continuous conduction mode, the duty cycle is related primarily to the input and output voltages.
VOUT + VD
1
=
VIN
1- D
æ æ
VIN
D = ç1 - ç
ç
V
è è OUT + VD
(10)
öö
÷ ÷÷
øø
(11)
In discontinuous mode, the duty cycle is a function of the load, input and output voltages, inductance, and
switching frequency.
D=
16
2 ´ (VOUT + VD )´ IOUT ´ L ´ fSW
(VIN )2
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Feature Description (continued)
All converters using a diode as the freewheeling or catch component have a load current level at which they
transition from discontinuous conduction to continuous conduction. This is the point where the inductor current
just falls to zero. At higher load currents, the inductor current does not fall to zero but remains flowing in a
positive direction and assumes a trapezoidal wave shape as opposed to a triangular wave shape. This load
boundary between discontinuous conduction and continuous conduction can be found for a set of converter
parameters as follows.
2
VOUT + VD - VIN )´ (VIN )
(
IOUT(crit) =
2
2 ´ (VOUT + VD ) ´ fSW ´ L
(13)
For loads higher than the result of Equation 13, the duty cycle is given by Equation 11 and for loads less that the
results of Equation 13, the duty cycle is given Equation 12. For Equations 1 through 4, the variable definitions are
as follows.
• VOUT is the output voltage of the converter in V
• VD is the forward conduction voltage drop across the rectifier or catch diode in V
• VIN is the input voltage to the converter in V
• IOUT is the output current of the converter in A
• L is the inductor value in H
• f SW is the switching frequency in Hz
7.3.5 Setting the Oscillator Frequency
The oscillator frequency is determined by a resistor and capacitor connected to the RC pin of the TPS40210. The
capacitor is charged to a level of approximately VDD/20 by current flowing through the resistor and is then
discharged by a transistor internal to the TPS40210. The required resistor for a given oscillator frequency is
found from either Figure 1 or Equation 14.
RT =
1
5.8 ´ 10
-8
´ fSW ´ C T + 8 ´ 10
- 10
2
´ fSW + 1.4 ´ 10
-7
´ fSW - 1.5 ´ 10 - 4 + 1.7 ´ 10 - 6 ´ C T - 4 ´ 10 - 9 ´ C T 2
where
•
•
•
RT is the timing resistance in kΩ
f SW is the switching frequency in kHz
CT is the timing capacitance in pF
(14)
For most applications, a capacitor in the range of 68 pF to 120 pF gives the best results. Resistor values should
be limited to between 100 kΩ and 1 MΩ as well. If the resistor value falls below 100 kΩ, decrease the capacitor
size and recalculate the resistor value for the desired frequency. As the capacitor size decreases below 47 pF,
the accuracy of Equation 14 degrades and empirical means can be needed to fine tune the timing component
values to achieve the desired switching frequency.
7.3.6 Synchronizing the Oscillator
The TPS40210 and TPS40211 can be synchronized to an external clock source. Figure 23 shows the functional
diagram of the oscillator. When synchronizing the oscillator to an external clock, the RC pin must be pulled below
150 mV for 20 ns or more. The external clock frequency must be higher than the free running frequency of the
converter as well. When synchronizing the controller, if the RC pin is held low for an excessive amount of time,
erratic operation can occur. The maximum amount of time that the RC pin should be held low is 50% of a
nominal output pulse, or 10% of the period of the synchronization frequency. If the external clock signal cannot
operate with a low enough duty cycle to limit the amount of time the RC pin is held low, a resistor and capacitor
can be added at the gate of the synchronization MOSFET. The capacitor should be added in series with the gate
of the MOSFET to AC couple the rising edge of the synchronization signal. The resistor should be added from
the gate of the MOSFET to ground to turn off the MOSFET. Typical values for the resistor and capacitor are 220
pF and 1 kΩ.
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Feature Description (continued)
Under circumstances where the duty cycle is less than 50%, a Schottky diode connected from the RC pin to an
external clock can be used to synchronize the oscillator. The cathode of the diode is connected to the RC pin.
The trip point of the oscillator is set by an internal voltage divider to be 1/20 of the input voltage. The clock signal
must have an amplitude higher than this trip point. When the clock goes low, it allows the reset current to restart
the RC ramp, synchronizing the oscillator to the external clock. This provides a simple, single-component method
for clock synchronization.
VDD
8
VIN
+
RRC
External Frequency
Synchronization
(optional)
RC
Q
R
Q
CLK
+
1
+
CRC
S
150 mV
GND
5
TPS40210/11
UDG-08063
Figure 23. Oscillator Functional Diagram
VDD
Amplitude >
VIN
8
VIN
+
20
RRC
Duty Cycle < 50%
RC
+
CRC
Q
R
Q
CLK
+
1
Frequency > Controller
Frequency
S
150 mV
GND
5
TPS40210/11
UDG-08064
Figure 24. Diode Connected Synchronization
18
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Feature Description (continued)
7.3.7 Current Sense and Overcurrent
The TPS4021x is a current mode controller that uses a resistor in series with the source terminal power FET to
sense current for both the current mode control and overcurrent protection. The device enters a current limit state
if the voltage on the ISNS pin exceeds the current limit threshold voltage VISNS(oc) from the Electrical
Characteristics. When this happens, the controller discharges the SS capacitor through a relatively high
impedance and then attempts to restart. The amount of output current that causes this to happen is dependent
on several variables in the converter.
TPS40210/11
VIN
10 VDD
TPS40210/11
RT
L
1
RC
6
GND
VOUT
VDD 10
CT
GDRV
8
ISNS
7
RIFLT
UDG-07119
CIFLT
GND
RISNS
6
UDG-07120
Figure 25. Oscillator Components
Figure 26. Current Sense Components
The load current overcurrent threshold is set by proper choice of RISNS. If the converter is operating in
discontinuous mode, the current sense resistor is found in Equation 15.
RISNS =
fSW ´ L ´ VISNS(oc)
2 ´ L ´ fSW ´ IOUT(oc) ´ (VOUT + VD - VIN )
(15)
If the converter is operating in continuous conduction mode, RISNS can be found in Equation 16.
RISNS =
VISNS
VISNS
=
æ IOUT ö æ IRIPPLE ö æ IOUT ö æ D ´ VIN ö
+
ç 1- D ÷ + ç
2 ÷ø çç (1 - D ) ÷÷ ç 2 ´ fSW ´ L ÷
è
ø è
ø
è
ø è
where
•
•
•
•
•
•
•
•
RISNS is the value of the current sense resistor in Ω
VISNS(oc) is the overcurrent threshold voltage at the ISNS pin (from electrical specifications)
D is the duty cycle (from Equation 11)
fSW is the switching frequency in Hz
VIN is the input voltage to the power stage in V (see text)
L is the value of the inductor in H
IOUT(oc) is the desired overcurrent trip point in A
VD is the drop across the diode in Figure 26
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Feature Description (continued)
The TPS40210 and TPS40211 have a fixed undervoltage lockout (UVLO) that allows the controller to start at a
typical input voltage of 4.25 V. If the input voltage is slowly rising, the converter might have less than its designed
nominal input voltage available when it has reached regulation. As a result, this can decrease the apparent
current limit load current value and must be taken into consideration when selecting RISNS. The value of VIN used
to calculate RISNS must be the value at which the converter finishes start-up. The total converter output current at
start-up is the sum of the external load current and the current required to charge the output capacitor or
capacitors. See the Soft Start section of this data sheet for information on calculating the required output
capacitor charging current.
The topology of the standard boost converter has no method to limit current from the input to the output in the
event of a short circuit fault on the output of the converter. If protection from this type of event is desired, it is
necessary to use some secondary protection scheme, such as a fuse, or rely on the current limit of the upstream
power source.
7.3.8 Current Sense and Subharmonic Instability
A characteristic of peak current mode control results in a condition where the current control loop can exhibit
instability. This results in alternating long and short pulses from the pulse width modulator. The voltage loop
maintains regulation and does not oscillate, but the output ripple voltage increases. The condition occurs only
when the converter is operating in continuous conduction mode and the duty cycle is 50% or greater. The cause
of this condition is described in the Modeling, Analysis and Compensation of the Current-Mode Converter
Application Report. The remedy for this condition is to apply a compensating ramp from the oscillator to the
signal going to the pulse width modulator. In the TPS40210 and TPS40211, the oscillator ramp is applied in a
fixed amount to the pulse width modulator. The slope of the ramp is given in Equation 17.
æV
ö
s e = fSW ´ ç VDD ÷
20
è
ø
(17)
To ensure that the converter does not enter into subharmonic instability, the slope of the compensating ramp
signal must be at least half of the down slope of the current ramp signal. Since the compensating ramp is fixed in
the TPS40210 and TPS40211, this places a constraint on the selection of the current sense resistor.
The down slope of the current sense wave form at the pulse width modulator is described in Equation 18.
m2 =
A CS ´ RISNS ´ (VOUT + VD - VIN )
L
(18)
Since the slope compensation ramp must be at least half, and preferably equal to the down slope of the current
sense waveform seen at the pulse width modulator, a maximum value is placed on the current sense resistor
when operating in continuous mode at 50% duty cycle or greater. For design purposes, some margin should be
applied to the actual value of the current sense resistor. As a starting point, the actual resistor chosen should be
80% or less that the value calculated in Equation 19. This equation calculates the resistor value that makes the
slope compensation ramp equal to one half of the current ramp downslope. Values no more than 80% of this
result would be acceptable.
RISNS(max) =
VVDD ´ L ´ fSW
60 ´ (VOUT + VD - VIN )
where
•
•
•
•
•
•
•
20
Se is the slope of the voltage compensating ramp applied to the pulse width modulator in V/s
f SW is the switching frequency in Hz
VDD is the voltage at the VDD pin in V
m2 is the down slope of the current sense waveform seen at the pulse width modulator in V/s
RISNS is the value of the current sense resistor in Ω
VOUT is the converter output voltage VIN is the converter power stage input voltage
VD is the drop across the diode in Figure 26
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Feature Description (continued)
It is possible to increase the voltage compensation ramp slope by connecting the VDD pin to the output voltage
of the converter instead of the input voltage as shown in Figure 26. This can help in situations where the
converter design calls for a large ripple current value in relation to the desired output current limit setting.
NOTE
Connecting the VDD pin to the output voltage of the converter affects the start-up voltage
of the converter since the controller undervoltage lockout (UVLO) circuit monitors the VDD
pin and senses the input voltage less the diode drop before start-up. The effect is to
increase the start-up voltage by the value of the diode voltage drop.
If an acceptable RISNS value is not available, the next higher value can be used and the signal from the resistor
divided down to an acceptable level by placing another resistor in parallel with CIFLT.
7.3.9 Current Sense Filtering
In most cases, a small filter placed on the ISNS pin improves performance of the converter. These are the
components RIFLT and CIFLT in Figure 26. The time constant of this filter should be approximately 10% of the
nominal pulse width of the converter. The pulse width can be found using Equation 20.
tON =
D
fSW
(20)
The suggested time constant is then
RIFLT ´ CIFLT = 0.1´ tON
(21)
The range of RIFLT should be from about 1 kΩ to 5 kΩ for best results. Higher values can be used but this raises
the impedance of the ISNS pin connection more than necessary and can lead to noise pickup issues in some
layouts. CIFLT should be located as close as possible to the ISNS pin as well to provide noise immunity.
7.3.10 Control Loop Considerations
There are two methods to design a suitable control loop for the TPS4021x. The first and preferred if equipment is
available is to use a frequency response analyzer to measure the open loop modulator and power stage gain
and to then design compensation to fit that. The usage of these tools for this purpose is well documented with
the literature that accompanies the tool and is not be discussed here.
The second option is to make an initial guess at compensation, and then evaluate the transient response of the
system to see if the compensation is acceptable to the application or not. For most systems, an adequate
response can be obtained by simply placing a series resistor and capacitor (RFB and CFB) from the COMP pin to
the FB pin as shown in Figure 27. The initial compensation selection can be done more accurately with aid of
WEBENCH® to select the components or the average Spice model to simulate the open loop modulator and
power stage gain.
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Feature Description (continued)
VIN
TPS40210
1
RC
2
SS
3
DIS/EN
L
VOUT
VDD 10
BP
9
GDRV
8
CHF
CFB
RFB
COUT
RIFLT
4
COMP
5
FB
ISNS
7
GND
6
CIFLT
ROUT
RSENSE
R1
R2
UDG-07177
Figure 27. Basic Compensation Network
The natural phase characteristics of most capacitors used for boost outputs combined with the current mode
control provide adequate phase margin when using this type of compensation. To determine an initial starting
point for the compensation, the desired crossover frequency must be considered when estimating the control to
output gain. The model used is a current source into the output capacitor and load.
When using these equations, the loop bandwidth should be no more than 20% of the switching frequency, fSW. A
more reasonable loop bandwidth would be 10% of the switching frequency. Be sure to evaluate the transient
response of the converter over the expected load range to ensure acceptable operation.
K CO = gM ´ ZOUT (fCO )
0.13 ´ L ´
gM =
(22)
fSW
ROUT
(RISNS )2 ´ (120 ´ RISNS + L ´ fSW )
(23)
(1+ (2p ´ f ´ R
L
ZOUT = ROUT ´
(
2
ESR
2
´ COUT )
2
)
)
2
1 + (ROUT ) + 2 ´ ROUT ´ RESR + (RESR ) ´ (2p ´ fL ´ COUT )
where
•
•
•
•
•
•
22
KCO is the control to output gain of the converter, in V/V
gM is the transconductance of the power stage and modulator, in S
ROUT is the output load equivalent resistance, in Ω
ZOUT is the output impedance, including the output capacitor, in Ω
RISNS is the value of the current sense resistor, in Ω
L is the value of the inductor, in H
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Feature Description (continued)
•
•
•
•
COUT is the value of the output capacitance, in F
RESR is the equivalent series resistance of COUT, in Ω
f SW is the switching frequency, in Hz
f L is the desired crossover frequency for the control loop, in Hz
(24)
These equations assume that the operation is discontinuous and that the load is purely resistive. The gain in
continuous conduction can be found by evaluating Equation 23 at the resistance that gives the critical conduction
current for the converter. Loads that are more like current sources give slightly higher gains than predicted here.
To find the gain of the compensation network required for a control loop of bandwidth fL, take the reciprocal of
Equation 22.
K COMP =
1
K CO
(25)
The GBWP of the error amplifier is only guaranteed to be at least 1.5MHz. If KCOMP multiplied by fL is greater
than 750 kHz, reduce the desired loop crossover frequency until this condition is satisfied. This ensures that the
high-frequency pole from the error amplifier response with the compensation network in place does not cause
excessive phase lag at fL and decreased phase margin in the loop.
The RC network connected from COMP to FB places a zero in the compensation response. That zero should be
approximately 1/10th of the desired crossover frequency, fL. With that being the case, RFB and CFB can be found
from Equation 26 and Equation 27.
RFB =
CFB =
R1
= R1´ K COMP
K CO
(26)
10
2p ´ fL ´ RFB
where
•
•
R1 is the high side feedback resistor in Figure 27, in Ω
fL is the desired loop crossover frequency, in Hz
(27)
Thought not strictly necessary, it is recommended that a capacitor be added between COMP and FB to provide
high-frequency noise attenuation in the control loop circuit. This capacitor introduces another pole in the
compensation response. The allowable location of that pole frequency determines the capacitor value. As a
starting point, the pole frequency should be 10 × fL. The value of CHF can be found from Equation 28.
CHF =
1
20p ´ fL ´ RFB
(28)
While the error amplifier GBWP will usually be higher, it can be as low as 1.5MHz. If 10 × KComp × fL > 1.5MHz,
the error amplifier gain-bandwidth product may limit the high-frequency response below that of the highfrequency capacitor. To maintain a consistent high-frequency gain roll-off, CHF can be calculated by Equation 29.
CHF =
1
6
2p ´ 1.5 ´ (10 ) ´ RFB
where
•
•
CHF is the high-frequency roll-off capacitor value in F
RFB is the mid band gain setting resistor value in Ω
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Feature Description (continued)
7.3.11 Gate Drive Circuit
Some applications benefit from the addition of a resistor connected between the GDRV pin and the gate of the
switching MOSFET. In applications that have particularly stringent load regulation (under 0.75%) requirements
and operate from input voltages above 5 V, or are sensitive to pulse jitter in the discontinuous conduction region,
this resistor is recommended. The recommended starting point for the value of this resistor can be calculated
from Equation 30.
RG =
105
QG
where
•
•
QG is the MOSFET total gate charge at 8 V, VGS in nC
RG is the suggested starting point gate resistance in Ω
(30)
VIN
TPS40210/11
L
VDD 10
VOUT
RG
GDRV
8
ISNS
7
GND
6
UDG-07196
Figure 28. Gate Drive Resistor
7.3.12 TPS40211
The only difference between the TPS40210 and the TPS40211 is the reference voltage that the error amplifier
uses to regulate the output voltage. The TPS40211 uses a 260-mV reference and is intended for applications
where the output is actually a current instead of a regulated voltage. A typical example of an application of this
type is an LED driver. An example schematic is shown in Figure 29.
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Feature Description (continued)
VIN
IOUT
TPS40210/11
1
RC
2
SS
3 DIS/EN
L
VDD 10
BP
9
GDRV
8
4
COMP
ISNS 7
5
FB
GND
RIFB
6
UDG-07197
Figure 29. Typical LED Drive Schematic
The current in the LED string is set by the choice of the resistor RISNS as shown in Equation 31.
RIFB =
VFB
IOUT
where
•
•
•
RIFB is the value of the current sense resistor for the LED string in Ω
VFB is the reference voltage for the TPS40211 in V (0.260 V typ.)
IOUT is the desired DC current in the LED string in A
(31)
7.4 Device Functional Modes
7.4.1 Operation Near Minimum Input Voltage
The TPS4021x is designed to operate with input voltages above 4.5 V. The typical VDD UVLO threshold is 4.25
V and the device can operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. When VVDD passes the UVLO threshold the device will become active.
Switching is enabled and the soft-start sequence is initiated. The TPS4021x will ramp up the output voltage at
the rate determined by the external capacitor at the SS pin.
7.4.2 Operation With DIS/EN Pin
The DIS/EN pin has a 1.2-V typical threshold which can be used to disable the TPS4021x. With DIS/EN forced
above this threshold voltage, the device is disabled and switching is inhibited even if VVDD is above its UVLO
threshold. Hysteresis on the DIS/EN pin threshold gives a typical turnon threshold of 1.05 V. If the DIS/EN is left
floating or is pulled below the 1.05-V threshold while VVDD is above its UVLO threshold, the device becomes
active. Switching is enabled and the soft-start sequence is initiated. The TPS4021x will ramp up the output
voltage at the rate determined by the external capacitor at the soft-start pin.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS4021x is a 4.5-V to 52-V low-side controller with an integrated gate driver for a low-side N-channel
MOSFET. This device is typically used in a boost topology to convert a lower DC voltage to a higher DC voltage
with a peak current limit set by an external current sense resistor. It can also be configured in a SEPIC, Flyback
and LED drive applications. In higher current applications, the maximum current can also be limited by the
thermal performance of the external MOSFET and rectifying diode switch. Use the following design procedure to
select external components for the TPS4021x. The design procedure illustrates the design of a typical boost
regulator with the TPS40210. Alternatively, use the WEBENCH software to generate a complete design. The
WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design.
8.2 Typical Applications
8.2.1 12-V to 24-V Nonsynchronous Boost Regulator
The following example illustrates the design process and component selection for a 12-V to 24-V
nonsynchronous boost regulator using the TPS40210 controller.
+
+
Figure 30. TPS40210 Design Example – 12 V to 24 V at 2 A
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Typical Applications (continued)
8.2.1.1 Design Requirements
Table 1. TPS40210 Design Example Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INPUT CHARACTERISTICS
VIN
Input voltage
IIN
Input current
8
12
No load input current
VIN(UVLO)
14
4.4
0.05
Input undervoltage lockout
4.5
V
A
V
OUTPUT CHARACTERISTICS
VOUT
Output voltage
23.5
24.0
Line regulation
24.5
V
1%
Load regulation
1%
VOUT(ripple)
Output voltage ripple
500
IOUT
Output current
IOCP
Output overcurrent inception point
8 V ≤ VIN ≤ 14 V
0.1
1
2.0
3.5
mVPP
A
Transient response
ΔI
Load step
Load slew rate
Overshoot threshold voltage
Settling time
1
A
1
A/μs
500
mV
5
ms
600
kHz
SYSTEM CHARACTERISTICS
fSW
Switching frequency
ηPK
Peak efficiency
VIN = 12 V
95%
η
Full load efficiency
VIN = 12 V, IOUT = 2 A
94%
TOP
Operating temperature range
8 V ≤ VIN ≤ 14 V, IOUT ≤ 2 A
25
°C
MECHANICAL DIMENSIONS
W
Width
1.5
L
Length
1.5
h
Height
0.5
inch
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the TPS40210 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
8.2.1.2.2 Duty Cycle Estimation
The duty cycle of the main switching MOSFET is estimated using Equation 32 and Equation 33.
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Typical Applications (continued)
DMIN »
VOUT - VIN(max) + VFD
DMAX »
VOUT + VFD
VOUT - VIN(m in) + VFD
VOUT + VFD
=
=
24 V - 14 V + 0.5 V
= 42.9%
24 V + 0.5 V
(32)
24 V - 8 V + 0.5 V
= 67.3%
24 V + 0.5 V
(33)
Using an estimated forward drop (VFD) of 0.5 V for a schottky rectifier diode, the approximate duty cycle is 42.9%
(minimum) to 67.3% (maximum).
8.2.1.2.3 Inductor Selection
The peak-to-peak ripple is chosen to be 30% of the maximum input current.
IOUT(max)
2
IRIPPLE(max) = 0.3 ´
= 0.3 ´
= 1.05 A
1 - DMIN
1 - 0.429
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Typical Applications (continued)
The minimum inductor size can be estimated using Equation 35.
VIN(max)
1
14 V
1
LMIN »
´ DMIN ´
=
´ 0.429 ´
= 9.5 mH
IRIPPLE(max)
fSW 1.05 A
600kHz
(35)
The next higher standard inductor value of 10 μH is selected. The ripple current for nominal and minimum VIN is
estimated by Equation 36 and Equation 37.
V
1
12 V
1
IRIPPLE(Vintyp) » IN ´ D ´
=
´ 0.50 ´
= 1.02 A
L
fSW 10 mH
600kHz
(36)
V
1
8V
1
IRIPPLE(Vinmin) » IN ´ D ´
=
´ 0.673 ´
= 0.90 A
L
fSW 10 mH
600kHz
(37)
The worst case peak-to-peak ripple current occurs at 50% duty cycle (VIN = 12.25 V) and is estimated as 1.02 A.
Worst case RMS current through the inductor is approximated by Equation 38.
ILrms =
(I ( ) ) + (
2
L avg
1 I
12 RIPPLE
)
2
æ IOUT(max)
» ç
ç 1- D
MAX
è
2
ö
÷÷ +
ø
(112IRIPPLE(VINmin) )
2
2
2
æ
ö
= ç
÷ +
1
0.673
è
ø
((112)´ 0.90A )
2
= 6.13 Arms
(38)
The worst case RMS inductor current is 6.13 Arms. The peak inductor current is estimated by Equation 39.
IOUT(max)
2
ILpeak »
+ (12 )IRIPPLE(Vinmin) =
+ (12 )0.90 = 6.57 A
1 - DMAX
1 - 0.673
(39)
A 10-μH inductor with a minimum RMS current rating of 6.13 A and minimum saturation current rating of 6.57 A
must be selected. A TDK RLF12560T-100M-7R5 7.5-A 10-μH inductor is selected.
This inductor power dissipation is estimated by Equation 40.
2
PL » (ILrms ) ´ DCR
(40)
The TDK RLF12560T-100M-7R5 12.4-mΩ DCR dissipates 466-mW of power.
8.2.1.2.4 Rectifier Diode Selection
A low forward voltage drop schottky diode is used as a rectifier diode to reduce its power dissipation and improve
efficiency. Using 80% derating on VOUT for ringing on the switch node, the rectifier diode minimum reverse breakdown voltage is given by Equation 41.
V
V(BR)R(min) ³ OUT = 1.25 ´ VOUT = 1.25 ´ 24 V = 30 V
0.8
(41)
The diode must have reverse breakdown voltage greater than 30 V. The rectifier diode peak and average
currents are estimated by Equation 42 and Equation 43.
ID (avg ) » IOUT (m ax ) = 2 A
(42)
ID(peak ) = IL(peak ) = 6.57 A
(43)
The power dissipation in the diode is estimated by Equation 44.
PD(max) » VFD ´ ID(avg) = 0.5 V ´ 2 A = 1W
(44)
For this design, the maximum power dissipation is estimated as 1 W. Reviewing 30-V and 40-V schottky diodes,
the MBRS340T3, 40-V, 3-A diode in an SMC package is selected. This diode has a forward voltage drop of 0.48
V at 6 A, so the conduction power dissipation is approximately 960 mW, less than half its rated power
dissipation.
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Typical Applications (continued)
8.2.1.2.5 Output Capacitor Selection
Output capacitors must be selected to meet the required output ripple and transient specifications.
I
´D
æ 2 A ´ 0.673 ö
1
1
COUT = 8 OUT
´
= 8ç
= 36 mF
÷´
VOUT(ripple) fSW
è 500mV ø 600kHz
ESR =
VOUT(ripple )
7
7
500mV
´
= ´
= 96mW
8 IL(peak ) - IOUT 8 6.57 A - 2 A
(45)
(46)
A Panasonic EEEFC1V330P 35-V 33-μF, 120-mΩ bulk capacitor and a 6.8-μF ceramic capacitor are selected to
provide the required capacitance and ESR at the switching frequency. The combined capacitance of 39.8 μF and
ESR of 60 mΩ are used in compensation calculations.
8.2.1.2.6 Input Capacitor Selection
Since a boost converter has continuous input current, the input capacitor senses only the inductor ripple current.
The input capacitor value can be calculated by Equation 47 and Equation 48.
IRIPPLE
1.02 A
CIN >
=
= 7.1mF
4 ´ VIN(ripple ) ´ fSW
4 ´ 60mV ´ 600kHz
(47)
ESR <
VIN(ripple )
2 ´ IRIPPLE
=
60mV
= 29mW
2 ´ 1.02 A
(48)
For this design to meet a maximum input ripple of 60 mV (1/2% of VIN nominal), a minimum 7.1-μF input
capacitor with ESR less than 29 mΩ is needed. A 10-μF, X7R ceramic capacitor is selected.
8.2.1.2.7 Current Sense and Current Limit
The maximum allowable current sense resistor value is limited by both the current limit and sub-harmonic
stability. These two limitations are given by Equation 49 and Equation 50.
VISNS(OC)MIN
120mV
=
= 15.4mW
RISNS <
1.1´ (6.57 A + 0.50 A)
1.1´ IL(peak ) + IDrive
(
RISNS <
)
VIN(MAX) ´ L ´ fSW
60 ´ (VOUT + VFD - VIN )
(49)
=
14 V ´ 10 mH ´ 600kHz
= 134mW
60 ´ (24 V + 0.48 V - 14 V)
(50)
With 10% margin on the current limit trip point (the 1.1 factor) and assuming a maximum gate drive current of
500 mA, the current limit requires a resistor less than 15.4 mΩ and stability requires a sense resistor less than
134 mΩ. A 10-mΩ resistor is selected. Approximately 2 mΩ of routing resistance is added in compensation
calculations.
The power dissipation in RISNS is calculated by Equation 51.
PRISNS = (ILRMS )2 × RISNS × D
(51)
At maximum duty cycle, this is 0.253 W.
8.2.1.2.8 Current Sense Filter
To remove switching noise from the current sense, an RC filter is placed between the current sense resistor and
the ISNS pin. A resistor with a value between 1 kΩ and 5 kΩ is selected and a capacitor value is calculated by
Equation 52.
0.1´ DMIN
0.1´ 0.429
CIFLT =
=
= 71pF
fSW ´ RIFLT 600kHz ´ 1kW
(52)
For a 1-kΩ filter resistor, 71 pF is calculated and a 100-pF capacitor is selected.
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Typical Applications (continued)
8.2.1.2.9 Switching MOSFET Selection
The TPS40210 drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on
the desired efficiency target.
æ1 ö
æ1 ö
æ 1
ö
- 1÷ = 2.526 W
PDISS(total) » POUT ´ ç - 1÷ = VOUT ´ IOUT ´ ç - 1÷ = 24 V ´ 2 A ´ ç
è 0.95 ø
èh ø
èh ø
(53)
For a target of 95% efficiency with a 24-V input voltage at 2 A, maximum power dissipation is limited to 2.526 W.
The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated
circuit, the TPS40210.
PFET < PDISS(total) - PL - PD - PRisns - VIN(max) ´ IVDD(max)
(54)
This leaves 812 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too
hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can
determine a target RDS(on) and QGS for the MOSFET by Equation 55 and Equation 56.
QGS <
3 ´ PFET ´ IDRIVE
3 ´ 0.50 W ´ 0.50 A
=
= 13.0nC
2 ´ VOUT ´ IOUT ´ fSW 2 ´ 24 V ´ 2 A ´ 600kHz
(55)
A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less
than 250 mW.
PFET
0.50 W
RDS(on ) <
=
= 9.9mW
2
2
2 ´ (IRMS ) ´ D 2 ´ 6.13 ´ 0.673
(56)
A target MOSFET RDS(on) of 9.9 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing
30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 30.
The maximum gate charge at VGS= 8V for the Si4386DY is 33.2 nC, this implies RG = 3.3 Ω.
8.2.1.2.10 Feedback Divider Resistors
The primary feedback divider resistor (RFB) from VOUT to FB should be selected between 10 kΩ and 100 kΩ to
maintain a balance between power dissipation and noise sensitivity. For a 24-V output, a high feedback
resistance is desirable to limit power dissipation so RFB = 51.1 kΩ is selected.
RBIAS =
VFB ´ RFB
0.700 V ´ 51.1kW
=
= 1.53kW
VOUT - VFB
24 V - 0.700 V
(57)
RBIAS = 1.50 kΩ is selected.
8.2.1.2.11 Error Amplifier Compensation
Compensation selection can be done with aid of WEBENCH to select compensation components or with the aid
of the average Spice model to simulate the open loop modulator and power stage gain. Alternatively, the
following procedure gives a good starting point.
While current mode control typically only requires Type II compensation, it is desirable to layout for Type III
compensation to increase flexibility during design and development. Current mode control boost converters have
higher gain with higher output impedance, so it is necessary to calculate the control loop gain at the maximum
output impedance, estimated by Equation 58.
ROUT(max ) =
VOUT
24 V
=
= 240 W
IOUT(min ) 0.1A
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Typical Applications (continued)
The transconductance of the TPS40210 current mode control can be estimated by Equation 59.
0.13 ´ L ´
gM =
fSW
ROUT
0.13 ´ 10 mH ´
=
2
600kHz
240 W
= 19.2 A
2
(RISNS ) ´ (120 ´ RISNS + L ´ fSW ) (12mW ) ´ (120 ´ 12mW + 10 mH ´ 600kHz )
V
(59)
The maximum output impedance ZOUT, can be estimated by Equation 60.
(1+ (2p ´ f ´ R
)
1 + ((R
) + 2 ´ R ´ R + (R ) )´ (2p ´ f ´ C )
1 + (2p ´ 30kHz ´ 60mW ´ 39.8 mF ) )
(
=
240
W
´
)
1 + ((240 W ) + 2 ´ 240 W ´ 60mW + (60mW ) )´ (2p ´ 30kHz ´ 39.8 mF )
ESR
ZOUT (f ) = ROUT ´
2
´ COUT )
2
2
OUT
OUT
ESR
2
ESR
OUT
(60)
2
ZOUT (fL
2
2
2
= 0.146 W
(61)
At the desired crossover frequency (fL) of 30 kHz, ZOUT becomes 0.146 Ω.
The modulator gain at the desired cross-over can be estimated by Equation 62.
K CO = gM ´ ZOUT (fCO ) = 19.2 A ´ 0.146 W = 2.80
V
(62)
The feedback compensation network needs to be designed to provide an inverse gain at the cross-over
frequency for unity loop gain. This sets the compensation mid-band gain at a value calculated in Equation 63.
1
1
K COMP =
=
= 0.357
K CO
2.80
(63)
To set the mid-band gain of the error amplifier to KCOMP, use Equation 64.
R4 = R7 ´ K COMP =
R7
51.1kW
=
= 18.2kW
K CO
2.80
(64)
R4 = 18.7 kΩ selected.
Place the zero at 1/10th of the desired cross-over frequency.
C2 =
10
10
=
= 2837pF
2p ´ fL ´ R4 2p ´ 30kHz ´ 18.7kW
(65)
C2 = 2200 pF selected.
Place a high-frequency pole at about five times the desired cross-over frequency and less than one-half the unity
gain bandwidth of the error amplifier:
C4 »
C4 >
1
1
=
= 56.74pF
10p ´ fL ´ R4 10p ´ 30kHz ´ 18.7kW
(66)
1
1
=
= 11.35pF
p ´ GBW ´ R4 p ´ 1.5MHz ´ 18.7kW
(67)
C4 = 47 pF selected.
8.2.1.2.12 RC Oscillator
The RC oscillator calculation is given as shown in Equation 14 in the data sheet, substituting 100 for CT and 600
for fSW. For a 600-kHz switching frequency, a 100pF capacitor is selected and a 262-kΩ resistor is calculated
(261-kΩ selected).
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Typical Applications (continued)
8.2.1.2.13 Soft-Start Capacitor
Since VDD > 8 V, the soft-start capacitor is selected by using Equation 68 to calculate the value.
CSS = 20 ´ TSS ´ 10-6
(68)
For TSS = 12 ms, CSS = 240 nF. A 220-nF capacitor is selected.
8.2.1.2.14 Regulator Bypass
A regulator bypass (BP) capacitor of 1.0 μF is selected per the datasheet recommendation.
8.2.1.2.15 Bill of Materials
Table 2. Bill of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SIZE
PART
NUMBER
MANUFACTURER
0.406 x 0.457
EEEFC1V101P
Panasonic
C1
100 μF, aluminum capacitor, SM, ± 20%, 35 V
C2
2200 pF, ceramic capacitor, 25 V, X7R, 20%
0603
Std
Std
C3
100 pF, ceramic capacitor, 16 V, C0G, 10%
0603
Std
Std
C4
47 pF, ceramic capacitor, 16V, X7R, 20%
0603
Std
Std
C5
0.22 μF, ceramic capacitor, 16 V, X7R, 20%
0603
Std
Std
C7
1.0 μF, ceramic capacitor, 16 V, X5R, 20%
0603
Std
Std
C8
10 μF, ceramic capacitor, 25 V, X7R, 20%
0805
C3225X7R1E106M
TDK
C9
0.1 μF, ceramic capacitor, 50 V, X7R, 20%
0603
Std
Std
C10
100 pF, ceramic capacitor, 16 V, X7R, 20%
0603
Std
Std
D1
Schottky diode, 3 A, 40 V
SMC
MBRS340T3
On Semi
L1
10 μH, inductor, SMT, 7.5 A, 12.4 mΩ
0.325 x 0.318 inch
RLF12560T-100M-7R5
TDK
Q1
MOSFET, N-channel, 40 V, 14 A, 9mΩ
SO-8
Si4840DY
Vishay
R3
10 kΩ, chip resistor, 1/16 W, 5%
0603
Std
Std
R4
18.7 kΩ, chip resistor, 1/16 W, 1%
0603
Std
Std
R5
1.5 kΩ, chip resistor, 1/16 W, 1%
0603
Std
Std
R6
261 kΩ, chip resistor, 1/16 W, 1%
0603
Std
Std
R7
51.1 kΩ, chip resistor, 1/16 W, 1%
0603
Std
Std
R9
3.3 Ω, chip resistor, 1/16 W, 5%
0603
Std
Std
R10
1.0 kΩ, chip resistor, 1/16 W, 5%
0603
Std
Std
R11
10 mΩ, chip resistor, 1/2 W, 2%
1812
Std
Std
U1
IC, 4.5 V-52 V I/P, current mode boost controller
DGQ10
TPS40210DGQ
TI
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8.2.1.3 Application Curves
80
180
60
135
VIN = 8 V
VOUT = 24 V
IOUT = 2 A
40
90
20
45
0
0
Gain
-20
-45
-40
-90
-60
-135
-80
100
FET Vds
(20 V/ div)
-180
1M
1000
10 k
100 k
fSW – Frequency – Hz
T – Time – 400 ns
Figure 32. FET VDS and VGS Voltages vs Time
Figure 31. Gain and Phase vs Frequency
6
100
96
5
94
92
VIN = 12 V
90
88
VIN (V)
14
12
8
VIN = 14V
PLOSS – Power Loss – W
VIN (V)
14
12
8
98
h – Efficiency – %
GDRV
(5 V/ div)
Phase – °
Gain – dB
Phase
VIN = 8 V
86
VIN = 8 V
4
VIN = 12 V
3
2
VIN = 14 V
84
1
82
80
0
0
0.5
1.0
1.5
2.0
ILOAD – Load Current – A
0
2.5
Figure 33. Efficiency vs Load Current
0.5
1.0
1.5
2.0
ILOAD – Load Current – A
2.5
Figure 34. Power Loss vs Load Current
24.820
VOUT – Output Voltage – V
24.772
24.724
VIN (V)
14
12
8
VIN = 8 V
24.676
24.628
24.580
VIN = 14 V
24.532
VIN = 12 V
24.484
24.436
24.388
24.340
0
0.5
1.0
1.5
2.0
ILOAD – Load Current – A
2.5
Figure 35. Output Voltage vs Load Current
34
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8.2.2 12-V Input, 700-mA LED Driver, Up to 35-V LED String
This application uses the TPS40211 as a boost controller that drives a string of LED diodes. The feedback point
for this circuit is a sense resistor in series with this string. The low 260-mV reference minimizes power wasted in
this resistor, and maintains the LED current at a value given by 0.26/R6. As the input voltage is varied, the duty
cycle changes to maintain the LED current at a constant value so that the light intensity does not change with
large input voltage variations.
L1
VIN
C21
C1
GDRV
C2
D1
B2100
Q1
R2
ISNS
C3
R1
R11
C4
VIN
R3
D2
C8
1
U1
TPS40211
RC
VIN 10
C10
C9
Loop
Response
Injection
C6
R23
R13
R4
DIS/EN
C11
2
SS
BP
9
3
DIS/EN GDRV
8
4
COMP
ISNS
7
5
FB
GND
6
C5
LEDC
GDRV
LEDC
ISNS
R24
C13
R6
D3
R15
Q3
C14
PWM Dimming
UDG-08015
Figure 36. 12-V Input, 700-mA LED Driver, Up to 35-V LED String
8.2.2.1 Design Requirements
Table 3. TPS40211 Design Example Specifications
PARAMETER
MIN
TYP
MAX
UNIT
8
12
20
V
35
V
INPUT CHARACTERISTICS
VIN
Input voltage
OUTPUT CHARACTERISTICS
VOUT
Output voltage
IOUT
Output current
0.7
A
400
kHz
SYSTEM CHARACTERISTICS
fSW
Switching frequency
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8.2.2.2 Detailed Design Procedure
Table 4. TPS40211 LED Driver Bill of Materials
REFERENCE
DESIGNATOR
TYPE
DESCRIPTION
SIZE
C1,C2
10 μF, 25 V
1206
C3, C4
2.2 μF, 100 V
1210
C5
1 nF, NPO
0603
C6
100 pF, NPO
0603
C8
100 pF
0603
0.1 μF
0603
C10
0.1 μF, 25 V
0805
C11
1 μF, 25 V
1206
C13
220 pF
0603
C14
10 nF, X7R
0603
C21
330 μF, 25 V electrolytic
D1
B2100, SHTKY, 100 V, 2 A
C9
D2
Capacitor
Diode
D3
L1
Q1
Q3
SMB
BZT52C43
SOD-123
MMBD7000
Inductor
MOSFET
SOT-23
Wurth 7447709100, 10 μH, 6 A
12mm × 12mm × 10mm
Si7850DP, 60 V, 31 mΩ
SO-8
2N7002, 60 V, 0.1 A
SOT-23
R1
15 mΩ
2512
R2
3.01 Ω
0805
R3
402 kΩ
0603
R4
14.3 kΩ
0603
R6
0.36 Ω
2512
R11
Resistor
1 kΩ
0603
R13
30.1 kΩ
0603
R15
49.9 kΩ
0603
R24
10 kΩ
0603
10 Ω
R23
U1
36
Integrated circuit
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0603
TPS40211
DRC-10
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9 Power Supply Recommendations
The TPS4021x is designed to operate from an input voltage supply range between 4.5 V and 52 V. This input
supply should remain within the input voltage range of the TPS4021x. If the input supply is located more than a
few inches from the buck power stage controlled by the TPS4021x, additional bulk capacitance can be required
in addition to ceramic-bypass capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
For the maximum effectiveness from C9, place it near the VDD pin of the controller. Excessive high frequency
noise on VDD during switching degrades overall regulation as the load increases.
Keep the output loop (Q1-D1-C12-R11) as small as possible. A larger loop can degrade current limit accuracy
and increase rediated emissions.
For best current limit accuracy keep the ISNS filter components C10 and R10 near the ISNS and GND pins.
Avoid connecting traces carrying large AC currents through a ground plane. Instead, use PCB traces on the
top layer to conduct the AC current and use the ground plane as a noise shield.
Split the ground plane as necessary to keep noise away from the TPS4021x and noise sensitive areas such
as components connected to the RC pin, FB pin, COMP pin, and SS pin. Also keep these noise sensitive
components close to the TPS4021x IC.
Keep C7 near the BP and GND pins to provide good bypass for the BP regulator.
The GDRV trace should be as close as possible to the power FET gate to minimize parisitic resistance and
inductance in the trace. The parasitics should also be minimized in the return path from the source of the
MOSFET, through the sense resistor and back to the GND pin.
Keep the SW node as physically small as possible to minimize parasitic capacitance and radiated emissions.
For good output voltage regulation, Kelvin connections should be brought from the load to the top FB resistor
R7.
10.2 Layout Example
Figure 37. Component Placement
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Layout Example (continued)
Figure 38. Top Copper
Figure 39. Bottom Copper Viewed From Top
38
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Layout Example (continued)
Figure 40. Internal 1 Copper Viewed From Top
Figure 41. Internal 2 Copper Viewed From Top
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
• Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series
• Designing Stable Control Loops, SEM 1400, 2001 Seminar Series
11.1.2 Related Devices
The following devices have characteristics similar to the TPS40210 and may be of interest.
Table 5. Related Parts
DEVICE
DESCRIPTION
TPS6100x
Single- and Dual-Cell Boost Converter with Start-up into Full Load
TPS6101x
High Efficiency 1-Cell and 2-Cell Boost Converters
TPS6300x
High Efficiency Single Inductor Buck-Boost Converter with 1.8A Switches
11.1.3 Development Support
11.1.3.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the TPS40210 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
11.2 Documentation Support
11.2.1 Related Documentation
These references may be found on the web at www.power.ti.com under Technical Documents. Many design
tools and links to additional references, may also be found at www.power.ti.com.
• PowerPAD™ Thermally Enhanced Package
• PowerPAD™ Made Easy
• AC-DC Non-Isolated SMPS for Single-Phase Smart Meters Based on UCC28722
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
40
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Related Links (continued)
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS40210
Click here
Click here
Click here
Click here
Click here
TPS40211
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Trademarks
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40210DGQ
ACTIVE
HVSSOP
DGQ
10
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
40210
TPS40210DGQG4
ACTIVE
HVSSOP
DGQ
10
80
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
40210
TPS40210DGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
40210
TPS40210DGQRG4
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
40210
TPS40210DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4210
TPS40210DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4210
TPS40211DGQ
ACTIVE
HVSSOP
DGQ
10
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
40211
TPS40211DGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
40211
TPS40211DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4211
TPS40211DRCRG4
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4211
TPS40211DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4211
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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