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Table of Contents
User’s Guide
TPS40305 Buck Controller Evaluation Module User's
Guide
ABSTRACT
The TPS40305EVM-488 evaluation module (EVM) is a synchronous buck converter providing a fixed 1.8-V
output at up to 10 A from a 12-V input bus. The EVM is designed to start-up from a single supply, so no
additional bias voltage is required for start-up. The module uses the TPS40305 high performance, mid-input
voltage synchronous buck controller and TI’s NexFET™ high performance MOSFETs.
Table of Contents
1 Description.............................................................................................................................................................................. 2
1.1 Applications........................................................................................................................................................................2
1.2 Features............................................................................................................................................................................. 2
2 TPS40305EVM-488 Electrical Performance Specifications................................................................................................ 2
3 TPS40305EVM-488 Schematic...............................................................................................................................................3
4 Connector and Test Point Descriptions................................................................................................................................4
4.1 Enable Jumper (JP2)......................................................................................................................................................... 4
4.2 Frequency Spread Spectrum – FSS Jumper (JP1)............................................................................................................4
4.3 Test Point Descriptions.......................................................................................................................................................4
5 Test Set Up.............................................................................................................................................................................. 6
5.1 Equipment.......................................................................................................................................................................... 6
5.2 Equipment Setup................................................................................................................................................................6
5.3 Start-Up/Shutdown Procedure........................................................................................................................................... 8
5.4 Output Ripple Voltage Measurement Procedure................................................................................................................8
5.5 Control Loop Gain and Phase Measurement Procedure................................................................................................... 8
5.6 Equipment Shutdown......................................................................................................................................................... 9
6 TPS40305EVM-488 Test Data............................................................................................................................................... 10
6.1 Efficiency..........................................................................................................................................................................10
6.2 Line and Load Regulation................................................................................................................................................ 10
6.3 Output Voltage Ripple.......................................................................................................................................................11
6.4 Switch Node..................................................................................................................................................................... 11
6.5 Control Loop Bode Diagram.............................................................................................................................................12
6.6 Additional Waveforms...................................................................................................................................................... 12
7 TPS40305EVM-488 Assembly Drawings and Layout........................................................................................................ 13
8 TPS40305EVM-488 Bill of Materials.................................................................................................................................... 16
9 Revision History................................................................................................................................................................... 16
Trademarks
NexFET™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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1
Description
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1 Description
The TPS40305EVM-488 is designed to use a regulated 12-V (8 V–14 V) bus voltage to provide a regulated
1.8-V output at up to 10 A of load current. The TPS40305EVM-488 is designed to demonstrate the TPS40305
controller and TI's NexFETs in a typical 12-V bus to low-voltage application while providing a number of noninvasive test points to evaluate the performance of the TPS40305 and TI's NexFETs in a given application.
1.1 Applications
•
•
•
•
High-current, low-voltage FPGA or microcontroller core supplies
High-current point of load modules
Telecommunications equipment
Computer peripherals
1.2 Features
•
•
•
•
•
•
8-V to 14-V input voltage rating
1.8-V ± 2% output voltage rating
10-A steady state load current
1.2-MHz switching frequency
Simple access to IC features including power good, enable, soft start, and error amplifier
Convenient test points for simple, non-invasive measurements of converter performance
2 TPS40305EVM-488 Electrical Performance Specifications
Table 2-1. TPS40305EVM-488 Electrical and Performance Specifications
Parameter
Notes and Conditions
Min
Typ
Max
Unit
Inputs Characteristics
VIN
Input voltage
8
12
14
V
IIN
Input current
VIN = 12 V, IOUT = 10 A
—
1.7
2.00
A
No load input current
VIN = 12 V, IOUT = 0 A
—
47
60
Input UVLO
IOUT = 10 A
VIN_UVLO
3.0
mA
V
Outputs Characteristics
VOUT1
Output voltage 1
VIN = 12 V, IOUT = 10 A
1.76
1.8
1.84
Line regulation
Load regulation
VOUT_ripple
IOUT1
VIN = 8 V to 14 V
—
—
0.5%
IOUT = 0 A to 10 A
—
—
0.5%
Output voltage ripple
VIN = 12 V, IOUT = 10 A
—
—
24
mVpp
Output current 1
VIN = 8 V to 14 V
10
A
0
V
Systems Characteristics
2
FSW
Switching frequency
ηpk
Peak efficiency
η
Full load efficiency
1000
1200
1400
VIN = 12 V
—
88%
—
VIN = 12 V, IOUT = 10 A
—
86%
—
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kHz
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TPS40305EVM-488 Schematic
+
3 TPS40305EVM-488 Schematic
For reference only. See Section 8 for specific values.
Figure 3-1. TPS40305EVM-488 Schematic
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Connector and Test Point Descriptions
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4 Connector and Test Point Descriptions
4.1 Enable Jumper (JP2)
The TPS40305EVM-488 is designed with a Disable Jumper (JP2) using a 0.1" spacing header and shunt.
Installing a shunt in the JP2 position connects the EN/SS pin to GND, discharges the soft-start capacitor, and
disables the TPS40305 controller. This forces the output into a high-impedance state (approximately 15 kΩ to
GND).
4.2 Frequency Spread Spectrum – FSS Jumper (JP1)
The TPS40305EVM-488 is designed with a FSS Enable Jumper (JP1) using a 0.1" spacing header and shunt.
Installing a shunt in the JP1 position connects the EN/SS pin to BP via a 267-kΩ resistor (R10) to enable
frequency spread spectrum.
Frequency spread spectrum modulates the switching frequency to ±10% of the nominal value at 30 kHz to
reduce EMI at the switching frequency and its harmonics, however, there can be a 30-kHz component to the
output ripple (see Figure 6-6).
The TPS40305EVM-488 does not dynamically monitor the JP1 status for programming FSS. The
TPS40305EVM-488 must be disabled through JP2 or powered down by reducing VIN to less than 3.0 V to
remove or install JP1.
4.3 Test Point Descriptions
Table 4-1. Test Point Description
Test Point
Label
Use
Section
TP1
VIN
Measurement test point for input voltage
Section 4.3.1
TP2
GND
Ground test point for input voltage
Section 4.3.1
TP3
VOUT
Measurement test point for output voltage
Section 4.3.1
TP4
GND
Ground test point for output voltage
Section 4.3.2
TP5
CHB
Measurement test point for channel B of loop response
Section 4.3.3
TP6
SGND
Ground test point for channel B of loop response
Section 4.3.3
TP7
CHA
Measurement test point for channel A of loop response
Section 4.3.3
TP8
SGND
Ground test point for channel A of loop response
Section 4.3.3
TP9
SGND
Ground test point for error amplifier measurements
Section 4.3.4
TP10
COMP
Measurement test point for error amplifier output voltage
Section 4.3.4
TP11
FB
Measurement test point for error amplifier input voltage
Section 4.3.4
TP12
HDRV
Measurement test point for high-side gate driver voltage
Section 4.3.5
TP13
LDRV
Measurement test point for low-side gate driver voltage
Section 4.3.5
TP14
PGND
Ground test point for switch node and gate drive voltages
Section 4.3.5
TP15
SW
Measurement test point for switch node voltage
Section 4.3.5
TP16
PGOOD
Measurement test point for power good
Section 4.3.6
TP17
EN/SS
Measurement test point for enable/soft start
Section 4.3.7
TP18
SGND
Ground test point for power good and enable/soft start
Section 4.3.6 and
Section 4.3.7
4.3.1 Input Voltage Monitoring (TP1 and TP2)
The TPS40305EVM-488 provides two test points for measuring the input voltage applied to the module. This
allows the user to measure the actual input module voltage without losses from input cables and connectors. All
input voltage measurements should be made between TP1 and TP2. To use TP1 and TP2, connect a voltmeter
positive input to TP1 and input terminal to TP2.
4.3.2 Output Voltage Monitoring (TP3 and TP4)
The TPS40305EVM-488 provides two test points for measuring the output voltage generated by the module.
This allows the user to measure the actual module output voltage without losses from input cables and
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Connector and Test Point Descriptions
connectors. All input voltage measurements should be made between TP3 and TP4. To use TP3 and TP4,
connect a voltmeter positive input to TP3 and negative input to TP4.
4.3.3 Loop Response Testing (TP5, TP6, TP7, TP8, and R3)
The TPS40305EVM-488 provides four test points (two signal and two ground) for measuring the control loop
frequency response. This allows the user to measure the actual module loop response without modifying the
evaluation board. A transformer isolated signal up to 30 mV can be injected between TP5 and TP7. The injected
signal amplitude can be measured by the AC coupled amplitude at CHA (TP7) and the resulting output voltage
deviation can be measured at CHB (TP5). See Figure 5-3 for additional detail.
4.3.4 Error Amplifier Voltage Monitoring (TP9, TP10, and TP11)
The TPS40305EVM-488 provides three test points for measuring the error amplifier input and output voltages.
This allows the user to directly measure the feedback and control voltages of the TPS40305 controller. The
control voltage (TP10) can also be used to measure the control to output or power stage frequency response or
output to control or error amplifier frequency response. See Section 5.5 for additional details.
4.3.5 Switching Waveform Monitoring (TP12, TP13, TP14, and TP15)
The TPS40305EVM-488 provides three test points and a local power ground for measuring the switching
waveforms of the module power stage. This allows the user to monitor actual switching waveforms during
operation. TP15 is a 0.040" square pad of exposed PCB copper to minimize EMI radiation from the high
transient voltages on the switch node. Switching waveform measurements should be made using power ground
(TP14) as the ground reference for more accurate measurements.
4.3.6 Power-Good Voltage Monitoring (TP16 and TP18)
The TPS40305EVM-488 provides a test point and local ground for measuring the power good output voltage. A
100-kΩ resistor pullup to BP (R9) is included to allow the power-good signal to be monitored without requiring
an external pullup. For true open-drain operation with no pullup, remove R9. With R9 removed, TP16 can be
connected to TP17 of another TPS40305EVM-488 to provide sequential start-up of the two TPS40305EVM-488
converters.
4.3.7 Enable and Soft-Start Voltage Monitoring (TP17 and TP18)
The TPS40305EVM-488 provides a test point and local ground for measuring the enable and soft-start voltage.
TP17 and TP18 or JP2 can be used to provide an external enable signal. Due to the nature of the soft-start
function, the external signal must be open-collector or open-drain without pullup.
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Test Set Up
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5 Test Set Up
5.1 Equipment
5.1.1 Voltage Source
VIN — The input voltage source (VIN) is a 0-V to 15-V variable DC source capable of supplying 2.5 ADC.
5.1.2 Meters
A1: — Input current meter, 0-ADC to 2.5-ADC ammeter
V1: — Input voltage meter, 0-V to 15-V voltmeter
V2: — Output voltage meter, 0-V to 2-V voltmeter
5.1.3 Loads
LOAD1— Output load. Electronic load set for constant current or constant resistance capable of 0 ADC – 10 ADC
at 1.8 VDC.
5.1.4 Oscilloscope
For Output Voltage Ripple— The oscilloscope is an analog or digital oscilloscope set for AC-coupled
measurement with 20-MHz bandwidth limiting. Use 20-mV/division vertical resolution and 200-ns/division
horizontal resolution.
For Switching Waveforms— The oscilloscope is an analog or digital oscilloscope set for DC-coupled
measurement with 20-MHz bandwidth limiting. Use 2-V/division or 5-V/division vertical resolution and 200-ns/
division horizontal resolution.
5.1.5 Recommended Wire Gauge
VIN to J1— The connection between the source voltage (VIN) and J1 of the TPS40305EVM-488 can carry as
much as 2.5 ADC of current. The minimum recommended wire size is AWG #16 with the total length of wire less
than two feet (1-foot input, 1-foot return).
J2 to LOAD1— The connection between the source voltage (VIN) and J1 of the TPS40305EVM-488 can carry
as much as 10 ADC of current. The minimum recommended wire size is AWG #14 with the total length of wire
less than two feet (1-foot input, 1-foot return).
5.1.6 Other
FAN— The TPS40305EVM-488 evaluation module includes components that can get hot to the touch when
operating. Because this evaluation module is not enclosed to allow probing of circuit nodes, a small fan capable
of 200 lfm–400 lfm is recommended to reduce component temperatures when operating.
5.2 Equipment Setup
Shown in Figure 5-1 is the basic test set up recommended to evaluate the TPS40305EVM-488. Note that
although the return for J1 and JP2 are the same system ground, the connections should remain separate as
shown in Figure 5-1.
5.2.1 Procedure
1. Working at an ESD workstation, make sure that any wrist straps, bootstraps, or mats are connected
referencing the user to earth ground before power is applied to the EVM. Electrostatic smock and safety
glasses should also be worn.
2. Prior to connecting the DC input source, VIN, it is advisable to limit the source current from VIN to 3.0-A
maximum. Make sure VIN is initially set to 0 V and connected as shown in Figure 5-1.
3. Connect VIN to J1 as shown in Figure 5-1.
4. Connect ammeter A1 between VIN and J1 as shown in Figure 5-1.
5. Connect voltmeter V1 to TP1 and TP2 as shown in Figure 5-1.
6. Connect voltmeter V2 to TP3 and TP4 as shown in Figure 5-1.
7. Connect oscilloscope probes to desired test points per Table 4-1.
6
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Test Set Up
8. Place the fan as shown in Figure 5-1 and turn on making sure to blow air directly across the evaluation
module.
5.2.2 Diagram
FAN
Oscilloscope
1MW, AC
20mV / div
20MHz
See Tip and Barrel
Measurement for
Vout ripple
+
+
A1
-
VVIN
+
V1
V2
-
+
-
LOAD1
1.8V @
10A
Figure 5-1. TPS40305EVM-488 Recommended Test Setup
Metal Ground Barrel
Probe Tip
TP3
TP4
Tip and Barrel Vout ripple
measurement
Figure 5-2. Output Ripple Measurement – Tip and Barrel using TP3 and TP4
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Test Set Up
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Network
Analyzer
Oscilloscope
1MW, AC
20mV / div
20MHz
See Tip and Barrel
Measurement for
Vout ripple
Isolation
Transformer
+
+
A1
-
VIN
+
V1
V2
-
+
-
LOAD1
1.2V @
20A
Figure 5-3. Control Loop Measurement Setup
5.3 Start-Up/Shutdown Procedure
1.
2.
3.
4.
5.
6.
7.
Verify shunt position for JP1 for desired FSS status.
Remove shunt from JP2 location if present.
Increase VIN from 0 VDC to 12 VDC.
Vary LOAD1 from 0 ADC to 10 ADC.
Vary VIN from 8 V to 14 V.
Decrease VIN to 0 V.
Decrease LOAD1 to 0 A.
5.4 Output Ripple Voltage Measurement Procedure
1.
2.
3.
4.
Follow steps 1–5 from Section 5.3 to set VIN and LOAD1 to the desired operating condition
Connect an oscilloscope probe with exposed metal barrel to TP3 and TP4 per Figure 5-2.
Set the oscilloscope per oscilloscope for output voltage ripple measurement in Section 5.2.2.
Follow steps 6 and 7 from Section 5.3 to power down.
5.5 Control Loop Gain and Phase Measurement Procedure
1. Follow steps 1 – 5 from Section 5.3 to set VIN and LOAD1 to desired operating condition.
a. If JP1 is installed (FSS enabled), loop response data about the modulation frequency (30 kHz) can be
affected.
2. Connect a 1-kHz to 1-MHz isolation transformer to TP5 and TP7 as shown in Figure 5-3.
3. Connect input signal amplitude measurement probe (channel A) to TP7 as shown in Figure 5-3
4. Connect output signal amplitude measurement probe (channel B) to TP5 as shown in Figure 5-3.
5. Connect ground lead of channel A and channel B to TP6 and TP8 as shown in Figure 5-3
6. Inject 30-mV or less signal across R3 through an isolation transformer.
7. Sweep frequency from 1 kHz to 1 MHz with 10-Hz or lower post filter.
8
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8.
9.
10.
11.
12.
Test Set Up
æ Channel B ö
20 ´ LOG ç
÷
è Channel A ø .
Control loop gain can be measured by
Control loop phase can be measured by the phase difference between channel A and channel B.
Control to output response (power stage transfer function) can be measured by connecting channel A probe
to TP10 (COMP) and channel B probe to TP5 (CHB).
Output to control response (compensated error amplifier transfer function) can be measured by connecting
channel A probe to TP7 (CHA) and channel B probe to TP10 (COMP).
Follow steps 6 and 7 from Section 5.3 to power down.
5.6 Equipment Shutdown
1.
2.
3.
4.
Shut down oscilloscope.
Shut down LOAD1.
Shut down VIN.
Shut down fan.
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TPS40305EVM-488 Test Data
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6 TPS40305EVM-488 Test Data
Figure 6-1 through Figure 7-1 present typical performance curves for the TPS40305EVM-488. Since actual
performance data can be affected by measurement techniques and environmental variables, these curves are
presented for reference and may differ from actual field measurements.
6.1 Efficiency
95
8V
90
12 V
85
h - Efficiency - %
80
14 V
75
70
65
60
VIN = 8 V-14 V,
VOUT = 1.8 V,
IOUT = 0-10 A
55
50
0
2
4
6
IL - Load Current - A
8
10
VIN = 8.0 V–14 V, VOUT = 1.8 V, IOUT = 0 A–10 A
Figure 6-1. TPS40305EVM-488 Efficiency vs Load Current
6.2 Line and Load Regulation
1.817
1.812
VIN = 8 V-14 V,
VOUT = 1.8 V,
IOUT = 0-10 A
8V
VOUT - Output Voltage - V
14 V
1.807
1.802
12 V
1.797
1.792
1.787
1.782
0
2
4
6
IL - Load Current - A
8
10
12
VIN = 8.0 V–14 V, VOUT = 1.8 V, IOUT = 0 A–10 A
Figure 6-2. TPS40305EVM-488 Output Voltage vs Load Current
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TPS40305EVM-488 Test Data
6.3 Output Voltage Ripple
TPS40305/HPA488 Rev A
Vin = 14 V, Vout = 1.8 V, Iout = 10 A
Output Ripple
VIN = 14 V, VOUT = 1.8 V, IOUT = 10 A
Figure 6-3. TPS40305EVM-488 Output Voltage Ripple
6.4 Switch Node
TPS40305/HPA488 Switching Waveforms
Vin = 14 V, Vout = 1.8 V, Iout = 10 A
VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A, Ch1: TP12 (HDRV), Ch2:13 TP (SW), Ch3: TP14 (LDRV)
Figure 6-4. TPS40305EVM-488 Switching Waveforms
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TPS40305EVM-488 Test Data
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6.5 Control Loop Bode Diagram
100
225
80
180
Gain - dB
Phase
60
135
40
90
20
45
Gain
0
0
-20
-45
-40
-90
-60
0.1
1
10
f - Frequency - kHz
100
-135
1000
VIN = 14 V, VOUT = 1.8 V, IOUT = 10 A, Bandwidth: 83 kHz, Phase Margin: 55°
Figure 6-5. TPS40305EVM-488 Gain and Phase vs. Frequency
6.6 Additional Waveforms
6.6.1 Output Ripple with Frequency Spread Spectrum (FSS) Enabled
Frequency spread spectrum varies the output switching frequency. This change in switching frequency can
produce a small change in the output voltage at the modulation frequency. Figure 6-6 shows the approximately
50-mV modulation of the output voltage generated when frequency spread spectrum is enabled.
TPS40305/HPA488 Rev A
Vin = 14 V, Vout = 1.8 V, Iout = 10 A
Output Ripple
Figure 6-6. TPS40305EVM-488 Output Ripple with FSS Enabled
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TPS40305EVM-488 Assembly Drawings and Layout
7 TPS40305EVM-488 Assembly Drawings and Layout
Figure 7-1 through Figure 7-6 show the design of the TPS40305EVM-488 printed circuit board. The EVM has
been designed using a 4-layer, 2-oz. copper-clad circuit board 2.5-inch × 2.5-inch with all populated components
on the top to allow the user to easily view, probe. and evaluate the TPS40305 control IC in a practical doublesided application. Moving components to both sides of the PCB or using additional internal layers can offer
additional size reduction for space constrained systems.
Figure 7-1. TPS40305EVM-488 Top Component Placement (Top View)
Figure 7-2. TPS40305EVM-488 Silk Screen (Top View)
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TPS40305EVM-488 Assembly Drawings and Layout
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Figure 7-3. TPS40305EVM-488 Top Copper (Top View)
Figure 7-4. TPS40305EVM-488 Bottom Copper (Top View)
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TPS40305EVM-488 Assembly Drawings and Layout
Figure 7-5. TPS40305EVM-488 Internal 1 (X-Ray Top View)
Figure 7-6. TPS40305EVM-488 Internal 2 (X-Ray Top View)
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TPS40305EVM-488 Bill of Materials
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8 TPS40305EVM-488 Bill of Materials
Table 8-1. TPS40305EVM-488 Bill of Materials
QTY
RefDes
Value
Description
Size
Part Number
MFR
2
C1, C2
10 µF
Capacitor, Ceramic, 25 V, X7R, 10%
1210
Std
Std
1
C10
4.7 µF
Capacitor, Ceramic, 10 V, X7R, 20%
0805
Std
Std
1
C11
1 µF
Capacitor, Ceramic, 25 V, X7R, 20%
0805
Std
Std
0
C12
1 nF
Capacitor, Ceramic, 25 V, X5R, 20%
0603
Std
Std
1
C13
3.3 nF
Capacitor, Ceramic, 10 V, X7R, 20%
0603
Std
Std
1
C3
330 µF
Capacitor, Aluminum, 25 V, ±20%, 160mΩ
0.328 × 0.390 inch
EEEFK1E331P
Panasonic
1
C4
3300 pF
Capacitor, Ceramic, 25 V, X7R, 10%
0603
Std
Std
1
C5
150 pF
Capacitor, Ceramic, 25 V, X7R, 10%
0603
Std
Std
1
C6
820 pF
Capacitor, Ceramic, 25 V, X7R, 10%
0603
Std
Std
1
C7
100 nF
Capacitor, Ceramic, 16 V, X7R, 20%
0603
Std
Std
2
C8, C9
22 µF
Capacitor, Ceramic, 6.3 V, X5R, 20%
0805
Std
Std
2
J1, J2
ED120/2DS
Terminal Block, 2-pin, 15-A, 5.1 mm
0.40 × 0.35 inch
ED120/2DS
OST
2
JP1, JP2
PEC02SAAN
Header, 2-pin, 100-mil spacing
0.100 inch x 2
PEC02SAAN
Sullins
1
L1
0.32 µH
Inductor, SMT, 17A
0.268 × 0.268 inch
PG0083.401NLT
Pulse
1
Q1*
CSD16410Q5A
MOSFET, N-Chan, 25 V, 59 A, 9.6 mΩ
QFN-8 POWER
CSD16410Q5A
TI
1
Q2*
CSD16322Q5
MOSFET, N-Chan, 25 V, 97 A, 4.5 mΩ
QFN-8 POWER
CSD16322Q5
TI
1
R1
2.20 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R2
422 Ω
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R3
49.9 Ω
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R4
10.0 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R5
0Ω
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R6
4.99 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
0
R7
2.2 Ω
Resistor, Chip, 1/8W, 5%
1206
Std
Std
1
R8
2.37 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
2
R9, R10
267 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
2
TP1, TP3
5000
Test Point, Red, Thru Hole Color Keyed
0.100 × 0.100 inch
5000
Keystone
0
TP15
None
Test Point, SM, 2 × 3 mm
0.118 × 0.079 inch
6
TP2, TP4,
TP6, TP8,
TP9, TP18
5001
Test Point, Black, Thru Hole Color Keyed
0.100 × 0.100 inch
5001
Keystone
9
TP5, TP7,
5002
TP10– TP14,
TP16, TP17
Test Point, White, Thru Hole Color Keyed
0.100 × 0.100 inch
5002
Keystone
1
U1*
IC, 3-V to 20-V sync. 600-kHz Buck Controller w/ LLE
and FSS
DRC10
TPS40305DRC
TI
TPS40305DRC
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2010) to Revision A (January 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
• Updated the user's guide title ............................................................................................................................ 2
16
TPS40305 Buck Controller Evaluation Module User's Guide
SLUU406A – FEBRUARY 2010 – REVISED JANUARY 2022
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